]>
Commit | Line | Data |
---|---|---|
3d9edf09 VB |
1 | /* |
2 | * TI DaVinci GPIO Support | |
3 | * | |
dce1115b | 4 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 VB |
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
2f8163ba | 12 | #include <linux/gpio.h> |
3d9edf09 VB |
13 | #include <linux/errno.h> |
14 | #include <linux/kernel.h> | |
3d9edf09 VB |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
118150f2 | 18 | #include <linux/irq.h> |
9211ff31 | 19 | #include <linux/irqdomain.h> |
c770844c KS |
20 | #include <linux/module.h> |
21 | #include <linux/of.h> | |
22 | #include <linux/of_device.h> | |
118150f2 KS |
23 | #include <linux/platform_device.h> |
24 | #include <linux/platform_data/gpio-davinci.h> | |
0d978eb7 | 25 | #include <linux/irqchip/chained_irq.h> |
3d9edf09 | 26 | |
c12f415a CC |
27 | struct davinci_gpio_regs { |
28 | u32 dir; | |
29 | u32 out_data; | |
30 | u32 set_data; | |
31 | u32 clr_data; | |
32 | u32 in_data; | |
33 | u32 set_rising; | |
34 | u32 clr_rising; | |
35 | u32 set_falling; | |
36 | u32 clr_falling; | |
37 | u32 intstat; | |
38 | }; | |
39 | ||
0c6feb07 GS |
40 | typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); |
41 | ||
131a10a3 | 42 | #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
e0275034 | 43 | #define MAX_LABEL_SIZE 20 |
131a10a3 | 44 | |
b8d44293 | 45 | static void __iomem *gpio_base; |
8f7cf8c6 | 46 | static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; |
3d9edf09 | 47 | |
1765d671 | 48 | static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) |
21ce873d | 49 | { |
99e9e52d | 50 | struct davinci_gpio_regs __iomem *g; |
21ce873d | 51 | |
1765d671 | 52 | g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); |
21ce873d KH |
53 | |
54 | return g; | |
55 | } | |
56 | ||
118150f2 | 57 | static int davinci_gpio_irq_setup(struct platform_device *pdev); |
dce1115b DB |
58 | |
59 | /*--------------------------------------------------------------------------*/ | |
60 | ||
5b3a05ca | 61 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
ba4a984e CC |
62 | static inline int __davinci_direction(struct gpio_chip *chip, |
63 | unsigned offset, bool out, int value) | |
3d9edf09 | 64 | { |
72a1ca2c | 65 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 | 66 | struct davinci_gpio_regs __iomem *g; |
b27b6d03 | 67 | unsigned long flags; |
dce1115b | 68 | u32 temp; |
b5cf3fd8 K |
69 | int bank = offset / 32; |
70 | u32 mask = __gpio_mask(offset); | |
3d9edf09 | 71 | |
b5cf3fd8 | 72 | g = d->regs[bank]; |
b27b6d03 | 73 | spin_lock_irqsave(&d->lock, flags); |
388291c3 | 74 | temp = readl_relaxed(&g->dir); |
ba4a984e CC |
75 | if (out) { |
76 | temp &= ~mask; | |
388291c3 | 77 | writel_relaxed(mask, value ? &g->set_data : &g->clr_data); |
ba4a984e CC |
78 | } else { |
79 | temp |= mask; | |
80 | } | |
388291c3 | 81 | writel_relaxed(temp, &g->dir); |
b27b6d03 | 82 | spin_unlock_irqrestore(&d->lock, flags); |
3d9edf09 | 83 | |
dce1115b DB |
84 | return 0; |
85 | } | |
3d9edf09 | 86 | |
ba4a984e CC |
87 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
88 | { | |
89 | return __davinci_direction(chip, offset, false, 0); | |
90 | } | |
91 | ||
92 | static int | |
93 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
94 | { | |
95 | return __davinci_direction(chip, offset, true, value); | |
96 | } | |
97 | ||
3d9edf09 VB |
98 | /* |
99 | * Read the pin's value (works even if it's set up as output); | |
100 | * returns zero/nonzero. | |
101 | * | |
102 | * Note that changes are synched to the GPIO clock, so reading values back | |
103 | * right after you've set them may give old values. | |
104 | */ | |
dce1115b | 105 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 106 | { |
72a1ca2c | 107 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 K |
108 | struct davinci_gpio_regs __iomem *g; |
109 | int bank = offset / 32; | |
3d9edf09 | 110 | |
b5cf3fd8 K |
111 | g = d->regs[bank]; |
112 | ||
113 | return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); | |
3d9edf09 | 114 | } |
3d9edf09 | 115 | |
dce1115b DB |
116 | /* |
117 | * Assuming the pin is muxed as a gpio output, set its output value. | |
118 | */ | |
119 | static void | |
120 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 121 | { |
72a1ca2c | 122 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
b5cf3fd8 K |
123 | struct davinci_gpio_regs __iomem *g; |
124 | int bank = offset / 32; | |
3d9edf09 | 125 | |
b5cf3fd8 K |
126 | g = d->regs[bank]; |
127 | ||
128 | writel_relaxed(__gpio_mask(offset), | |
129 | value ? &g->set_data : &g->clr_data); | |
dce1115b DB |
130 | } |
131 | ||
c770844c KS |
132 | static struct davinci_gpio_platform_data * |
133 | davinci_gpio_get_pdata(struct platform_device *pdev) | |
134 | { | |
135 | struct device_node *dn = pdev->dev.of_node; | |
136 | struct davinci_gpio_platform_data *pdata; | |
137 | int ret; | |
138 | u32 val; | |
139 | ||
140 | if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) | |
ab128afc | 141 | return dev_get_platdata(&pdev->dev); |
c770844c KS |
142 | |
143 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
144 | if (!pdata) | |
145 | return NULL; | |
146 | ||
147 | ret = of_property_read_u32(dn, "ti,ngpio", &val); | |
148 | if (ret) | |
149 | goto of_err; | |
150 | ||
151 | pdata->ngpio = val; | |
152 | ||
153 | ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); | |
154 | if (ret) | |
155 | goto of_err; | |
156 | ||
157 | pdata->gpio_unbanked = val; | |
158 | ||
159 | return pdata; | |
160 | ||
161 | of_err: | |
162 | dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); | |
163 | return NULL; | |
164 | } | |
165 | ||
118150f2 | 166 | static int davinci_gpio_probe(struct platform_device *pdev) |
dce1115b | 167 | { |
8e11047b | 168 | static int ctrl_num, bank_base; |
b5cf3fd8 | 169 | int gpio, bank; |
6ec9249a | 170 | unsigned ngpio, nbank; |
118150f2 KS |
171 | struct davinci_gpio_controller *chips; |
172 | struct davinci_gpio_platform_data *pdata; | |
118150f2 KS |
173 | struct device *dev = &pdev->dev; |
174 | struct resource *res; | |
e0275034 | 175 | char label[MAX_LABEL_SIZE]; |
118150f2 | 176 | |
c770844c | 177 | pdata = davinci_gpio_get_pdata(pdev); |
118150f2 KS |
178 | if (!pdata) { |
179 | dev_err(dev, "No platform data found\n"); | |
180 | return -EINVAL; | |
181 | } | |
686b634a | 182 | |
c770844c KS |
183 | dev->platform_data = pdata; |
184 | ||
a994955c MG |
185 | /* |
186 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
187 | * and "ngpio" is one more than the largest zero-based |
188 | * bit index that's valid. | |
189 | */ | |
118150f2 | 190 | ngpio = pdata->ngpio; |
a994955c | 191 | if (ngpio == 0) { |
118150f2 | 192 | dev_err(dev, "How many GPIOs?\n"); |
474dad54 DB |
193 | return -EINVAL; |
194 | } | |
195 | ||
c21d500b GS |
196 | if (WARN_ON(ARCH_NR_GPIOS < ngpio)) |
197 | ngpio = ARCH_NR_GPIOS; | |
474dad54 | 198 | |
6ec9249a | 199 | nbank = DIV_ROUND_UP(ngpio, 32); |
118150f2 | 200 | chips = devm_kzalloc(dev, |
6ec9249a | 201 | nbank * sizeof(struct davinci_gpio_controller), |
118150f2 | 202 | GFP_KERNEL); |
9ea9363c | 203 | if (!chips) |
b8d44293 | 204 | return -ENOMEM; |
118150f2 KS |
205 | |
206 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
118150f2 KS |
207 | gpio_base = devm_ioremap_resource(dev, res); |
208 | if (IS_ERR(gpio_base)) | |
209 | return PTR_ERR(gpio_base); | |
b8d44293 | 210 | |
b5cf3fd8 K |
211 | snprintf(label, MAX_LABEL_SIZE, "davinci_gpio.%d", ctrl_num++); |
212 | chips->chip.label = devm_kstrdup(dev, label, GFP_KERNEL); | |
213 | if (!chips->chip.label) | |
e0275034 | 214 | return -ENOMEM; |
dce1115b | 215 | |
b5cf3fd8 K |
216 | chips->chip.direction_input = davinci_direction_in; |
217 | chips->chip.get = davinci_gpio_get; | |
218 | chips->chip.direction_output = davinci_direction_out; | |
219 | chips->chip.set = davinci_gpio_set; | |
dce1115b | 220 | |
b5cf3fd8 | 221 | chips->chip.ngpio = ngpio; |
8e11047b | 222 | chips->chip.base = bank_base; |
dce1115b | 223 | |
c770844c | 224 | #ifdef CONFIG_OF_GPIO |
b5cf3fd8 | 225 | chips->chip.of_gpio_n_cells = 2; |
b5cf3fd8 K |
226 | chips->chip.parent = dev; |
227 | chips->chip.of_node = dev->of_node; | |
c770844c | 228 | #endif |
b5cf3fd8 | 229 | spin_lock_init(&chips->lock); |
8e11047b | 230 | bank_base += ngpio; |
dce1115b | 231 | |
b5cf3fd8 K |
232 | for (gpio = 0, bank = 0; gpio < ngpio; gpio += 32, bank++) |
233 | chips->regs[bank] = gpio_base + offset_array[bank]; | |
3d9edf09 | 234 | |
b5cf3fd8 | 235 | gpiochip_add_data(&chips->chip, chips); |
118150f2 KS |
236 | platform_set_drvdata(pdev, chips); |
237 | davinci_gpio_irq_setup(pdev); | |
3d9edf09 VB |
238 | return 0; |
239 | } | |
3d9edf09 | 240 | |
dce1115b | 241 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
242 | /* |
243 | * We expect irqs will normally be set up as input pins, but they can also be | |
244 | * used as output pins ... which is convenient for testing. | |
245 | * | |
474dad54 | 246 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 247 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 248 | * |
474dad54 | 249 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
250 | * serve as EDMA event triggers. |
251 | */ | |
252 | ||
23265442 | 253 | static void gpio_irq_disable(struct irq_data *d) |
3d9edf09 | 254 | { |
1765d671 | 255 | struct davinci_gpio_regs __iomem *g = irq2regs(d); |
6845664a | 256 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
3d9edf09 | 257 | |
388291c3 LP |
258 | writel_relaxed(mask, &g->clr_falling); |
259 | writel_relaxed(mask, &g->clr_rising); | |
3d9edf09 VB |
260 | } |
261 | ||
23265442 | 262 | static void gpio_irq_enable(struct irq_data *d) |
3d9edf09 | 263 | { |
1765d671 | 264 | struct davinci_gpio_regs __iomem *g = irq2regs(d); |
6845664a | 265 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
5093aec8 | 266 | unsigned status = irqd_get_trigger_type(d); |
3d9edf09 | 267 | |
df4aab46 DB |
268 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
269 | if (!status) | |
270 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
271 | ||
272 | if (status & IRQ_TYPE_EDGE_FALLING) | |
388291c3 | 273 | writel_relaxed(mask, &g->set_falling); |
df4aab46 | 274 | if (status & IRQ_TYPE_EDGE_RISING) |
388291c3 | 275 | writel_relaxed(mask, &g->set_rising); |
3d9edf09 VB |
276 | } |
277 | ||
23265442 | 278 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
3d9edf09 | 279 | { |
3d9edf09 VB |
280 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
281 | return -EINVAL; | |
282 | ||
3d9edf09 VB |
283 | return 0; |
284 | } | |
285 | ||
286 | static struct irq_chip gpio_irqchip = { | |
287 | .name = "GPIO", | |
23265442 LB |
288 | .irq_enable = gpio_irq_enable, |
289 | .irq_disable = gpio_irq_disable, | |
290 | .irq_set_type = gpio_irq_type, | |
5093aec8 | 291 | .flags = IRQCHIP_SET_TYPE_MASKED, |
3d9edf09 VB |
292 | }; |
293 | ||
bd0b9ac4 | 294 | static void gpio_irq_handler(struct irq_desc *desc) |
3d9edf09 | 295 | { |
74164016 | 296 | struct davinci_gpio_regs __iomem *g; |
3d9edf09 | 297 | u32 mask = 0xffff; |
b5cf3fd8 | 298 | int bank_num; |
f299bb95 | 299 | struct davinci_gpio_controller *d; |
b5cf3fd8 | 300 | struct davinci_gpio_irq_data *irqdata; |
3d9edf09 | 301 | |
b5cf3fd8 K |
302 | irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc); |
303 | bank_num = irqdata->bank_num; | |
304 | g = irqdata->regs; | |
305 | d = irqdata->chip; | |
74164016 | 306 | |
3d9edf09 | 307 | /* we only care about one bank */ |
b5cf3fd8 | 308 | if ((bank_num % 2) == 1) |
3d9edf09 VB |
309 | mask <<= 16; |
310 | ||
311 | /* temporarily mask (level sensitive) parent IRQ */ | |
0d978eb7 | 312 | chained_irq_enter(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
313 | while (1) { |
314 | u32 status; | |
9211ff31 | 315 | int bit; |
b5cf3fd8 | 316 | irq_hw_number_t hw_irq; |
3d9edf09 VB |
317 | |
318 | /* ack any irqs */ | |
388291c3 | 319 | status = readl_relaxed(&g->intstat) & mask; |
3d9edf09 VB |
320 | if (!status) |
321 | break; | |
388291c3 | 322 | writel_relaxed(status, &g->intstat); |
3d9edf09 VB |
323 | |
324 | /* now demux them to the right lowlevel handler */ | |
f299bb95 | 325 | |
3d9edf09 | 326 | while (status) { |
9211ff31 LP |
327 | bit = __ffs(status); |
328 | status &= ~BIT(bit); | |
b5cf3fd8 K |
329 | /* Max number of gpios per controller is 144 so |
330 | * hw_irq will be in [0..143] | |
331 | */ | |
332 | hw_irq = (bank_num / 2) * 32 + bit; | |
333 | ||
9211ff31 | 334 | generic_handle_irq( |
b5cf3fd8 | 335 | irq_find_mapping(d->irq_domain, hw_irq)); |
3d9edf09 VB |
336 | } |
337 | } | |
0d978eb7 | 338 | chained_irq_exit(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
339 | /* now it may re-trigger */ |
340 | } | |
341 | ||
7a36071e DB |
342 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
343 | { | |
72a1ca2c | 344 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
7a36071e | 345 | |
6075a8b2 | 346 | if (d->irq_domain) |
b5cf3fd8 | 347 | return irq_create_mapping(d->irq_domain, offset); |
6075a8b2 GS |
348 | else |
349 | return -ENXIO; | |
7a36071e DB |
350 | } |
351 | ||
352 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
353 | { | |
72a1ca2c | 354 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
7a36071e | 355 | |
131a10a3 PA |
356 | /* |
357 | * NOTE: we assume for now that only irqs in the first gpio_chip | |
7a36071e DB |
358 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
359 | */ | |
34af1ab4 | 360 | if (offset < d->gpio_unbanked) |
b5cf3fd8 | 361 | return d->base_irq + offset; |
7a36071e DB |
362 | else |
363 | return -ENODEV; | |
364 | } | |
365 | ||
ab2dde99 | 366 | static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
7a36071e | 367 | { |
ab2dde99 SN |
368 | struct davinci_gpio_controller *d; |
369 | struct davinci_gpio_regs __iomem *g; | |
ab2dde99 SN |
370 | u32 mask; |
371 | ||
c16edb8b | 372 | d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); |
ab2dde99 | 373 | g = (struct davinci_gpio_regs __iomem *)d->regs; |
b5cf3fd8 | 374 | mask = __gpio_mask(data->irq - d->base_irq); |
7a36071e DB |
375 | |
376 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
377 | return -EINVAL; | |
378 | ||
388291c3 | 379 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
7a36071e | 380 | ? &g->set_falling : &g->clr_falling); |
388291c3 | 381 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
7a36071e DB |
382 | ? &g->set_rising : &g->clr_rising); |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
9211ff31 LP |
387 | static int |
388 | davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
389 | irq_hw_number_t hw) | |
390 | { | |
8f7cf8c6 K |
391 | struct davinci_gpio_controller *chips = |
392 | (struct davinci_gpio_controller *)d->host_data; | |
b5cf3fd8 | 393 | struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; |
9211ff31 LP |
394 | |
395 | irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, | |
396 | "davinci_gpio"); | |
397 | irq_set_irq_type(irq, IRQ_TYPE_NONE); | |
398 | irq_set_chip_data(irq, (__force void *)g); | |
399 | irq_set_handler_data(irq, (void *)__gpio_mask(hw)); | |
9211ff31 LP |
400 | |
401 | return 0; | |
402 | } | |
403 | ||
404 | static const struct irq_domain_ops davinci_gpio_irq_ops = { | |
405 | .map = davinci_gpio_irq_map, | |
406 | .xlate = irq_domain_xlate_onetwocell, | |
407 | }; | |
408 | ||
0c6feb07 GS |
409 | static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) |
410 | { | |
411 | static struct irq_chip_type gpio_unbanked; | |
412 | ||
ccdbddfe | 413 | gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq)); |
0c6feb07 GS |
414 | |
415 | return &gpio_unbanked.chip; | |
416 | }; | |
417 | ||
418 | static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) | |
419 | { | |
420 | static struct irq_chip gpio_unbanked; | |
421 | ||
422 | gpio_unbanked = *irq_get_chip(irq); | |
423 | return &gpio_unbanked; | |
424 | }; | |
425 | ||
426 | static const struct of_device_id davinci_gpio_ids[]; | |
427 | ||
3d9edf09 | 428 | /* |
474dad54 DB |
429 | * NOTE: for suspend/resume, probably best to make a platform_device with |
430 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
431 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
432 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 433 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
434 | */ |
435 | ||
118150f2 | 436 | static int davinci_gpio_irq_setup(struct platform_device *pdev) |
3d9edf09 | 437 | { |
58c0f5aa AS |
438 | unsigned gpio, bank; |
439 | int irq; | |
6dc0048c | 440 | int ret; |
3d9edf09 | 441 | struct clk *clk; |
474dad54 | 442 | u32 binten = 0; |
a994955c | 443 | unsigned ngpio, bank_irq; |
118150f2 KS |
444 | struct device *dev = &pdev->dev; |
445 | struct resource *res; | |
446 | struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); | |
447 | struct davinci_gpio_platform_data *pdata = dev->platform_data; | |
448 | struct davinci_gpio_regs __iomem *g; | |
6075a8b2 | 449 | struct irq_domain *irq_domain = NULL; |
0c6feb07 GS |
450 | const struct of_device_id *match; |
451 | struct irq_chip *irq_chip; | |
b5cf3fd8 | 452 | struct davinci_gpio_irq_data *irqdata; |
0c6feb07 GS |
453 | gpio_get_irq_chip_cb_t gpio_get_irq_chip; |
454 | ||
455 | /* | |
456 | * Use davinci_gpio_get_irq_chip by default to handle non DT cases | |
457 | */ | |
458 | gpio_get_irq_chip = davinci_gpio_get_irq_chip; | |
459 | match = of_match_device(of_match_ptr(davinci_gpio_ids), | |
460 | dev); | |
461 | if (match) | |
462 | gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; | |
a994955c | 463 | |
118150f2 KS |
464 | ngpio = pdata->ngpio; |
465 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
466 | if (!res) { | |
467 | dev_err(dev, "Invalid IRQ resource\n"); | |
468 | return -EBUSY; | |
469 | } | |
474dad54 | 470 | |
118150f2 KS |
471 | bank_irq = res->start; |
472 | ||
473 | if (!bank_irq) { | |
474 | dev_err(dev, "Invalid IRQ resource\n"); | |
475 | return -ENODEV; | |
474dad54 | 476 | } |
3d9edf09 | 477 | |
118150f2 | 478 | clk = devm_clk_get(dev, "gpio"); |
3d9edf09 VB |
479 | if (IS_ERR(clk)) { |
480 | printk(KERN_ERR "Error %ld getting gpio clock?\n", | |
481 | PTR_ERR(clk)); | |
474dad54 | 482 | return PTR_ERR(clk); |
3d9edf09 | 483 | } |
6dc0048c AY |
484 | ret = clk_prepare_enable(clk); |
485 | if (ret) | |
486 | return ret; | |
3d9edf09 | 487 | |
6075a8b2 | 488 | if (!pdata->gpio_unbanked) { |
a1a3c2d5 | 489 | irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); |
6075a8b2 GS |
490 | if (irq < 0) { |
491 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
6dc0048c | 492 | clk_disable_unprepare(clk); |
6075a8b2 GS |
493 | return irq; |
494 | } | |
9211ff31 | 495 | |
310a7e60 | 496 | irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, |
6075a8b2 GS |
497 | &davinci_gpio_irq_ops, |
498 | chips); | |
499 | if (!irq_domain) { | |
500 | dev_err(dev, "Couldn't register an IRQ domain\n"); | |
6dc0048c | 501 | clk_disable_unprepare(clk); |
6075a8b2 GS |
502 | return -ENODEV; |
503 | } | |
9211ff31 LP |
504 | } |
505 | ||
131a10a3 PA |
506 | /* |
507 | * Arrange gpio_to_irq() support, handling either direct IRQs or | |
7a36071e DB |
508 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
509 | * IRQs, while the others use banked IRQs, would need some setup | |
510 | * tweaks to recognize hardware which can do that. | |
511 | */ | |
b5cf3fd8 K |
512 | chips->chip.to_irq = gpio_to_irq_banked; |
513 | chips->irq_domain = irq_domain; | |
7a36071e DB |
514 | |
515 | /* | |
516 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
517 | * controller only handling trigger modes. We currently assume no | |
518 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
519 | */ | |
118150f2 | 520 | if (pdata->gpio_unbanked) { |
7a36071e | 521 | /* pass "bank 0" GPIO IRQs to AINTC */ |
b5cf3fd8 K |
522 | chips->chip.to_irq = gpio_to_irq_unbanked; |
523 | chips->base_irq = bank_irq; | |
524 | chips->gpio_unbanked = pdata->gpio_unbanked; | |
3685bbce | 525 | binten = GENMASK(pdata->gpio_unbanked / 16, 0); |
7a36071e DB |
526 | |
527 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
528 | irq = bank_irq; | |
0c6feb07 GS |
529 | irq_chip = gpio_get_irq_chip(irq); |
530 | irq_chip->name = "GPIO-AINTC"; | |
531 | irq_chip->irq_set_type = gpio_irq_type_unbanked; | |
7a36071e DB |
532 | |
533 | /* default trigger: both edges */ | |
b5cf3fd8 | 534 | g = chips->regs[0]; |
388291c3 LP |
535 | writel_relaxed(~0, &g->set_falling); |
536 | writel_relaxed(~0, &g->set_rising); | |
7a36071e DB |
537 | |
538 | /* set the direct IRQs up to use that irqchip */ | |
118150f2 | 539 | for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { |
0c6feb07 | 540 | irq_set_chip(irq, irq_chip); |
b5cf3fd8 | 541 | irq_set_handler_data(irq, chips); |
5093aec8 | 542 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); |
7a36071e DB |
543 | } |
544 | ||
545 | goto done; | |
546 | } | |
547 | ||
548 | /* | |
549 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
550 | * then chain through our own handler. | |
551 | */ | |
9211ff31 | 552 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) { |
8f7cf8c6 K |
553 | /* disabled by default, enabled only as needed |
554 | * There are register sets for 32 GPIOs. 2 banks of 16 | |
555 | * GPIOs are covered by each set of registers hence divide by 2 | |
556 | */ | |
b5cf3fd8 | 557 | g = chips->regs[bank / 2]; |
388291c3 LP |
558 | writel_relaxed(~0, &g->clr_falling); |
559 | writel_relaxed(~0, &g->clr_rising); | |
3d9edf09 | 560 | |
f299bb95 IY |
561 | /* |
562 | * Each chip handles 32 gpios, and each irq bank consists of 16 | |
563 | * gpio irqs. Pass the irq bank's corresponding controller to | |
564 | * the chained irq handler. | |
565 | */ | |
b5cf3fd8 K |
566 | irqdata = devm_kzalloc(&pdev->dev, |
567 | sizeof(struct | |
568 | davinci_gpio_irq_data), | |
569 | GFP_KERNEL); | |
6dc0048c AY |
570 | if (!irqdata) { |
571 | clk_disable_unprepare(clk); | |
b5cf3fd8 | 572 | return -ENOMEM; |
6dc0048c | 573 | } |
b5cf3fd8 K |
574 | |
575 | irqdata->regs = g; | |
576 | irqdata->bank_num = bank; | |
577 | irqdata->chip = chips; | |
578 | ||
bdac2b6d | 579 | irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler, |
b5cf3fd8 | 580 | irqdata); |
3d9edf09 | 581 | |
474dad54 | 582 | binten |= BIT(bank); |
3d9edf09 VB |
583 | } |
584 | ||
7a36071e | 585 | done: |
131a10a3 PA |
586 | /* |
587 | * BINTEN -- per-bank interrupt enable. genirq would also let these | |
3d9edf09 VB |
588 | * bits be set/cleared dynamically. |
589 | */ | |
388291c3 | 590 | writel_relaxed(binten, gpio_base + BINTEN); |
3d9edf09 | 591 | |
3d9edf09 VB |
592 | return 0; |
593 | } | |
118150f2 | 594 | |
c770844c KS |
595 | #if IS_ENABLED(CONFIG_OF) |
596 | static const struct of_device_id davinci_gpio_ids[] = { | |
0c6feb07 GS |
597 | { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, |
598 | { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, | |
c770844c KS |
599 | { /* sentinel */ }, |
600 | }; | |
601 | MODULE_DEVICE_TABLE(of, davinci_gpio_ids); | |
602 | #endif | |
603 | ||
118150f2 KS |
604 | static struct platform_driver davinci_gpio_driver = { |
605 | .probe = davinci_gpio_probe, | |
606 | .driver = { | |
c770844c | 607 | .name = "davinci_gpio", |
c770844c | 608 | .of_match_table = of_match_ptr(davinci_gpio_ids), |
118150f2 KS |
609 | }, |
610 | }; | |
611 | ||
612 | /** | |
613 | * GPIO driver registration needs to be done before machine_init functions | |
614 | * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. | |
615 | */ | |
616 | static int __init davinci_gpio_drv_reg(void) | |
617 | { | |
618 | return platform_driver_register(&davinci_gpio_driver); | |
619 | } | |
620 | postcore_initcall(davinci_gpio_drv_reg); |