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[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-davinci.c
CommitLineData
3d9edf09
VB
1/*
2 * TI DaVinci GPIO Support
3 *
dce1115b 4 * Copyright (c) 2006-2007 David Brownell
3d9edf09
VB
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
2f8163ba 12#include <linux/gpio.h>
3d9edf09
VB
13#include <linux/errno.h>
14#include <linux/kernel.h>
3d9edf09
VB
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
118150f2 18#include <linux/irq.h>
9211ff31 19#include <linux/irqdomain.h>
c770844c
KS
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
118150f2
KS
23#include <linux/platform_device.h>
24#include <linux/platform_data/gpio-davinci.h>
0d978eb7 25#include <linux/irqchip/chained_irq.h>
3d9edf09 26
c12f415a
CC
27struct davinci_gpio_regs {
28 u32 dir;
29 u32 out_data;
30 u32 set_data;
31 u32 clr_data;
32 u32 in_data;
33 u32 set_rising;
34 u32 clr_rising;
35 u32 set_falling;
36 u32 clr_falling;
37 u32 intstat;
38};
39
0c6feb07
GS
40typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
41
131a10a3
PA
42#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
43
b8d44293 44static void __iomem *gpio_base;
3d9edf09 45
118150f2 46static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
3d9edf09 47{
c12f415a 48 void __iomem *ptr;
c12f415a
CC
49
50 if (gpio < 32 * 1)
b8d44293 51 ptr = gpio_base + 0x10;
c12f415a 52 else if (gpio < 32 * 2)
b8d44293 53 ptr = gpio_base + 0x38;
c12f415a 54 else if (gpio < 32 * 3)
b8d44293 55 ptr = gpio_base + 0x60;
c12f415a 56 else if (gpio < 32 * 4)
b8d44293 57 ptr = gpio_base + 0x88;
c12f415a 58 else if (gpio < 32 * 5)
b8d44293 59 ptr = gpio_base + 0xb0;
c12f415a
CC
60 else
61 ptr = NULL;
62 return ptr;
3d9edf09
VB
63}
64
1765d671 65static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
21ce873d 66{
99e9e52d 67 struct davinci_gpio_regs __iomem *g;
21ce873d 68
1765d671 69 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
21ce873d
KH
70
71 return g;
72}
73
118150f2 74static int davinci_gpio_irq_setup(struct platform_device *pdev);
dce1115b
DB
75
76/*--------------------------------------------------------------------------*/
77
5b3a05ca 78/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
ba4a984e
CC
79static inline int __davinci_direction(struct gpio_chip *chip,
80 unsigned offset, bool out, int value)
3d9edf09 81{
72a1ca2c 82 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
99e9e52d 83 struct davinci_gpio_regs __iomem *g = d->regs;
b27b6d03 84 unsigned long flags;
dce1115b 85 u32 temp;
ba4a984e 86 u32 mask = 1 << offset;
3d9edf09 87
b27b6d03 88 spin_lock_irqsave(&d->lock, flags);
388291c3 89 temp = readl_relaxed(&g->dir);
ba4a984e
CC
90 if (out) {
91 temp &= ~mask;
388291c3 92 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
ba4a984e
CC
93 } else {
94 temp |= mask;
95 }
388291c3 96 writel_relaxed(temp, &g->dir);
b27b6d03 97 spin_unlock_irqrestore(&d->lock, flags);
3d9edf09 98
dce1115b
DB
99 return 0;
100}
3d9edf09 101
ba4a984e
CC
102static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
103{
104 return __davinci_direction(chip, offset, false, 0);
105}
106
107static int
108davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
109{
110 return __davinci_direction(chip, offset, true, value);
111}
112
3d9edf09
VB
113/*
114 * Read the pin's value (works even if it's set up as output);
115 * returns zero/nonzero.
116 *
117 * Note that changes are synched to the GPIO clock, so reading values back
118 * right after you've set them may give old values.
119 */
dce1115b 120static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
3d9edf09 121{
72a1ca2c 122 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
99e9e52d 123 struct davinci_gpio_regs __iomem *g = d->regs;
3d9edf09 124
5b8d8fb0 125 return !!((1 << offset) & readl_relaxed(&g->in_data));
3d9edf09 126}
3d9edf09 127
dce1115b
DB
128/*
129 * Assuming the pin is muxed as a gpio output, set its output value.
130 */
131static void
132davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3d9edf09 133{
72a1ca2c 134 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
99e9e52d 135 struct davinci_gpio_regs __iomem *g = d->regs;
3d9edf09 136
388291c3 137 writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
dce1115b
DB
138}
139
c770844c
KS
140static struct davinci_gpio_platform_data *
141davinci_gpio_get_pdata(struct platform_device *pdev)
142{
143 struct device_node *dn = pdev->dev.of_node;
144 struct davinci_gpio_platform_data *pdata;
145 int ret;
146 u32 val;
147
148 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
ab128afc 149 return dev_get_platdata(&pdev->dev);
c770844c
KS
150
151 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
152 if (!pdata)
153 return NULL;
154
155 ret = of_property_read_u32(dn, "ti,ngpio", &val);
156 if (ret)
157 goto of_err;
158
159 pdata->ngpio = val;
160
161 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
162 if (ret)
163 goto of_err;
164
165 pdata->gpio_unbanked = val;
166
167 return pdata;
168
169of_err:
170 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
171 return NULL;
172}
173
758afe42
AH
174#ifdef CONFIG_OF_GPIO
175static int davinci_gpio_of_xlate(struct gpio_chip *gc,
176 const struct of_phandle_args *gpiospec,
177 u32 *flags)
178{
58383c78
LW
179 struct davinci_gpio_controller *chips = dev_get_drvdata(gc->parent);
180 struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->parent);
758afe42
AH
181
182 if (gpiospec->args[0] > pdata->ngpio)
183 return -EINVAL;
184
185 if (gc != &chips[gpiospec->args[0] / 32].chip)
186 return -EINVAL;
187
188 if (flags)
189 *flags = gpiospec->args[1];
190
191 return gpiospec->args[0] % 32;
192}
193#endif
194
118150f2 195static int davinci_gpio_probe(struct platform_device *pdev)
dce1115b
DB
196{
197 int i, base;
6ec9249a 198 unsigned ngpio, nbank;
118150f2
KS
199 struct davinci_gpio_controller *chips;
200 struct davinci_gpio_platform_data *pdata;
201 struct davinci_gpio_regs __iomem *regs;
202 struct device *dev = &pdev->dev;
203 struct resource *res;
204
c770844c 205 pdata = davinci_gpio_get_pdata(pdev);
118150f2
KS
206 if (!pdata) {
207 dev_err(dev, "No platform data found\n");
208 return -EINVAL;
209 }
686b634a 210
c770844c
KS
211 dev->platform_data = pdata;
212
a994955c
MG
213 /*
214 * The gpio banks conceptually expose a segmented bitmap,
474dad54
DB
215 * and "ngpio" is one more than the largest zero-based
216 * bit index that's valid.
217 */
118150f2 218 ngpio = pdata->ngpio;
a994955c 219 if (ngpio == 0) {
118150f2 220 dev_err(dev, "How many GPIOs?\n");
474dad54
DB
221 return -EINVAL;
222 }
223
c21d500b
GS
224 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
225 ngpio = ARCH_NR_GPIOS;
474dad54 226
6ec9249a 227 nbank = DIV_ROUND_UP(ngpio, 32);
118150f2 228 chips = devm_kzalloc(dev,
6ec9249a 229 nbank * sizeof(struct davinci_gpio_controller),
118150f2 230 GFP_KERNEL);
9ea9363c 231 if (!chips)
b8d44293 232 return -ENOMEM;
118150f2
KS
233
234 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
118150f2
KS
235 gpio_base = devm_ioremap_resource(dev, res);
236 if (IS_ERR(gpio_base))
237 return PTR_ERR(gpio_base);
b8d44293 238
474dad54 239 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
dce1115b
DB
240 chips[i].chip.label = "DaVinci";
241
242 chips[i].chip.direction_input = davinci_direction_in;
243 chips[i].chip.get = davinci_gpio_get;
244 chips[i].chip.direction_output = davinci_direction_out;
245 chips[i].chip.set = davinci_gpio_set;
246
247 chips[i].chip.base = base;
474dad54 248 chips[i].chip.ngpio = ngpio - base;
dce1115b
DB
249 if (chips[i].chip.ngpio > 32)
250 chips[i].chip.ngpio = 32;
251
c770844c 252#ifdef CONFIG_OF_GPIO
758afe42
AH
253 chips[i].chip.of_gpio_n_cells = 2;
254 chips[i].chip.of_xlate = davinci_gpio_of_xlate;
6ddbaed3 255 chips[i].chip.parent = dev;
c770844c
KS
256 chips[i].chip.of_node = dev->of_node;
257#endif
b27b6d03
CC
258 spin_lock_init(&chips[i].lock);
259
c12f415a
CC
260 regs = gpio2regs(base);
261 chips[i].regs = regs;
262 chips[i].set_data = &regs->set_data;
263 chips[i].clr_data = &regs->clr_data;
264 chips[i].in_data = &regs->in_data;
dce1115b 265
72a1ca2c 266 gpiochip_add_data(&chips[i].chip, &chips[i]);
dce1115b 267 }
3d9edf09 268
118150f2
KS
269 platform_set_drvdata(pdev, chips);
270 davinci_gpio_irq_setup(pdev);
3d9edf09
VB
271 return 0;
272}
3d9edf09 273
dce1115b 274/*--------------------------------------------------------------------------*/
3d9edf09
VB
275/*
276 * We expect irqs will normally be set up as input pins, but they can also be
277 * used as output pins ... which is convenient for testing.
278 *
474dad54 279 * NOTE: The first few GPIOs also have direct INTC hookups in addition
7a36071e 280 * to their GPIOBNK0 irq, with a bit less overhead.
3d9edf09 281 *
474dad54 282 * All those INTC hookups (direct, plus several IRQ banks) can also
3d9edf09
VB
283 * serve as EDMA event triggers.
284 */
285
23265442 286static void gpio_irq_disable(struct irq_data *d)
3d9edf09 287{
1765d671 288 struct davinci_gpio_regs __iomem *g = irq2regs(d);
6845664a 289 u32 mask = (u32) irq_data_get_irq_handler_data(d);
3d9edf09 290
388291c3
LP
291 writel_relaxed(mask, &g->clr_falling);
292 writel_relaxed(mask, &g->clr_rising);
3d9edf09
VB
293}
294
23265442 295static void gpio_irq_enable(struct irq_data *d)
3d9edf09 296{
1765d671 297 struct davinci_gpio_regs __iomem *g = irq2regs(d);
6845664a 298 u32 mask = (u32) irq_data_get_irq_handler_data(d);
5093aec8 299 unsigned status = irqd_get_trigger_type(d);
3d9edf09 300
df4aab46
DB
301 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
302 if (!status)
303 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
304
305 if (status & IRQ_TYPE_EDGE_FALLING)
388291c3 306 writel_relaxed(mask, &g->set_falling);
df4aab46 307 if (status & IRQ_TYPE_EDGE_RISING)
388291c3 308 writel_relaxed(mask, &g->set_rising);
3d9edf09
VB
309}
310
23265442 311static int gpio_irq_type(struct irq_data *d, unsigned trigger)
3d9edf09 312{
3d9edf09
VB
313 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
314 return -EINVAL;
315
3d9edf09
VB
316 return 0;
317}
318
319static struct irq_chip gpio_irqchip = {
320 .name = "GPIO",
23265442
LB
321 .irq_enable = gpio_irq_enable,
322 .irq_disable = gpio_irq_disable,
323 .irq_set_type = gpio_irq_type,
5093aec8 324 .flags = IRQCHIP_SET_TYPE_MASKED,
3d9edf09
VB
325};
326
bd0b9ac4 327static void gpio_irq_handler(struct irq_desc *desc)
3d9edf09 328{
c3ca1e6f 329 unsigned int irq = irq_desc_get_irq(desc);
74164016 330 struct davinci_gpio_regs __iomem *g;
3d9edf09 331 u32 mask = 0xffff;
f299bb95 332 struct davinci_gpio_controller *d;
3d9edf09 333
f299bb95
IY
334 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
335 g = (struct davinci_gpio_regs __iomem *)d->regs;
74164016 336
3d9edf09
VB
337 /* we only care about one bank */
338 if (irq & 1)
339 mask <<= 16;
340
341 /* temporarily mask (level sensitive) parent IRQ */
0d978eb7 342 chained_irq_enter(irq_desc_get_chip(desc), desc);
3d9edf09
VB
343 while (1) {
344 u32 status;
9211ff31 345 int bit;
3d9edf09
VB
346
347 /* ack any irqs */
388291c3 348 status = readl_relaxed(&g->intstat) & mask;
3d9edf09
VB
349 if (!status)
350 break;
388291c3 351 writel_relaxed(status, &g->intstat);
3d9edf09
VB
352
353 /* now demux them to the right lowlevel handler */
f299bb95 354
3d9edf09 355 while (status) {
9211ff31
LP
356 bit = __ffs(status);
357 status &= ~BIT(bit);
358 generic_handle_irq(
359 irq_find_mapping(d->irq_domain,
360 d->chip.base + bit));
3d9edf09
VB
361 }
362 }
0d978eb7 363 chained_irq_exit(irq_desc_get_chip(desc), desc);
3d9edf09
VB
364 /* now it may re-trigger */
365}
366
7a36071e
DB
367static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
368{
72a1ca2c 369 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
7a36071e 370
6075a8b2
GS
371 if (d->irq_domain)
372 return irq_create_mapping(d->irq_domain, d->chip.base + offset);
373 else
374 return -ENXIO;
7a36071e
DB
375}
376
377static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
378{
72a1ca2c 379 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
7a36071e 380
131a10a3
PA
381 /*
382 * NOTE: we assume for now that only irqs in the first gpio_chip
7a36071e
DB
383 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
384 */
34af1ab4 385 if (offset < d->gpio_unbanked)
118150f2 386 return d->gpio_irq + offset;
7a36071e
DB
387 else
388 return -ENODEV;
389}
390
ab2dde99 391static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
7a36071e 392{
ab2dde99
SN
393 struct davinci_gpio_controller *d;
394 struct davinci_gpio_regs __iomem *g;
ab2dde99
SN
395 u32 mask;
396
c16edb8b 397 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
ab2dde99 398 g = (struct davinci_gpio_regs __iomem *)d->regs;
118150f2 399 mask = __gpio_mask(data->irq - d->gpio_irq);
7a36071e
DB
400
401 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
402 return -EINVAL;
403
388291c3 404 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
7a36071e 405 ? &g->set_falling : &g->clr_falling);
388291c3 406 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
7a36071e
DB
407 ? &g->set_rising : &g->clr_rising);
408
409 return 0;
410}
411
9211ff31
LP
412static int
413davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
414 irq_hw_number_t hw)
415{
416 struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
417
418 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
419 "davinci_gpio");
420 irq_set_irq_type(irq, IRQ_TYPE_NONE);
421 irq_set_chip_data(irq, (__force void *)g);
422 irq_set_handler_data(irq, (void *)__gpio_mask(hw));
9211ff31
LP
423
424 return 0;
425}
426
427static const struct irq_domain_ops davinci_gpio_irq_ops = {
428 .map = davinci_gpio_irq_map,
429 .xlate = irq_domain_xlate_onetwocell,
430};
431
0c6feb07
GS
432static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
433{
434 static struct irq_chip_type gpio_unbanked;
435
436 gpio_unbanked = *container_of(irq_get_chip(irq),
437 struct irq_chip_type, chip);
438
439 return &gpio_unbanked.chip;
440};
441
442static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
443{
444 static struct irq_chip gpio_unbanked;
445
446 gpio_unbanked = *irq_get_chip(irq);
447 return &gpio_unbanked;
448};
449
450static const struct of_device_id davinci_gpio_ids[];
451
3d9edf09 452/*
474dad54
DB
453 * NOTE: for suspend/resume, probably best to make a platform_device with
454 * suspend_late/resume_resume calls hooking into results of the set_wake()
3d9edf09
VB
455 * calls ... so if no gpios are wakeup events the clock can be disabled,
456 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
474dad54 457 * (dm6446) can be set appropriately for GPIOV33 pins.
3d9edf09
VB
458 */
459
118150f2 460static int davinci_gpio_irq_setup(struct platform_device *pdev)
3d9edf09 461{
58c0f5aa
AS
462 unsigned gpio, bank;
463 int irq;
3d9edf09 464 struct clk *clk;
474dad54 465 u32 binten = 0;
a994955c 466 unsigned ngpio, bank_irq;
118150f2
KS
467 struct device *dev = &pdev->dev;
468 struct resource *res;
469 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
470 struct davinci_gpio_platform_data *pdata = dev->platform_data;
471 struct davinci_gpio_regs __iomem *g;
6075a8b2 472 struct irq_domain *irq_domain = NULL;
0c6feb07
GS
473 const struct of_device_id *match;
474 struct irq_chip *irq_chip;
475 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
476
477 /*
478 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
479 */
480 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
481 match = of_match_device(of_match_ptr(davinci_gpio_ids),
482 dev);
483 if (match)
484 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
a994955c 485
118150f2
KS
486 ngpio = pdata->ngpio;
487 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
488 if (!res) {
489 dev_err(dev, "Invalid IRQ resource\n");
490 return -EBUSY;
491 }
474dad54 492
118150f2
KS
493 bank_irq = res->start;
494
495 if (!bank_irq) {
496 dev_err(dev, "Invalid IRQ resource\n");
497 return -ENODEV;
474dad54 498 }
3d9edf09 499
118150f2 500 clk = devm_clk_get(dev, "gpio");
3d9edf09
VB
501 if (IS_ERR(clk)) {
502 printk(KERN_ERR "Error %ld getting gpio clock?\n",
503 PTR_ERR(clk));
474dad54 504 return PTR_ERR(clk);
3d9edf09 505 }
ce6b658d 506 clk_prepare_enable(clk);
3d9edf09 507
6075a8b2
GS
508 if (!pdata->gpio_unbanked) {
509 irq = irq_alloc_descs(-1, 0, ngpio, 0);
510 if (irq < 0) {
511 dev_err(dev, "Couldn't allocate IRQ numbers\n");
512 return irq;
513 }
9211ff31 514
310a7e60 515 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
6075a8b2
GS
516 &davinci_gpio_irq_ops,
517 chips);
518 if (!irq_domain) {
519 dev_err(dev, "Couldn't register an IRQ domain\n");
520 return -ENODEV;
521 }
9211ff31
LP
522 }
523
131a10a3
PA
524 /*
525 * Arrange gpio_to_irq() support, handling either direct IRQs or
7a36071e
DB
526 * banked IRQs. Having GPIOs in the first GPIO bank use direct
527 * IRQs, while the others use banked IRQs, would need some setup
528 * tweaks to recognize hardware which can do that.
529 */
530 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
531 chips[bank].chip.to_irq = gpio_to_irq_banked;
6075a8b2 532 chips[bank].irq_domain = irq_domain;
7a36071e
DB
533 }
534
535 /*
536 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
537 * controller only handling trigger modes. We currently assume no
538 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
539 */
118150f2 540 if (pdata->gpio_unbanked) {
7a36071e
DB
541 /* pass "bank 0" GPIO IRQs to AINTC */
542 chips[0].chip.to_irq = gpio_to_irq_unbanked;
34af1ab4
LP
543 chips[0].gpio_irq = bank_irq;
544 chips[0].gpio_unbanked = pdata->gpio_unbanked;
3685bbce 545 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
7a36071e
DB
546
547 /* AINTC handles mask/unmask; GPIO handles triggering */
548 irq = bank_irq;
0c6feb07
GS
549 irq_chip = gpio_get_irq_chip(irq);
550 irq_chip->name = "GPIO-AINTC";
551 irq_chip->irq_set_type = gpio_irq_type_unbanked;
7a36071e
DB
552
553 /* default trigger: both edges */
99e9e52d 554 g = gpio2regs(0);
388291c3
LP
555 writel_relaxed(~0, &g->set_falling);
556 writel_relaxed(~0, &g->set_rising);
7a36071e
DB
557
558 /* set the direct IRQs up to use that irqchip */
118150f2 559 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
0c6feb07 560 irq_set_chip(irq, irq_chip);
ab2dde99 561 irq_set_handler_data(irq, &chips[gpio / 32]);
5093aec8 562 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
7a36071e
DB
563 }
564
565 goto done;
566 }
567
568 /*
569 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
570 * then chain through our own handler.
571 */
9211ff31 572 for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
7a36071e 573 /* disabled by default, enabled only as needed */
99e9e52d 574 g = gpio2regs(gpio);
388291c3
LP
575 writel_relaxed(~0, &g->clr_falling);
576 writel_relaxed(~0, &g->clr_rising);
3d9edf09 577
f299bb95
IY
578 /*
579 * Each chip handles 32 gpios, and each irq bank consists of 16
580 * gpio irqs. Pass the irq bank's corresponding controller to
581 * the chained irq handler.
582 */
bdac2b6d
TG
583 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
584 &chips[gpio / 32]);
3d9edf09 585
474dad54 586 binten |= BIT(bank);
3d9edf09
VB
587 }
588
7a36071e 589done:
131a10a3
PA
590 /*
591 * BINTEN -- per-bank interrupt enable. genirq would also let these
3d9edf09
VB
592 * bits be set/cleared dynamically.
593 */
388291c3 594 writel_relaxed(binten, gpio_base + BINTEN);
3d9edf09 595
3d9edf09
VB
596 return 0;
597}
118150f2 598
c770844c
KS
599#if IS_ENABLED(CONFIG_OF)
600static const struct of_device_id davinci_gpio_ids[] = {
0c6feb07
GS
601 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
602 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
c770844c
KS
603 { /* sentinel */ },
604};
605MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
606#endif
607
118150f2
KS
608static struct platform_driver davinci_gpio_driver = {
609 .probe = davinci_gpio_probe,
610 .driver = {
c770844c 611 .name = "davinci_gpio",
c770844c 612 .of_match_table = of_match_ptr(davinci_gpio_ids),
118150f2
KS
613 },
614};
615
616/**
617 * GPIO driver registration needs to be done before machine_init functions
618 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
619 */
620static int __init davinci_gpio_drv_reg(void)
621{
622 return platform_driver_register(&davinci_gpio_driver);
623}
624postcore_initcall(davinci_gpio_drv_reg);