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Commit | Line | Data |
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3d9edf09 VB |
1 | /* |
2 | * TI DaVinci GPIO Support | |
3 | * | |
dce1115b | 4 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 VB |
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
2f8163ba | 12 | #include <linux/gpio.h> |
3d9edf09 VB |
13 | #include <linux/errno.h> |
14 | #include <linux/kernel.h> | |
3d9edf09 VB |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
118150f2 | 18 | #include <linux/irq.h> |
9211ff31 | 19 | #include <linux/irqdomain.h> |
c770844c KS |
20 | #include <linux/module.h> |
21 | #include <linux/of.h> | |
22 | #include <linux/of_device.h> | |
118150f2 KS |
23 | #include <linux/platform_device.h> |
24 | #include <linux/platform_data/gpio-davinci.h> | |
0d978eb7 | 25 | #include <linux/irqchip/chained_irq.h> |
3d9edf09 | 26 | |
c12f415a CC |
27 | struct davinci_gpio_regs { |
28 | u32 dir; | |
29 | u32 out_data; | |
30 | u32 set_data; | |
31 | u32 clr_data; | |
32 | u32 in_data; | |
33 | u32 set_rising; | |
34 | u32 clr_rising; | |
35 | u32 set_falling; | |
36 | u32 clr_falling; | |
37 | u32 intstat; | |
38 | }; | |
39 | ||
0c6feb07 GS |
40 | typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); |
41 | ||
131a10a3 | 42 | #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
e0275034 | 43 | #define MAX_LABEL_SIZE 20 |
131a10a3 | 44 | |
b8d44293 | 45 | static void __iomem *gpio_base; |
8f7cf8c6 | 46 | static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; |
3d9edf09 | 47 | |
1765d671 | 48 | static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) |
21ce873d | 49 | { |
99e9e52d | 50 | struct davinci_gpio_regs __iomem *g; |
21ce873d | 51 | |
1765d671 | 52 | g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); |
21ce873d KH |
53 | |
54 | return g; | |
55 | } | |
56 | ||
118150f2 | 57 | static int davinci_gpio_irq_setup(struct platform_device *pdev); |
dce1115b DB |
58 | |
59 | /*--------------------------------------------------------------------------*/ | |
60 | ||
5b3a05ca | 61 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
ba4a984e CC |
62 | static inline int __davinci_direction(struct gpio_chip *chip, |
63 | unsigned offset, bool out, int value) | |
3d9edf09 | 64 | { |
72a1ca2c | 65 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
99e9e52d | 66 | struct davinci_gpio_regs __iomem *g = d->regs; |
b27b6d03 | 67 | unsigned long flags; |
dce1115b | 68 | u32 temp; |
ba4a984e | 69 | u32 mask = 1 << offset; |
3d9edf09 | 70 | |
b27b6d03 | 71 | spin_lock_irqsave(&d->lock, flags); |
388291c3 | 72 | temp = readl_relaxed(&g->dir); |
ba4a984e CC |
73 | if (out) { |
74 | temp &= ~mask; | |
388291c3 | 75 | writel_relaxed(mask, value ? &g->set_data : &g->clr_data); |
ba4a984e CC |
76 | } else { |
77 | temp |= mask; | |
78 | } | |
388291c3 | 79 | writel_relaxed(temp, &g->dir); |
b27b6d03 | 80 | spin_unlock_irqrestore(&d->lock, flags); |
3d9edf09 | 81 | |
dce1115b DB |
82 | return 0; |
83 | } | |
3d9edf09 | 84 | |
ba4a984e CC |
85 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
86 | { | |
87 | return __davinci_direction(chip, offset, false, 0); | |
88 | } | |
89 | ||
90 | static int | |
91 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
92 | { | |
93 | return __davinci_direction(chip, offset, true, value); | |
94 | } | |
95 | ||
3d9edf09 VB |
96 | /* |
97 | * Read the pin's value (works even if it's set up as output); | |
98 | * returns zero/nonzero. | |
99 | * | |
100 | * Note that changes are synched to the GPIO clock, so reading values back | |
101 | * right after you've set them may give old values. | |
102 | */ | |
dce1115b | 103 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 104 | { |
72a1ca2c | 105 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
99e9e52d | 106 | struct davinci_gpio_regs __iomem *g = d->regs; |
3d9edf09 | 107 | |
5b8d8fb0 | 108 | return !!((1 << offset) & readl_relaxed(&g->in_data)); |
3d9edf09 | 109 | } |
3d9edf09 | 110 | |
dce1115b DB |
111 | /* |
112 | * Assuming the pin is muxed as a gpio output, set its output value. | |
113 | */ | |
114 | static void | |
115 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 116 | { |
72a1ca2c | 117 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
99e9e52d | 118 | struct davinci_gpio_regs __iomem *g = d->regs; |
3d9edf09 | 119 | |
388291c3 | 120 | writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data); |
dce1115b DB |
121 | } |
122 | ||
c770844c KS |
123 | static struct davinci_gpio_platform_data * |
124 | davinci_gpio_get_pdata(struct platform_device *pdev) | |
125 | { | |
126 | struct device_node *dn = pdev->dev.of_node; | |
127 | struct davinci_gpio_platform_data *pdata; | |
128 | int ret; | |
129 | u32 val; | |
130 | ||
131 | if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) | |
ab128afc | 132 | return dev_get_platdata(&pdev->dev); |
c770844c KS |
133 | |
134 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
135 | if (!pdata) | |
136 | return NULL; | |
137 | ||
138 | ret = of_property_read_u32(dn, "ti,ngpio", &val); | |
139 | if (ret) | |
140 | goto of_err; | |
141 | ||
142 | pdata->ngpio = val; | |
143 | ||
144 | ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); | |
145 | if (ret) | |
146 | goto of_err; | |
147 | ||
148 | pdata->gpio_unbanked = val; | |
149 | ||
150 | return pdata; | |
151 | ||
152 | of_err: | |
153 | dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); | |
154 | return NULL; | |
155 | } | |
156 | ||
758afe42 AH |
157 | #ifdef CONFIG_OF_GPIO |
158 | static int davinci_gpio_of_xlate(struct gpio_chip *gc, | |
159 | const struct of_phandle_args *gpiospec, | |
160 | u32 *flags) | |
161 | { | |
58383c78 LW |
162 | struct davinci_gpio_controller *chips = dev_get_drvdata(gc->parent); |
163 | struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->parent); | |
758afe42 AH |
164 | |
165 | if (gpiospec->args[0] > pdata->ngpio) | |
166 | return -EINVAL; | |
167 | ||
168 | if (gc != &chips[gpiospec->args[0] / 32].chip) | |
169 | return -EINVAL; | |
170 | ||
171 | if (flags) | |
172 | *flags = gpiospec->args[1]; | |
173 | ||
174 | return gpiospec->args[0] % 32; | |
175 | } | |
176 | #endif | |
177 | ||
118150f2 | 178 | static int davinci_gpio_probe(struct platform_device *pdev) |
dce1115b DB |
179 | { |
180 | int i, base; | |
6ec9249a | 181 | unsigned ngpio, nbank; |
118150f2 KS |
182 | struct davinci_gpio_controller *chips; |
183 | struct davinci_gpio_platform_data *pdata; | |
184 | struct davinci_gpio_regs __iomem *regs; | |
185 | struct device *dev = &pdev->dev; | |
186 | struct resource *res; | |
e0275034 | 187 | char label[MAX_LABEL_SIZE]; |
118150f2 | 188 | |
c770844c | 189 | pdata = davinci_gpio_get_pdata(pdev); |
118150f2 KS |
190 | if (!pdata) { |
191 | dev_err(dev, "No platform data found\n"); | |
192 | return -EINVAL; | |
193 | } | |
686b634a | 194 | |
c770844c KS |
195 | dev->platform_data = pdata; |
196 | ||
a994955c MG |
197 | /* |
198 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
199 | * and "ngpio" is one more than the largest zero-based |
200 | * bit index that's valid. | |
201 | */ | |
118150f2 | 202 | ngpio = pdata->ngpio; |
a994955c | 203 | if (ngpio == 0) { |
118150f2 | 204 | dev_err(dev, "How many GPIOs?\n"); |
474dad54 DB |
205 | return -EINVAL; |
206 | } | |
207 | ||
c21d500b GS |
208 | if (WARN_ON(ARCH_NR_GPIOS < ngpio)) |
209 | ngpio = ARCH_NR_GPIOS; | |
474dad54 | 210 | |
6ec9249a | 211 | nbank = DIV_ROUND_UP(ngpio, 32); |
118150f2 | 212 | chips = devm_kzalloc(dev, |
6ec9249a | 213 | nbank * sizeof(struct davinci_gpio_controller), |
118150f2 | 214 | GFP_KERNEL); |
9ea9363c | 215 | if (!chips) |
b8d44293 | 216 | return -ENOMEM; |
118150f2 KS |
217 | |
218 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
118150f2 KS |
219 | gpio_base = devm_ioremap_resource(dev, res); |
220 | if (IS_ERR(gpio_base)) | |
221 | return PTR_ERR(gpio_base); | |
b8d44293 | 222 | |
474dad54 | 223 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { |
e0275034 AH |
224 | snprintf(label, MAX_LABEL_SIZE, "davinci_gpio.%d", i); |
225 | chips[i].chip.label = devm_kstrdup(dev, label, GFP_KERNEL); | |
226 | if (!chips[i].chip.label) | |
227 | return -ENOMEM; | |
dce1115b DB |
228 | |
229 | chips[i].chip.direction_input = davinci_direction_in; | |
230 | chips[i].chip.get = davinci_gpio_get; | |
231 | chips[i].chip.direction_output = davinci_direction_out; | |
232 | chips[i].chip.set = davinci_gpio_set; | |
233 | ||
234 | chips[i].chip.base = base; | |
474dad54 | 235 | chips[i].chip.ngpio = ngpio - base; |
dce1115b DB |
236 | if (chips[i].chip.ngpio > 32) |
237 | chips[i].chip.ngpio = 32; | |
238 | ||
c770844c | 239 | #ifdef CONFIG_OF_GPIO |
758afe42 AH |
240 | chips[i].chip.of_gpio_n_cells = 2; |
241 | chips[i].chip.of_xlate = davinci_gpio_of_xlate; | |
6ddbaed3 | 242 | chips[i].chip.parent = dev; |
c770844c KS |
243 | chips[i].chip.of_node = dev->of_node; |
244 | #endif | |
b27b6d03 CC |
245 | spin_lock_init(&chips[i].lock); |
246 | ||
8f7cf8c6 | 247 | regs = gpio_base + offset_array[i]; |
d6f434e8 NK |
248 | if (!regs) |
249 | return -ENXIO; | |
c12f415a | 250 | chips[i].regs = regs; |
dce1115b | 251 | |
72a1ca2c | 252 | gpiochip_add_data(&chips[i].chip, &chips[i]); |
dce1115b | 253 | } |
3d9edf09 | 254 | |
118150f2 KS |
255 | platform_set_drvdata(pdev, chips); |
256 | davinci_gpio_irq_setup(pdev); | |
3d9edf09 VB |
257 | return 0; |
258 | } | |
3d9edf09 | 259 | |
dce1115b | 260 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
261 | /* |
262 | * We expect irqs will normally be set up as input pins, but they can also be | |
263 | * used as output pins ... which is convenient for testing. | |
264 | * | |
474dad54 | 265 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 266 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 267 | * |
474dad54 | 268 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
269 | * serve as EDMA event triggers. |
270 | */ | |
271 | ||
23265442 | 272 | static void gpio_irq_disable(struct irq_data *d) |
3d9edf09 | 273 | { |
1765d671 | 274 | struct davinci_gpio_regs __iomem *g = irq2regs(d); |
6845664a | 275 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
3d9edf09 | 276 | |
388291c3 LP |
277 | writel_relaxed(mask, &g->clr_falling); |
278 | writel_relaxed(mask, &g->clr_rising); | |
3d9edf09 VB |
279 | } |
280 | ||
23265442 | 281 | static void gpio_irq_enable(struct irq_data *d) |
3d9edf09 | 282 | { |
1765d671 | 283 | struct davinci_gpio_regs __iomem *g = irq2regs(d); |
6845664a | 284 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
5093aec8 | 285 | unsigned status = irqd_get_trigger_type(d); |
3d9edf09 | 286 | |
df4aab46 DB |
287 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
288 | if (!status) | |
289 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
290 | ||
291 | if (status & IRQ_TYPE_EDGE_FALLING) | |
388291c3 | 292 | writel_relaxed(mask, &g->set_falling); |
df4aab46 | 293 | if (status & IRQ_TYPE_EDGE_RISING) |
388291c3 | 294 | writel_relaxed(mask, &g->set_rising); |
3d9edf09 VB |
295 | } |
296 | ||
23265442 | 297 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
3d9edf09 | 298 | { |
3d9edf09 VB |
299 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
300 | return -EINVAL; | |
301 | ||
3d9edf09 VB |
302 | return 0; |
303 | } | |
304 | ||
305 | static struct irq_chip gpio_irqchip = { | |
306 | .name = "GPIO", | |
23265442 LB |
307 | .irq_enable = gpio_irq_enable, |
308 | .irq_disable = gpio_irq_disable, | |
309 | .irq_set_type = gpio_irq_type, | |
5093aec8 | 310 | .flags = IRQCHIP_SET_TYPE_MASKED, |
3d9edf09 VB |
311 | }; |
312 | ||
bd0b9ac4 | 313 | static void gpio_irq_handler(struct irq_desc *desc) |
3d9edf09 | 314 | { |
c3ca1e6f | 315 | unsigned int irq = irq_desc_get_irq(desc); |
74164016 | 316 | struct davinci_gpio_regs __iomem *g; |
3d9edf09 | 317 | u32 mask = 0xffff; |
f299bb95 | 318 | struct davinci_gpio_controller *d; |
3d9edf09 | 319 | |
f299bb95 IY |
320 | d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); |
321 | g = (struct davinci_gpio_regs __iomem *)d->regs; | |
74164016 | 322 | |
3d9edf09 VB |
323 | /* we only care about one bank */ |
324 | if (irq & 1) | |
325 | mask <<= 16; | |
326 | ||
327 | /* temporarily mask (level sensitive) parent IRQ */ | |
0d978eb7 | 328 | chained_irq_enter(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
329 | while (1) { |
330 | u32 status; | |
9211ff31 | 331 | int bit; |
3d9edf09 VB |
332 | |
333 | /* ack any irqs */ | |
388291c3 | 334 | status = readl_relaxed(&g->intstat) & mask; |
3d9edf09 VB |
335 | if (!status) |
336 | break; | |
388291c3 | 337 | writel_relaxed(status, &g->intstat); |
3d9edf09 VB |
338 | |
339 | /* now demux them to the right lowlevel handler */ | |
f299bb95 | 340 | |
3d9edf09 | 341 | while (status) { |
9211ff31 LP |
342 | bit = __ffs(status); |
343 | status &= ~BIT(bit); | |
344 | generic_handle_irq( | |
345 | irq_find_mapping(d->irq_domain, | |
346 | d->chip.base + bit)); | |
3d9edf09 VB |
347 | } |
348 | } | |
0d978eb7 | 349 | chained_irq_exit(irq_desc_get_chip(desc), desc); |
3d9edf09 VB |
350 | /* now it may re-trigger */ |
351 | } | |
352 | ||
7a36071e DB |
353 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
354 | { | |
72a1ca2c | 355 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
7a36071e | 356 | |
6075a8b2 GS |
357 | if (d->irq_domain) |
358 | return irq_create_mapping(d->irq_domain, d->chip.base + offset); | |
359 | else | |
360 | return -ENXIO; | |
7a36071e DB |
361 | } |
362 | ||
363 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
364 | { | |
72a1ca2c | 365 | struct davinci_gpio_controller *d = gpiochip_get_data(chip); |
7a36071e | 366 | |
131a10a3 PA |
367 | /* |
368 | * NOTE: we assume for now that only irqs in the first gpio_chip | |
7a36071e DB |
369 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
370 | */ | |
34af1ab4 | 371 | if (offset < d->gpio_unbanked) |
118150f2 | 372 | return d->gpio_irq + offset; |
7a36071e DB |
373 | else |
374 | return -ENODEV; | |
375 | } | |
376 | ||
ab2dde99 | 377 | static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
7a36071e | 378 | { |
ab2dde99 SN |
379 | struct davinci_gpio_controller *d; |
380 | struct davinci_gpio_regs __iomem *g; | |
ab2dde99 SN |
381 | u32 mask; |
382 | ||
c16edb8b | 383 | d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); |
ab2dde99 | 384 | g = (struct davinci_gpio_regs __iomem *)d->regs; |
118150f2 | 385 | mask = __gpio_mask(data->irq - d->gpio_irq); |
7a36071e DB |
386 | |
387 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
388 | return -EINVAL; | |
389 | ||
388291c3 | 390 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
7a36071e | 391 | ? &g->set_falling : &g->clr_falling); |
388291c3 | 392 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
7a36071e DB |
393 | ? &g->set_rising : &g->clr_rising); |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
9211ff31 LP |
398 | static int |
399 | davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
400 | irq_hw_number_t hw) | |
401 | { | |
8f7cf8c6 K |
402 | struct davinci_gpio_controller *chips = |
403 | (struct davinci_gpio_controller *)d->host_data; | |
404 | struct davinci_gpio_regs __iomem *g = chips[hw / 32].regs; | |
9211ff31 LP |
405 | |
406 | irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, | |
407 | "davinci_gpio"); | |
408 | irq_set_irq_type(irq, IRQ_TYPE_NONE); | |
409 | irq_set_chip_data(irq, (__force void *)g); | |
410 | irq_set_handler_data(irq, (void *)__gpio_mask(hw)); | |
9211ff31 LP |
411 | |
412 | return 0; | |
413 | } | |
414 | ||
415 | static const struct irq_domain_ops davinci_gpio_irq_ops = { | |
416 | .map = davinci_gpio_irq_map, | |
417 | .xlate = irq_domain_xlate_onetwocell, | |
418 | }; | |
419 | ||
0c6feb07 GS |
420 | static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) |
421 | { | |
422 | static struct irq_chip_type gpio_unbanked; | |
423 | ||
ccdbddfe | 424 | gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq)); |
0c6feb07 GS |
425 | |
426 | return &gpio_unbanked.chip; | |
427 | }; | |
428 | ||
429 | static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) | |
430 | { | |
431 | static struct irq_chip gpio_unbanked; | |
432 | ||
433 | gpio_unbanked = *irq_get_chip(irq); | |
434 | return &gpio_unbanked; | |
435 | }; | |
436 | ||
437 | static const struct of_device_id davinci_gpio_ids[]; | |
438 | ||
3d9edf09 | 439 | /* |
474dad54 DB |
440 | * NOTE: for suspend/resume, probably best to make a platform_device with |
441 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
442 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
443 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 444 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
445 | */ |
446 | ||
118150f2 | 447 | static int davinci_gpio_irq_setup(struct platform_device *pdev) |
3d9edf09 | 448 | { |
58c0f5aa AS |
449 | unsigned gpio, bank; |
450 | int irq; | |
3d9edf09 | 451 | struct clk *clk; |
474dad54 | 452 | u32 binten = 0; |
a994955c | 453 | unsigned ngpio, bank_irq; |
118150f2 KS |
454 | struct device *dev = &pdev->dev; |
455 | struct resource *res; | |
456 | struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); | |
457 | struct davinci_gpio_platform_data *pdata = dev->platform_data; | |
458 | struct davinci_gpio_regs __iomem *g; | |
6075a8b2 | 459 | struct irq_domain *irq_domain = NULL; |
0c6feb07 GS |
460 | const struct of_device_id *match; |
461 | struct irq_chip *irq_chip; | |
462 | gpio_get_irq_chip_cb_t gpio_get_irq_chip; | |
463 | ||
464 | /* | |
465 | * Use davinci_gpio_get_irq_chip by default to handle non DT cases | |
466 | */ | |
467 | gpio_get_irq_chip = davinci_gpio_get_irq_chip; | |
468 | match = of_match_device(of_match_ptr(davinci_gpio_ids), | |
469 | dev); | |
470 | if (match) | |
471 | gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; | |
a994955c | 472 | |
118150f2 KS |
473 | ngpio = pdata->ngpio; |
474 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
475 | if (!res) { | |
476 | dev_err(dev, "Invalid IRQ resource\n"); | |
477 | return -EBUSY; | |
478 | } | |
474dad54 | 479 | |
118150f2 KS |
480 | bank_irq = res->start; |
481 | ||
482 | if (!bank_irq) { | |
483 | dev_err(dev, "Invalid IRQ resource\n"); | |
484 | return -ENODEV; | |
474dad54 | 485 | } |
3d9edf09 | 486 | |
118150f2 | 487 | clk = devm_clk_get(dev, "gpio"); |
3d9edf09 VB |
488 | if (IS_ERR(clk)) { |
489 | printk(KERN_ERR "Error %ld getting gpio clock?\n", | |
490 | PTR_ERR(clk)); | |
474dad54 | 491 | return PTR_ERR(clk); |
3d9edf09 | 492 | } |
ce6b658d | 493 | clk_prepare_enable(clk); |
3d9edf09 | 494 | |
6075a8b2 GS |
495 | if (!pdata->gpio_unbanked) { |
496 | irq = irq_alloc_descs(-1, 0, ngpio, 0); | |
497 | if (irq < 0) { | |
498 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
499 | return irq; | |
500 | } | |
9211ff31 | 501 | |
310a7e60 | 502 | irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, |
6075a8b2 GS |
503 | &davinci_gpio_irq_ops, |
504 | chips); | |
505 | if (!irq_domain) { | |
506 | dev_err(dev, "Couldn't register an IRQ domain\n"); | |
507 | return -ENODEV; | |
508 | } | |
9211ff31 LP |
509 | } |
510 | ||
131a10a3 PA |
511 | /* |
512 | * Arrange gpio_to_irq() support, handling either direct IRQs or | |
7a36071e DB |
513 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
514 | * IRQs, while the others use banked IRQs, would need some setup | |
515 | * tweaks to recognize hardware which can do that. | |
516 | */ | |
517 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { | |
518 | chips[bank].chip.to_irq = gpio_to_irq_banked; | |
6075a8b2 | 519 | chips[bank].irq_domain = irq_domain; |
7a36071e DB |
520 | } |
521 | ||
522 | /* | |
523 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
524 | * controller only handling trigger modes. We currently assume no | |
525 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
526 | */ | |
118150f2 | 527 | if (pdata->gpio_unbanked) { |
7a36071e DB |
528 | /* pass "bank 0" GPIO IRQs to AINTC */ |
529 | chips[0].chip.to_irq = gpio_to_irq_unbanked; | |
34af1ab4 LP |
530 | chips[0].gpio_irq = bank_irq; |
531 | chips[0].gpio_unbanked = pdata->gpio_unbanked; | |
3685bbce | 532 | binten = GENMASK(pdata->gpio_unbanked / 16, 0); |
7a36071e DB |
533 | |
534 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
535 | irq = bank_irq; | |
0c6feb07 GS |
536 | irq_chip = gpio_get_irq_chip(irq); |
537 | irq_chip->name = "GPIO-AINTC"; | |
538 | irq_chip->irq_set_type = gpio_irq_type_unbanked; | |
7a36071e DB |
539 | |
540 | /* default trigger: both edges */ | |
8f7cf8c6 | 541 | g = chips[0].regs; |
388291c3 LP |
542 | writel_relaxed(~0, &g->set_falling); |
543 | writel_relaxed(~0, &g->set_rising); | |
7a36071e DB |
544 | |
545 | /* set the direct IRQs up to use that irqchip */ | |
118150f2 | 546 | for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { |
0c6feb07 | 547 | irq_set_chip(irq, irq_chip); |
ab2dde99 | 548 | irq_set_handler_data(irq, &chips[gpio / 32]); |
5093aec8 | 549 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); |
7a36071e DB |
550 | } |
551 | ||
552 | goto done; | |
553 | } | |
554 | ||
555 | /* | |
556 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
557 | * then chain through our own handler. | |
558 | */ | |
9211ff31 | 559 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) { |
8f7cf8c6 K |
560 | /* disabled by default, enabled only as needed |
561 | * There are register sets for 32 GPIOs. 2 banks of 16 | |
562 | * GPIOs are covered by each set of registers hence divide by 2 | |
563 | */ | |
564 | g = chips[bank / 2].regs; | |
388291c3 LP |
565 | writel_relaxed(~0, &g->clr_falling); |
566 | writel_relaxed(~0, &g->clr_rising); | |
3d9edf09 | 567 | |
f299bb95 IY |
568 | /* |
569 | * Each chip handles 32 gpios, and each irq bank consists of 16 | |
570 | * gpio irqs. Pass the irq bank's corresponding controller to | |
571 | * the chained irq handler. | |
572 | */ | |
bdac2b6d TG |
573 | irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler, |
574 | &chips[gpio / 32]); | |
3d9edf09 | 575 | |
474dad54 | 576 | binten |= BIT(bank); |
3d9edf09 VB |
577 | } |
578 | ||
7a36071e | 579 | done: |
131a10a3 PA |
580 | /* |
581 | * BINTEN -- per-bank interrupt enable. genirq would also let these | |
3d9edf09 VB |
582 | * bits be set/cleared dynamically. |
583 | */ | |
388291c3 | 584 | writel_relaxed(binten, gpio_base + BINTEN); |
3d9edf09 | 585 | |
3d9edf09 VB |
586 | return 0; |
587 | } | |
118150f2 | 588 | |
c770844c KS |
589 | #if IS_ENABLED(CONFIG_OF) |
590 | static const struct of_device_id davinci_gpio_ids[] = { | |
0c6feb07 GS |
591 | { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, |
592 | { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, | |
c770844c KS |
593 | { /* sentinel */ }, |
594 | }; | |
595 | MODULE_DEVICE_TABLE(of, davinci_gpio_ids); | |
596 | #endif | |
597 | ||
118150f2 KS |
598 | static struct platform_driver davinci_gpio_driver = { |
599 | .probe = davinci_gpio_probe, | |
600 | .driver = { | |
c770844c | 601 | .name = "davinci_gpio", |
c770844c | 602 | .of_match_table = of_match_ptr(davinci_gpio_ids), |
118150f2 KS |
603 | }, |
604 | }; | |
605 | ||
606 | /** | |
607 | * GPIO driver registration needs to be done before machine_init functions | |
608 | * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. | |
609 | */ | |
610 | static int __init davinci_gpio_drv_reg(void) | |
611 | { | |
612 | return platform_driver_register(&davinci_gpio_driver); | |
613 | } | |
614 | postcore_initcall(davinci_gpio_drv_reg); |