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Commit | Line | Data |
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3d9edf09 VB |
1 | /* |
2 | * TI DaVinci GPIO Support | |
3 | * | |
dce1115b | 4 | * Copyright (c) 2006-2007 David Brownell |
3d9edf09 VB |
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
2f8163ba | 12 | #include <linux/gpio.h> |
3d9edf09 VB |
13 | #include <linux/errno.h> |
14 | #include <linux/kernel.h> | |
3d9edf09 VB |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
118150f2 | 18 | #include <linux/irq.h> |
9211ff31 | 19 | #include <linux/irqdomain.h> |
118150f2 KS |
20 | #include <linux/platform_device.h> |
21 | #include <linux/platform_data/gpio-davinci.h> | |
3d9edf09 | 22 | |
c12f415a CC |
23 | struct davinci_gpio_regs { |
24 | u32 dir; | |
25 | u32 out_data; | |
26 | u32 set_data; | |
27 | u32 clr_data; | |
28 | u32 in_data; | |
29 | u32 set_rising; | |
30 | u32 clr_rising; | |
31 | u32 set_falling; | |
32 | u32 clr_falling; | |
33 | u32 intstat; | |
34 | }; | |
35 | ||
131a10a3 PA |
36 | #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ |
37 | ||
ba4a984e | 38 | #define chip2controller(chip) \ |
99e9e52d | 39 | container_of(chip, struct davinci_gpio_controller, chip) |
ba4a984e | 40 | |
b8d44293 | 41 | static void __iomem *gpio_base; |
3d9edf09 | 42 | |
118150f2 | 43 | static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio) |
3d9edf09 | 44 | { |
c12f415a | 45 | void __iomem *ptr; |
c12f415a CC |
46 | |
47 | if (gpio < 32 * 1) | |
b8d44293 | 48 | ptr = gpio_base + 0x10; |
c12f415a | 49 | else if (gpio < 32 * 2) |
b8d44293 | 50 | ptr = gpio_base + 0x38; |
c12f415a | 51 | else if (gpio < 32 * 3) |
b8d44293 | 52 | ptr = gpio_base + 0x60; |
c12f415a | 53 | else if (gpio < 32 * 4) |
b8d44293 | 54 | ptr = gpio_base + 0x88; |
c12f415a | 55 | else if (gpio < 32 * 5) |
b8d44293 | 56 | ptr = gpio_base + 0xb0; |
c12f415a CC |
57 | else |
58 | ptr = NULL; | |
59 | return ptr; | |
3d9edf09 VB |
60 | } |
61 | ||
99e9e52d | 62 | static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) |
21ce873d | 63 | { |
99e9e52d | 64 | struct davinci_gpio_regs __iomem *g; |
21ce873d | 65 | |
6845664a | 66 | g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); |
21ce873d KH |
67 | |
68 | return g; | |
69 | } | |
70 | ||
118150f2 | 71 | static int davinci_gpio_irq_setup(struct platform_device *pdev); |
dce1115b DB |
72 | |
73 | /*--------------------------------------------------------------------------*/ | |
74 | ||
5b3a05ca | 75 | /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ |
ba4a984e CC |
76 | static inline int __davinci_direction(struct gpio_chip *chip, |
77 | unsigned offset, bool out, int value) | |
3d9edf09 | 78 | { |
99e9e52d CC |
79 | struct davinci_gpio_controller *d = chip2controller(chip); |
80 | struct davinci_gpio_regs __iomem *g = d->regs; | |
b27b6d03 | 81 | unsigned long flags; |
dce1115b | 82 | u32 temp; |
ba4a984e | 83 | u32 mask = 1 << offset; |
3d9edf09 | 84 | |
b27b6d03 | 85 | spin_lock_irqsave(&d->lock, flags); |
388291c3 | 86 | temp = readl_relaxed(&g->dir); |
ba4a984e CC |
87 | if (out) { |
88 | temp &= ~mask; | |
388291c3 | 89 | writel_relaxed(mask, value ? &g->set_data : &g->clr_data); |
ba4a984e CC |
90 | } else { |
91 | temp |= mask; | |
92 | } | |
388291c3 | 93 | writel_relaxed(temp, &g->dir); |
b27b6d03 | 94 | spin_unlock_irqrestore(&d->lock, flags); |
3d9edf09 | 95 | |
dce1115b DB |
96 | return 0; |
97 | } | |
3d9edf09 | 98 | |
ba4a984e CC |
99 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
100 | { | |
101 | return __davinci_direction(chip, offset, false, 0); | |
102 | } | |
103 | ||
104 | static int | |
105 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | |
106 | { | |
107 | return __davinci_direction(chip, offset, true, value); | |
108 | } | |
109 | ||
3d9edf09 VB |
110 | /* |
111 | * Read the pin's value (works even if it's set up as output); | |
112 | * returns zero/nonzero. | |
113 | * | |
114 | * Note that changes are synched to the GPIO clock, so reading values back | |
115 | * right after you've set them may give old values. | |
116 | */ | |
dce1115b | 117 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
3d9edf09 | 118 | { |
99e9e52d CC |
119 | struct davinci_gpio_controller *d = chip2controller(chip); |
120 | struct davinci_gpio_regs __iomem *g = d->regs; | |
3d9edf09 | 121 | |
388291c3 | 122 | return (1 << offset) & readl_relaxed(&g->in_data); |
3d9edf09 | 123 | } |
3d9edf09 | 124 | |
dce1115b DB |
125 | /* |
126 | * Assuming the pin is muxed as a gpio output, set its output value. | |
127 | */ | |
128 | static void | |
129 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
3d9edf09 | 130 | { |
99e9e52d CC |
131 | struct davinci_gpio_controller *d = chip2controller(chip); |
132 | struct davinci_gpio_regs __iomem *g = d->regs; | |
3d9edf09 | 133 | |
388291c3 | 134 | writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data); |
dce1115b DB |
135 | } |
136 | ||
118150f2 | 137 | static int davinci_gpio_probe(struct platform_device *pdev) |
dce1115b DB |
138 | { |
139 | int i, base; | |
a994955c | 140 | unsigned ngpio; |
118150f2 KS |
141 | struct davinci_gpio_controller *chips; |
142 | struct davinci_gpio_platform_data *pdata; | |
143 | struct davinci_gpio_regs __iomem *regs; | |
144 | struct device *dev = &pdev->dev; | |
145 | struct resource *res; | |
146 | ||
147 | pdata = dev->platform_data; | |
148 | if (!pdata) { | |
149 | dev_err(dev, "No platform data found\n"); | |
150 | return -EINVAL; | |
151 | } | |
686b634a | 152 | |
a994955c MG |
153 | /* |
154 | * The gpio banks conceptually expose a segmented bitmap, | |
474dad54 DB |
155 | * and "ngpio" is one more than the largest zero-based |
156 | * bit index that's valid. | |
157 | */ | |
118150f2 | 158 | ngpio = pdata->ngpio; |
a994955c | 159 | if (ngpio == 0) { |
118150f2 | 160 | dev_err(dev, "How many GPIOs?\n"); |
474dad54 DB |
161 | return -EINVAL; |
162 | } | |
163 | ||
c21d500b GS |
164 | if (WARN_ON(ARCH_NR_GPIOS < ngpio)) |
165 | ngpio = ARCH_NR_GPIOS; | |
474dad54 | 166 | |
118150f2 KS |
167 | chips = devm_kzalloc(dev, |
168 | ngpio * sizeof(struct davinci_gpio_controller), | |
169 | GFP_KERNEL); | |
170 | if (!chips) { | |
171 | dev_err(dev, "Memory allocation failed\n"); | |
b8d44293 | 172 | return -ENOMEM; |
118150f2 KS |
173 | } |
174 | ||
175 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
176 | if (!res) { | |
177 | dev_err(dev, "Invalid memory resource\n"); | |
178 | return -EBUSY; | |
179 | } | |
180 | ||
181 | gpio_base = devm_ioremap_resource(dev, res); | |
182 | if (IS_ERR(gpio_base)) | |
183 | return PTR_ERR(gpio_base); | |
b8d44293 | 184 | |
474dad54 | 185 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { |
dce1115b DB |
186 | chips[i].chip.label = "DaVinci"; |
187 | ||
188 | chips[i].chip.direction_input = davinci_direction_in; | |
189 | chips[i].chip.get = davinci_gpio_get; | |
190 | chips[i].chip.direction_output = davinci_direction_out; | |
191 | chips[i].chip.set = davinci_gpio_set; | |
192 | ||
193 | chips[i].chip.base = base; | |
474dad54 | 194 | chips[i].chip.ngpio = ngpio - base; |
dce1115b DB |
195 | if (chips[i].chip.ngpio > 32) |
196 | chips[i].chip.ngpio = 32; | |
197 | ||
b27b6d03 CC |
198 | spin_lock_init(&chips[i].lock); |
199 | ||
c12f415a CC |
200 | regs = gpio2regs(base); |
201 | chips[i].regs = regs; | |
202 | chips[i].set_data = ®s->set_data; | |
203 | chips[i].clr_data = ®s->clr_data; | |
204 | chips[i].in_data = ®s->in_data; | |
dce1115b DB |
205 | |
206 | gpiochip_add(&chips[i].chip); | |
207 | } | |
3d9edf09 | 208 | |
118150f2 KS |
209 | platform_set_drvdata(pdev, chips); |
210 | davinci_gpio_irq_setup(pdev); | |
3d9edf09 VB |
211 | return 0; |
212 | } | |
3d9edf09 | 213 | |
dce1115b | 214 | /*--------------------------------------------------------------------------*/ |
3d9edf09 VB |
215 | /* |
216 | * We expect irqs will normally be set up as input pins, but they can also be | |
217 | * used as output pins ... which is convenient for testing. | |
218 | * | |
474dad54 | 219 | * NOTE: The first few GPIOs also have direct INTC hookups in addition |
7a36071e | 220 | * to their GPIOBNK0 irq, with a bit less overhead. |
3d9edf09 | 221 | * |
474dad54 | 222 | * All those INTC hookups (direct, plus several IRQ banks) can also |
3d9edf09 VB |
223 | * serve as EDMA event triggers. |
224 | */ | |
225 | ||
23265442 | 226 | static void gpio_irq_disable(struct irq_data *d) |
3d9edf09 | 227 | { |
23265442 | 228 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
6845664a | 229 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
3d9edf09 | 230 | |
388291c3 LP |
231 | writel_relaxed(mask, &g->clr_falling); |
232 | writel_relaxed(mask, &g->clr_rising); | |
3d9edf09 VB |
233 | } |
234 | ||
23265442 | 235 | static void gpio_irq_enable(struct irq_data *d) |
3d9edf09 | 236 | { |
23265442 | 237 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
6845664a | 238 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
5093aec8 | 239 | unsigned status = irqd_get_trigger_type(d); |
3d9edf09 | 240 | |
df4aab46 DB |
241 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
242 | if (!status) | |
243 | status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | |
244 | ||
245 | if (status & IRQ_TYPE_EDGE_FALLING) | |
388291c3 | 246 | writel_relaxed(mask, &g->set_falling); |
df4aab46 | 247 | if (status & IRQ_TYPE_EDGE_RISING) |
388291c3 | 248 | writel_relaxed(mask, &g->set_rising); |
3d9edf09 VB |
249 | } |
250 | ||
23265442 | 251 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
3d9edf09 | 252 | { |
3d9edf09 VB |
253 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
254 | return -EINVAL; | |
255 | ||
3d9edf09 VB |
256 | return 0; |
257 | } | |
258 | ||
259 | static struct irq_chip gpio_irqchip = { | |
260 | .name = "GPIO", | |
23265442 LB |
261 | .irq_enable = gpio_irq_enable, |
262 | .irq_disable = gpio_irq_disable, | |
263 | .irq_set_type = gpio_irq_type, | |
5093aec8 | 264 | .flags = IRQCHIP_SET_TYPE_MASKED, |
3d9edf09 VB |
265 | }; |
266 | ||
267 | static void | |
268 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
269 | { | |
74164016 | 270 | struct davinci_gpio_regs __iomem *g; |
3d9edf09 | 271 | u32 mask = 0xffff; |
f299bb95 | 272 | struct davinci_gpio_controller *d; |
3d9edf09 | 273 | |
f299bb95 IY |
274 | d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); |
275 | g = (struct davinci_gpio_regs __iomem *)d->regs; | |
74164016 | 276 | |
3d9edf09 VB |
277 | /* we only care about one bank */ |
278 | if (irq & 1) | |
279 | mask <<= 16; | |
280 | ||
281 | /* temporarily mask (level sensitive) parent IRQ */ | |
23265442 LB |
282 | desc->irq_data.chip->irq_mask(&desc->irq_data); |
283 | desc->irq_data.chip->irq_ack(&desc->irq_data); | |
3d9edf09 VB |
284 | while (1) { |
285 | u32 status; | |
9211ff31 | 286 | int bit; |
3d9edf09 VB |
287 | |
288 | /* ack any irqs */ | |
388291c3 | 289 | status = readl_relaxed(&g->intstat) & mask; |
3d9edf09 VB |
290 | if (!status) |
291 | break; | |
388291c3 | 292 | writel_relaxed(status, &g->intstat); |
3d9edf09 VB |
293 | |
294 | /* now demux them to the right lowlevel handler */ | |
f299bb95 | 295 | |
3d9edf09 | 296 | while (status) { |
9211ff31 LP |
297 | bit = __ffs(status); |
298 | status &= ~BIT(bit); | |
299 | generic_handle_irq( | |
300 | irq_find_mapping(d->irq_domain, | |
301 | d->chip.base + bit)); | |
3d9edf09 VB |
302 | } |
303 | } | |
23265442 | 304 | desc->irq_data.chip->irq_unmask(&desc->irq_data); |
3d9edf09 VB |
305 | /* now it may re-trigger */ |
306 | } | |
307 | ||
7a36071e DB |
308 | static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) |
309 | { | |
99e9e52d | 310 | struct davinci_gpio_controller *d = chip2controller(chip); |
7a36071e | 311 | |
9211ff31 | 312 | return irq_create_mapping(d->irq_domain, d->chip.base + offset); |
7a36071e DB |
313 | } |
314 | ||
315 | static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |
316 | { | |
118150f2 | 317 | struct davinci_gpio_controller *d = chip2controller(chip); |
7a36071e | 318 | |
131a10a3 PA |
319 | /* |
320 | * NOTE: we assume for now that only irqs in the first gpio_chip | |
7a36071e DB |
321 | * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). |
322 | */ | |
34af1ab4 | 323 | if (offset < d->gpio_unbanked) |
118150f2 | 324 | return d->gpio_irq + offset; |
7a36071e DB |
325 | else |
326 | return -ENODEV; | |
327 | } | |
328 | ||
ab2dde99 | 329 | static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) |
7a36071e | 330 | { |
ab2dde99 SN |
331 | struct davinci_gpio_controller *d; |
332 | struct davinci_gpio_regs __iomem *g; | |
ab2dde99 SN |
333 | u32 mask; |
334 | ||
335 | d = (struct davinci_gpio_controller *)data->handler_data; | |
336 | g = (struct davinci_gpio_regs __iomem *)d->regs; | |
118150f2 | 337 | mask = __gpio_mask(data->irq - d->gpio_irq); |
7a36071e DB |
338 | |
339 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
340 | return -EINVAL; | |
341 | ||
388291c3 | 342 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) |
7a36071e | 343 | ? &g->set_falling : &g->clr_falling); |
388291c3 | 344 | writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) |
7a36071e DB |
345 | ? &g->set_rising : &g->clr_rising); |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
9211ff31 LP |
350 | static int |
351 | davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, | |
352 | irq_hw_number_t hw) | |
353 | { | |
354 | struct davinci_gpio_regs __iomem *g = gpio2regs(hw); | |
355 | ||
356 | irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, | |
357 | "davinci_gpio"); | |
358 | irq_set_irq_type(irq, IRQ_TYPE_NONE); | |
359 | irq_set_chip_data(irq, (__force void *)g); | |
360 | irq_set_handler_data(irq, (void *)__gpio_mask(hw)); | |
361 | set_irq_flags(irq, IRQF_VALID); | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
366 | static const struct irq_domain_ops davinci_gpio_irq_ops = { | |
367 | .map = davinci_gpio_irq_map, | |
368 | .xlate = irq_domain_xlate_onetwocell, | |
369 | }; | |
370 | ||
3d9edf09 | 371 | /* |
474dad54 DB |
372 | * NOTE: for suspend/resume, probably best to make a platform_device with |
373 | * suspend_late/resume_resume calls hooking into results of the set_wake() | |
3d9edf09 VB |
374 | * calls ... so if no gpios are wakeup events the clock can be disabled, |
375 | * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 | |
474dad54 | 376 | * (dm6446) can be set appropriately for GPIOV33 pins. |
3d9edf09 VB |
377 | */ |
378 | ||
118150f2 | 379 | static int davinci_gpio_irq_setup(struct platform_device *pdev) |
3d9edf09 VB |
380 | { |
381 | unsigned gpio, irq, bank; | |
382 | struct clk *clk; | |
474dad54 | 383 | u32 binten = 0; |
a994955c | 384 | unsigned ngpio, bank_irq; |
118150f2 KS |
385 | struct device *dev = &pdev->dev; |
386 | struct resource *res; | |
387 | struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); | |
388 | struct davinci_gpio_platform_data *pdata = dev->platform_data; | |
389 | struct davinci_gpio_regs __iomem *g; | |
9211ff31 | 390 | struct irq_domain *irq_domain; |
a994955c | 391 | |
118150f2 KS |
392 | ngpio = pdata->ngpio; |
393 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
394 | if (!res) { | |
395 | dev_err(dev, "Invalid IRQ resource\n"); | |
396 | return -EBUSY; | |
397 | } | |
474dad54 | 398 | |
118150f2 KS |
399 | bank_irq = res->start; |
400 | ||
401 | if (!bank_irq) { | |
402 | dev_err(dev, "Invalid IRQ resource\n"); | |
403 | return -ENODEV; | |
474dad54 | 404 | } |
3d9edf09 | 405 | |
118150f2 | 406 | clk = devm_clk_get(dev, "gpio"); |
3d9edf09 VB |
407 | if (IS_ERR(clk)) { |
408 | printk(KERN_ERR "Error %ld getting gpio clock?\n", | |
409 | PTR_ERR(clk)); | |
474dad54 | 410 | return PTR_ERR(clk); |
3d9edf09 | 411 | } |
ce6b658d | 412 | clk_prepare_enable(clk); |
3d9edf09 | 413 | |
9211ff31 LP |
414 | irq = irq_alloc_descs(-1, 0, ngpio, 0); |
415 | if (irq < 0) { | |
416 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
417 | return irq; | |
418 | } | |
419 | ||
420 | irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0, | |
421 | &davinci_gpio_irq_ops, | |
422 | chips); | |
423 | if (!irq_domain) { | |
424 | dev_err(dev, "Couldn't register an IRQ domain\n"); | |
425 | return -ENODEV; | |
426 | } | |
427 | ||
131a10a3 PA |
428 | /* |
429 | * Arrange gpio_to_irq() support, handling either direct IRQs or | |
7a36071e DB |
430 | * banked IRQs. Having GPIOs in the first GPIO bank use direct |
431 | * IRQs, while the others use banked IRQs, would need some setup | |
432 | * tweaks to recognize hardware which can do that. | |
433 | */ | |
434 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { | |
435 | chips[bank].chip.to_irq = gpio_to_irq_banked; | |
9211ff31 LP |
436 | if (!pdata->gpio_unbanked) |
437 | chips[bank].irq_domain = irq_domain; | |
7a36071e DB |
438 | } |
439 | ||
440 | /* | |
441 | * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO | |
442 | * controller only handling trigger modes. We currently assume no | |
443 | * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. | |
444 | */ | |
118150f2 | 445 | if (pdata->gpio_unbanked) { |
81b279d8 | 446 | static struct irq_chip_type gpio_unbanked; |
7a36071e DB |
447 | |
448 | /* pass "bank 0" GPIO IRQs to AINTC */ | |
449 | chips[0].chip.to_irq = gpio_to_irq_unbanked; | |
34af1ab4 LP |
450 | chips[0].gpio_irq = bank_irq; |
451 | chips[0].gpio_unbanked = pdata->gpio_unbanked; | |
7a36071e DB |
452 | binten = BIT(0); |
453 | ||
454 | /* AINTC handles mask/unmask; GPIO handles triggering */ | |
455 | irq = bank_irq; | |
81b279d8 SN |
456 | gpio_unbanked = *container_of(irq_get_chip(irq), |
457 | struct irq_chip_type, chip); | |
458 | gpio_unbanked.chip.name = "GPIO-AINTC"; | |
459 | gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked; | |
7a36071e DB |
460 | |
461 | /* default trigger: both edges */ | |
99e9e52d | 462 | g = gpio2regs(0); |
388291c3 LP |
463 | writel_relaxed(~0, &g->set_falling); |
464 | writel_relaxed(~0, &g->set_rising); | |
7a36071e DB |
465 | |
466 | /* set the direct IRQs up to use that irqchip */ | |
118150f2 | 467 | for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { |
81b279d8 | 468 | irq_set_chip(irq, &gpio_unbanked.chip); |
ab2dde99 | 469 | irq_set_handler_data(irq, &chips[gpio / 32]); |
5093aec8 | 470 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); |
7a36071e DB |
471 | } |
472 | ||
473 | goto done; | |
474 | } | |
475 | ||
476 | /* | |
477 | * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we | |
478 | * then chain through our own handler. | |
479 | */ | |
9211ff31 | 480 | for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) { |
7a36071e | 481 | /* disabled by default, enabled only as needed */ |
99e9e52d | 482 | g = gpio2regs(gpio); |
388291c3 LP |
483 | writel_relaxed(~0, &g->clr_falling); |
484 | writel_relaxed(~0, &g->clr_rising); | |
3d9edf09 VB |
485 | |
486 | /* set up all irqs in this bank */ | |
6845664a | 487 | irq_set_chained_handler(bank_irq, gpio_irq_handler); |
f299bb95 IY |
488 | |
489 | /* | |
490 | * Each chip handles 32 gpios, and each irq bank consists of 16 | |
491 | * gpio irqs. Pass the irq bank's corresponding controller to | |
492 | * the chained irq handler. | |
493 | */ | |
494 | irq_set_handler_data(bank_irq, &chips[gpio / 32]); | |
3d9edf09 | 495 | |
474dad54 | 496 | binten |= BIT(bank); |
3d9edf09 VB |
497 | } |
498 | ||
7a36071e | 499 | done: |
131a10a3 PA |
500 | /* |
501 | * BINTEN -- per-bank interrupt enable. genirq would also let these | |
3d9edf09 VB |
502 | * bits be set/cleared dynamically. |
503 | */ | |
388291c3 | 504 | writel_relaxed(binten, gpio_base + BINTEN); |
3d9edf09 | 505 | |
3d9edf09 VB |
506 | return 0; |
507 | } | |
118150f2 KS |
508 | |
509 | static struct platform_driver davinci_gpio_driver = { | |
510 | .probe = davinci_gpio_probe, | |
511 | .driver = { | |
512 | .name = "davinci_gpio", | |
513 | .owner = THIS_MODULE, | |
514 | }, | |
515 | }; | |
516 | ||
517 | /** | |
518 | * GPIO driver registration needs to be done before machine_init functions | |
519 | * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. | |
520 | */ | |
521 | static int __init davinci_gpio_drv_reg(void) | |
522 | { | |
523 | return platform_driver_register(&davinci_gpio_driver); | |
524 | } | |
525 | postcore_initcall(davinci_gpio_drv_reg); |