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Commit | Line | Data |
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7779b345 JI |
1 | /* |
2 | * Copyright (c) 2011 Jamie Iles | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * All enquiries to support@picochip.com | |
9 | */ | |
e6cb3486 | 10 | #include <linux/acpi.h> |
0f4630f3 LW |
11 | #include <linux/gpio/driver.h> |
12 | /* FIXME: for gpio_get_value(), replace this with direct register read */ | |
13 | #include <linux/gpio.h> | |
7779b345 JI |
14 | #include <linux/err.h> |
15 | #include <linux/init.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/ioport.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/irqdomain.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
a72b8c4a | 24 | #include <linux/of_device.h> |
7779b345 JI |
25 | #include <linux/of_irq.h> |
26 | #include <linux/platform_device.h> | |
4ba8cfa7 | 27 | #include <linux/property.h> |
07901a94 | 28 | #include <linux/reset.h> |
7779b345 | 29 | #include <linux/spinlock.h> |
3d2613c4 WC |
30 | #include <linux/platform_data/gpio-dwapb.h> |
31 | #include <linux/slab.h> | |
7779b345 | 32 | |
e6cb3486 JQ |
33 | #include "gpiolib.h" |
34 | ||
7779b345 JI |
35 | #define GPIO_SWPORTA_DR 0x00 |
36 | #define GPIO_SWPORTA_DDR 0x04 | |
37 | #define GPIO_SWPORTB_DR 0x0c | |
38 | #define GPIO_SWPORTB_DDR 0x10 | |
39 | #define GPIO_SWPORTC_DR 0x18 | |
40 | #define GPIO_SWPORTC_DDR 0x1c | |
41 | #define GPIO_SWPORTD_DR 0x24 | |
42 | #define GPIO_SWPORTD_DDR 0x28 | |
43 | #define GPIO_INTEN 0x30 | |
44 | #define GPIO_INTMASK 0x34 | |
45 | #define GPIO_INTTYPE_LEVEL 0x38 | |
46 | #define GPIO_INT_POLARITY 0x3c | |
47 | #define GPIO_INTSTATUS 0x40 | |
5d60d9ef | 48 | #define GPIO_PORTA_DEBOUNCE 0x48 |
7779b345 JI |
49 | #define GPIO_PORTA_EOI 0x4c |
50 | #define GPIO_EXT_PORTA 0x50 | |
51 | #define GPIO_EXT_PORTB 0x54 | |
52 | #define GPIO_EXT_PORTC 0x58 | |
53 | #define GPIO_EXT_PORTD 0x5c | |
54 | ||
55 | #define DWAPB_MAX_PORTS 4 | |
56 | #define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA) | |
57 | #define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR) | |
58 | #define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR) | |
59 | ||
a72b8c4a HT |
60 | #define GPIO_REG_OFFSET_V2 1 |
61 | ||
62 | #define GPIO_INTMASK_V2 0x44 | |
63 | #define GPIO_INTTYPE_LEVEL_V2 0x34 | |
64 | #define GPIO_INT_POLARITY_V2 0x38 | |
65 | #define GPIO_INTSTATUS_V2 0x3c | |
66 | #define GPIO_PORTA_EOI_V2 0x40 | |
67 | ||
7779b345 JI |
68 | struct dwapb_gpio; |
69 | ||
1e960dbb WC |
70 | #ifdef CONFIG_PM_SLEEP |
71 | /* Store GPIO context across system-wide suspend/resume transitions */ | |
72 | struct dwapb_context { | |
73 | u32 data; | |
74 | u32 dir; | |
75 | u32 ext; | |
76 | u32 int_en; | |
77 | u32 int_mask; | |
78 | u32 int_type; | |
79 | u32 int_pol; | |
80 | u32 int_deb; | |
6437c7ba | 81 | u32 wake_en; |
1e960dbb WC |
82 | }; |
83 | #endif | |
84 | ||
7779b345 | 85 | struct dwapb_gpio_port { |
0f4630f3 | 86 | struct gpio_chip gc; |
7779b345 JI |
87 | bool is_registered; |
88 | struct dwapb_gpio *gpio; | |
1e960dbb WC |
89 | #ifdef CONFIG_PM_SLEEP |
90 | struct dwapb_context *ctx; | |
91 | #endif | |
92 | unsigned int idx; | |
7779b345 JI |
93 | }; |
94 | ||
95 | struct dwapb_gpio { | |
96 | struct device *dev; | |
97 | void __iomem *regs; | |
98 | struct dwapb_gpio_port *ports; | |
99 | unsigned int nr_ports; | |
100 | struct irq_domain *domain; | |
a72b8c4a | 101 | unsigned int flags; |
07901a94 | 102 | struct reset_control *rst; |
7779b345 JI |
103 | }; |
104 | ||
a72b8c4a HT |
105 | static inline u32 gpio_reg_v2_convert(unsigned int offset) |
106 | { | |
107 | switch (offset) { | |
108 | case GPIO_INTMASK: | |
109 | return GPIO_INTMASK_V2; | |
110 | case GPIO_INTTYPE_LEVEL: | |
111 | return GPIO_INTTYPE_LEVEL_V2; | |
112 | case GPIO_INT_POLARITY: | |
113 | return GPIO_INT_POLARITY_V2; | |
114 | case GPIO_INTSTATUS: | |
115 | return GPIO_INTSTATUS_V2; | |
116 | case GPIO_PORTA_EOI: | |
117 | return GPIO_PORTA_EOI_V2; | |
118 | } | |
119 | ||
120 | return offset; | |
121 | } | |
122 | ||
123 | static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset) | |
124 | { | |
125 | if (gpio->flags & GPIO_REG_OFFSET_V2) | |
126 | return gpio_reg_v2_convert(offset); | |
127 | ||
128 | return offset; | |
129 | } | |
130 | ||
67809b97 WC |
131 | static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) |
132 | { | |
0f4630f3 | 133 | struct gpio_chip *gc = &gpio->ports[0].gc; |
67809b97 WC |
134 | void __iomem *reg_base = gpio->regs; |
135 | ||
a72b8c4a | 136 | return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); |
67809b97 WC |
137 | } |
138 | ||
139 | static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, | |
140 | u32 val) | |
141 | { | |
0f4630f3 | 142 | struct gpio_chip *gc = &gpio->ports[0].gc; |
67809b97 WC |
143 | void __iomem *reg_base = gpio->regs; |
144 | ||
a72b8c4a | 145 | gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); |
67809b97 WC |
146 | } |
147 | ||
7779b345 JI |
148 | static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
149 | { | |
0f4630f3 | 150 | struct dwapb_gpio_port *port = gpiochip_get_data(gc); |
7779b345 JI |
151 | struct dwapb_gpio *gpio = port->gpio; |
152 | ||
153 | return irq_find_mapping(gpio->domain, offset); | |
154 | } | |
155 | ||
156 | static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) | |
157 | { | |
67809b97 | 158 | u32 v = dwapb_read(gpio, GPIO_INT_POLARITY); |
7779b345 | 159 | |
0f4630f3 | 160 | if (gpio_get_value(gpio->ports[0].gc.base + offs)) |
7779b345 JI |
161 | v &= ~BIT(offs); |
162 | else | |
163 | v |= BIT(offs); | |
164 | ||
67809b97 | 165 | dwapb_write(gpio, GPIO_INT_POLARITY, v); |
7779b345 JI |
166 | } |
167 | ||
3d2613c4 | 168 | static u32 dwapb_do_irq(struct dwapb_gpio *gpio) |
7779b345 | 169 | { |
5664aa1c | 170 | u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS); |
3d2613c4 | 171 | u32 ret = irq_status; |
7779b345 JI |
172 | |
173 | while (irq_status) { | |
174 | int hwirq = fls(irq_status) - 1; | |
175 | int gpio_irq = irq_find_mapping(gpio->domain, hwirq); | |
176 | ||
177 | generic_handle_irq(gpio_irq); | |
178 | irq_status &= ~BIT(hwirq); | |
179 | ||
180 | if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK) | |
181 | == IRQ_TYPE_EDGE_BOTH) | |
182 | dwapb_toggle_trigger(gpio, hwirq); | |
183 | } | |
184 | ||
3d2613c4 WC |
185 | return ret; |
186 | } | |
187 | ||
bd0b9ac4 | 188 | static void dwapb_irq_handler(struct irq_desc *desc) |
3d2613c4 | 189 | { |
476f8b4c | 190 | struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); |
3d2613c4 WC |
191 | struct irq_chip *chip = irq_desc_get_chip(desc); |
192 | ||
193 | dwapb_do_irq(gpio); | |
194 | ||
7779b345 JI |
195 | if (chip->irq_eoi) |
196 | chip->irq_eoi(irq_desc_get_irq_data(desc)); | |
197 | } | |
198 | ||
199 | static void dwapb_irq_enable(struct irq_data *d) | |
200 | { | |
201 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
202 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 203 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 JI |
204 | unsigned long flags; |
205 | u32 val; | |
206 | ||
0f4630f3 | 207 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 | 208 | val = dwapb_read(gpio, GPIO_INTEN); |
7779b345 | 209 | val |= BIT(d->hwirq); |
67809b97 | 210 | dwapb_write(gpio, GPIO_INTEN, val); |
0f4630f3 | 211 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
212 | } |
213 | ||
214 | static void dwapb_irq_disable(struct irq_data *d) | |
215 | { | |
216 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
217 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 218 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 JI |
219 | unsigned long flags; |
220 | u32 val; | |
221 | ||
0f4630f3 | 222 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 | 223 | val = dwapb_read(gpio, GPIO_INTEN); |
7779b345 | 224 | val &= ~BIT(d->hwirq); |
67809b97 | 225 | dwapb_write(gpio, GPIO_INTEN, val); |
0f4630f3 | 226 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
227 | } |
228 | ||
57ef0428 | 229 | static int dwapb_irq_reqres(struct irq_data *d) |
7779b345 JI |
230 | { |
231 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
232 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 233 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 | 234 | |
0f4630f3 | 235 | if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) { |
7779b345 JI |
236 | dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n", |
237 | irqd_to_hwirq(d)); | |
57ef0428 LW |
238 | return -EINVAL; |
239 | } | |
7779b345 JI |
240 | return 0; |
241 | } | |
242 | ||
57ef0428 | 243 | static void dwapb_irq_relres(struct irq_data *d) |
7779b345 JI |
244 | { |
245 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
246 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 247 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 | 248 | |
0f4630f3 | 249 | gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d)); |
7779b345 JI |
250 | } |
251 | ||
252 | static int dwapb_irq_set_type(struct irq_data *d, u32 type) | |
253 | { | |
254 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
255 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 256 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 JI |
257 | int bit = d->hwirq; |
258 | unsigned long level, polarity, flags; | |
259 | ||
260 | if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | |
261 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
262 | return -EINVAL; | |
263 | ||
0f4630f3 | 264 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 WC |
265 | level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); |
266 | polarity = dwapb_read(gpio, GPIO_INT_POLARITY); | |
7779b345 JI |
267 | |
268 | switch (type) { | |
269 | case IRQ_TYPE_EDGE_BOTH: | |
270 | level |= BIT(bit); | |
271 | dwapb_toggle_trigger(gpio, bit); | |
272 | break; | |
273 | case IRQ_TYPE_EDGE_RISING: | |
274 | level |= BIT(bit); | |
275 | polarity |= BIT(bit); | |
276 | break; | |
277 | case IRQ_TYPE_EDGE_FALLING: | |
278 | level |= BIT(bit); | |
279 | polarity &= ~BIT(bit); | |
280 | break; | |
281 | case IRQ_TYPE_LEVEL_HIGH: | |
282 | level &= ~BIT(bit); | |
283 | polarity |= BIT(bit); | |
284 | break; | |
285 | case IRQ_TYPE_LEVEL_LOW: | |
286 | level &= ~BIT(bit); | |
287 | polarity &= ~BIT(bit); | |
288 | break; | |
289 | } | |
290 | ||
6a2f4b7d SAS |
291 | irq_setup_alt_chip(d, type); |
292 | ||
67809b97 | 293 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); |
edadced2 XC |
294 | if (type != IRQ_TYPE_EDGE_BOTH) |
295 | dwapb_write(gpio, GPIO_INT_POLARITY, polarity); | |
0f4630f3 | 296 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
297 | |
298 | return 0; | |
299 | } | |
300 | ||
6437c7ba HT |
301 | #ifdef CONFIG_PM_SLEEP |
302 | static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable) | |
303 | { | |
304 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
305 | struct dwapb_gpio *gpio = igc->private; | |
306 | struct dwapb_context *ctx = gpio->ports[0].ctx; | |
307 | ||
308 | if (enable) | |
309 | ctx->wake_en |= BIT(d->hwirq); | |
310 | else | |
311 | ctx->wake_en &= ~BIT(d->hwirq); | |
312 | ||
313 | return 0; | |
314 | } | |
315 | #endif | |
316 | ||
5d60d9ef WC |
317 | static int dwapb_gpio_set_debounce(struct gpio_chip *gc, |
318 | unsigned offset, unsigned debounce) | |
319 | { | |
0f4630f3 | 320 | struct dwapb_gpio_port *port = gpiochip_get_data(gc); |
5d60d9ef WC |
321 | struct dwapb_gpio *gpio = port->gpio; |
322 | unsigned long flags, val_deb; | |
d97a1b56 | 323 | unsigned long mask = BIT(offset); |
5d60d9ef | 324 | |
0f4630f3 | 325 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
5d60d9ef WC |
326 | |
327 | val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
328 | if (debounce) | |
329 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask); | |
330 | else | |
331 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask); | |
332 | ||
0f4630f3 | 333 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
5d60d9ef WC |
334 | |
335 | return 0; | |
336 | } | |
337 | ||
2956b5d9 MW |
338 | static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset, |
339 | unsigned long config) | |
340 | { | |
341 | u32 debounce; | |
342 | ||
343 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
344 | return -ENOTSUPP; | |
345 | ||
346 | debounce = pinconf_to_config_argument(config); | |
347 | return dwapb_gpio_set_debounce(gc, offset, debounce); | |
348 | } | |
349 | ||
3d2613c4 WC |
350 | static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id) |
351 | { | |
352 | u32 worked; | |
353 | struct dwapb_gpio *gpio = dev_id; | |
354 | ||
355 | worked = dwapb_do_irq(gpio); | |
356 | ||
357 | return worked ? IRQ_HANDLED : IRQ_NONE; | |
358 | } | |
359 | ||
7779b345 | 360 | static void dwapb_configure_irqs(struct dwapb_gpio *gpio, |
3d2613c4 WC |
361 | struct dwapb_gpio_port *port, |
362 | struct dwapb_port_property *pp) | |
7779b345 | 363 | { |
0f4630f3 | 364 | struct gpio_chip *gc = &port->gc; |
4ba8cfa7 | 365 | struct fwnode_handle *fwnode = pp->fwnode; |
3d2613c4 | 366 | struct irq_chip_generic *irq_gc = NULL; |
7779b345 JI |
367 | unsigned int hwirq, ngpio = gc->ngpio; |
368 | struct irq_chip_type *ct; | |
3d2613c4 | 369 | int err, i; |
7779b345 | 370 | |
4ba8cfa7 JQ |
371 | gpio->domain = irq_domain_create_linear(fwnode, ngpio, |
372 | &irq_generic_chip_ops, gpio); | |
7779b345 JI |
373 | if (!gpio->domain) |
374 | return; | |
375 | ||
6a2f4b7d | 376 | err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2, |
7779b345 JI |
377 | "gpio-dwapb", handle_level_irq, |
378 | IRQ_NOREQUEST, 0, | |
379 | IRQ_GC_INIT_NESTED_LOCK); | |
380 | if (err) { | |
381 | dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n"); | |
382 | irq_domain_remove(gpio->domain); | |
383 | gpio->domain = NULL; | |
384 | return; | |
385 | } | |
386 | ||
387 | irq_gc = irq_get_domain_generic_chip(gpio->domain, 0); | |
388 | if (!irq_gc) { | |
389 | irq_domain_remove(gpio->domain); | |
390 | gpio->domain = NULL; | |
391 | return; | |
392 | } | |
393 | ||
394 | irq_gc->reg_base = gpio->regs; | |
395 | irq_gc->private = gpio; | |
396 | ||
6a2f4b7d SAS |
397 | for (i = 0; i < 2; i++) { |
398 | ct = &irq_gc->chip_types[i]; | |
399 | ct->chip.irq_ack = irq_gc_ack_set_bit; | |
400 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
401 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
402 | ct->chip.irq_set_type = dwapb_irq_set_type; | |
403 | ct->chip.irq_enable = dwapb_irq_enable; | |
404 | ct->chip.irq_disable = dwapb_irq_disable; | |
405 | ct->chip.irq_request_resources = dwapb_irq_reqres; | |
406 | ct->chip.irq_release_resources = dwapb_irq_relres; | |
6437c7ba HT |
407 | #ifdef CONFIG_PM_SLEEP |
408 | ct->chip.irq_set_wake = dwapb_irq_set_wake; | |
409 | #endif | |
a72b8c4a HT |
410 | ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI); |
411 | ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK); | |
6a2f4b7d SAS |
412 | ct->type = IRQ_TYPE_LEVEL_MASK; |
413 | } | |
414 | ||
415 | irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; | |
416 | irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; | |
417 | irq_gc->chip_types[1].handler = handle_edge_irq; | |
7779b345 | 418 | |
3d2613c4 | 419 | if (!pp->irq_shared) { |
6218b88d TG |
420 | irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler, |
421 | gpio); | |
3d2613c4 WC |
422 | } else { |
423 | /* | |
424 | * Request a shared IRQ since where MFD would have devices | |
425 | * using the same irq pin | |
426 | */ | |
427 | err = devm_request_irq(gpio->dev, pp->irq, | |
428 | dwapb_irq_handler_mfd, | |
429 | IRQF_SHARED, "gpio-dwapb-mfd", gpio); | |
430 | if (err) { | |
431 | dev_err(gpio->dev, "error requesting IRQ\n"); | |
432 | irq_domain_remove(gpio->domain); | |
433 | gpio->domain = NULL; | |
434 | return; | |
435 | } | |
436 | } | |
7779b345 JI |
437 | |
438 | for (hwirq = 0 ; hwirq < ngpio ; hwirq++) | |
439 | irq_create_mapping(gpio->domain, hwirq); | |
440 | ||
0f4630f3 | 441 | port->gc.to_irq = dwapb_gpio_to_irq; |
7779b345 JI |
442 | } |
443 | ||
444 | static void dwapb_irq_teardown(struct dwapb_gpio *gpio) | |
445 | { | |
446 | struct dwapb_gpio_port *port = &gpio->ports[0]; | |
0f4630f3 | 447 | struct gpio_chip *gc = &port->gc; |
7779b345 JI |
448 | unsigned int ngpio = gc->ngpio; |
449 | irq_hw_number_t hwirq; | |
450 | ||
451 | if (!gpio->domain) | |
452 | return; | |
453 | ||
454 | for (hwirq = 0 ; hwirq < ngpio ; hwirq++) | |
455 | irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq)); | |
456 | ||
457 | irq_domain_remove(gpio->domain); | |
458 | gpio->domain = NULL; | |
459 | } | |
460 | ||
461 | static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, | |
3d2613c4 | 462 | struct dwapb_port_property *pp, |
7779b345 JI |
463 | unsigned int offs) |
464 | { | |
465 | struct dwapb_gpio_port *port; | |
7779b345 JI |
466 | void __iomem *dat, *set, *dirout; |
467 | int err; | |
468 | ||
7779b345 JI |
469 | port = &gpio->ports[offs]; |
470 | port->gpio = gpio; | |
1e960dbb WC |
471 | port->idx = pp->idx; |
472 | ||
473 | #ifdef CONFIG_PM_SLEEP | |
474 | port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); | |
475 | if (!port->ctx) | |
476 | return -ENOMEM; | |
477 | #endif | |
7779b345 | 478 | |
3d2613c4 WC |
479 | dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE); |
480 | set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE); | |
7779b345 | 481 | dirout = gpio->regs + GPIO_SWPORTA_DDR + |
3d2613c4 | 482 | (pp->idx * GPIO_SWPORT_DDR_SIZE); |
7779b345 | 483 | |
0f4630f3 | 484 | err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, |
d97a1b56 | 485 | NULL, 0); |
7779b345 | 486 | if (err) { |
e8159181 JQ |
487 | dev_err(gpio->dev, "failed to init gpio chip for port%d\n", |
488 | port->idx); | |
7779b345 JI |
489 | return err; |
490 | } | |
491 | ||
3d2613c4 | 492 | #ifdef CONFIG_OF_GPIO |
4ba8cfa7 | 493 | port->gc.of_node = to_of_node(pp->fwnode); |
3d2613c4 | 494 | #endif |
0f4630f3 LW |
495 | port->gc.ngpio = pp->ngpio; |
496 | port->gc.base = pp->gpio_base; | |
7779b345 | 497 | |
5d60d9ef WC |
498 | /* Only port A support debounce */ |
499 | if (pp->idx == 0) | |
2956b5d9 | 500 | port->gc.set_config = dwapb_gpio_set_config; |
5d60d9ef | 501 | |
3d2613c4 WC |
502 | if (pp->irq) |
503 | dwapb_configure_irqs(gpio, port, pp); | |
7779b345 | 504 | |
0f4630f3 | 505 | err = gpiochip_add_data(&port->gc, port); |
7779b345 | 506 | if (err) |
e8159181 JQ |
507 | dev_err(gpio->dev, "failed to register gpiochip for port%d\n", |
508 | port->idx); | |
7779b345 JI |
509 | else |
510 | port->is_registered = true; | |
511 | ||
e6cb3486 JQ |
512 | /* Add GPIO-signaled ACPI event support */ |
513 | if (pp->irq) | |
514 | acpi_gpiochip_request_interrupts(&port->gc); | |
515 | ||
7779b345 JI |
516 | return err; |
517 | } | |
518 | ||
519 | static void dwapb_gpio_unregister(struct dwapb_gpio *gpio) | |
520 | { | |
521 | unsigned int m; | |
522 | ||
523 | for (m = 0; m < gpio->nr_ports; ++m) | |
524 | if (gpio->ports[m].is_registered) | |
0f4630f3 | 525 | gpiochip_remove(&gpio->ports[m].gc); |
7779b345 JI |
526 | } |
527 | ||
3d2613c4 | 528 | static struct dwapb_platform_data * |
4ba8cfa7 | 529 | dwapb_gpio_get_pdata(struct device *dev) |
3d2613c4 | 530 | { |
4ba8cfa7 | 531 | struct fwnode_handle *fwnode; |
3d2613c4 WC |
532 | struct dwapb_platform_data *pdata; |
533 | struct dwapb_port_property *pp; | |
534 | int nports; | |
535 | int i; | |
536 | ||
4ba8cfa7 | 537 | nports = device_get_child_node_count(dev); |
3d2613c4 WC |
538 | if (nports == 0) |
539 | return ERR_PTR(-ENODEV); | |
540 | ||
da9df93e | 541 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
3d2613c4 WC |
542 | if (!pdata) |
543 | return ERR_PTR(-ENOMEM); | |
544 | ||
da9df93e AL |
545 | pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); |
546 | if (!pdata->properties) | |
3d2613c4 | 547 | return ERR_PTR(-ENOMEM); |
3d2613c4 WC |
548 | |
549 | pdata->nports = nports; | |
550 | ||
551 | i = 0; | |
4ba8cfa7 | 552 | device_for_each_child_node(dev, fwnode) { |
3d2613c4 | 553 | pp = &pdata->properties[i++]; |
4ba8cfa7 | 554 | pp->fwnode = fwnode; |
3d2613c4 | 555 | |
4ba8cfa7 | 556 | if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || |
3d2613c4 | 557 | pp->idx >= DWAPB_MAX_PORTS) { |
e8159181 JQ |
558 | dev_err(dev, |
559 | "missing/invalid port index for port%d\n", i); | |
bfab7c8f | 560 | fwnode_handle_put(fwnode); |
3d2613c4 WC |
561 | return ERR_PTR(-EINVAL); |
562 | } | |
563 | ||
4ba8cfa7 | 564 | if (fwnode_property_read_u32(fwnode, "snps,nr-gpios", |
3d2613c4 | 565 | &pp->ngpio)) { |
e8159181 JQ |
566 | dev_info(dev, |
567 | "failed to get number of gpios for port%d\n", | |
568 | i); | |
3d2613c4 WC |
569 | pp->ngpio = 32; |
570 | } | |
571 | ||
572 | /* | |
573 | * Only port A can provide interrupts in all configurations of | |
574 | * the IP. | |
575 | */ | |
4ba8cfa7 JQ |
576 | if (dev->of_node && pp->idx == 0 && |
577 | fwnode_property_read_bool(fwnode, | |
578 | "interrupt-controller")) { | |
579 | pp->irq = irq_of_parse_and_map(to_of_node(fwnode), 0); | |
e8159181 JQ |
580 | if (!pp->irq) |
581 | dev_warn(dev, "no irq for port%d\n", pp->idx); | |
3d2613c4 WC |
582 | } |
583 | ||
e6cb3486 JQ |
584 | if (has_acpi_companion(dev) && pp->idx == 0) |
585 | pp->irq = platform_get_irq(to_platform_device(dev), 0); | |
586 | ||
3d2613c4 WC |
587 | pp->irq_shared = false; |
588 | pp->gpio_base = -1; | |
3d2613c4 WC |
589 | } |
590 | ||
591 | return pdata; | |
592 | } | |
593 | ||
a72b8c4a HT |
594 | static const struct of_device_id dwapb_of_match[] = { |
595 | { .compatible = "snps,dw-apb-gpio", .data = (void *)0}, | |
596 | { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2}, | |
597 | { /* Sentinel */ } | |
598 | }; | |
599 | MODULE_DEVICE_TABLE(of, dwapb_of_match); | |
600 | ||
601 | static const struct acpi_device_id dwapb_acpi_match[] = { | |
602 | {"HISI0181", 0}, | |
603 | {"APMC0D07", 0}, | |
604 | {"APMC0D81", GPIO_REG_OFFSET_V2}, | |
605 | { } | |
606 | }; | |
607 | MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match); | |
608 | ||
7779b345 JI |
609 | static int dwapb_gpio_probe(struct platform_device *pdev) |
610 | { | |
3d2613c4 | 611 | unsigned int i; |
7779b345 JI |
612 | struct resource *res; |
613 | struct dwapb_gpio *gpio; | |
7779b345 | 614 | int err; |
3d2613c4 WC |
615 | struct device *dev = &pdev->dev; |
616 | struct dwapb_platform_data *pdata = dev_get_platdata(dev); | |
3d2613c4 | 617 | |
da9df93e | 618 | if (!pdata) { |
4ba8cfa7 | 619 | pdata = dwapb_gpio_get_pdata(dev); |
3d2613c4 WC |
620 | if (IS_ERR(pdata)) |
621 | return PTR_ERR(pdata); | |
622 | } | |
7779b345 | 623 | |
da9df93e AL |
624 | if (!pdata->nports) |
625 | return -ENODEV; | |
7779b345 | 626 | |
3d2613c4 | 627 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); |
da9df93e AL |
628 | if (!gpio) |
629 | return -ENOMEM; | |
630 | ||
3d2613c4 WC |
631 | gpio->dev = &pdev->dev; |
632 | gpio->nr_ports = pdata->nports; | |
633 | ||
07901a94 AT |
634 | gpio->rst = devm_reset_control_get_optional_shared(dev, NULL); |
635 | if (IS_ERR(gpio->rst)) | |
636 | return PTR_ERR(gpio->rst); | |
637 | ||
638 | reset_control_deassert(gpio->rst); | |
639 | ||
3d2613c4 | 640 | gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, |
7779b345 | 641 | sizeof(*gpio->ports), GFP_KERNEL); |
da9df93e AL |
642 | if (!gpio->ports) |
643 | return -ENOMEM; | |
7779b345 JI |
644 | |
645 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
646 | gpio->regs = devm_ioremap_resource(&pdev->dev, res); | |
da9df93e AL |
647 | if (IS_ERR(gpio->regs)) |
648 | return PTR_ERR(gpio->regs); | |
7779b345 | 649 | |
a72b8c4a HT |
650 | gpio->flags = 0; |
651 | if (dev->of_node) { | |
652 | const struct of_device_id *of_devid; | |
653 | ||
654 | of_devid = of_match_device(dwapb_of_match, dev); | |
655 | if (of_devid) { | |
656 | if (of_devid->data) | |
657 | gpio->flags = (uintptr_t)of_devid->data; | |
658 | } | |
659 | } else if (has_acpi_companion(dev)) { | |
660 | const struct acpi_device_id *acpi_id; | |
661 | ||
662 | acpi_id = acpi_match_device(dwapb_acpi_match, dev); | |
663 | if (acpi_id) { | |
664 | if (acpi_id->driver_data) | |
665 | gpio->flags = acpi_id->driver_data; | |
666 | } | |
667 | } | |
668 | ||
3d2613c4 WC |
669 | for (i = 0; i < gpio->nr_ports; i++) { |
670 | err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); | |
7779b345 JI |
671 | if (err) |
672 | goto out_unregister; | |
673 | } | |
674 | platform_set_drvdata(pdev, gpio); | |
675 | ||
da9df93e | 676 | return 0; |
7779b345 JI |
677 | |
678 | out_unregister: | |
679 | dwapb_gpio_unregister(gpio); | |
680 | dwapb_irq_teardown(gpio); | |
681 | ||
7779b345 JI |
682 | return err; |
683 | } | |
684 | ||
685 | static int dwapb_gpio_remove(struct platform_device *pdev) | |
686 | { | |
687 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
688 | ||
689 | dwapb_gpio_unregister(gpio); | |
690 | dwapb_irq_teardown(gpio); | |
07901a94 | 691 | reset_control_assert(gpio->rst); |
7779b345 JI |
692 | |
693 | return 0; | |
694 | } | |
695 | ||
1e960dbb WC |
696 | #ifdef CONFIG_PM_SLEEP |
697 | static int dwapb_gpio_suspend(struct device *dev) | |
698 | { | |
699 | struct platform_device *pdev = to_platform_device(dev); | |
700 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
0f4630f3 | 701 | struct gpio_chip *gc = &gpio->ports[0].gc; |
1e960dbb WC |
702 | unsigned long flags; |
703 | int i; | |
704 | ||
0f4630f3 | 705 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
1e960dbb WC |
706 | for (i = 0; i < gpio->nr_ports; i++) { |
707 | unsigned int offset; | |
708 | unsigned int idx = gpio->ports[i].idx; | |
709 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
710 | ||
58a3b92d | 711 | BUG_ON(!ctx); |
1e960dbb WC |
712 | |
713 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE; | |
714 | ctx->dir = dwapb_read(gpio, offset); | |
715 | ||
716 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE; | |
717 | ctx->data = dwapb_read(gpio, offset); | |
718 | ||
719 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE; | |
720 | ctx->ext = dwapb_read(gpio, offset); | |
721 | ||
722 | /* Only port A can provide interrupts */ | |
723 | if (idx == 0) { | |
724 | ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); | |
725 | ctx->int_en = dwapb_read(gpio, GPIO_INTEN); | |
726 | ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); | |
727 | ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); | |
728 | ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
729 | ||
730 | /* Mask out interrupts */ | |
6437c7ba HT |
731 | dwapb_write(gpio, GPIO_INTMASK, |
732 | 0xffffffff & ~ctx->wake_en); | |
1e960dbb WC |
733 | } |
734 | } | |
0f4630f3 | 735 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
1e960dbb WC |
736 | |
737 | return 0; | |
738 | } | |
739 | ||
740 | static int dwapb_gpio_resume(struct device *dev) | |
741 | { | |
742 | struct platform_device *pdev = to_platform_device(dev); | |
743 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
0f4630f3 | 744 | struct gpio_chip *gc = &gpio->ports[0].gc; |
1e960dbb WC |
745 | unsigned long flags; |
746 | int i; | |
747 | ||
0f4630f3 | 748 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
1e960dbb WC |
749 | for (i = 0; i < gpio->nr_ports; i++) { |
750 | unsigned int offset; | |
751 | unsigned int idx = gpio->ports[i].idx; | |
752 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
753 | ||
58a3b92d | 754 | BUG_ON(!ctx); |
1e960dbb WC |
755 | |
756 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE; | |
757 | dwapb_write(gpio, offset, ctx->data); | |
758 | ||
759 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE; | |
760 | dwapb_write(gpio, offset, ctx->dir); | |
761 | ||
762 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE; | |
763 | dwapb_write(gpio, offset, ctx->ext); | |
764 | ||
765 | /* Only port A can provide interrupts */ | |
766 | if (idx == 0) { | |
767 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); | |
768 | dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); | |
769 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); | |
770 | dwapb_write(gpio, GPIO_INTEN, ctx->int_en); | |
771 | dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); | |
772 | ||
773 | /* Clear out spurious interrupts */ | |
774 | dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); | |
775 | } | |
776 | } | |
0f4630f3 | 777 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
1e960dbb WC |
778 | |
779 | return 0; | |
780 | } | |
781 | #endif | |
782 | ||
783 | static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend, | |
784 | dwapb_gpio_resume); | |
785 | ||
7779b345 JI |
786 | static struct platform_driver dwapb_gpio_driver = { |
787 | .driver = { | |
788 | .name = "gpio-dwapb", | |
1e960dbb | 789 | .pm = &dwapb_gpio_pm_ops, |
7779b345 | 790 | .of_match_table = of_match_ptr(dwapb_of_match), |
e6cb3486 | 791 | .acpi_match_table = ACPI_PTR(dwapb_acpi_match), |
7779b345 JI |
792 | }, |
793 | .probe = dwapb_gpio_probe, | |
794 | .remove = dwapb_gpio_remove, | |
795 | }; | |
796 | ||
797 | module_platform_driver(dwapb_gpio_driver); | |
798 | ||
799 | MODULE_LICENSE("GPL"); | |
800 | MODULE_AUTHOR("Jamie Iles"); | |
801 | MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver"); |