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Commit | Line | Data |
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7779b345 JI |
1 | /* |
2 | * Copyright (c) 2011 Jamie Iles | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * All enquiries to support@picochip.com | |
9 | */ | |
e6cb3486 | 10 | #include <linux/acpi.h> |
0f4630f3 LW |
11 | #include <linux/gpio/driver.h> |
12 | /* FIXME: for gpio_get_value(), replace this with direct register read */ | |
13 | #include <linux/gpio.h> | |
7779b345 JI |
14 | #include <linux/err.h> |
15 | #include <linux/init.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/ioport.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/irqdomain.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/of_irq.h> | |
25 | #include <linux/platform_device.h> | |
4ba8cfa7 | 26 | #include <linux/property.h> |
7779b345 | 27 | #include <linux/spinlock.h> |
3d2613c4 WC |
28 | #include <linux/platform_data/gpio-dwapb.h> |
29 | #include <linux/slab.h> | |
7779b345 | 30 | |
e6cb3486 JQ |
31 | #include "gpiolib.h" |
32 | ||
7779b345 JI |
33 | #define GPIO_SWPORTA_DR 0x00 |
34 | #define GPIO_SWPORTA_DDR 0x04 | |
35 | #define GPIO_SWPORTB_DR 0x0c | |
36 | #define GPIO_SWPORTB_DDR 0x10 | |
37 | #define GPIO_SWPORTC_DR 0x18 | |
38 | #define GPIO_SWPORTC_DDR 0x1c | |
39 | #define GPIO_SWPORTD_DR 0x24 | |
40 | #define GPIO_SWPORTD_DDR 0x28 | |
41 | #define GPIO_INTEN 0x30 | |
42 | #define GPIO_INTMASK 0x34 | |
43 | #define GPIO_INTTYPE_LEVEL 0x38 | |
44 | #define GPIO_INT_POLARITY 0x3c | |
45 | #define GPIO_INTSTATUS 0x40 | |
5d60d9ef | 46 | #define GPIO_PORTA_DEBOUNCE 0x48 |
7779b345 JI |
47 | #define GPIO_PORTA_EOI 0x4c |
48 | #define GPIO_EXT_PORTA 0x50 | |
49 | #define GPIO_EXT_PORTB 0x54 | |
50 | #define GPIO_EXT_PORTC 0x58 | |
51 | #define GPIO_EXT_PORTD 0x5c | |
52 | ||
53 | #define DWAPB_MAX_PORTS 4 | |
54 | #define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA) | |
55 | #define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR) | |
56 | #define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR) | |
57 | ||
58 | struct dwapb_gpio; | |
59 | ||
1e960dbb WC |
60 | #ifdef CONFIG_PM_SLEEP |
61 | /* Store GPIO context across system-wide suspend/resume transitions */ | |
62 | struct dwapb_context { | |
63 | u32 data; | |
64 | u32 dir; | |
65 | u32 ext; | |
66 | u32 int_en; | |
67 | u32 int_mask; | |
68 | u32 int_type; | |
69 | u32 int_pol; | |
70 | u32 int_deb; | |
71 | }; | |
72 | #endif | |
73 | ||
7779b345 | 74 | struct dwapb_gpio_port { |
0f4630f3 | 75 | struct gpio_chip gc; |
7779b345 JI |
76 | bool is_registered; |
77 | struct dwapb_gpio *gpio; | |
1e960dbb WC |
78 | #ifdef CONFIG_PM_SLEEP |
79 | struct dwapb_context *ctx; | |
80 | #endif | |
81 | unsigned int idx; | |
7779b345 JI |
82 | }; |
83 | ||
84 | struct dwapb_gpio { | |
85 | struct device *dev; | |
86 | void __iomem *regs; | |
87 | struct dwapb_gpio_port *ports; | |
88 | unsigned int nr_ports; | |
89 | struct irq_domain *domain; | |
90 | }; | |
91 | ||
67809b97 WC |
92 | static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) |
93 | { | |
0f4630f3 | 94 | struct gpio_chip *gc = &gpio->ports[0].gc; |
67809b97 WC |
95 | void __iomem *reg_base = gpio->regs; |
96 | ||
0f4630f3 | 97 | return gc->read_reg(reg_base + offset); |
67809b97 WC |
98 | } |
99 | ||
100 | static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, | |
101 | u32 val) | |
102 | { | |
0f4630f3 | 103 | struct gpio_chip *gc = &gpio->ports[0].gc; |
67809b97 WC |
104 | void __iomem *reg_base = gpio->regs; |
105 | ||
0f4630f3 | 106 | gc->write_reg(reg_base + offset, val); |
67809b97 WC |
107 | } |
108 | ||
7779b345 JI |
109 | static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
110 | { | |
0f4630f3 | 111 | struct dwapb_gpio_port *port = gpiochip_get_data(gc); |
7779b345 JI |
112 | struct dwapb_gpio *gpio = port->gpio; |
113 | ||
114 | return irq_find_mapping(gpio->domain, offset); | |
115 | } | |
116 | ||
117 | static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) | |
118 | { | |
67809b97 | 119 | u32 v = dwapb_read(gpio, GPIO_INT_POLARITY); |
7779b345 | 120 | |
0f4630f3 | 121 | if (gpio_get_value(gpio->ports[0].gc.base + offs)) |
7779b345 JI |
122 | v &= ~BIT(offs); |
123 | else | |
124 | v |= BIT(offs); | |
125 | ||
67809b97 | 126 | dwapb_write(gpio, GPIO_INT_POLARITY, v); |
7779b345 JI |
127 | } |
128 | ||
3d2613c4 | 129 | static u32 dwapb_do_irq(struct dwapb_gpio *gpio) |
7779b345 | 130 | { |
7779b345 | 131 | u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS); |
3d2613c4 | 132 | u32 ret = irq_status; |
7779b345 JI |
133 | |
134 | while (irq_status) { | |
135 | int hwirq = fls(irq_status) - 1; | |
136 | int gpio_irq = irq_find_mapping(gpio->domain, hwirq); | |
137 | ||
138 | generic_handle_irq(gpio_irq); | |
139 | irq_status &= ~BIT(hwirq); | |
140 | ||
141 | if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK) | |
142 | == IRQ_TYPE_EDGE_BOTH) | |
143 | dwapb_toggle_trigger(gpio, hwirq); | |
144 | } | |
145 | ||
3d2613c4 WC |
146 | return ret; |
147 | } | |
148 | ||
bd0b9ac4 | 149 | static void dwapb_irq_handler(struct irq_desc *desc) |
3d2613c4 | 150 | { |
476f8b4c | 151 | struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); |
3d2613c4 WC |
152 | struct irq_chip *chip = irq_desc_get_chip(desc); |
153 | ||
154 | dwapb_do_irq(gpio); | |
155 | ||
7779b345 JI |
156 | if (chip->irq_eoi) |
157 | chip->irq_eoi(irq_desc_get_irq_data(desc)); | |
158 | } | |
159 | ||
160 | static void dwapb_irq_enable(struct irq_data *d) | |
161 | { | |
162 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
163 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 164 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 JI |
165 | unsigned long flags; |
166 | u32 val; | |
167 | ||
0f4630f3 | 168 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 | 169 | val = dwapb_read(gpio, GPIO_INTEN); |
7779b345 | 170 | val |= BIT(d->hwirq); |
67809b97 | 171 | dwapb_write(gpio, GPIO_INTEN, val); |
0f4630f3 | 172 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
173 | } |
174 | ||
175 | static void dwapb_irq_disable(struct irq_data *d) | |
176 | { | |
177 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
178 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 179 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 JI |
180 | unsigned long flags; |
181 | u32 val; | |
182 | ||
0f4630f3 | 183 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 | 184 | val = dwapb_read(gpio, GPIO_INTEN); |
7779b345 | 185 | val &= ~BIT(d->hwirq); |
67809b97 | 186 | dwapb_write(gpio, GPIO_INTEN, val); |
0f4630f3 | 187 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
188 | } |
189 | ||
57ef0428 | 190 | static int dwapb_irq_reqres(struct irq_data *d) |
7779b345 JI |
191 | { |
192 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
193 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 194 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 | 195 | |
0f4630f3 | 196 | if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) { |
7779b345 JI |
197 | dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n", |
198 | irqd_to_hwirq(d)); | |
57ef0428 LW |
199 | return -EINVAL; |
200 | } | |
7779b345 JI |
201 | return 0; |
202 | } | |
203 | ||
57ef0428 | 204 | static void dwapb_irq_relres(struct irq_data *d) |
7779b345 JI |
205 | { |
206 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
207 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 208 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 | 209 | |
0f4630f3 | 210 | gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d)); |
7779b345 JI |
211 | } |
212 | ||
213 | static int dwapb_irq_set_type(struct irq_data *d, u32 type) | |
214 | { | |
215 | struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); | |
216 | struct dwapb_gpio *gpio = igc->private; | |
0f4630f3 | 217 | struct gpio_chip *gc = &gpio->ports[0].gc; |
7779b345 JI |
218 | int bit = d->hwirq; |
219 | unsigned long level, polarity, flags; | |
220 | ||
221 | if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | | |
222 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
223 | return -EINVAL; | |
224 | ||
0f4630f3 | 225 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 WC |
226 | level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); |
227 | polarity = dwapb_read(gpio, GPIO_INT_POLARITY); | |
7779b345 JI |
228 | |
229 | switch (type) { | |
230 | case IRQ_TYPE_EDGE_BOTH: | |
231 | level |= BIT(bit); | |
232 | dwapb_toggle_trigger(gpio, bit); | |
233 | break; | |
234 | case IRQ_TYPE_EDGE_RISING: | |
235 | level |= BIT(bit); | |
236 | polarity |= BIT(bit); | |
237 | break; | |
238 | case IRQ_TYPE_EDGE_FALLING: | |
239 | level |= BIT(bit); | |
240 | polarity &= ~BIT(bit); | |
241 | break; | |
242 | case IRQ_TYPE_LEVEL_HIGH: | |
243 | level &= ~BIT(bit); | |
244 | polarity |= BIT(bit); | |
245 | break; | |
246 | case IRQ_TYPE_LEVEL_LOW: | |
247 | level &= ~BIT(bit); | |
248 | polarity &= ~BIT(bit); | |
249 | break; | |
250 | } | |
251 | ||
6a2f4b7d SAS |
252 | irq_setup_alt_chip(d, type); |
253 | ||
67809b97 WC |
254 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); |
255 | dwapb_write(gpio, GPIO_INT_POLARITY, polarity); | |
0f4630f3 | 256 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
257 | |
258 | return 0; | |
259 | } | |
260 | ||
5d60d9ef WC |
261 | static int dwapb_gpio_set_debounce(struct gpio_chip *gc, |
262 | unsigned offset, unsigned debounce) | |
263 | { | |
0f4630f3 | 264 | struct dwapb_gpio_port *port = gpiochip_get_data(gc); |
5d60d9ef WC |
265 | struct dwapb_gpio *gpio = port->gpio; |
266 | unsigned long flags, val_deb; | |
0f4630f3 | 267 | unsigned long mask = gc->pin2mask(gc, offset); |
5d60d9ef | 268 | |
0f4630f3 | 269 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
5d60d9ef WC |
270 | |
271 | val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
272 | if (debounce) | |
273 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask); | |
274 | else | |
275 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask); | |
276 | ||
0f4630f3 | 277 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
5d60d9ef WC |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
2956b5d9 MW |
282 | static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset, |
283 | unsigned long config) | |
284 | { | |
285 | u32 debounce; | |
286 | ||
287 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
288 | return -ENOTSUPP; | |
289 | ||
290 | debounce = pinconf_to_config_argument(config); | |
291 | return dwapb_gpio_set_debounce(gc, offset, debounce); | |
292 | } | |
293 | ||
3d2613c4 WC |
294 | static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id) |
295 | { | |
296 | u32 worked; | |
297 | struct dwapb_gpio *gpio = dev_id; | |
298 | ||
299 | worked = dwapb_do_irq(gpio); | |
300 | ||
301 | return worked ? IRQ_HANDLED : IRQ_NONE; | |
302 | } | |
303 | ||
7779b345 | 304 | static void dwapb_configure_irqs(struct dwapb_gpio *gpio, |
3d2613c4 WC |
305 | struct dwapb_gpio_port *port, |
306 | struct dwapb_port_property *pp) | |
7779b345 | 307 | { |
0f4630f3 | 308 | struct gpio_chip *gc = &port->gc; |
4ba8cfa7 | 309 | struct fwnode_handle *fwnode = pp->fwnode; |
3d2613c4 | 310 | struct irq_chip_generic *irq_gc = NULL; |
7779b345 JI |
311 | unsigned int hwirq, ngpio = gc->ngpio; |
312 | struct irq_chip_type *ct; | |
3d2613c4 | 313 | int err, i; |
7779b345 | 314 | |
4ba8cfa7 JQ |
315 | gpio->domain = irq_domain_create_linear(fwnode, ngpio, |
316 | &irq_generic_chip_ops, gpio); | |
7779b345 JI |
317 | if (!gpio->domain) |
318 | return; | |
319 | ||
6a2f4b7d | 320 | err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2, |
7779b345 JI |
321 | "gpio-dwapb", handle_level_irq, |
322 | IRQ_NOREQUEST, 0, | |
323 | IRQ_GC_INIT_NESTED_LOCK); | |
324 | if (err) { | |
325 | dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n"); | |
326 | irq_domain_remove(gpio->domain); | |
327 | gpio->domain = NULL; | |
328 | return; | |
329 | } | |
330 | ||
331 | irq_gc = irq_get_domain_generic_chip(gpio->domain, 0); | |
332 | if (!irq_gc) { | |
333 | irq_domain_remove(gpio->domain); | |
334 | gpio->domain = NULL; | |
335 | return; | |
336 | } | |
337 | ||
338 | irq_gc->reg_base = gpio->regs; | |
339 | irq_gc->private = gpio; | |
340 | ||
6a2f4b7d SAS |
341 | for (i = 0; i < 2; i++) { |
342 | ct = &irq_gc->chip_types[i]; | |
343 | ct->chip.irq_ack = irq_gc_ack_set_bit; | |
344 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
345 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
346 | ct->chip.irq_set_type = dwapb_irq_set_type; | |
347 | ct->chip.irq_enable = dwapb_irq_enable; | |
348 | ct->chip.irq_disable = dwapb_irq_disable; | |
349 | ct->chip.irq_request_resources = dwapb_irq_reqres; | |
350 | ct->chip.irq_release_resources = dwapb_irq_relres; | |
351 | ct->regs.ack = GPIO_PORTA_EOI; | |
352 | ct->regs.mask = GPIO_INTMASK; | |
353 | ct->type = IRQ_TYPE_LEVEL_MASK; | |
354 | } | |
355 | ||
356 | irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; | |
357 | irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; | |
358 | irq_gc->chip_types[1].handler = handle_edge_irq; | |
7779b345 | 359 | |
3d2613c4 | 360 | if (!pp->irq_shared) { |
6218b88d TG |
361 | irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler, |
362 | gpio); | |
3d2613c4 WC |
363 | } else { |
364 | /* | |
365 | * Request a shared IRQ since where MFD would have devices | |
366 | * using the same irq pin | |
367 | */ | |
368 | err = devm_request_irq(gpio->dev, pp->irq, | |
369 | dwapb_irq_handler_mfd, | |
370 | IRQF_SHARED, "gpio-dwapb-mfd", gpio); | |
371 | if (err) { | |
372 | dev_err(gpio->dev, "error requesting IRQ\n"); | |
373 | irq_domain_remove(gpio->domain); | |
374 | gpio->domain = NULL; | |
375 | return; | |
376 | } | |
377 | } | |
7779b345 JI |
378 | |
379 | for (hwirq = 0 ; hwirq < ngpio ; hwirq++) | |
380 | irq_create_mapping(gpio->domain, hwirq); | |
381 | ||
0f4630f3 | 382 | port->gc.to_irq = dwapb_gpio_to_irq; |
7779b345 JI |
383 | } |
384 | ||
385 | static void dwapb_irq_teardown(struct dwapb_gpio *gpio) | |
386 | { | |
387 | struct dwapb_gpio_port *port = &gpio->ports[0]; | |
0f4630f3 | 388 | struct gpio_chip *gc = &port->gc; |
7779b345 JI |
389 | unsigned int ngpio = gc->ngpio; |
390 | irq_hw_number_t hwirq; | |
391 | ||
392 | if (!gpio->domain) | |
393 | return; | |
394 | ||
395 | for (hwirq = 0 ; hwirq < ngpio ; hwirq++) | |
396 | irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq)); | |
397 | ||
398 | irq_domain_remove(gpio->domain); | |
399 | gpio->domain = NULL; | |
400 | } | |
401 | ||
402 | static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, | |
3d2613c4 | 403 | struct dwapb_port_property *pp, |
7779b345 JI |
404 | unsigned int offs) |
405 | { | |
406 | struct dwapb_gpio_port *port; | |
7779b345 JI |
407 | void __iomem *dat, *set, *dirout; |
408 | int err; | |
409 | ||
7779b345 JI |
410 | port = &gpio->ports[offs]; |
411 | port->gpio = gpio; | |
1e960dbb WC |
412 | port->idx = pp->idx; |
413 | ||
414 | #ifdef CONFIG_PM_SLEEP | |
415 | port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); | |
416 | if (!port->ctx) | |
417 | return -ENOMEM; | |
418 | #endif | |
7779b345 | 419 | |
3d2613c4 WC |
420 | dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE); |
421 | set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE); | |
7779b345 | 422 | dirout = gpio->regs + GPIO_SWPORTA_DDR + |
3d2613c4 | 423 | (pp->idx * GPIO_SWPORT_DDR_SIZE); |
7779b345 | 424 | |
0f4630f3 | 425 | err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, |
7779b345 JI |
426 | NULL, false); |
427 | if (err) { | |
e8159181 JQ |
428 | dev_err(gpio->dev, "failed to init gpio chip for port%d\n", |
429 | port->idx); | |
7779b345 JI |
430 | return err; |
431 | } | |
432 | ||
3d2613c4 | 433 | #ifdef CONFIG_OF_GPIO |
4ba8cfa7 | 434 | port->gc.of_node = to_of_node(pp->fwnode); |
3d2613c4 | 435 | #endif |
0f4630f3 LW |
436 | port->gc.ngpio = pp->ngpio; |
437 | port->gc.base = pp->gpio_base; | |
7779b345 | 438 | |
5d60d9ef WC |
439 | /* Only port A support debounce */ |
440 | if (pp->idx == 0) | |
2956b5d9 | 441 | port->gc.set_config = dwapb_gpio_set_config; |
5d60d9ef | 442 | |
3d2613c4 WC |
443 | if (pp->irq) |
444 | dwapb_configure_irqs(gpio, port, pp); | |
7779b345 | 445 | |
0f4630f3 | 446 | err = gpiochip_add_data(&port->gc, port); |
7779b345 | 447 | if (err) |
e8159181 JQ |
448 | dev_err(gpio->dev, "failed to register gpiochip for port%d\n", |
449 | port->idx); | |
7779b345 JI |
450 | else |
451 | port->is_registered = true; | |
452 | ||
e6cb3486 JQ |
453 | /* Add GPIO-signaled ACPI event support */ |
454 | if (pp->irq) | |
455 | acpi_gpiochip_request_interrupts(&port->gc); | |
456 | ||
7779b345 JI |
457 | return err; |
458 | } | |
459 | ||
460 | static void dwapb_gpio_unregister(struct dwapb_gpio *gpio) | |
461 | { | |
462 | unsigned int m; | |
463 | ||
464 | for (m = 0; m < gpio->nr_ports; ++m) | |
465 | if (gpio->ports[m].is_registered) | |
0f4630f3 | 466 | gpiochip_remove(&gpio->ports[m].gc); |
7779b345 JI |
467 | } |
468 | ||
3d2613c4 | 469 | static struct dwapb_platform_data * |
4ba8cfa7 | 470 | dwapb_gpio_get_pdata(struct device *dev) |
3d2613c4 | 471 | { |
4ba8cfa7 | 472 | struct fwnode_handle *fwnode; |
3d2613c4 WC |
473 | struct dwapb_platform_data *pdata; |
474 | struct dwapb_port_property *pp; | |
475 | int nports; | |
476 | int i; | |
477 | ||
4ba8cfa7 | 478 | nports = device_get_child_node_count(dev); |
3d2613c4 WC |
479 | if (nports == 0) |
480 | return ERR_PTR(-ENODEV); | |
481 | ||
da9df93e | 482 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
3d2613c4 WC |
483 | if (!pdata) |
484 | return ERR_PTR(-ENOMEM); | |
485 | ||
da9df93e AL |
486 | pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); |
487 | if (!pdata->properties) | |
3d2613c4 | 488 | return ERR_PTR(-ENOMEM); |
3d2613c4 WC |
489 | |
490 | pdata->nports = nports; | |
491 | ||
492 | i = 0; | |
4ba8cfa7 | 493 | device_for_each_child_node(dev, fwnode) { |
3d2613c4 | 494 | pp = &pdata->properties[i++]; |
4ba8cfa7 | 495 | pp->fwnode = fwnode; |
3d2613c4 | 496 | |
4ba8cfa7 | 497 | if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || |
3d2613c4 | 498 | pp->idx >= DWAPB_MAX_PORTS) { |
e8159181 JQ |
499 | dev_err(dev, |
500 | "missing/invalid port index for port%d\n", i); | |
bfab7c8f | 501 | fwnode_handle_put(fwnode); |
3d2613c4 WC |
502 | return ERR_PTR(-EINVAL); |
503 | } | |
504 | ||
4ba8cfa7 | 505 | if (fwnode_property_read_u32(fwnode, "snps,nr-gpios", |
3d2613c4 | 506 | &pp->ngpio)) { |
e8159181 JQ |
507 | dev_info(dev, |
508 | "failed to get number of gpios for port%d\n", | |
509 | i); | |
3d2613c4 WC |
510 | pp->ngpio = 32; |
511 | } | |
512 | ||
513 | /* | |
514 | * Only port A can provide interrupts in all configurations of | |
515 | * the IP. | |
516 | */ | |
4ba8cfa7 JQ |
517 | if (dev->of_node && pp->idx == 0 && |
518 | fwnode_property_read_bool(fwnode, | |
519 | "interrupt-controller")) { | |
520 | pp->irq = irq_of_parse_and_map(to_of_node(fwnode), 0); | |
e8159181 JQ |
521 | if (!pp->irq) |
522 | dev_warn(dev, "no irq for port%d\n", pp->idx); | |
3d2613c4 WC |
523 | } |
524 | ||
e6cb3486 JQ |
525 | if (has_acpi_companion(dev) && pp->idx == 0) |
526 | pp->irq = platform_get_irq(to_platform_device(dev), 0); | |
527 | ||
3d2613c4 WC |
528 | pp->irq_shared = false; |
529 | pp->gpio_base = -1; | |
3d2613c4 WC |
530 | } |
531 | ||
532 | return pdata; | |
533 | } | |
534 | ||
7779b345 JI |
535 | static int dwapb_gpio_probe(struct platform_device *pdev) |
536 | { | |
3d2613c4 | 537 | unsigned int i; |
7779b345 JI |
538 | struct resource *res; |
539 | struct dwapb_gpio *gpio; | |
7779b345 | 540 | int err; |
3d2613c4 WC |
541 | struct device *dev = &pdev->dev; |
542 | struct dwapb_platform_data *pdata = dev_get_platdata(dev); | |
3d2613c4 | 543 | |
da9df93e | 544 | if (!pdata) { |
4ba8cfa7 | 545 | pdata = dwapb_gpio_get_pdata(dev); |
3d2613c4 WC |
546 | if (IS_ERR(pdata)) |
547 | return PTR_ERR(pdata); | |
548 | } | |
7779b345 | 549 | |
da9df93e AL |
550 | if (!pdata->nports) |
551 | return -ENODEV; | |
7779b345 | 552 | |
3d2613c4 | 553 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); |
da9df93e AL |
554 | if (!gpio) |
555 | return -ENOMEM; | |
556 | ||
3d2613c4 WC |
557 | gpio->dev = &pdev->dev; |
558 | gpio->nr_ports = pdata->nports; | |
559 | ||
560 | gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, | |
7779b345 | 561 | sizeof(*gpio->ports), GFP_KERNEL); |
da9df93e AL |
562 | if (!gpio->ports) |
563 | return -ENOMEM; | |
7779b345 JI |
564 | |
565 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
566 | gpio->regs = devm_ioremap_resource(&pdev->dev, res); | |
da9df93e AL |
567 | if (IS_ERR(gpio->regs)) |
568 | return PTR_ERR(gpio->regs); | |
7779b345 | 569 | |
3d2613c4 WC |
570 | for (i = 0; i < gpio->nr_ports; i++) { |
571 | err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); | |
7779b345 JI |
572 | if (err) |
573 | goto out_unregister; | |
574 | } | |
575 | platform_set_drvdata(pdev, gpio); | |
576 | ||
da9df93e | 577 | return 0; |
7779b345 JI |
578 | |
579 | out_unregister: | |
580 | dwapb_gpio_unregister(gpio); | |
581 | dwapb_irq_teardown(gpio); | |
582 | ||
7779b345 JI |
583 | return err; |
584 | } | |
585 | ||
586 | static int dwapb_gpio_remove(struct platform_device *pdev) | |
587 | { | |
588 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
589 | ||
590 | dwapb_gpio_unregister(gpio); | |
591 | dwapb_irq_teardown(gpio); | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | static const struct of_device_id dwapb_of_match[] = { | |
597 | { .compatible = "snps,dw-apb-gpio" }, | |
598 | { /* Sentinel */ } | |
599 | }; | |
600 | MODULE_DEVICE_TABLE(of, dwapb_of_match); | |
601 | ||
e6cb3486 JQ |
602 | static const struct acpi_device_id dwapb_acpi_match[] = { |
603 | {"HISI0181", 0}, | |
1b0d5287 | 604 | {"APMC0D07", 0}, |
e6cb3486 JQ |
605 | { } |
606 | }; | |
607 | MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match); | |
608 | ||
1e960dbb WC |
609 | #ifdef CONFIG_PM_SLEEP |
610 | static int dwapb_gpio_suspend(struct device *dev) | |
611 | { | |
612 | struct platform_device *pdev = to_platform_device(dev); | |
613 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
0f4630f3 | 614 | struct gpio_chip *gc = &gpio->ports[0].gc; |
1e960dbb WC |
615 | unsigned long flags; |
616 | int i; | |
617 | ||
0f4630f3 | 618 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
1e960dbb WC |
619 | for (i = 0; i < gpio->nr_ports; i++) { |
620 | unsigned int offset; | |
621 | unsigned int idx = gpio->ports[i].idx; | |
622 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
623 | ||
58a3b92d | 624 | BUG_ON(!ctx); |
1e960dbb WC |
625 | |
626 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE; | |
627 | ctx->dir = dwapb_read(gpio, offset); | |
628 | ||
629 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE; | |
630 | ctx->data = dwapb_read(gpio, offset); | |
631 | ||
632 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE; | |
633 | ctx->ext = dwapb_read(gpio, offset); | |
634 | ||
635 | /* Only port A can provide interrupts */ | |
636 | if (idx == 0) { | |
637 | ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); | |
638 | ctx->int_en = dwapb_read(gpio, GPIO_INTEN); | |
639 | ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); | |
640 | ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); | |
641 | ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
642 | ||
643 | /* Mask out interrupts */ | |
644 | dwapb_write(gpio, GPIO_INTMASK, 0xffffffff); | |
645 | } | |
646 | } | |
0f4630f3 | 647 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
1e960dbb WC |
648 | |
649 | return 0; | |
650 | } | |
651 | ||
652 | static int dwapb_gpio_resume(struct device *dev) | |
653 | { | |
654 | struct platform_device *pdev = to_platform_device(dev); | |
655 | struct dwapb_gpio *gpio = platform_get_drvdata(pdev); | |
0f4630f3 | 656 | struct gpio_chip *gc = &gpio->ports[0].gc; |
1e960dbb WC |
657 | unsigned long flags; |
658 | int i; | |
659 | ||
0f4630f3 | 660 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
1e960dbb WC |
661 | for (i = 0; i < gpio->nr_ports; i++) { |
662 | unsigned int offset; | |
663 | unsigned int idx = gpio->ports[i].idx; | |
664 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
665 | ||
58a3b92d | 666 | BUG_ON(!ctx); |
1e960dbb WC |
667 | |
668 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE; | |
669 | dwapb_write(gpio, offset, ctx->data); | |
670 | ||
671 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE; | |
672 | dwapb_write(gpio, offset, ctx->dir); | |
673 | ||
674 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE; | |
675 | dwapb_write(gpio, offset, ctx->ext); | |
676 | ||
677 | /* Only port A can provide interrupts */ | |
678 | if (idx == 0) { | |
679 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); | |
680 | dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); | |
681 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); | |
682 | dwapb_write(gpio, GPIO_INTEN, ctx->int_en); | |
683 | dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); | |
684 | ||
685 | /* Clear out spurious interrupts */ | |
686 | dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); | |
687 | } | |
688 | } | |
0f4630f3 | 689 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
1e960dbb WC |
690 | |
691 | return 0; | |
692 | } | |
693 | #endif | |
694 | ||
695 | static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend, | |
696 | dwapb_gpio_resume); | |
697 | ||
7779b345 JI |
698 | static struct platform_driver dwapb_gpio_driver = { |
699 | .driver = { | |
700 | .name = "gpio-dwapb", | |
1e960dbb | 701 | .pm = &dwapb_gpio_pm_ops, |
7779b345 | 702 | .of_match_table = of_match_ptr(dwapb_of_match), |
e6cb3486 | 703 | .acpi_match_table = ACPI_PTR(dwapb_acpi_match), |
7779b345 JI |
704 | }, |
705 | .probe = dwapb_gpio_probe, | |
706 | .remove = dwapb_gpio_remove, | |
707 | }; | |
708 | ||
709 | module_platform_driver(dwapb_gpio_driver); | |
710 | ||
711 | MODULE_LICENSE("GPL"); | |
712 | MODULE_AUTHOR("Jamie Iles"); | |
713 | MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver"); |