[mirror_ubuntu-zesty-kernel.git] / drivers / gpio / gpio-dwapb.c

/*
 * Copyright (c) 2011 Jamie Iles
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * All enquiries to support@picochip.com
 */
#include <linux/basic_mmio_gpio.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/platform_data/gpio-dwapb.h>
#include <linux/slab.h>

#define GPIO_SWPORTA_DR		0x00
#define GPIO_SWPORTA_DDR	0x04
#define GPIO_SWPORTB_DR		0x0c
#define GPIO_SWPORTB_DDR	0x10
#define GPIO_SWPORTC_DR		0x18
#define GPIO_SWPORTC_DDR	0x1c
#define GPIO_SWPORTD_DR		0x24
#define GPIO_SWPORTD_DDR	0x28
#define GPIO_INTEN		0x30
#define GPIO_INTMASK		0x34
#define GPIO_INTTYPE_LEVEL	0x38
#define GPIO_INT_POLARITY	0x3c
#define GPIO_INTSTATUS		0x40
#define GPIO_PORTA_DEBOUNCE	0x48
#define GPIO_PORTA_EOI		0x4c
#define GPIO_EXT_PORTA		0x50
#define GPIO_EXT_PORTB		0x54
#define GPIO_EXT_PORTC		0x58
#define GPIO_EXT_PORTD		0x5c

#define DWAPB_MAX_PORTS		4
#define GPIO_EXT_PORT_SIZE	(GPIO_EXT_PORTB - GPIO_EXT_PORTA)
#define GPIO_SWPORT_DR_SIZE	(GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
#define GPIO_SWPORT_DDR_SIZE	(GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)

struct dwapb_gpio;

struct dwapb_gpio_port {
	struct bgpio_chip	bgc;
	bool			is_registered;
	struct dwapb_gpio	*gpio;
};

struct dwapb_gpio {
	struct	device		*dev;
	void __iomem		*regs;
	struct dwapb_gpio_port	*ports;
	unsigned int		nr_ports;
	struct irq_domain	*domain;
};

static inline struct dwapb_gpio_port *
to_dwapb_gpio_port(struct bgpio_chip *bgc)
{
	return container_of(bgc, struct dwapb_gpio_port, bgc);
}

static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
{
	struct bgpio_chip *bgc	= &gpio->ports[0].bgc;
	void __iomem *reg_base	= gpio->regs;

	return bgc->read_reg(reg_base + offset);
}

static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
			       u32 val)
{
	struct bgpio_chip *bgc	= &gpio->ports[0].bgc;
	void __iomem *reg_base	= gpio->regs;

	bgc->write_reg(reg_base + offset, val);
}

static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
	struct dwapb_gpio *gpio = port->gpio;

	return irq_find_mapping(gpio->domain, offset);
}

static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
{
	u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);

	if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
		v &= ~BIT(offs);
	else
		v |= BIT(offs);

	dwapb_write(gpio, GPIO_INT_POLARITY, v);
}

static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
{
	u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
	u32 ret = irq_status;

	while (irq_status) {
		int hwirq = fls(irq_status) - 1;
		int gpio_irq = irq_find_mapping(gpio->domain, hwirq);

		generic_handle_irq(gpio_irq);
		irq_status &= ~BIT(hwirq);

		if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
			== IRQ_TYPE_EDGE_BOTH)
			dwapb_toggle_trigger(gpio, hwirq);
	}

	return ret;
}

static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
{
	struct dwapb_gpio *gpio = irq_get_handler_data(irq);
	struct irq_chip *chip = irq_desc_get_chip(desc);

	dwapb_do_irq(gpio);

	if (chip->irq_eoi)
		chip->irq_eoi(irq_desc_get_irq_data(desc));
}

static void dwapb_irq_enable(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&bgc->lock, flags);
	val = dwapb_read(gpio, GPIO_INTEN);
	val |= BIT(d->hwirq);
	dwapb_write(gpio, GPIO_INTEN, val);
	spin_unlock_irqrestore(&bgc->lock, flags);
}

static void dwapb_irq_disable(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&bgc->lock, flags);
	val = dwapb_read(gpio, GPIO_INTEN);
	val &= ~BIT(d->hwirq);
	dwapb_write(gpio, GPIO_INTEN, val);
	spin_unlock_irqrestore(&bgc->lock, flags);
}

static int dwapb_irq_reqres(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;

	if (gpio_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
		dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
			irqd_to_hwirq(d));
		return -EINVAL;
	}
	return 0;
}

static void dwapb_irq_relres(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;

	gpio_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
}

static int dwapb_irq_set_type(struct irq_data *d, u32 type)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	int bit = d->hwirq;
	unsigned long level, polarity, flags;

	if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
		     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
		return -EINVAL;

	spin_lock_irqsave(&bgc->lock, flags);
	level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
	polarity = dwapb_read(gpio, GPIO_INT_POLARITY);

	switch (type) {
	case IRQ_TYPE_EDGE_BOTH:
		level |= BIT(bit);
		dwapb_toggle_trigger(gpio, bit);
		break;
	case IRQ_TYPE_EDGE_RISING:
		level |= BIT(bit);
		polarity |= BIT(bit);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		level |= BIT(bit);
		polarity &= ~BIT(bit);
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		level &= ~BIT(bit);
		polarity |= BIT(bit);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		level &= ~BIT(bit);
		polarity &= ~BIT(bit);
		break;
	}

	irq_setup_alt_chip(d, type);

	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
	dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
				   unsigned offset, unsigned debounce)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
	struct dwapb_gpio *gpio = port->gpio;
	unsigned long flags, val_deb;
	unsigned long mask = bgc->pin2mask(bgc, offset);

	spin_lock_irqsave(&bgc->lock, flags);

	val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
	if (debounce)
		dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
	else
		dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
{
	u32 worked;
	struct dwapb_gpio *gpio = dev_id;

	worked = dwapb_do_irq(gpio);

	return worked ? IRQ_HANDLED : IRQ_NONE;
}

static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
				 struct dwapb_gpio_port *port,
				 struct dwapb_port_property *pp)
{
	struct gpio_chip *gc = &port->bgc.gc;
	struct device_node *node = pp->node;
	struct irq_chip_generic	*irq_gc = NULL;
	unsigned int hwirq, ngpio = gc->ngpio;
	struct irq_chip_type *ct;
	int err, i;

	gpio->domain = irq_domain_add_linear(node, ngpio,
					     &irq_generic_chip_ops, gpio);
	if (!gpio->domain)
		return;

	err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
					     "gpio-dwapb", handle_level_irq,
					     IRQ_NOREQUEST, 0,
					     IRQ_GC_INIT_NESTED_LOCK);
	if (err) {
		dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
		irq_domain_remove(gpio->domain);
		gpio->domain = NULL;
		return;
	}

	irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
	if (!irq_gc) {
		irq_domain_remove(gpio->domain);
		gpio->domain = NULL;
		return;
	}

	irq_gc->reg_base = gpio->regs;
	irq_gc->private = gpio;

	for (i = 0; i < 2; i++) {
		ct = &irq_gc->chip_types[i];
		ct->chip.irq_ack = irq_gc_ack_set_bit;
		ct->chip.irq_mask = irq_gc_mask_set_bit;
		ct->chip.irq_unmask = irq_gc_mask_clr_bit;
		ct->chip.irq_set_type = dwapb_irq_set_type;
		ct->chip.irq_enable = dwapb_irq_enable;
		ct->chip.irq_disable = dwapb_irq_disable;
		ct->chip.irq_request_resources = dwapb_irq_reqres;
		ct->chip.irq_release_resources = dwapb_irq_relres;
		ct->regs.ack = GPIO_PORTA_EOI;
		ct->regs.mask = GPIO_INTMASK;
		ct->type = IRQ_TYPE_LEVEL_MASK;
	}

	irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
	irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
	irq_gc->chip_types[1].handler = handle_edge_irq;

	if (!pp->irq_shared) {
		irq_set_chained_handler(pp->irq, dwapb_irq_handler);
		irq_set_handler_data(pp->irq, gpio);
	} else {
		/*
		 * Request a shared IRQ since where MFD would have devices
		 * using the same irq pin
		 */
		err = devm_request_irq(gpio->dev, pp->irq,
				       dwapb_irq_handler_mfd,
				       IRQF_SHARED, "gpio-dwapb-mfd", gpio);
		if (err) {
			dev_err(gpio->dev, "error requesting IRQ\n");
			irq_domain_remove(gpio->domain);
			gpio->domain = NULL;
			return;
		}
	}

	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
		irq_create_mapping(gpio->domain, hwirq);

	port->bgc.gc.to_irq = dwapb_gpio_to_irq;
}

static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
{
	struct dwapb_gpio_port *port = &gpio->ports[0];
	struct gpio_chip *gc = &port->bgc.gc;
	unsigned int ngpio = gc->ngpio;
	irq_hw_number_t hwirq;

	if (!gpio->domain)
		return;

	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
		irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));

	irq_domain_remove(gpio->domain);
	gpio->domain = NULL;
}

static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
			       struct dwapb_port_property *pp,
			       unsigned int offs)
{
	struct dwapb_gpio_port *port;
	void __iomem *dat, *set, *dirout;
	int err;

	port = &gpio->ports[offs];
	port->gpio = gpio;

	dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
	set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
	dirout = gpio->regs + GPIO_SWPORTA_DDR +
		(pp->idx * GPIO_SWPORT_DDR_SIZE);

	err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
			 NULL, false);
	if (err) {
		dev_err(gpio->dev, "failed to init gpio chip for %s\n",
			pp->name);
		return err;
	}

#ifdef CONFIG_OF_GPIO
	port->bgc.gc.of_node = pp->node;
#endif
	port->bgc.gc.ngpio = pp->ngpio;
	port->bgc.gc.base = pp->gpio_base;

	/* Only port A support debounce */
	if (pp->idx == 0)
		port->bgc.gc.set_debounce = dwapb_gpio_set_debounce;

	if (pp->irq)
		dwapb_configure_irqs(gpio, port, pp);

	err = gpiochip_add(&port->bgc.gc);
	if (err)
		dev_err(gpio->dev, "failed to register gpiochip for %s\n",
			pp->name);
	else
		port->is_registered = true;

	return err;
}

static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
{
	unsigned int m;

	for (m = 0; m < gpio->nr_ports; ++m)
		if (gpio->ports[m].is_registered)
			gpiochip_remove(&gpio->ports[m].bgc.gc);
}

static struct dwapb_platform_data *
dwapb_gpio_get_pdata_of(struct device *dev)
{
	struct device_node *node, *port_np;
	struct dwapb_platform_data *pdata;
	struct dwapb_port_property *pp;
	int nports;
	int i;

	node = dev->of_node;
	if (!IS_ENABLED(CONFIG_OF_GPIO) || !node)
		return ERR_PTR(-ENODEV);

	nports = of_get_child_count(node);
	if (nports == 0)
		return ERR_PTR(-ENODEV);

	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return ERR_PTR(-ENOMEM);

	pdata->properties = kcalloc(nports, sizeof(*pp), GFP_KERNEL);
	if (!pdata->properties) {
		kfree(pdata);
		return ERR_PTR(-ENOMEM);
	}

	pdata->nports = nports;

	i = 0;
	for_each_child_of_node(node, port_np) {
		pp = &pdata->properties[i++];
		pp->node = port_np;

		if (of_property_read_u32(port_np, "reg", &pp->idx) ||
		    pp->idx >= DWAPB_MAX_PORTS) {
			dev_err(dev, "missing/invalid port index for %s\n",
				port_np->full_name);
			kfree(pdata->properties);
			kfree(pdata);
			return ERR_PTR(-EINVAL);
		}

		if (of_property_read_u32(port_np, "snps,nr-gpios",
					 &pp->ngpio)) {
			dev_info(dev, "failed to get number of gpios for %s\n",
				 port_np->full_name);
			pp->ngpio = 32;
		}

		/*
		 * Only port A can provide interrupts in all configurations of
		 * the IP.
		 */
		if (pp->idx == 0 &&
		    of_property_read_bool(port_np, "interrupt-controller")) {
			pp->irq = irq_of_parse_and_map(port_np, 0);
			if (!pp->irq) {
				dev_warn(dev, "no irq for bank %s\n",
					 port_np->full_name);
			}
		}

		pp->irq_shared	= false;
		pp->gpio_base	= -1;
		pp->name	= port_np->full_name;
	}

	return pdata;
}

static inline void dwapb_free_pdata_of(struct dwapb_platform_data *pdata)
{
	if (!IS_ENABLED(CONFIG_OF_GPIO) || !pdata)
		return;

	kfree(pdata->properties);
	kfree(pdata);
}

static int dwapb_gpio_probe(struct platform_device *pdev)
{
	unsigned int i;
	struct resource *res;
	struct dwapb_gpio *gpio;
	int err;
	struct device *dev = &pdev->dev;
	struct dwapb_platform_data *pdata = dev_get_platdata(dev);
	bool is_pdata_alloc = !pdata;

	if (is_pdata_alloc) {
		pdata = dwapb_gpio_get_pdata_of(dev);
		if (IS_ERR(pdata))
			return PTR_ERR(pdata);
	}

	if (!pdata->nports) {
		err = -ENODEV;
		goto out_err;
	}

	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	if (!gpio) {
		err = -ENOMEM;
		goto out_err;
	}
	gpio->dev = &pdev->dev;
	gpio->nr_ports = pdata->nports;

	gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
				   sizeof(*gpio->ports), GFP_KERNEL);
	if (!gpio->ports) {
		err = -ENOMEM;
		goto out_err;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	gpio->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(gpio->regs)) {
		err = PTR_ERR(gpio->regs);
		goto out_err;
	}

	for (i = 0; i < gpio->nr_ports; i++) {
		err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
		if (err)
			goto out_unregister;
	}
	platform_set_drvdata(pdev, gpio);

	goto out_err;

out_unregister:
	dwapb_gpio_unregister(gpio);
	dwapb_irq_teardown(gpio);

out_err:
	if (is_pdata_alloc)
		dwapb_free_pdata_of(pdata);

	return err;
}

static int dwapb_gpio_remove(struct platform_device *pdev)
{
	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);

	dwapb_gpio_unregister(gpio);
	dwapb_irq_teardown(gpio);

	return 0;
}

static const struct of_device_id dwapb_of_match[] = {
	{ .compatible = "snps,dw-apb-gpio" },
	{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dwapb_of_match);

static struct platform_driver dwapb_gpio_driver = {
	.driver		= {
		.name	= "gpio-dwapb",
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(dwapb_of_match),
	},
	.probe		= dwapb_gpio_probe,
	.remove		= dwapb_gpio_remove,
};

module_platform_driver(dwapb_gpio_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jamie Iles");
MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
Commit	Line	Data
7779b345 JI	1	/*
	2	* Copyright (c) 2011 Jamie Iles
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* All enquiries to support@picochip.com
	9	*/
	10	#include <linux/basic_mmio_gpio.h>
	11	#include <linux/err.h>
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/io.h>
	15	#include <linux/ioport.h>
	16	#include <linux/irq.h>
	17	#include <linux/irqdomain.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_address.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/spinlock.h>
3d2613c4 WC	24	#include <linux/platform_data/gpio-dwapb.h>
3d2613c4 WC	25	#include <linux/slab.h>
7779b345 JI	26
	27	#define GPIO_SWPORTA_DR 0x00
	28	#define GPIO_SWPORTA_DDR 0x04
	29	#define GPIO_SWPORTB_DR 0x0c
	30	#define GPIO_SWPORTB_DDR 0x10
	31	#define GPIO_SWPORTC_DR 0x18
	32	#define GPIO_SWPORTC_DDR 0x1c
	33	#define GPIO_SWPORTD_DR 0x24
	34	#define GPIO_SWPORTD_DDR 0x28
	35	#define GPIO_INTEN 0x30
	36	#define GPIO_INTMASK 0x34
	37	#define GPIO_INTTYPE_LEVEL 0x38
	38	#define GPIO_INT_POLARITY 0x3c
	39	#define GPIO_INTSTATUS 0x40
5d60d9ef	40	#define GPIO_PORTA_DEBOUNCE 0x48
7779b345 JI	41	#define GPIO_PORTA_EOI 0x4c
	42	#define GPIO_EXT_PORTA 0x50
	43	#define GPIO_EXT_PORTB 0x54
	44	#define GPIO_EXT_PORTC 0x58
	45	#define GPIO_EXT_PORTD 0x5c
	46
	47	#define DWAPB_MAX_PORTS 4
	48	#define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
	49	#define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
	50	#define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
	51
	52	struct dwapb_gpio;
	53
	54	struct dwapb_gpio_port {
	55	struct bgpio_chip bgc;
	56	bool is_registered;
	57	struct dwapb_gpio *gpio;
	58	};
	59
	60	struct dwapb_gpio {
	61	struct device *dev;
	62	void __iomem *regs;
	63	struct dwapb_gpio_port *ports;
	64	unsigned int nr_ports;
	65	struct irq_domain *domain;
	66	};
	67
5d60d9ef WC	68	static inline struct dwapb_gpio_port *
	69	to_dwapb_gpio_port(struct bgpio_chip *bgc)
	70	{
	71	return container_of(bgc, struct dwapb_gpio_port, bgc);
	72	}
	73
67809b97 WC	74	static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
	75	{
	76	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	77	void __iomem *reg_base = gpio->regs;
	78
	79	return bgc->read_reg(reg_base + offset);
	80	}
	81
	82	static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
	83	u32 val)
	84	{
	85	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	86	void __iomem *reg_base = gpio->regs;
	87
	88	bgc->write_reg(reg_base + offset, val);
	89	}
	90
7779b345 JI	91	static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
	92	{
	93	struct bgpio_chip *bgc = to_bgpio_chip(gc);
5d60d9ef	94	struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
7779b345 JI	95	struct dwapb_gpio *gpio = port->gpio;
	96
	97	return irq_find_mapping(gpio->domain, offset);
	98	}
	99
	100	static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
	101	{
67809b97	102	u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
7779b345 JI	103
	104	if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
	105	v &= ~BIT(offs);
	106	else
	107	v \|= BIT(offs);
	108
67809b97	109	dwapb_write(gpio, GPIO_INT_POLARITY, v);
7779b345 JI	110	}
7779b345 JI	111
3d2613c4	112	static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
7779b345	113	{
7779b345	114	u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
3d2613c4	115	u32 ret = irq_status;
7779b345 JI	116
	117	while (irq_status) {
	118	int hwirq = fls(irq_status) - 1;
	119	int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
	120
	121	generic_handle_irq(gpio_irq);
	122	irq_status &= ~BIT(hwirq);
	123
	124	if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
	125	== IRQ_TYPE_EDGE_BOTH)
	126	dwapb_toggle_trigger(gpio, hwirq);
	127	}
	128
3d2613c4 WC	129	return ret;
	130	}
	131
	132	static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
	133	{
	134	struct dwapb_gpio *gpio = irq_get_handler_data(irq);
	135	struct irq_chip *chip = irq_desc_get_chip(desc);
	136
	137	dwapb_do_irq(gpio);
	138
7779b345 JI	139	if (chip->irq_eoi)
	140	chip->irq_eoi(irq_desc_get_irq_data(desc));
	141	}
	142
	143	static void dwapb_irq_enable(struct irq_data *d)
	144	{
	145	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	146	struct dwapb_gpio *gpio = igc->private;
	147	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	148	unsigned long flags;
	149	u32 val;
	150
	151	spin_lock_irqsave(&bgc->lock, flags);
67809b97	152	val = dwapb_read(gpio, GPIO_INTEN);
7779b345	153	val \|= BIT(d->hwirq);
67809b97	154	dwapb_write(gpio, GPIO_INTEN, val);
7779b345 JI	155	spin_unlock_irqrestore(&bgc->lock, flags);
	156	}
	157
	158	static void dwapb_irq_disable(struct irq_data *d)
	159	{
	160	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	161	struct dwapb_gpio *gpio = igc->private;
	162	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	163	unsigned long flags;
	164	u32 val;
	165
	166	spin_lock_irqsave(&bgc->lock, flags);
67809b97	167	val = dwapb_read(gpio, GPIO_INTEN);
7779b345	168	val &= ~BIT(d->hwirq);
67809b97	169	dwapb_write(gpio, GPIO_INTEN, val);
7779b345 JI	170	spin_unlock_irqrestore(&bgc->lock, flags);
	171	}
	172
57ef0428	173	static int dwapb_irq_reqres(struct irq_data *d)
7779b345 JI	174	{
	175	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	176	struct dwapb_gpio *gpio = igc->private;
	177	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	178
57ef0428	179	if (gpio_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
7779b345 JI	180	dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
7779b345 JI	181	irqd_to_hwirq(d));
57ef0428 LW	182	return -EINVAL;
57ef0428 LW	183	}
7779b345 JI	184	return 0;
	185	}
	186
57ef0428	187	static void dwapb_irq_relres(struct irq_data *d)
7779b345 JI	188	{
	189	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	190	struct dwapb_gpio *gpio = igc->private;
	191	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	192
7779b345 JI	193	gpio_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
	194	}
	195
	196	static int dwapb_irq_set_type(struct irq_data *d, u32 type)
	197	{
	198	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	199	struct dwapb_gpio *gpio = igc->private;
	200	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	201	int bit = d->hwirq;
	202	unsigned long level, polarity, flags;
	203
	204	if (type & ~(IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING \|
	205	IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW))
	206	return -EINVAL;
	207
	208	spin_lock_irqsave(&bgc->lock, flags);
67809b97 WC	209	level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
67809b97 WC	210	polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
7779b345 JI	211
	212	switch (type) {
	213	case IRQ_TYPE_EDGE_BOTH:
	214	level \|= BIT(bit);
	215	dwapb_toggle_trigger(gpio, bit);
	216	break;
	217	case IRQ_TYPE_EDGE_RISING:
	218	level \|= BIT(bit);
	219	polarity \|= BIT(bit);
	220	break;
	221	case IRQ_TYPE_EDGE_FALLING:
	222	level \|= BIT(bit);
	223	polarity &= ~BIT(bit);
	224	break;
	225	case IRQ_TYPE_LEVEL_HIGH:
	226	level &= ~BIT(bit);
	227	polarity \|= BIT(bit);
	228	break;
	229	case IRQ_TYPE_LEVEL_LOW:
	230	level &= ~BIT(bit);
	231	polarity &= ~BIT(bit);
	232	break;
	233	}
	234
6a2f4b7d SAS	235	irq_setup_alt_chip(d, type);
6a2f4b7d SAS	236
67809b97 WC	237	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
67809b97 WC	238	dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
7779b345 JI	239	spin_unlock_irqrestore(&bgc->lock, flags);
	240
	241	return 0;
	242	}
	243
5d60d9ef WC	244	static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
	245	unsigned offset, unsigned debounce)
	246	{
	247	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	248	struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
	249	struct dwapb_gpio *gpio = port->gpio;
	250	unsigned long flags, val_deb;
	251	unsigned long mask = bgc->pin2mask(bgc, offset);
	252
	253	spin_lock_irqsave(&bgc->lock, flags);
	254
	255	val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
	256	if (debounce)
	257	dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb \| mask);
	258	else
	259	dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
	260
	261	spin_unlock_irqrestore(&bgc->lock, flags);
	262
	263	return 0;
	264	}
	265
3d2613c4 WC	266	static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
	267	{
	268	u32 worked;
	269	struct dwapb_gpio *gpio = dev_id;
	270
	271	worked = dwapb_do_irq(gpio);
	272
	273	return worked ? IRQ_HANDLED : IRQ_NONE;
	274	}
	275
7779b345	276	static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
3d2613c4 WC	277	struct dwapb_gpio_port *port,
3d2613c4 WC	278	struct dwapb_port_property *pp)
7779b345 JI	279	{
7779b345 JI	280	struct gpio_chip *gc = &port->bgc.gc;
3d2613c4 WC	281	struct device_node *node = pp->node;
3d2613c4 WC	282	struct irq_chip_generic *irq_gc = NULL;
7779b345 JI	283	unsigned int hwirq, ngpio = gc->ngpio;
7779b345 JI	284	struct irq_chip_type *ct;
3d2613c4	285	int err, i;
7779b345 JI	286
	287	gpio->domain = irq_domain_add_linear(node, ngpio,
	288	&irq_generic_chip_ops, gpio);
	289	if (!gpio->domain)
	290	return;
	291
6a2f4b7d	292	err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
7779b345 JI	293	"gpio-dwapb", handle_level_irq,
	294	IRQ_NOREQUEST, 0,
	295	IRQ_GC_INIT_NESTED_LOCK);
	296	if (err) {
	297	dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
	298	irq_domain_remove(gpio->domain);
	299	gpio->domain = NULL;
	300	return;
	301	}
	302
	303	irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
	304	if (!irq_gc) {
	305	irq_domain_remove(gpio->domain);
	306	gpio->domain = NULL;
	307	return;
	308	}
	309
	310	irq_gc->reg_base = gpio->regs;
	311	irq_gc->private = gpio;
	312
6a2f4b7d SAS	313	for (i = 0; i < 2; i++) {
	314	ct = &irq_gc->chip_types[i];
	315	ct->chip.irq_ack = irq_gc_ack_set_bit;
	316	ct->chip.irq_mask = irq_gc_mask_set_bit;
	317	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
	318	ct->chip.irq_set_type = dwapb_irq_set_type;
	319	ct->chip.irq_enable = dwapb_irq_enable;
	320	ct->chip.irq_disable = dwapb_irq_disable;
	321	ct->chip.irq_request_resources = dwapb_irq_reqres;
	322	ct->chip.irq_release_resources = dwapb_irq_relres;
	323	ct->regs.ack = GPIO_PORTA_EOI;
	324	ct->regs.mask = GPIO_INTMASK;
	325	ct->type = IRQ_TYPE_LEVEL_MASK;
	326	}
	327
	328	irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
	329	irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
	330	irq_gc->chip_types[1].handler = handle_edge_irq;
7779b345	331
3d2613c4 WC	332	if (!pp->irq_shared) {
	333	irq_set_chained_handler(pp->irq, dwapb_irq_handler);
	334	irq_set_handler_data(pp->irq, gpio);
	335	} else {
	336	/*
	337	* Request a shared IRQ since where MFD would have devices
	338	* using the same irq pin
	339	*/
	340	err = devm_request_irq(gpio->dev, pp->irq,
	341	dwapb_irq_handler_mfd,
	342	IRQF_SHARED, "gpio-dwapb-mfd", gpio);
	343	if (err) {
	344	dev_err(gpio->dev, "error requesting IRQ\n");
	345	irq_domain_remove(gpio->domain);
	346	gpio->domain = NULL;
	347	return;
	348	}
	349	}
7779b345 JI	350
	351	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
	352	irq_create_mapping(gpio->domain, hwirq);
	353
	354	port->bgc.gc.to_irq = dwapb_gpio_to_irq;
	355	}
	356
	357	static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
	358	{
	359	struct dwapb_gpio_port *port = &gpio->ports[0];
	360	struct gpio_chip *gc = &port->bgc.gc;
	361	unsigned int ngpio = gc->ngpio;
	362	irq_hw_number_t hwirq;
	363
	364	if (!gpio->domain)
	365	return;
	366
	367	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
	368	irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
	369
	370	irq_domain_remove(gpio->domain);
	371	gpio->domain = NULL;
	372	}
	373
	374	static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
3d2613c4	375	struct dwapb_port_property *pp,
7779b345 JI	376	unsigned int offs)
	377	{
	378	struct dwapb_gpio_port *port;
7779b345 JI	379	void __iomem dat, set, *dirout;
	380	int err;
	381
7779b345 JI	382	port = &gpio->ports[offs];
	383	port->gpio = gpio;
	384
3d2613c4 WC	385	dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
3d2613c4 WC	386	set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
7779b345	387	dirout = gpio->regs + GPIO_SWPORTA_DDR +
3d2613c4	388	(pp->idx * GPIO_SWPORT_DDR_SIZE);
7779b345 JI	389
	390	err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
	391	NULL, false);
	392	if (err) {
	393	dev_err(gpio->dev, "failed to init gpio chip for %s\n",
3d2613c4	394	pp->name);
7779b345 JI	395	return err;
	396	}
	397
3d2613c4 WC	398	#ifdef CONFIG_OF_GPIO
	399	port->bgc.gc.of_node = pp->node;
	400	#endif
	401	port->bgc.gc.ngpio = pp->ngpio;
	402	port->bgc.gc.base = pp->gpio_base;
7779b345	403
5d60d9ef WC	404	/* Only port A support debounce */
	405	if (pp->idx == 0)
	406	port->bgc.gc.set_debounce = dwapb_gpio_set_debounce;
	407
3d2613c4 WC	408	if (pp->irq)
3d2613c4 WC	409	dwapb_configure_irqs(gpio, port, pp);
7779b345 JI	410
	411	err = gpiochip_add(&port->bgc.gc);
	412	if (err)
	413	dev_err(gpio->dev, "failed to register gpiochip for %s\n",
3d2613c4	414	pp->name);
7779b345 JI	415	else
	416	port->is_registered = true;
	417
	418	return err;
	419	}
	420
	421	static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
	422	{
	423	unsigned int m;
	424
	425	for (m = 0; m < gpio->nr_ports; ++m)
	426	if (gpio->ports[m].is_registered)
9f5132ae	427	gpiochip_remove(&gpio->ports[m].bgc.gc);
7779b345 JI	428	}
7779b345 JI	429
3d2613c4 WC	430	static struct dwapb_platform_data *
	431	dwapb_gpio_get_pdata_of(struct device *dev)
	432	{
	433	struct device_node node, port_np;
	434	struct dwapb_platform_data *pdata;
	435	struct dwapb_port_property *pp;
	436	int nports;
	437	int i;
	438
	439	node = dev->of_node;
	440	if (!IS_ENABLED(CONFIG_OF_GPIO) \|\| !node)
	441	return ERR_PTR(-ENODEV);
	442
	443	nports = of_get_child_count(node);
	444	if (nports == 0)
	445	return ERR_PTR(-ENODEV);
	446
	447	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
	448	if (!pdata)
	449	return ERR_PTR(-ENOMEM);
	450
	451	pdata->properties = kcalloc(nports, sizeof(*pp), GFP_KERNEL);
	452	if (!pdata->properties) {
	453	kfree(pdata);
	454	return ERR_PTR(-ENOMEM);
	455	}
	456
	457	pdata->nports = nports;
	458
	459	i = 0;
	460	for_each_child_of_node(node, port_np) {
	461	pp = &pdata->properties[i++];
	462	pp->node = port_np;
	463
	464	if (of_property_read_u32(port_np, "reg", &pp->idx) \|\|
	465	pp->idx >= DWAPB_MAX_PORTS) {
	466	dev_err(dev, "missing/invalid port index for %s\n",
	467	port_np->full_name);
	468	kfree(pdata->properties);
	469	kfree(pdata);
	470	return ERR_PTR(-EINVAL);
	471	}
	472
	473	if (of_property_read_u32(port_np, "snps,nr-gpios",
	474	&pp->ngpio)) {
	475	dev_info(dev, "failed to get number of gpios for %s\n",
	476	port_np->full_name);
	477	pp->ngpio = 32;
	478	}
	479
	480	/*
	481	* Only port A can provide interrupts in all configurations of
	482	* the IP.
	483	*/
	484	if (pp->idx == 0 &&
	485	of_property_read_bool(port_np, "interrupt-controller")) {
	486	pp->irq = irq_of_parse_and_map(port_np, 0);
	487	if (!pp->irq) {
	488	dev_warn(dev, "no irq for bank %s\n",
	489	port_np->full_name);
	490	}
	491	}
	492
	493	pp->irq_shared = false;
494	pp->gpio_base = -1;
495	pp->name = port_np->full_name;
496	}
497
498	return pdata;
499	}
500
501	static inline void dwapb_free_pdata_of(struct dwapb_platform_data *pdata)
502	{
503	if (!IS_ENABLED(CONFIG_OF_GPIO) \|\| !pdata)
504	return;
505
506	kfree(pdata->properties);
507	kfree(pdata);
508	}
509
7779b345 JI	510	static int dwapb_gpio_probe(struct platform_device *pdev)
7779b345 JI	511	{
3d2613c4	512	unsigned int i;
7779b345 JI	513	struct resource *res;
7779b345 JI	514	struct dwapb_gpio *gpio;
7779b345	515	int err;
3d2613c4 WC	516	struct device *dev = &pdev->dev;
	517	struct dwapb_platform_data *pdata = dev_get_platdata(dev);
	518	bool is_pdata_alloc = !pdata;
	519
	520	if (is_pdata_alloc) {
	521	pdata = dwapb_gpio_get_pdata_of(dev);
	522	if (IS_ERR(pdata))
	523	return PTR_ERR(pdata);
	524	}
7779b345	525
3d2613c4 WC	526	if (!pdata->nports) {
	527	err = -ENODEV;
	528	goto out_err;
	529	}
7779b345	530
3d2613c4 WC	531	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	532	if (!gpio) {
	533	err = -ENOMEM;
7779b345 JI	534	goto out_err;
7779b345 JI	535	}
3d2613c4 WC	536	gpio->dev = &pdev->dev;
	537	gpio->nr_ports = pdata->nports;
	538
	539	gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
7779b345 JI	540	sizeof(*gpio->ports), GFP_KERNEL);
	541	if (!gpio->ports) {
	542	err = -ENOMEM;
	543	goto out_err;
	544	}
	545
	546	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	547	gpio->regs = devm_ioremap_resource(&pdev->dev, res);
	548	if (IS_ERR(gpio->regs)) {
	549	err = PTR_ERR(gpio->regs);
	550	goto out_err;
	551	}
	552
3d2613c4 WC	553	for (i = 0; i < gpio->nr_ports; i++) {
3d2613c4 WC	554	err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
7779b345 JI	555	if (err)
	556	goto out_unregister;
	557	}
	558	platform_set_drvdata(pdev, gpio);
	559
3d2613c4	560	goto out_err;
7779b345 JI	561
	562	out_unregister:
	563	dwapb_gpio_unregister(gpio);
	564	dwapb_irq_teardown(gpio);
	565
	566	out_err:
3d2613c4 WC	567	if (is_pdata_alloc)
	568	dwapb_free_pdata_of(pdata);
	569
7779b345 JI	570	return err;
	571	}
	572
	573	static int dwapb_gpio_remove(struct platform_device *pdev)
	574	{
	575	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
	576
	577	dwapb_gpio_unregister(gpio);
	578	dwapb_irq_teardown(gpio);
	579
	580	return 0;
	581	}
	582
	583	static const struct of_device_id dwapb_of_match[] = {
	584	{ .compatible = "snps,dw-apb-gpio" },
	585	{ /* Sentinel */ }
	586	};
	587	MODULE_DEVICE_TABLE(of, dwapb_of_match);
	588
	589	static struct platform_driver dwapb_gpio_driver = {
	590	.driver = {
	591	.name = "gpio-dwapb",
	592	.owner = THIS_MODULE,
	593	.of_match_table = of_match_ptr(dwapb_of_match),
	594	},
	595	.probe = dwapb_gpio_probe,
	596	.remove = dwapb_gpio_remove,
	597	};
	598
	599	module_platform_driver(dwapb_gpio_driver);
	600
	601	MODULE_LICENSE("GPL");
	602	MODULE_AUTHOR("Jamie Iles");
	603	MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");