[mirror_ubuntu-zesty-kernel.git] / drivers / gpio / gpio-dwapb.c

/*
 * Copyright (c) 2011 Jamie Iles
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * All enquiries to support@picochip.com
 */
#include <linux/basic_mmio_gpio.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/platform_data/gpio-dwapb.h>
#include <linux/slab.h>

#define GPIO_SWPORTA_DR		0x00
#define GPIO_SWPORTA_DDR	0x04
#define GPIO_SWPORTB_DR		0x0c
#define GPIO_SWPORTB_DDR	0x10
#define GPIO_SWPORTC_DR		0x18
#define GPIO_SWPORTC_DDR	0x1c
#define GPIO_SWPORTD_DR		0x24
#define GPIO_SWPORTD_DDR	0x28
#define GPIO_INTEN		0x30
#define GPIO_INTMASK		0x34
#define GPIO_INTTYPE_LEVEL	0x38
#define GPIO_INT_POLARITY	0x3c
#define GPIO_INTSTATUS		0x40
#define GPIO_PORTA_EOI		0x4c
#define GPIO_EXT_PORTA		0x50
#define GPIO_EXT_PORTB		0x54
#define GPIO_EXT_PORTC		0x58
#define GPIO_EXT_PORTD		0x5c

#define DWAPB_MAX_PORTS		4
#define GPIO_EXT_PORT_SIZE	(GPIO_EXT_PORTB - GPIO_EXT_PORTA)
#define GPIO_SWPORT_DR_SIZE	(GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
#define GPIO_SWPORT_DDR_SIZE	(GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)

struct dwapb_gpio;

struct dwapb_gpio_port {
	struct bgpio_chip	bgc;
	bool			is_registered;
	struct dwapb_gpio	*gpio;
};

struct dwapb_gpio {
	struct	device		*dev;
	void __iomem		*regs;
	struct dwapb_gpio_port	*ports;
	unsigned int		nr_ports;
	struct irq_domain	*domain;
};

static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
{
	struct bgpio_chip *bgc	= &gpio->ports[0].bgc;
	void __iomem *reg_base	= gpio->regs;

	return bgc->read_reg(reg_base + offset);
}

static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
			       u32 val)
{
	struct bgpio_chip *bgc	= &gpio->ports[0].bgc;
	void __iomem *reg_base	= gpio->regs;

	bgc->write_reg(reg_base + offset, val);
}

static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	struct dwapb_gpio_port *port = container_of(bgc, struct
						    dwapb_gpio_port, bgc);
	struct dwapb_gpio *gpio = port->gpio;

	return irq_find_mapping(gpio->domain, offset);
}

static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
{
	u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);

	if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
		v &= ~BIT(offs);
	else
		v |= BIT(offs);

	dwapb_write(gpio, GPIO_INT_POLARITY, v);
}

static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
{
	u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
	u32 ret = irq_status;

	while (irq_status) {
		int hwirq = fls(irq_status) - 1;
		int gpio_irq = irq_find_mapping(gpio->domain, hwirq);

		generic_handle_irq(gpio_irq);
		irq_status &= ~BIT(hwirq);

		if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
			== IRQ_TYPE_EDGE_BOTH)
			dwapb_toggle_trigger(gpio, hwirq);
	}

	return ret;
}

static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
{
	struct dwapb_gpio *gpio = irq_get_handler_data(irq);
	struct irq_chip *chip = irq_desc_get_chip(desc);

	dwapb_do_irq(gpio);

	if (chip->irq_eoi)
		chip->irq_eoi(irq_desc_get_irq_data(desc));
}

static void dwapb_irq_enable(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&bgc->lock, flags);
	val = dwapb_read(gpio, GPIO_INTEN);
	val |= BIT(d->hwirq);
	dwapb_write(gpio, GPIO_INTEN, val);
	spin_unlock_irqrestore(&bgc->lock, flags);
}

static void dwapb_irq_disable(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&bgc->lock, flags);
	val = dwapb_read(gpio, GPIO_INTEN);
	val &= ~BIT(d->hwirq);
	dwapb_write(gpio, GPIO_INTEN, val);
	spin_unlock_irqrestore(&bgc->lock, flags);
}

static int dwapb_irq_reqres(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;

	if (gpio_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
		dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
			irqd_to_hwirq(d));
		return -EINVAL;
	}
	return 0;
}

static void dwapb_irq_relres(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;

	gpio_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
}

static int dwapb_irq_set_type(struct irq_data *d, u32 type)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	int bit = d->hwirq;
	unsigned long level, polarity, flags;

	if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
		     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
		return -EINVAL;

	spin_lock_irqsave(&bgc->lock, flags);
	level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
	polarity = dwapb_read(gpio, GPIO_INT_POLARITY);

	switch (type) {
	case IRQ_TYPE_EDGE_BOTH:
		level |= BIT(bit);
		dwapb_toggle_trigger(gpio, bit);
		break;
	case IRQ_TYPE_EDGE_RISING:
		level |= BIT(bit);
		polarity |= BIT(bit);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		level |= BIT(bit);
		polarity &= ~BIT(bit);
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		level &= ~BIT(bit);
		polarity |= BIT(bit);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		level &= ~BIT(bit);
		polarity &= ~BIT(bit);
		break;
	}

	irq_setup_alt_chip(d, type);

	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
	dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
{
	u32 worked;
	struct dwapb_gpio *gpio = dev_id;

	worked = dwapb_do_irq(gpio);

	return worked ? IRQ_HANDLED : IRQ_NONE;
}

static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
				 struct dwapb_gpio_port *port,
				 struct dwapb_port_property *pp)
{
	struct gpio_chip *gc = &port->bgc.gc;
	struct device_node *node = pp->node;
	struct irq_chip_generic	*irq_gc = NULL;
	unsigned int hwirq, ngpio = gc->ngpio;
	struct irq_chip_type *ct;
	int err, i;

	gpio->domain = irq_domain_add_linear(node, ngpio,
					     &irq_generic_chip_ops, gpio);
	if (!gpio->domain)
		return;

	err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
					     "gpio-dwapb", handle_level_irq,
					     IRQ_NOREQUEST, 0,
					     IRQ_GC_INIT_NESTED_LOCK);
	if (err) {
		dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
		irq_domain_remove(gpio->domain);
		gpio->domain = NULL;
		return;
	}

	irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
	if (!irq_gc) {
		irq_domain_remove(gpio->domain);
		gpio->domain = NULL;
		return;
	}

	irq_gc->reg_base = gpio->regs;
	irq_gc->private = gpio;

	for (i = 0; i < 2; i++) {
		ct = &irq_gc->chip_types[i];
		ct->chip.irq_ack = irq_gc_ack_set_bit;
		ct->chip.irq_mask = irq_gc_mask_set_bit;
		ct->chip.irq_unmask = irq_gc_mask_clr_bit;
		ct->chip.irq_set_type = dwapb_irq_set_type;
		ct->chip.irq_enable = dwapb_irq_enable;
		ct->chip.irq_disable = dwapb_irq_disable;
		ct->chip.irq_request_resources = dwapb_irq_reqres;
		ct->chip.irq_release_resources = dwapb_irq_relres;
		ct->regs.ack = GPIO_PORTA_EOI;
		ct->regs.mask = GPIO_INTMASK;
		ct->type = IRQ_TYPE_LEVEL_MASK;
	}

	irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
	irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
	irq_gc->chip_types[1].handler = handle_edge_irq;

	if (!pp->irq_shared) {
		irq_set_chained_handler(pp->irq, dwapb_irq_handler);
		irq_set_handler_data(pp->irq, gpio);
	} else {
		/*
		 * Request a shared IRQ since where MFD would have devices
		 * using the same irq pin
		 */
		err = devm_request_irq(gpio->dev, pp->irq,
				       dwapb_irq_handler_mfd,
				       IRQF_SHARED, "gpio-dwapb-mfd", gpio);
		if (err) {
			dev_err(gpio->dev, "error requesting IRQ\n");
			irq_domain_remove(gpio->domain);
			gpio->domain = NULL;
			return;
		}
	}

	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
		irq_create_mapping(gpio->domain, hwirq);

	port->bgc.gc.to_irq = dwapb_gpio_to_irq;
}

static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
{
	struct dwapb_gpio_port *port = &gpio->ports[0];
	struct gpio_chip *gc = &port->bgc.gc;
	unsigned int ngpio = gc->ngpio;
	irq_hw_number_t hwirq;

	if (!gpio->domain)
		return;

	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
		irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));

	irq_domain_remove(gpio->domain);
	gpio->domain = NULL;
}

static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
			       struct dwapb_port_property *pp,
			       unsigned int offs)
{
	struct dwapb_gpio_port *port;
	void __iomem *dat, *set, *dirout;
	int err;

	port = &gpio->ports[offs];
	port->gpio = gpio;

	dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
	set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
	dirout = gpio->regs + GPIO_SWPORTA_DDR +
		(pp->idx * GPIO_SWPORT_DDR_SIZE);

	err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
			 NULL, false);
	if (err) {
		dev_err(gpio->dev, "failed to init gpio chip for %s\n",
			pp->name);
		return err;
	}

#ifdef CONFIG_OF_GPIO
	port->bgc.gc.of_node = pp->node;
#endif
	port->bgc.gc.ngpio = pp->ngpio;
	port->bgc.gc.base = pp->gpio_base;

	if (pp->irq)
		dwapb_configure_irqs(gpio, port, pp);

	err = gpiochip_add(&port->bgc.gc);
	if (err)
		dev_err(gpio->dev, "failed to register gpiochip for %s\n",
			pp->name);
	else
		port->is_registered = true;

	return err;
}

static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
{
	unsigned int m;

	for (m = 0; m < gpio->nr_ports; ++m)
		if (gpio->ports[m].is_registered)
			gpiochip_remove(&gpio->ports[m].bgc.gc);
}

static struct dwapb_platform_data *
dwapb_gpio_get_pdata_of(struct device *dev)
{
	struct device_node *node, *port_np;
	struct dwapb_platform_data *pdata;
	struct dwapb_port_property *pp;
	int nports;
	int i;

	node = dev->of_node;
	if (!IS_ENABLED(CONFIG_OF_GPIO) || !node)
		return ERR_PTR(-ENODEV);

	nports = of_get_child_count(node);
	if (nports == 0)
		return ERR_PTR(-ENODEV);

	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return ERR_PTR(-ENOMEM);

	pdata->properties = kcalloc(nports, sizeof(*pp), GFP_KERNEL);
	if (!pdata->properties) {
		kfree(pdata);
		return ERR_PTR(-ENOMEM);
	}

	pdata->nports = nports;

	i = 0;
	for_each_child_of_node(node, port_np) {
		pp = &pdata->properties[i++];
		pp->node = port_np;

		if (of_property_read_u32(port_np, "reg", &pp->idx) ||
		    pp->idx >= DWAPB_MAX_PORTS) {
			dev_err(dev, "missing/invalid port index for %s\n",
				port_np->full_name);
			kfree(pdata->properties);
			kfree(pdata);
			return ERR_PTR(-EINVAL);
		}

		if (of_property_read_u32(port_np, "snps,nr-gpios",
					 &pp->ngpio)) {
			dev_info(dev, "failed to get number of gpios for %s\n",
				 port_np->full_name);
			pp->ngpio = 32;
		}

		/*
		 * Only port A can provide interrupts in all configurations of
		 * the IP.
		 */
		if (pp->idx == 0 &&
		    of_property_read_bool(port_np, "interrupt-controller")) {
			pp->irq = irq_of_parse_and_map(port_np, 0);
			if (!pp->irq) {
				dev_warn(dev, "no irq for bank %s\n",
					 port_np->full_name);
			}
		}

		pp->irq_shared	= false;
		pp->gpio_base	= -1;
		pp->name	= port_np->full_name;
	}

	return pdata;
}

static inline void dwapb_free_pdata_of(struct dwapb_platform_data *pdata)
{
	if (!IS_ENABLED(CONFIG_OF_GPIO) || !pdata)
		return;

	kfree(pdata->properties);
	kfree(pdata);
}

static int dwapb_gpio_probe(struct platform_device *pdev)
{
	unsigned int i;
	struct resource *res;
	struct dwapb_gpio *gpio;
	int err;
	struct device *dev = &pdev->dev;
	struct dwapb_platform_data *pdata = dev_get_platdata(dev);
	bool is_pdata_alloc = !pdata;

	if (is_pdata_alloc) {
		pdata = dwapb_gpio_get_pdata_of(dev);
		if (IS_ERR(pdata))
			return PTR_ERR(pdata);
	}

	if (!pdata->nports) {
		err = -ENODEV;
		goto out_err;
	}

	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	if (!gpio) {
		err = -ENOMEM;
		goto out_err;
	}
	gpio->dev = &pdev->dev;
	gpio->nr_ports = pdata->nports;

	gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
				   sizeof(*gpio->ports), GFP_KERNEL);
	if (!gpio->ports) {
		err = -ENOMEM;
		goto out_err;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	gpio->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(gpio->regs)) {
		err = PTR_ERR(gpio->regs);
		goto out_err;
	}

	for (i = 0; i < gpio->nr_ports; i++) {
		err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
		if (err)
			goto out_unregister;
	}
	platform_set_drvdata(pdev, gpio);

	goto out_err;

out_unregister:
	dwapb_gpio_unregister(gpio);
	dwapb_irq_teardown(gpio);

out_err:
	if (is_pdata_alloc)
		dwapb_free_pdata_of(pdata);

	return err;
}

static int dwapb_gpio_remove(struct platform_device *pdev)
{
	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);

	dwapb_gpio_unregister(gpio);
	dwapb_irq_teardown(gpio);

	return 0;
}

static const struct of_device_id dwapb_of_match[] = {
	{ .compatible = "snps,dw-apb-gpio" },
	{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dwapb_of_match);

static struct platform_driver dwapb_gpio_driver = {
	.driver		= {
		.name	= "gpio-dwapb",
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(dwapb_of_match),
	},
	.probe		= dwapb_gpio_probe,
	.remove		= dwapb_gpio_remove,
};

module_platform_driver(dwapb_gpio_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jamie Iles");
MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
Commit	Line	Data
7779b345 JI	1	/*
	2	* Copyright (c) 2011 Jamie Iles
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* All enquiries to support@picochip.com
	9	*/
	10	#include <linux/basic_mmio_gpio.h>
	11	#include <linux/err.h>
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/io.h>
	15	#include <linux/ioport.h>
	16	#include <linux/irq.h>
	17	#include <linux/irqdomain.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_address.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/spinlock.h>
3d2613c4 WC	24	#include <linux/platform_data/gpio-dwapb.h>
3d2613c4 WC	25	#include <linux/slab.h>
7779b345 JI	26
	27	#define GPIO_SWPORTA_DR 0x00
	28	#define GPIO_SWPORTA_DDR 0x04
	29	#define GPIO_SWPORTB_DR 0x0c
	30	#define GPIO_SWPORTB_DDR 0x10
	31	#define GPIO_SWPORTC_DR 0x18
	32	#define GPIO_SWPORTC_DDR 0x1c
	33	#define GPIO_SWPORTD_DR 0x24
	34	#define GPIO_SWPORTD_DDR 0x28
	35	#define GPIO_INTEN 0x30
	36	#define GPIO_INTMASK 0x34
	37	#define GPIO_INTTYPE_LEVEL 0x38
	38	#define GPIO_INT_POLARITY 0x3c
	39	#define GPIO_INTSTATUS 0x40
	40	#define GPIO_PORTA_EOI 0x4c
	41	#define GPIO_EXT_PORTA 0x50
	42	#define GPIO_EXT_PORTB 0x54
	43	#define GPIO_EXT_PORTC 0x58
	44	#define GPIO_EXT_PORTD 0x5c
	45
	46	#define DWAPB_MAX_PORTS 4
	47	#define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
	48	#define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
	49	#define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
	50
	51	struct dwapb_gpio;
	52
	53	struct dwapb_gpio_port {
	54	struct bgpio_chip bgc;
	55	bool is_registered;
	56	struct dwapb_gpio *gpio;
	57	};
	58
	59	struct dwapb_gpio {
	60	struct device *dev;
	61	void __iomem *regs;
	62	struct dwapb_gpio_port *ports;
	63	unsigned int nr_ports;
	64	struct irq_domain *domain;
	65	};
	66
67809b97 WC	67	static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
	68	{
	69	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	70	void __iomem *reg_base = gpio->regs;
	71
	72	return bgc->read_reg(reg_base + offset);
	73	}
	74
	75	static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
	76	u32 val)
	77	{
	78	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	79	void __iomem *reg_base = gpio->regs;
	80
	81	bgc->write_reg(reg_base + offset, val);
	82	}
	83
7779b345 JI	84	static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
	85	{
	86	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	87	struct dwapb_gpio_port *port = container_of(bgc, struct
	88	dwapb_gpio_port, bgc);
	89	struct dwapb_gpio *gpio = port->gpio;
	90
	91	return irq_find_mapping(gpio->domain, offset);
	92	}
	93
	94	static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
	95	{
67809b97	96	u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
7779b345 JI	97
	98	if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
	99	v &= ~BIT(offs);
	100	else
	101	v \|= BIT(offs);
	102
67809b97	103	dwapb_write(gpio, GPIO_INT_POLARITY, v);
7779b345 JI	104	}
7779b345 JI	105
3d2613c4	106	static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
7779b345	107	{
7779b345	108	u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
3d2613c4	109	u32 ret = irq_status;
7779b345 JI	110
	111	while (irq_status) {
	112	int hwirq = fls(irq_status) - 1;
	113	int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
	114
	115	generic_handle_irq(gpio_irq);
	116	irq_status &= ~BIT(hwirq);
	117
	118	if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
	119	== IRQ_TYPE_EDGE_BOTH)
	120	dwapb_toggle_trigger(gpio, hwirq);
	121	}
	122
3d2613c4 WC	123	return ret;
	124	}
	125
	126	static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
	127	{
	128	struct dwapb_gpio *gpio = irq_get_handler_data(irq);
	129	struct irq_chip *chip = irq_desc_get_chip(desc);
	130
	131	dwapb_do_irq(gpio);
	132
7779b345 JI	133	if (chip->irq_eoi)
	134	chip->irq_eoi(irq_desc_get_irq_data(desc));
	135	}
	136
	137	static void dwapb_irq_enable(struct irq_data *d)
	138	{
	139	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	140	struct dwapb_gpio *gpio = igc->private;
	141	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	142	unsigned long flags;
	143	u32 val;
	144
	145	spin_lock_irqsave(&bgc->lock, flags);
67809b97	146	val = dwapb_read(gpio, GPIO_INTEN);
7779b345	147	val \|= BIT(d->hwirq);
67809b97	148	dwapb_write(gpio, GPIO_INTEN, val);
7779b345 JI	149	spin_unlock_irqrestore(&bgc->lock, flags);
	150	}
	151
	152	static void dwapb_irq_disable(struct irq_data *d)
	153	{
	154	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	155	struct dwapb_gpio *gpio = igc->private;
	156	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	157	unsigned long flags;
	158	u32 val;
	159
	160	spin_lock_irqsave(&bgc->lock, flags);
67809b97	161	val = dwapb_read(gpio, GPIO_INTEN);
7779b345	162	val &= ~BIT(d->hwirq);
67809b97	163	dwapb_write(gpio, GPIO_INTEN, val);
7779b345 JI	164	spin_unlock_irqrestore(&bgc->lock, flags);
	165	}
	166
57ef0428	167	static int dwapb_irq_reqres(struct irq_data *d)
7779b345 JI	168	{
	169	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	170	struct dwapb_gpio *gpio = igc->private;
	171	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	172
57ef0428	173	if (gpio_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
7779b345 JI	174	dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
7779b345 JI	175	irqd_to_hwirq(d));
57ef0428 LW	176	return -EINVAL;
57ef0428 LW	177	}
7779b345 JI	178	return 0;
	179	}
	180
57ef0428	181	static void dwapb_irq_relres(struct irq_data *d)
7779b345 JI	182	{
	183	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	184	struct dwapb_gpio *gpio = igc->private;
	185	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	186
7779b345 JI	187	gpio_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
	188	}
	189
	190	static int dwapb_irq_set_type(struct irq_data *d, u32 type)
	191	{
	192	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	193	struct dwapb_gpio *gpio = igc->private;
	194	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	195	int bit = d->hwirq;
	196	unsigned long level, polarity, flags;
	197
	198	if (type & ~(IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING \|
	199	IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW))
	200	return -EINVAL;
	201
	202	spin_lock_irqsave(&bgc->lock, flags);
67809b97 WC	203	level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
67809b97 WC	204	polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
7779b345 JI	205
	206	switch (type) {
	207	case IRQ_TYPE_EDGE_BOTH:
	208	level \|= BIT(bit);
	209	dwapb_toggle_trigger(gpio, bit);
	210	break;
	211	case IRQ_TYPE_EDGE_RISING:
	212	level \|= BIT(bit);
	213	polarity \|= BIT(bit);
	214	break;
	215	case IRQ_TYPE_EDGE_FALLING:
	216	level \|= BIT(bit);
	217	polarity &= ~BIT(bit);
	218	break;
	219	case IRQ_TYPE_LEVEL_HIGH:
	220	level &= ~BIT(bit);
	221	polarity \|= BIT(bit);
	222	break;
	223	case IRQ_TYPE_LEVEL_LOW:
	224	level &= ~BIT(bit);
	225	polarity &= ~BIT(bit);
	226	break;
	227	}
	228
6a2f4b7d SAS	229	irq_setup_alt_chip(d, type);
6a2f4b7d SAS	230
67809b97 WC	231	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
67809b97 WC	232	dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
7779b345 JI	233	spin_unlock_irqrestore(&bgc->lock, flags);
	234
	235	return 0;
	236	}
	237
3d2613c4 WC	238	static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
	239	{
	240	u32 worked;
	241	struct dwapb_gpio *gpio = dev_id;
	242
	243	worked = dwapb_do_irq(gpio);
	244
	245	return worked ? IRQ_HANDLED : IRQ_NONE;
	246	}
	247
7779b345	248	static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
3d2613c4 WC	249	struct dwapb_gpio_port *port,
3d2613c4 WC	250	struct dwapb_port_property *pp)
7779b345 JI	251	{
7779b345 JI	252	struct gpio_chip *gc = &port->bgc.gc;
3d2613c4 WC	253	struct device_node *node = pp->node;
3d2613c4 WC	254	struct irq_chip_generic *irq_gc = NULL;
7779b345 JI	255	unsigned int hwirq, ngpio = gc->ngpio;
7779b345 JI	256	struct irq_chip_type *ct;
3d2613c4	257	int err, i;
7779b345 JI	258
	259	gpio->domain = irq_domain_add_linear(node, ngpio,
	260	&irq_generic_chip_ops, gpio);
	261	if (!gpio->domain)
	262	return;
	263
6a2f4b7d	264	err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
7779b345 JI	265	"gpio-dwapb", handle_level_irq,
	266	IRQ_NOREQUEST, 0,
	267	IRQ_GC_INIT_NESTED_LOCK);
	268	if (err) {
	269	dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
	270	irq_domain_remove(gpio->domain);
	271	gpio->domain = NULL;
	272	return;
	273	}
	274
	275	irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
	276	if (!irq_gc) {
	277	irq_domain_remove(gpio->domain);
	278	gpio->domain = NULL;
	279	return;
	280	}
	281
	282	irq_gc->reg_base = gpio->regs;
	283	irq_gc->private = gpio;
	284
6a2f4b7d SAS	285	for (i = 0; i < 2; i++) {
	286	ct = &irq_gc->chip_types[i];
	287	ct->chip.irq_ack = irq_gc_ack_set_bit;
	288	ct->chip.irq_mask = irq_gc_mask_set_bit;
	289	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
	290	ct->chip.irq_set_type = dwapb_irq_set_type;
	291	ct->chip.irq_enable = dwapb_irq_enable;
	292	ct->chip.irq_disable = dwapb_irq_disable;
	293	ct->chip.irq_request_resources = dwapb_irq_reqres;
	294	ct->chip.irq_release_resources = dwapb_irq_relres;
	295	ct->regs.ack = GPIO_PORTA_EOI;
	296	ct->regs.mask = GPIO_INTMASK;
	297	ct->type = IRQ_TYPE_LEVEL_MASK;
	298	}
	299
	300	irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
	301	irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
	302	irq_gc->chip_types[1].handler = handle_edge_irq;
7779b345	303
3d2613c4 WC	304	if (!pp->irq_shared) {
	305	irq_set_chained_handler(pp->irq, dwapb_irq_handler);
	306	irq_set_handler_data(pp->irq, gpio);
	307	} else {
	308	/*
	309	* Request a shared IRQ since where MFD would have devices
	310	* using the same irq pin
	311	*/
	312	err = devm_request_irq(gpio->dev, pp->irq,
	313	dwapb_irq_handler_mfd,
	314	IRQF_SHARED, "gpio-dwapb-mfd", gpio);
	315	if (err) {
	316	dev_err(gpio->dev, "error requesting IRQ\n");
	317	irq_domain_remove(gpio->domain);
	318	gpio->domain = NULL;
	319	return;
	320	}
	321	}
7779b345 JI	322
	323	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
	324	irq_create_mapping(gpio->domain, hwirq);
	325
	326	port->bgc.gc.to_irq = dwapb_gpio_to_irq;
	327	}
	328
	329	static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
	330	{
	331	struct dwapb_gpio_port *port = &gpio->ports[0];
	332	struct gpio_chip *gc = &port->bgc.gc;
	333	unsigned int ngpio = gc->ngpio;
	334	irq_hw_number_t hwirq;
	335
	336	if (!gpio->domain)
	337	return;
	338
	339	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
	340	irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
	341
	342	irq_domain_remove(gpio->domain);
	343	gpio->domain = NULL;
	344	}
	345
	346	static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
3d2613c4	347	struct dwapb_port_property *pp,
7779b345 JI	348	unsigned int offs)
	349	{
	350	struct dwapb_gpio_port *port;
7779b345 JI	351	void __iomem dat, set, *dirout;
	352	int err;
	353
7779b345 JI	354	port = &gpio->ports[offs];
	355	port->gpio = gpio;
	356
3d2613c4 WC	357	dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
3d2613c4 WC	358	set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
7779b345	359	dirout = gpio->regs + GPIO_SWPORTA_DDR +
3d2613c4	360	(pp->idx * GPIO_SWPORT_DDR_SIZE);
7779b345 JI	361
	362	err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
	363	NULL, false);
	364	if (err) {
	365	dev_err(gpio->dev, "failed to init gpio chip for %s\n",
3d2613c4	366	pp->name);
7779b345 JI	367	return err;
	368	}
	369
3d2613c4 WC	370	#ifdef CONFIG_OF_GPIO
	371	port->bgc.gc.of_node = pp->node;
	372	#endif
	373	port->bgc.gc.ngpio = pp->ngpio;
	374	port->bgc.gc.base = pp->gpio_base;
7779b345	375
3d2613c4 WC	376	if (pp->irq)
3d2613c4 WC	377	dwapb_configure_irqs(gpio, port, pp);
7779b345 JI	378
	379	err = gpiochip_add(&port->bgc.gc);
	380	if (err)
	381	dev_err(gpio->dev, "failed to register gpiochip for %s\n",
3d2613c4	382	pp->name);
7779b345 JI	383	else
	384	port->is_registered = true;
	385
	386	return err;
	387	}
	388
	389	static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
	390	{
	391	unsigned int m;
	392
	393	for (m = 0; m < gpio->nr_ports; ++m)
	394	if (gpio->ports[m].is_registered)
9f5132ae	395	gpiochip_remove(&gpio->ports[m].bgc.gc);
7779b345 JI	396	}
7779b345 JI	397
3d2613c4 WC	398	static struct dwapb_platform_data *
	399	dwapb_gpio_get_pdata_of(struct device *dev)
	400	{
	401	struct device_node node, port_np;
	402	struct dwapb_platform_data *pdata;
	403	struct dwapb_port_property *pp;
	404	int nports;
	405	int i;
	406
	407	node = dev->of_node;
	408	if (!IS_ENABLED(CONFIG_OF_GPIO) \|\| !node)
	409	return ERR_PTR(-ENODEV);
	410
	411	nports = of_get_child_count(node);
	412	if (nports == 0)
	413	return ERR_PTR(-ENODEV);
	414
	415	pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
	416	if (!pdata)
	417	return ERR_PTR(-ENOMEM);
	418
	419	pdata->properties = kcalloc(nports, sizeof(*pp), GFP_KERNEL);
	420	if (!pdata->properties) {
	421	kfree(pdata);
	422	return ERR_PTR(-ENOMEM);
	423	}
	424
	425	pdata->nports = nports;
	426
	427	i = 0;
	428	for_each_child_of_node(node, port_np) {
	429	pp = &pdata->properties[i++];
	430	pp->node = port_np;
	431
	432	if (of_property_read_u32(port_np, "reg", &pp->idx) \|\|
	433	pp->idx >= DWAPB_MAX_PORTS) {
	434	dev_err(dev, "missing/invalid port index for %s\n",
	435	port_np->full_name);
	436	kfree(pdata->properties);
	437	kfree(pdata);
	438	return ERR_PTR(-EINVAL);
	439	}
	440
	441	if (of_property_read_u32(port_np, "snps,nr-gpios",
	442	&pp->ngpio)) {
	443	dev_info(dev, "failed to get number of gpios for %s\n",
	444	port_np->full_name);
	445	pp->ngpio = 32;
	446	}
	447
	448	/*
	449	* Only port A can provide interrupts in all configurations of
	450	* the IP.
	451	*/
	452	if (pp->idx == 0 &&
	453	of_property_read_bool(port_np, "interrupt-controller")) {
	454	pp->irq = irq_of_parse_and_map(port_np, 0);
	455	if (!pp->irq) {
	456	dev_warn(dev, "no irq for bank %s\n",
	457	port_np->full_name);
	458	}
	459	}
	460
	461	pp->irq_shared = false;
462	pp->gpio_base = -1;
463	pp->name = port_np->full_name;
464	}
465
466	return pdata;
467	}
468
469	static inline void dwapb_free_pdata_of(struct dwapb_platform_data *pdata)
470	{
471	if (!IS_ENABLED(CONFIG_OF_GPIO) \|\| !pdata)
472	return;
473
474	kfree(pdata->properties);
475	kfree(pdata);
476	}
477
7779b345 JI	478	static int dwapb_gpio_probe(struct platform_device *pdev)
7779b345 JI	479	{
3d2613c4	480	unsigned int i;
7779b345 JI	481	struct resource *res;
7779b345 JI	482	struct dwapb_gpio *gpio;
7779b345	483	int err;
3d2613c4 WC	484	struct device *dev = &pdev->dev;
	485	struct dwapb_platform_data *pdata = dev_get_platdata(dev);
	486	bool is_pdata_alloc = !pdata;
	487
	488	if (is_pdata_alloc) {
	489	pdata = dwapb_gpio_get_pdata_of(dev);
	490	if (IS_ERR(pdata))
	491	return PTR_ERR(pdata);
	492	}
7779b345	493
3d2613c4 WC	494	if (!pdata->nports) {
	495	err = -ENODEV;
	496	goto out_err;
	497	}
7779b345	498
3d2613c4 WC	499	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	500	if (!gpio) {
	501	err = -ENOMEM;
7779b345 JI	502	goto out_err;
7779b345 JI	503	}
3d2613c4 WC	504	gpio->dev = &pdev->dev;
	505	gpio->nr_ports = pdata->nports;
	506
	507	gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
7779b345 JI	508	sizeof(*gpio->ports), GFP_KERNEL);
	509	if (!gpio->ports) {
	510	err = -ENOMEM;
	511	goto out_err;
	512	}
	513
	514	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	515	gpio->regs = devm_ioremap_resource(&pdev->dev, res);
	516	if (IS_ERR(gpio->regs)) {
	517	err = PTR_ERR(gpio->regs);
	518	goto out_err;
	519	}
	520
3d2613c4 WC	521	for (i = 0; i < gpio->nr_ports; i++) {
3d2613c4 WC	522	err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
7779b345 JI	523	if (err)
	524	goto out_unregister;
	525	}
	526	platform_set_drvdata(pdev, gpio);
	527
3d2613c4	528	goto out_err;
7779b345 JI	529
	530	out_unregister:
	531	dwapb_gpio_unregister(gpio);
	532	dwapb_irq_teardown(gpio);
	533
	534	out_err:
3d2613c4 WC	535	if (is_pdata_alloc)
	536	dwapb_free_pdata_of(pdata);
	537
7779b345 JI	538	return err;
	539	}
	540
	541	static int dwapb_gpio_remove(struct platform_device *pdev)
	542	{
	543	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
	544
	545	dwapb_gpio_unregister(gpio);
	546	dwapb_irq_teardown(gpio);
	547
	548	return 0;
	549	}
	550
	551	static const struct of_device_id dwapb_of_match[] = {
	552	{ .compatible = "snps,dw-apb-gpio" },
	553	{ /* Sentinel */ }
	554	};
	555	MODULE_DEVICE_TABLE(of, dwapb_of_match);
	556
	557	static struct platform_driver dwapb_gpio_driver = {
	558	.driver = {
	559	.name = "gpio-dwapb",
	560	.owner = THIS_MODULE,
	561	.of_match_table = of_match_ptr(dwapb_of_match),
	562	},
	563	.probe = dwapb_gpio_probe,
	564	.remove = dwapb_gpio_remove,
	565	};
	566
	567	module_platform_driver(dwapb_gpio_driver);
	568
	569	MODULE_LICENSE("GPL");
	570	MODULE_AUTHOR("Jamie Iles");
	571	MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");