[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-dwapb.c

/*
 * Copyright (c) 2011 Jamie Iles
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * All enquiries to support@picochip.com
 */
#include <linux/basic_mmio_gpio.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>

#define GPIO_SWPORTA_DR		0x00
#define GPIO_SWPORTA_DDR	0x04
#define GPIO_SWPORTB_DR		0x0c
#define GPIO_SWPORTB_DDR	0x10
#define GPIO_SWPORTC_DR		0x18
#define GPIO_SWPORTC_DDR	0x1c
#define GPIO_SWPORTD_DR		0x24
#define GPIO_SWPORTD_DDR	0x28
#define GPIO_INTEN		0x30
#define GPIO_INTMASK		0x34
#define GPIO_INTTYPE_LEVEL	0x38
#define GPIO_INT_POLARITY	0x3c
#define GPIO_INTSTATUS		0x40
#define GPIO_PORTA_EOI		0x4c
#define GPIO_EXT_PORTA		0x50
#define GPIO_EXT_PORTB		0x54
#define GPIO_EXT_PORTC		0x58
#define GPIO_EXT_PORTD		0x5c

#define DWAPB_MAX_PORTS		4
#define GPIO_EXT_PORT_SIZE	(GPIO_EXT_PORTB - GPIO_EXT_PORTA)
#define GPIO_SWPORT_DR_SIZE	(GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
#define GPIO_SWPORT_DDR_SIZE	(GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)

struct dwapb_gpio;

struct dwapb_gpio_port {
	struct bgpio_chip	bgc;
	bool			is_registered;
	struct dwapb_gpio	*gpio;
};

struct dwapb_gpio {
	struct	device		*dev;
	void __iomem		*regs;
	struct dwapb_gpio_port	*ports;
	unsigned int		nr_ports;
	struct irq_domain	*domain;
};

static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	struct dwapb_gpio_port *port = container_of(bgc, struct
						    dwapb_gpio_port, bgc);
	struct dwapb_gpio *gpio = port->gpio;

	return irq_find_mapping(gpio->domain, offset);
}

static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
{
	u32 v = readl(gpio->regs + GPIO_INT_POLARITY);

	if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
		v &= ~BIT(offs);
	else
		v |= BIT(offs);

	writel(v, gpio->regs + GPIO_INT_POLARITY);
}

static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
{
	struct dwapb_gpio *gpio = irq_get_handler_data(irq);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);

	while (irq_status) {
		int hwirq = fls(irq_status) - 1;
		int gpio_irq = irq_find_mapping(gpio->domain, hwirq);

		generic_handle_irq(gpio_irq);
		irq_status &= ~BIT(hwirq);

		if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
			== IRQ_TYPE_EDGE_BOTH)
			dwapb_toggle_trigger(gpio, hwirq);
	}

	if (chip->irq_eoi)
		chip->irq_eoi(irq_desc_get_irq_data(desc));
}

static void dwapb_irq_enable(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&bgc->lock, flags);
	val = readl(gpio->regs + GPIO_INTEN);
	val |= BIT(d->hwirq);
	writel(val, gpio->regs + GPIO_INTEN);
	spin_unlock_irqrestore(&bgc->lock, flags);
}

static void dwapb_irq_disable(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&bgc->lock, flags);
	val = readl(gpio->regs + GPIO_INTEN);
	val &= ~BIT(d->hwirq);
	writel(val, gpio->regs + GPIO_INTEN);
	spin_unlock_irqrestore(&bgc->lock, flags);
}

static int dwapb_irq_reqres(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;

	if (gpio_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
		dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
			irqd_to_hwirq(d));
		return -EINVAL;
	}
	return 0;
}

static void dwapb_irq_relres(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;

	gpio_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
}

static int dwapb_irq_set_type(struct irq_data *d, u32 type)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	int bit = d->hwirq;
	unsigned long level, polarity, flags;

	if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
		     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
		return -EINVAL;

	spin_lock_irqsave(&bgc->lock, flags);
	level = readl(gpio->regs + GPIO_INTTYPE_LEVEL);
	polarity = readl(gpio->regs + GPIO_INT_POLARITY);

	switch (type) {
	case IRQ_TYPE_EDGE_BOTH:
		level |= BIT(bit);
		dwapb_toggle_trigger(gpio, bit);
		break;
	case IRQ_TYPE_EDGE_RISING:
		level |= BIT(bit);
		polarity |= BIT(bit);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		level |= BIT(bit);
		polarity &= ~BIT(bit);
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		level &= ~BIT(bit);
		polarity |= BIT(bit);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		level &= ~BIT(bit);
		polarity &= ~BIT(bit);
		break;
	}

	irq_setup_alt_chip(d, type);

	writel(level, gpio->regs + GPIO_INTTYPE_LEVEL);
	writel(polarity, gpio->regs + GPIO_INT_POLARITY);
	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
				 struct dwapb_gpio_port *port)
{
	struct gpio_chip *gc = &port->bgc.gc;
	struct device_node *node =  gc->of_node;
	struct irq_chip_generic	*irq_gc;
	unsigned int hwirq, ngpio = gc->ngpio;
	struct irq_chip_type *ct;
	int err, irq, i;

	irq = irq_of_parse_and_map(node, 0);
	if (!irq) {
		dev_warn(gpio->dev, "no irq for bank %s\n",
			port->bgc.gc.of_node->full_name);
		return;
	}

	gpio->domain = irq_domain_add_linear(node, ngpio,
					     &irq_generic_chip_ops, gpio);
	if (!gpio->domain)
		return;

	err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
					     "gpio-dwapb", handle_level_irq,
					     IRQ_NOREQUEST, 0,
					     IRQ_GC_INIT_NESTED_LOCK);
	if (err) {
		dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
		irq_domain_remove(gpio->domain);
		gpio->domain = NULL;
		return;
	}

	irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
	if (!irq_gc) {
		irq_domain_remove(gpio->domain);
		gpio->domain = NULL;
		return;
	}

	irq_gc->reg_base = gpio->regs;
	irq_gc->private = gpio;

	for (i = 0; i < 2; i++) {
		ct = &irq_gc->chip_types[i];
		ct->chip.irq_ack = irq_gc_ack_set_bit;
		ct->chip.irq_mask = irq_gc_mask_set_bit;
		ct->chip.irq_unmask = irq_gc_mask_clr_bit;
		ct->chip.irq_set_type = dwapb_irq_set_type;
		ct->chip.irq_enable = dwapb_irq_enable;
		ct->chip.irq_disable = dwapb_irq_disable;
		ct->chip.irq_request_resources = dwapb_irq_reqres;
		ct->chip.irq_release_resources = dwapb_irq_relres;
		ct->regs.ack = GPIO_PORTA_EOI;
		ct->regs.mask = GPIO_INTMASK;
		ct->type = IRQ_TYPE_LEVEL_MASK;
	}

	irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
	irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
	irq_gc->chip_types[1].handler = handle_edge_irq;

	irq_set_chained_handler(irq, dwapb_irq_handler);
	irq_set_handler_data(irq, gpio);

	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
		irq_create_mapping(gpio->domain, hwirq);

	port->bgc.gc.to_irq = dwapb_gpio_to_irq;
}

static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
{
	struct dwapb_gpio_port *port = &gpio->ports[0];
	struct gpio_chip *gc = &port->bgc.gc;
	unsigned int ngpio = gc->ngpio;
	irq_hw_number_t hwirq;

	if (!gpio->domain)
		return;

	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
		irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));

	irq_domain_remove(gpio->domain);
	gpio->domain = NULL;
}

static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
			       struct device_node *port_np,
			       unsigned int offs)
{
	struct dwapb_gpio_port *port;
	u32 port_idx, ngpio;
	void __iomem *dat, *set, *dirout;
	int err;

	if (of_property_read_u32(port_np, "reg", &port_idx) ||
		port_idx >= DWAPB_MAX_PORTS) {
		dev_err(gpio->dev, "missing/invalid port index for %s\n",
			port_np->full_name);
		return -EINVAL;
	}

	port = &gpio->ports[offs];
	port->gpio = gpio;

	if (of_property_read_u32(port_np, "snps,nr-gpios", &ngpio)) {
		dev_info(gpio->dev, "failed to get number of gpios for %s\n",
			 port_np->full_name);
		ngpio = 32;
	}

	dat = gpio->regs + GPIO_EXT_PORTA + (port_idx * GPIO_EXT_PORT_SIZE);
	set = gpio->regs + GPIO_SWPORTA_DR + (port_idx * GPIO_SWPORT_DR_SIZE);
	dirout = gpio->regs + GPIO_SWPORTA_DDR +
		(port_idx * GPIO_SWPORT_DDR_SIZE);

	err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
			 NULL, false);
	if (err) {
		dev_err(gpio->dev, "failed to init gpio chip for %s\n",
			port_np->full_name);
		return err;
	}

	port->bgc.gc.ngpio = ngpio;
	port->bgc.gc.of_node = port_np;

	/*
	 * Only port A can provide interrupts in all configurations of the IP.
	 */
	if (port_idx == 0 &&
	    of_property_read_bool(port_np, "interrupt-controller"))
		dwapb_configure_irqs(gpio, port);

	err = gpiochip_add(&port->bgc.gc);
	if (err)
		dev_err(gpio->dev, "failed to register gpiochip for %s\n",
			port_np->full_name);
	else
		port->is_registered = true;

	return err;
}

static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
{
	unsigned int m;

	for (m = 0; m < gpio->nr_ports; ++m)
		if (gpio->ports[m].is_registered)
			gpiochip_remove(&gpio->ports[m].bgc.gc);
}

static int dwapb_gpio_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct dwapb_gpio *gpio;
	struct device_node *np;
	int err;
	unsigned int offs = 0;

	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	if (!gpio)
		return -ENOMEM;
	gpio->dev = &pdev->dev;

	gpio->nr_ports = of_get_child_count(pdev->dev.of_node);
	if (!gpio->nr_ports) {
		err = -EINVAL;
		goto out_err;
	}
	gpio->ports = devm_kzalloc(&pdev->dev, gpio->nr_ports *
				   sizeof(*gpio->ports), GFP_KERNEL);
	if (!gpio->ports) {
		err = -ENOMEM;
		goto out_err;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	gpio->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(gpio->regs)) {
		err = PTR_ERR(gpio->regs);
		goto out_err;
	}

	for_each_child_of_node(pdev->dev.of_node, np) {
		err = dwapb_gpio_add_port(gpio, np, offs++);
		if (err)
			goto out_unregister;
	}
	platform_set_drvdata(pdev, gpio);

	return 0;

out_unregister:
	dwapb_gpio_unregister(gpio);
	dwapb_irq_teardown(gpio);

out_err:
	return err;
}

static int dwapb_gpio_remove(struct platform_device *pdev)
{
	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);

	dwapb_gpio_unregister(gpio);
	dwapb_irq_teardown(gpio);

	return 0;
}

static const struct of_device_id dwapb_of_match[] = {
	{ .compatible = "snps,dw-apb-gpio" },
	{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dwapb_of_match);

static struct platform_driver dwapb_gpio_driver = {
	.driver		= {
		.name	= "gpio-dwapb",
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(dwapb_of_match),
	},
	.probe		= dwapb_gpio_probe,
	.remove		= dwapb_gpio_remove,
};

module_platform_driver(dwapb_gpio_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jamie Iles");
MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
Commit	Line	Data
7779b345 JI	1	/*
	2	* Copyright (c) 2011 Jamie Iles
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* All enquiries to support@picochip.com
	9	*/
	10	#include <linux/basic_mmio_gpio.h>
	11	#include <linux/err.h>
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/io.h>
	15	#include <linux/ioport.h>
	16	#include <linux/irq.h>
	17	#include <linux/irqdomain.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_address.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/spinlock.h>
	24
	25	#define GPIO_SWPORTA_DR 0x00
	26	#define GPIO_SWPORTA_DDR 0x04
	27	#define GPIO_SWPORTB_DR 0x0c
	28	#define GPIO_SWPORTB_DDR 0x10
	29	#define GPIO_SWPORTC_DR 0x18
	30	#define GPIO_SWPORTC_DDR 0x1c
	31	#define GPIO_SWPORTD_DR 0x24
	32	#define GPIO_SWPORTD_DDR 0x28
	33	#define GPIO_INTEN 0x30
	34	#define GPIO_INTMASK 0x34
	35	#define GPIO_INTTYPE_LEVEL 0x38
	36	#define GPIO_INT_POLARITY 0x3c
	37	#define GPIO_INTSTATUS 0x40
	38	#define GPIO_PORTA_EOI 0x4c
	39	#define GPIO_EXT_PORTA 0x50
	40	#define GPIO_EXT_PORTB 0x54
	41	#define GPIO_EXT_PORTC 0x58
	42	#define GPIO_EXT_PORTD 0x5c
	43
	44	#define DWAPB_MAX_PORTS 4
	45	#define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
	46	#define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
	47	#define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
	48
	49	struct dwapb_gpio;
	50
	51	struct dwapb_gpio_port {
	52	struct bgpio_chip bgc;
	53	bool is_registered;
	54	struct dwapb_gpio *gpio;
	55	};
	56
	57	struct dwapb_gpio {
	58	struct device *dev;
	59	void __iomem *regs;
	60	struct dwapb_gpio_port *ports;
	61	unsigned int nr_ports;
	62	struct irq_domain *domain;
	63	};
	64
65	static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
66	{
67	struct bgpio_chip *bgc = to_bgpio_chip(gc);
68	struct dwapb_gpio_port *port = container_of(bgc, struct
69	dwapb_gpio_port, bgc);
70	struct dwapb_gpio *gpio = port->gpio;
71
72	return irq_find_mapping(gpio->domain, offset);
73	}
74
75	static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
76	{
77	u32 v = readl(gpio->regs + GPIO_INT_POLARITY);
78
79	if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
80	v &= ~BIT(offs);
81	else
82	v \|= BIT(offs);
83
84	writel(v, gpio->regs + GPIO_INT_POLARITY);
85	}
86
87	static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
88	{
89	struct dwapb_gpio *gpio = irq_get_handler_data(irq);
90	struct irq_chip *chip = irq_desc_get_chip(desc);
91	u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
92
93	while (irq_status) {
94	int hwirq = fls(irq_status) - 1;
95	int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
96
97	generic_handle_irq(gpio_irq);
98	irq_status &= ~BIT(hwirq);
99
100	if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
101	== IRQ_TYPE_EDGE_BOTH)
102	dwapb_toggle_trigger(gpio, hwirq);
103	}
104
105	if (chip->irq_eoi)
106	chip->irq_eoi(irq_desc_get_irq_data(desc));
107	}
108
109	static void dwapb_irq_enable(struct irq_data *d)
110	{
111	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
112	struct dwapb_gpio *gpio = igc->private;
113	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
114	unsigned long flags;
115	u32 val;
116
117	spin_lock_irqsave(&bgc->lock, flags);
118	val = readl(gpio->regs + GPIO_INTEN);
119	val \|= BIT(d->hwirq);
120	writel(val, gpio->regs + GPIO_INTEN);
121	spin_unlock_irqrestore(&bgc->lock, flags);
122	}
123
124	static void dwapb_irq_disable(struct irq_data *d)
125	{
126	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
127	struct dwapb_gpio *gpio = igc->private;
128	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
129	unsigned long flags;
130	u32 val;
131
132	spin_lock_irqsave(&bgc->lock, flags);
133	val = readl(gpio->regs + GPIO_INTEN);
134	val &= ~BIT(d->hwirq);
135	writel(val, gpio->regs + GPIO_INTEN);
136	spin_unlock_irqrestore(&bgc->lock, flags);
137	}
138
57ef0428	139	static int dwapb_irq_reqres(struct irq_data *d)
7779b345 JI	140	{
	141	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	142	struct dwapb_gpio *gpio = igc->private;
	143	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	144
57ef0428	145	if (gpio_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
7779b345 JI	146	dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
7779b345 JI	147	irqd_to_hwirq(d));
57ef0428 LW	148	return -EINVAL;
57ef0428 LW	149	}
7779b345 JI	150	return 0;
	151	}
	152
57ef0428	153	static void dwapb_irq_relres(struct irq_data *d)
7779b345 JI	154	{
	155	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	156	struct dwapb_gpio *gpio = igc->private;
	157	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	158
7779b345 JI	159	gpio_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
	160	}
	161
	162	static int dwapb_irq_set_type(struct irq_data *d, u32 type)
	163	{
	164	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	165	struct dwapb_gpio *gpio = igc->private;
	166	struct bgpio_chip *bgc = &gpio->ports[0].bgc;
	167	int bit = d->hwirq;
	168	unsigned long level, polarity, flags;
	169
	170	if (type & ~(IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING \|
	171	IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW))
	172	return -EINVAL;
	173
	174	spin_lock_irqsave(&bgc->lock, flags);
	175	level = readl(gpio->regs + GPIO_INTTYPE_LEVEL);
	176	polarity = readl(gpio->regs + GPIO_INT_POLARITY);
	177
	178	switch (type) {
	179	case IRQ_TYPE_EDGE_BOTH:
	180	level \|= BIT(bit);
	181	dwapb_toggle_trigger(gpio, bit);
	182	break;
	183	case IRQ_TYPE_EDGE_RISING:
	184	level \|= BIT(bit);
	185	polarity \|= BIT(bit);
	186	break;
	187	case IRQ_TYPE_EDGE_FALLING:
	188	level \|= BIT(bit);
	189	polarity &= ~BIT(bit);
	190	break;
	191	case IRQ_TYPE_LEVEL_HIGH:
	192	level &= ~BIT(bit);
	193	polarity \|= BIT(bit);
	194	break;
	195	case IRQ_TYPE_LEVEL_LOW:
	196	level &= ~BIT(bit);
	197	polarity &= ~BIT(bit);
	198	break;
	199	}
	200
6a2f4b7d SAS	201	irq_setup_alt_chip(d, type);
6a2f4b7d SAS	202
7779b345 JI	203	writel(level, gpio->regs + GPIO_INTTYPE_LEVEL);
	204	writel(polarity, gpio->regs + GPIO_INT_POLARITY);
	205	spin_unlock_irqrestore(&bgc->lock, flags);
	206
	207	return 0;
	208	}
	209
	210	static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
	211	struct dwapb_gpio_port *port)
	212	{
	213	struct gpio_chip *gc = &port->bgc.gc;
	214	struct device_node *node = gc->of_node;
	215	struct irq_chip_generic *irq_gc;
	216	unsigned int hwirq, ngpio = gc->ngpio;
	217	struct irq_chip_type *ct;
6a2f4b7d	218	int err, irq, i;
7779b345 JI	219
	220	irq = irq_of_parse_and_map(node, 0);
	221	if (!irq) {
	222	dev_warn(gpio->dev, "no irq for bank %s\n",
	223	port->bgc.gc.of_node->full_name);
	224	return;
	225	}
	226
	227	gpio->domain = irq_domain_add_linear(node, ngpio,
	228	&irq_generic_chip_ops, gpio);
	229	if (!gpio->domain)
	230	return;
	231
6a2f4b7d	232	err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
7779b345 JI	233	"gpio-dwapb", handle_level_irq,
	234	IRQ_NOREQUEST, 0,
	235	IRQ_GC_INIT_NESTED_LOCK);
	236	if (err) {
	237	dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
	238	irq_domain_remove(gpio->domain);
	239	gpio->domain = NULL;
	240	return;
	241	}
	242
	243	irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
	244	if (!irq_gc) {
	245	irq_domain_remove(gpio->domain);
	246	gpio->domain = NULL;
	247	return;
	248	}
	249
	250	irq_gc->reg_base = gpio->regs;
	251	irq_gc->private = gpio;
	252
6a2f4b7d SAS	253	for (i = 0; i < 2; i++) {
	254	ct = &irq_gc->chip_types[i];
	255	ct->chip.irq_ack = irq_gc_ack_set_bit;
	256	ct->chip.irq_mask = irq_gc_mask_set_bit;
	257	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
	258	ct->chip.irq_set_type = dwapb_irq_set_type;
	259	ct->chip.irq_enable = dwapb_irq_enable;
	260	ct->chip.irq_disable = dwapb_irq_disable;
	261	ct->chip.irq_request_resources = dwapb_irq_reqres;
	262	ct->chip.irq_release_resources = dwapb_irq_relres;
	263	ct->regs.ack = GPIO_PORTA_EOI;
	264	ct->regs.mask = GPIO_INTMASK;
	265	ct->type = IRQ_TYPE_LEVEL_MASK;
	266	}
	267
	268	irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
	269	irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
	270	irq_gc->chip_types[1].handler = handle_edge_irq;
7779b345 JI	271
	272	irq_set_chained_handler(irq, dwapb_irq_handler);
	273	irq_set_handler_data(irq, gpio);
	274
	275	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
	276	irq_create_mapping(gpio->domain, hwirq);
	277
	278	port->bgc.gc.to_irq = dwapb_gpio_to_irq;
	279	}
	280
	281	static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
	282	{
	283	struct dwapb_gpio_port *port = &gpio->ports[0];
	284	struct gpio_chip *gc = &port->bgc.gc;
	285	unsigned int ngpio = gc->ngpio;
	286	irq_hw_number_t hwirq;
	287
	288	if (!gpio->domain)
	289	return;
	290
	291	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
	292	irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
	293
	294	irq_domain_remove(gpio->domain);
	295	gpio->domain = NULL;
	296	}
	297
	298	static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
	299	struct device_node *port_np,
	300	unsigned int offs)
	301	{
	302	struct dwapb_gpio_port *port;
	303	u32 port_idx, ngpio;
	304	void __iomem dat, set, *dirout;
	305	int err;
	306
	307	if (of_property_read_u32(port_np, "reg", &port_idx) \|\|
	308	port_idx >= DWAPB_MAX_PORTS) {
	309	dev_err(gpio->dev, "missing/invalid port index for %s\n",
	310	port_np->full_name);
	311	return -EINVAL;
	312	}
	313
	314	port = &gpio->ports[offs];
	315	port->gpio = gpio;
	316
	317	if (of_property_read_u32(port_np, "snps,nr-gpios", &ngpio)) {
	318	dev_info(gpio->dev, "failed to get number of gpios for %s\n",
	319	port_np->full_name);
	320	ngpio = 32;
	321	}
	322
	323	dat = gpio->regs + GPIO_EXT_PORTA + (port_idx * GPIO_EXT_PORT_SIZE);
	324	set = gpio->regs + GPIO_SWPORTA_DR + (port_idx * GPIO_SWPORT_DR_SIZE);
	325	dirout = gpio->regs + GPIO_SWPORTA_DDR +
	326	(port_idx * GPIO_SWPORT_DDR_SIZE);
	327
	328	err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
	329	NULL, false);
	330	if (err) {
	331	dev_err(gpio->dev, "failed to init gpio chip for %s\n",
	332	port_np->full_name);
	333	return err;
	334	}
335
336	port->bgc.gc.ngpio = ngpio;
337	port->bgc.gc.of_node = port_np;
338
339	/*
340	* Only port A can provide interrupts in all configurations of the IP.
341	*/
342	if (port_idx == 0 &&
343	of_property_read_bool(port_np, "interrupt-controller"))
344	dwapb_configure_irqs(gpio, port);
345
346	err = gpiochip_add(&port->bgc.gc);
347	if (err)
348	dev_err(gpio->dev, "failed to register gpiochip for %s\n",
349	port_np->full_name);
350	else
351	port->is_registered = true;
352
353	return err;
354	}
355
356	static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
357	{
358	unsigned int m;
359
360	for (m = 0; m < gpio->nr_ports; ++m)
361	if (gpio->ports[m].is_registered)
9f5132ae	362	gpiochip_remove(&gpio->ports[m].bgc.gc);
7779b345 JI	363	}
	364
	365	static int dwapb_gpio_probe(struct platform_device *pdev)
	366	{
	367	struct resource *res;
	368	struct dwapb_gpio *gpio;
	369	struct device_node *np;
	370	int err;
	371	unsigned int offs = 0;
	372
	373	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	374	if (!gpio)
	375	return -ENOMEM;
	376	gpio->dev = &pdev->dev;
	377
	378	gpio->nr_ports = of_get_child_count(pdev->dev.of_node);
	379	if (!gpio->nr_ports) {
	380	err = -EINVAL;
	381	goto out_err;
	382	}
	383	gpio->ports = devm_kzalloc(&pdev->dev, gpio->nr_ports *
	384	sizeof(*gpio->ports), GFP_KERNEL);
	385	if (!gpio->ports) {
	386	err = -ENOMEM;
	387	goto out_err;
	388	}
	389
	390	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	391	gpio->regs = devm_ioremap_resource(&pdev->dev, res);
	392	if (IS_ERR(gpio->regs)) {
	393	err = PTR_ERR(gpio->regs);
	394	goto out_err;
	395	}
	396
	397	for_each_child_of_node(pdev->dev.of_node, np) {
	398	err = dwapb_gpio_add_port(gpio, np, offs++);
	399	if (err)
	400	goto out_unregister;
	401	}
	402	platform_set_drvdata(pdev, gpio);
	403
	404	return 0;
	405
	406	out_unregister:
	407	dwapb_gpio_unregister(gpio);
	408	dwapb_irq_teardown(gpio);
	409
	410	out_err:
	411	return err;
	412	}
	413
	414	static int dwapb_gpio_remove(struct platform_device *pdev)
	415	{
	416	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
	417
	418	dwapb_gpio_unregister(gpio);
	419	dwapb_irq_teardown(gpio);
	420
	421	return 0;
	422	}
	423
	424	static const struct of_device_id dwapb_of_match[] = {
	425	{ .compatible = "snps,dw-apb-gpio" },
	426	{ /* Sentinel */ }
427	};
428	MODULE_DEVICE_TABLE(of, dwapb_of_match);
429
430	static struct platform_driver dwapb_gpio_driver = {
431	.driver = {
432	.name = "gpio-dwapb",
433	.owner = THIS_MODULE,
434	.of_match_table = of_match_ptr(dwapb_of_match),
435	},
436	.probe = dwapb_gpio_probe,
437	.remove = dwapb_gpio_remove,
438	};
439
440	module_platform_driver(dwapb_gpio_driver);
441
442	MODULE_LICENSE("GPL");
443	MODULE_AUTHOR("Jamie Iles");
444	MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");