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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7779b345 JI |
2 | /* |
3 | * Copyright (c) 2011 Jamie Iles | |
4 | * | |
7779b345 JI |
5 | * All enquiries to support@picochip.com |
6 | */ | |
e6cb3486 | 7 | #include <linux/acpi.h> |
e6bf3773 | 8 | #include <linux/clk.h> |
7779b345 | 9 | #include <linux/err.h> |
e6bf3773 | 10 | #include <linux/gpio/driver.h> |
7779b345 JI |
11 | #include <linux/init.h> |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/irq.h> | |
7779b345 JI |
16 | #include <linux/module.h> |
17 | #include <linux/of.h> | |
18 | #include <linux/of_address.h> | |
a72b8c4a | 19 | #include <linux/of_device.h> |
7779b345 JI |
20 | #include <linux/of_irq.h> |
21 | #include <linux/platform_device.h> | |
4ba8cfa7 | 22 | #include <linux/property.h> |
07901a94 | 23 | #include <linux/reset.h> |
7779b345 | 24 | #include <linux/spinlock.h> |
3d2613c4 WC |
25 | #include <linux/platform_data/gpio-dwapb.h> |
26 | #include <linux/slab.h> | |
7779b345 | 27 | |
e6cb3486 | 28 | #include "gpiolib.h" |
77cb907a | 29 | #include "gpiolib-acpi.h" |
e6cb3486 | 30 | |
7779b345 JI |
31 | #define GPIO_SWPORTA_DR 0x00 |
32 | #define GPIO_SWPORTA_DDR 0x04 | |
33 | #define GPIO_SWPORTB_DR 0x0c | |
34 | #define GPIO_SWPORTB_DDR 0x10 | |
35 | #define GPIO_SWPORTC_DR 0x18 | |
36 | #define GPIO_SWPORTC_DDR 0x1c | |
37 | #define GPIO_SWPORTD_DR 0x24 | |
38 | #define GPIO_SWPORTD_DDR 0x28 | |
39 | #define GPIO_INTEN 0x30 | |
40 | #define GPIO_INTMASK 0x34 | |
41 | #define GPIO_INTTYPE_LEVEL 0x38 | |
42 | #define GPIO_INT_POLARITY 0x3c | |
43 | #define GPIO_INTSTATUS 0x40 | |
5d60d9ef | 44 | #define GPIO_PORTA_DEBOUNCE 0x48 |
7779b345 JI |
45 | #define GPIO_PORTA_EOI 0x4c |
46 | #define GPIO_EXT_PORTA 0x50 | |
47 | #define GPIO_EXT_PORTB 0x54 | |
48 | #define GPIO_EXT_PORTC 0x58 | |
49 | #define GPIO_EXT_PORTD 0x5c | |
50 | ||
c58220cb | 51 | #define DWAPB_DRIVER_NAME "gpio-dwapb" |
7779b345 | 52 | #define DWAPB_MAX_PORTS 4 |
c58220cb | 53 | |
89f99feb LW |
54 | #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */ |
55 | #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */ | |
56 | #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */ | |
7779b345 | 57 | |
a72b8c4a HT |
58 | #define GPIO_REG_OFFSET_V2 1 |
59 | ||
60 | #define GPIO_INTMASK_V2 0x44 | |
61 | #define GPIO_INTTYPE_LEVEL_V2 0x34 | |
62 | #define GPIO_INT_POLARITY_V2 0x38 | |
63 | #define GPIO_INTSTATUS_V2 0x3c | |
64 | #define GPIO_PORTA_EOI_V2 0x40 | |
65 | ||
5c544c92 SS |
66 | #define DWAPB_NR_CLOCKS 2 |
67 | ||
7779b345 JI |
68 | struct dwapb_gpio; |
69 | ||
1e960dbb WC |
70 | #ifdef CONFIG_PM_SLEEP |
71 | /* Store GPIO context across system-wide suspend/resume transitions */ | |
72 | struct dwapb_context { | |
73 | u32 data; | |
74 | u32 dir; | |
75 | u32 ext; | |
76 | u32 int_en; | |
77 | u32 int_mask; | |
78 | u32 int_type; | |
79 | u32 int_pol; | |
80 | u32 int_deb; | |
6437c7ba | 81 | u32 wake_en; |
1e960dbb WC |
82 | }; |
83 | #endif | |
84 | ||
0ea68393 SS |
85 | struct dwapb_gpio_port_irqchip { |
86 | struct irq_chip irqchip; | |
87 | unsigned int nr_irqs; | |
88 | unsigned int irq[DWAPB_MAX_GPIOS]; | |
89 | }; | |
90 | ||
7779b345 | 91 | struct dwapb_gpio_port { |
0f4630f3 | 92 | struct gpio_chip gc; |
0ea68393 | 93 | struct dwapb_gpio_port_irqchip *pirq; |
7779b345 | 94 | struct dwapb_gpio *gpio; |
1e960dbb WC |
95 | #ifdef CONFIG_PM_SLEEP |
96 | struct dwapb_context *ctx; | |
97 | #endif | |
98 | unsigned int idx; | |
7779b345 | 99 | }; |
0ea68393 SS |
100 | #define to_dwapb_gpio(_gc) \ |
101 | (container_of(_gc, struct dwapb_gpio_port, gc)->gpio) | |
7779b345 JI |
102 | |
103 | struct dwapb_gpio { | |
104 | struct device *dev; | |
105 | void __iomem *regs; | |
106 | struct dwapb_gpio_port *ports; | |
107 | unsigned int nr_ports; | |
a72b8c4a | 108 | unsigned int flags; |
07901a94 | 109 | struct reset_control *rst; |
5c544c92 | 110 | struct clk_bulk_data clks[DWAPB_NR_CLOCKS]; |
7779b345 JI |
111 | }; |
112 | ||
a72b8c4a HT |
113 | static inline u32 gpio_reg_v2_convert(unsigned int offset) |
114 | { | |
115 | switch (offset) { | |
116 | case GPIO_INTMASK: | |
117 | return GPIO_INTMASK_V2; | |
118 | case GPIO_INTTYPE_LEVEL: | |
119 | return GPIO_INTTYPE_LEVEL_V2; | |
120 | case GPIO_INT_POLARITY: | |
121 | return GPIO_INT_POLARITY_V2; | |
122 | case GPIO_INTSTATUS: | |
123 | return GPIO_INTSTATUS_V2; | |
124 | case GPIO_PORTA_EOI: | |
125 | return GPIO_PORTA_EOI_V2; | |
126 | } | |
127 | ||
128 | return offset; | |
129 | } | |
130 | ||
131 | static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset) | |
132 | { | |
133 | if (gpio->flags & GPIO_REG_OFFSET_V2) | |
134 | return gpio_reg_v2_convert(offset); | |
135 | ||
136 | return offset; | |
137 | } | |
138 | ||
67809b97 WC |
139 | static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) |
140 | { | |
0f4630f3 | 141 | struct gpio_chip *gc = &gpio->ports[0].gc; |
67809b97 WC |
142 | void __iomem *reg_base = gpio->regs; |
143 | ||
a72b8c4a | 144 | return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); |
67809b97 WC |
145 | } |
146 | ||
147 | static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, | |
148 | u32 val) | |
149 | { | |
0f4630f3 | 150 | struct gpio_chip *gc = &gpio->ports[0].gc; |
67809b97 WC |
151 | void __iomem *reg_base = gpio->regs; |
152 | ||
a72b8c4a | 153 | gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); |
67809b97 WC |
154 | } |
155 | ||
62c16234 LW |
156 | static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs) |
157 | { | |
158 | struct dwapb_gpio_port *port; | |
159 | int i; | |
160 | ||
161 | for (i = 0; i < gpio->nr_ports; i++) { | |
162 | port = &gpio->ports[i]; | |
f9f890ba | 163 | if (port->idx == offs / DWAPB_MAX_GPIOS) |
62c16234 LW |
164 | return port; |
165 | } | |
166 | ||
167 | return NULL; | |
168 | } | |
169 | ||
7779b345 JI |
170 | static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) |
171 | { | |
62c16234 LW |
172 | struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs); |
173 | struct gpio_chip *gc; | |
174 | u32 pol; | |
175 | int val; | |
176 | ||
177 | if (!port) | |
178 | return; | |
179 | gc = &port->gc; | |
7779b345 | 180 | |
62c16234 LW |
181 | pol = dwapb_read(gpio, GPIO_INT_POLARITY); |
182 | /* Just read the current value right out of the data register */ | |
f9f890ba | 183 | val = gc->get(gc, offs % DWAPB_MAX_GPIOS); |
62c16234 LW |
184 | if (val) |
185 | pol &= ~BIT(offs); | |
7779b345 | 186 | else |
62c16234 | 187 | pol |= BIT(offs); |
7779b345 | 188 | |
62c16234 | 189 | dwapb_write(gpio, GPIO_INT_POLARITY, pol); |
7779b345 JI |
190 | } |
191 | ||
3d2613c4 | 192 | static u32 dwapb_do_irq(struct dwapb_gpio *gpio) |
7779b345 | 193 | { |
0ea68393 | 194 | struct gpio_chip *gc = &gpio->ports[0].gc; |
038aa1f0 | 195 | unsigned long irq_status; |
e092bc50 | 196 | irq_hw_number_t hwirq; |
7779b345 | 197 | |
038aa1f0 | 198 | irq_status = dwapb_read(gpio, GPIO_INTSTATUS); |
f9f890ba | 199 | for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) { |
0ea68393 | 200 | int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq); |
038aa1f0 | 201 | u32 irq_type = irq_get_trigger_type(gpio_irq); |
7779b345 JI |
202 | |
203 | generic_handle_irq(gpio_irq); | |
7779b345 | 204 | |
038aa1f0 | 205 | if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
7779b345 JI |
206 | dwapb_toggle_trigger(gpio, hwirq); |
207 | } | |
208 | ||
038aa1f0 | 209 | return irq_status; |
3d2613c4 WC |
210 | } |
211 | ||
bd0b9ac4 | 212 | static void dwapb_irq_handler(struct irq_desc *desc) |
3d2613c4 | 213 | { |
476f8b4c | 214 | struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); |
3d2613c4 WC |
215 | struct irq_chip *chip = irq_desc_get_chip(desc); |
216 | ||
9b0aef32 | 217 | chained_irq_enter(chip, desc); |
3d2613c4 | 218 | dwapb_do_irq(gpio); |
9b0aef32 | 219 | chained_irq_exit(chip, desc); |
7779b345 JI |
220 | } |
221 | ||
75c1236a SS |
222 | static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id) |
223 | { | |
224 | return IRQ_RETVAL(dwapb_do_irq(dev_id)); | |
225 | } | |
226 | ||
0ea68393 SS |
227 | static void dwapb_irq_ack(struct irq_data *d) |
228 | { | |
229 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
230 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
231 | u32 val = BIT(irqd_to_hwirq(d)); | |
232 | unsigned long flags; | |
233 | ||
234 | spin_lock_irqsave(&gc->bgpio_lock, flags); | |
235 | dwapb_write(gpio, GPIO_PORTA_EOI, val); | |
236 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); | |
237 | } | |
238 | ||
239 | static void dwapb_irq_mask(struct irq_data *d) | |
240 | { | |
241 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
242 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
243 | unsigned long flags; | |
244 | u32 val; | |
245 | ||
246 | spin_lock_irqsave(&gc->bgpio_lock, flags); | |
247 | val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d)); | |
248 | dwapb_write(gpio, GPIO_INTMASK, val); | |
249 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); | |
250 | } | |
251 | ||
252 | static void dwapb_irq_unmask(struct irq_data *d) | |
253 | { | |
254 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
255 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
256 | unsigned long flags; | |
257 | u32 val; | |
258 | ||
259 | spin_lock_irqsave(&gc->bgpio_lock, flags); | |
260 | val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d)); | |
261 | dwapb_write(gpio, GPIO_INTMASK, val); | |
262 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); | |
263 | } | |
264 | ||
7779b345 JI |
265 | static void dwapb_irq_enable(struct irq_data *d) |
266 | { | |
0ea68393 SS |
267 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
268 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
7779b345 JI |
269 | unsigned long flags; |
270 | u32 val; | |
271 | ||
0f4630f3 | 272 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 | 273 | val = dwapb_read(gpio, GPIO_INTEN); |
e092bc50 | 274 | val |= BIT(irqd_to_hwirq(d)); |
67809b97 | 275 | dwapb_write(gpio, GPIO_INTEN, val); |
0f4630f3 | 276 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
277 | } |
278 | ||
279 | static void dwapb_irq_disable(struct irq_data *d) | |
280 | { | |
0ea68393 SS |
281 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
282 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
7779b345 JI |
283 | unsigned long flags; |
284 | u32 val; | |
285 | ||
0f4630f3 | 286 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 | 287 | val = dwapb_read(gpio, GPIO_INTEN); |
e092bc50 | 288 | val &= ~BIT(irqd_to_hwirq(d)); |
67809b97 | 289 | dwapb_write(gpio, GPIO_INTEN, val); |
0f4630f3 | 290 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
291 | } |
292 | ||
7779b345 JI |
293 | static int dwapb_irq_set_type(struct irq_data *d, u32 type) |
294 | { | |
0ea68393 SS |
295 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
296 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
e092bc50 | 297 | irq_hw_number_t bit = irqd_to_hwirq(d); |
7779b345 JI |
298 | unsigned long level, polarity, flags; |
299 | ||
d31275a9 | 300 | if (type & ~IRQ_TYPE_SENSE_MASK) |
7779b345 JI |
301 | return -EINVAL; |
302 | ||
0f4630f3 | 303 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
67809b97 WC |
304 | level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); |
305 | polarity = dwapb_read(gpio, GPIO_INT_POLARITY); | |
7779b345 JI |
306 | |
307 | switch (type) { | |
308 | case IRQ_TYPE_EDGE_BOTH: | |
309 | level |= BIT(bit); | |
310 | dwapb_toggle_trigger(gpio, bit); | |
311 | break; | |
312 | case IRQ_TYPE_EDGE_RISING: | |
313 | level |= BIT(bit); | |
314 | polarity |= BIT(bit); | |
315 | break; | |
316 | case IRQ_TYPE_EDGE_FALLING: | |
317 | level |= BIT(bit); | |
318 | polarity &= ~BIT(bit); | |
319 | break; | |
320 | case IRQ_TYPE_LEVEL_HIGH: | |
321 | level &= ~BIT(bit); | |
322 | polarity |= BIT(bit); | |
323 | break; | |
324 | case IRQ_TYPE_LEVEL_LOW: | |
325 | level &= ~BIT(bit); | |
326 | polarity &= ~BIT(bit); | |
327 | break; | |
328 | } | |
329 | ||
0ea68393 SS |
330 | if (type & IRQ_TYPE_LEVEL_MASK) |
331 | irq_set_handler_locked(d, handle_level_irq); | |
332 | else if (type & IRQ_TYPE_EDGE_BOTH) | |
333 | irq_set_handler_locked(d, handle_edge_irq); | |
6a2f4b7d | 334 | |
67809b97 | 335 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); |
edadced2 XC |
336 | if (type != IRQ_TYPE_EDGE_BOTH) |
337 | dwapb_write(gpio, GPIO_INT_POLARITY, polarity); | |
0f4630f3 | 338 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
7779b345 JI |
339 | |
340 | return 0; | |
341 | } | |
342 | ||
6437c7ba HT |
343 | #ifdef CONFIG_PM_SLEEP |
344 | static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable) | |
345 | { | |
3fe37204 JH |
346 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
347 | struct dwapb_gpio *gpio = to_dwapb_gpio(gc); | |
6437c7ba | 348 | struct dwapb_context *ctx = gpio->ports[0].ctx; |
e092bc50 | 349 | irq_hw_number_t bit = irqd_to_hwirq(d); |
6437c7ba HT |
350 | |
351 | if (enable) | |
e092bc50 | 352 | ctx->wake_en |= BIT(bit); |
6437c7ba | 353 | else |
e092bc50 | 354 | ctx->wake_en &= ~BIT(bit); |
6437c7ba HT |
355 | |
356 | return 0; | |
357 | } | |
358 | #endif | |
359 | ||
5d60d9ef WC |
360 | static int dwapb_gpio_set_debounce(struct gpio_chip *gc, |
361 | unsigned offset, unsigned debounce) | |
362 | { | |
0f4630f3 | 363 | struct dwapb_gpio_port *port = gpiochip_get_data(gc); |
5d60d9ef WC |
364 | struct dwapb_gpio *gpio = port->gpio; |
365 | unsigned long flags, val_deb; | |
d97a1b56 | 366 | unsigned long mask = BIT(offset); |
5d60d9ef | 367 | |
0f4630f3 | 368 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
5d60d9ef WC |
369 | |
370 | val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
371 | if (debounce) | |
48ce8056 | 372 | val_deb |= mask; |
5d60d9ef | 373 | else |
48ce8056 AS |
374 | val_deb &= ~mask; |
375 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb); | |
5d60d9ef | 376 | |
0f4630f3 | 377 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
5d60d9ef WC |
378 | |
379 | return 0; | |
380 | } | |
381 | ||
2956b5d9 MW |
382 | static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset, |
383 | unsigned long config) | |
384 | { | |
385 | u32 debounce; | |
386 | ||
387 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
388 | return -ENOTSUPP; | |
389 | ||
390 | debounce = pinconf_to_config_argument(config); | |
391 | return dwapb_gpio_set_debounce(gc, offset, debounce); | |
392 | } | |
393 | ||
0ea68393 SS |
394 | static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq, |
395 | struct dwapb_port_property *pp) | |
396 | { | |
397 | int i; | |
398 | ||
399 | /* Group all available IRQs into an array of parental IRQs. */ | |
400 | for (i = 0; i < pp->ngpio; ++i) { | |
401 | if (!pp->irq[i]) | |
402 | continue; | |
403 | ||
404 | pirq->irq[pirq->nr_irqs++] = pp->irq[i]; | |
405 | } | |
406 | ||
407 | return pirq->nr_irqs ? 0 : -ENOENT; | |
408 | } | |
409 | ||
7779b345 | 410 | static void dwapb_configure_irqs(struct dwapb_gpio *gpio, |
3d2613c4 WC |
411 | struct dwapb_gpio_port *port, |
412 | struct dwapb_port_property *pp) | |
7779b345 | 413 | { |
0ea68393 | 414 | struct dwapb_gpio_port_irqchip *pirq; |
0f4630f3 | 415 | struct gpio_chip *gc = &port->gc; |
0ea68393 SS |
416 | struct gpio_irq_chip *girq; |
417 | int err; | |
7779b345 | 418 | |
0ea68393 SS |
419 | pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL); |
420 | if (!pirq) | |
7779b345 | 421 | return; |
7779b345 | 422 | |
0ea68393 SS |
423 | if (dwapb_convert_irqs(pirq, pp)) { |
424 | dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx); | |
425 | goto err_kfree_pirq; | |
7779b345 JI |
426 | } |
427 | ||
0ea68393 SS |
428 | girq = &gc->irq; |
429 | girq->handler = handle_bad_irq; | |
430 | girq->default_type = IRQ_TYPE_NONE; | |
431 | ||
432 | port->pirq = pirq; | |
433 | pirq->irqchip.name = DWAPB_DRIVER_NAME; | |
434 | pirq->irqchip.irq_ack = dwapb_irq_ack; | |
435 | pirq->irqchip.irq_mask = dwapb_irq_mask; | |
436 | pirq->irqchip.irq_unmask = dwapb_irq_unmask; | |
437 | pirq->irqchip.irq_set_type = dwapb_irq_set_type; | |
438 | pirq->irqchip.irq_enable = dwapb_irq_enable; | |
439 | pirq->irqchip.irq_disable = dwapb_irq_disable; | |
6437c7ba | 440 | #ifdef CONFIG_PM_SLEEP |
0ea68393 | 441 | pirq->irqchip.irq_set_wake = dwapb_irq_set_wake; |
6437c7ba | 442 | #endif |
7779b345 | 443 | |
3d2613c4 | 444 | if (!pp->irq_shared) { |
0ea68393 SS |
445 | girq->num_parents = pirq->nr_irqs; |
446 | girq->parents = pirq->irq; | |
447 | girq->parent_handler_data = gpio; | |
448 | girq->parent_handler = dwapb_irq_handler; | |
3d2613c4 | 449 | } else { |
0ea68393 SS |
450 | /* This will let us handle the parent IRQ in the driver */ |
451 | girq->num_parents = 0; | |
452 | girq->parents = NULL; | |
453 | girq->parent_handler = NULL; | |
454 | ||
3d2613c4 WC |
455 | /* |
456 | * Request a shared IRQ since where MFD would have devices | |
457 | * using the same irq pin | |
458 | */ | |
e6ca26ab | 459 | err = devm_request_irq(gpio->dev, pp->irq[0], |
3d2613c4 | 460 | dwapb_irq_handler_mfd, |
c58220cb | 461 | IRQF_SHARED, DWAPB_DRIVER_NAME, gpio); |
3d2613c4 WC |
462 | if (err) { |
463 | dev_err(gpio->dev, "error requesting IRQ\n"); | |
0ea68393 | 464 | goto err_kfree_pirq; |
3d2613c4 WC |
465 | } |
466 | } | |
7779b345 | 467 | |
0ea68393 | 468 | girq->chip = &pirq->irqchip; |
7779b345 | 469 | |
0ea68393 | 470 | return; |
7779b345 | 471 | |
0ea68393 SS |
472 | err_kfree_pirq: |
473 | devm_kfree(gpio->dev, pirq); | |
7779b345 JI |
474 | } |
475 | ||
476 | static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, | |
3d2613c4 | 477 | struct dwapb_port_property *pp, |
7779b345 JI |
478 | unsigned int offs) |
479 | { | |
480 | struct dwapb_gpio_port *port; | |
7779b345 JI |
481 | void __iomem *dat, *set, *dirout; |
482 | int err; | |
483 | ||
7779b345 JI |
484 | port = &gpio->ports[offs]; |
485 | port->gpio = gpio; | |
1e960dbb WC |
486 | port->idx = pp->idx; |
487 | ||
488 | #ifdef CONFIG_PM_SLEEP | |
489 | port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); | |
490 | if (!port->ctx) | |
491 | return -ENOMEM; | |
492 | #endif | |
7779b345 | 493 | |
1475b629 AS |
494 | dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE; |
495 | set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE; | |
496 | dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE; | |
7779b345 | 497 | |
62c16234 | 498 | /* This registers 32 GPIO lines per port */ |
0f4630f3 | 499 | err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, |
d97a1b56 | 500 | NULL, 0); |
7779b345 | 501 | if (err) { |
e8159181 JQ |
502 | dev_err(gpio->dev, "failed to init gpio chip for port%d\n", |
503 | port->idx); | |
7779b345 JI |
504 | return err; |
505 | } | |
506 | ||
3d2613c4 | 507 | #ifdef CONFIG_OF_GPIO |
4ba8cfa7 | 508 | port->gc.of_node = to_of_node(pp->fwnode); |
3d2613c4 | 509 | #endif |
0f4630f3 LW |
510 | port->gc.ngpio = pp->ngpio; |
511 | port->gc.base = pp->gpio_base; | |
7779b345 | 512 | |
5d60d9ef WC |
513 | /* Only port A support debounce */ |
514 | if (pp->idx == 0) | |
2956b5d9 | 515 | port->gc.set_config = dwapb_gpio_set_config; |
5d60d9ef | 516 | |
551cb86c AS |
517 | /* Only port A can provide interrupts in all configurations of the IP */ |
518 | if (pp->idx == 0) | |
3d2613c4 | 519 | dwapb_configure_irqs(gpio, port, pp); |
7779b345 | 520 | |
feeaefd3 | 521 | err = devm_gpiochip_add_data(gpio->dev, &port->gc, port); |
494a94e3 | 522 | if (err) { |
e8159181 JQ |
523 | dev_err(gpio->dev, "failed to register gpiochip for port%d\n", |
524 | port->idx); | |
494a94e3 AS |
525 | return err; |
526 | } | |
7779b345 | 527 | |
494a94e3 | 528 | return 0; |
7779b345 JI |
529 | } |
530 | ||
4c2b54f7 AS |
531 | static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode, |
532 | struct dwapb_port_property *pp) | |
533 | { | |
534 | struct device_node *np = NULL; | |
aa90939d | 535 | int irq = -ENXIO, j; |
4c2b54f7 AS |
536 | |
537 | if (fwnode_property_read_bool(fwnode, "interrupt-controller")) | |
538 | np = to_of_node(fwnode); | |
539 | ||
540 | for (j = 0; j < pp->ngpio; j++) { | |
4c2b54f7 | 541 | if (np) |
aa90939d | 542 | irq = of_irq_get(np, j); |
4c2b54f7 | 543 | else if (has_acpi_companion(dev)) |
aa90939d AS |
544 | irq = platform_get_irq_optional(to_platform_device(dev), j); |
545 | if (irq > 0) | |
546 | pp->irq[j] = irq; | |
4c2b54f7 | 547 | } |
4c2b54f7 AS |
548 | } |
549 | ||
550 | static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev) | |
3d2613c4 | 551 | { |
4ba8cfa7 | 552 | struct fwnode_handle *fwnode; |
3d2613c4 WC |
553 | struct dwapb_platform_data *pdata; |
554 | struct dwapb_port_property *pp; | |
555 | int nports; | |
4c2b54f7 | 556 | int i; |
3d2613c4 | 557 | |
4ba8cfa7 | 558 | nports = device_get_child_node_count(dev); |
3d2613c4 WC |
559 | if (nports == 0) |
560 | return ERR_PTR(-ENODEV); | |
561 | ||
da9df93e | 562 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
3d2613c4 WC |
563 | if (!pdata) |
564 | return ERR_PTR(-ENOMEM); | |
565 | ||
da9df93e AL |
566 | pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); |
567 | if (!pdata->properties) | |
3d2613c4 | 568 | return ERR_PTR(-ENOMEM); |
3d2613c4 WC |
569 | |
570 | pdata->nports = nports; | |
571 | ||
572 | i = 0; | |
4ba8cfa7 | 573 | device_for_each_child_node(dev, fwnode) { |
3d2613c4 | 574 | pp = &pdata->properties[i++]; |
4ba8cfa7 | 575 | pp->fwnode = fwnode; |
3d2613c4 | 576 | |
4ba8cfa7 | 577 | if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || |
3d2613c4 | 578 | pp->idx >= DWAPB_MAX_PORTS) { |
e8159181 JQ |
579 | dev_err(dev, |
580 | "missing/invalid port index for port%d\n", i); | |
bfab7c8f | 581 | fwnode_handle_put(fwnode); |
3d2613c4 WC |
582 | return ERR_PTR(-EINVAL); |
583 | } | |
584 | ||
7569486d SS |
585 | if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) && |
586 | fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) { | |
e8159181 JQ |
587 | dev_info(dev, |
588 | "failed to get number of gpios for port%d\n", | |
589 | i); | |
f9f890ba | 590 | pp->ngpio = DWAPB_MAX_GPIOS; |
3d2613c4 WC |
591 | } |
592 | ||
da069d5d PE |
593 | pp->irq_shared = false; |
594 | pp->gpio_base = -1; | |
595 | ||
3d2613c4 WC |
596 | /* |
597 | * Only port A can provide interrupts in all configurations of | |
598 | * the IP. | |
599 | */ | |
4c2b54f7 AS |
600 | if (pp->idx == 0) |
601 | dwapb_get_irq(dev, fwnode, pp); | |
3d2613c4 WC |
602 | } |
603 | ||
604 | return pdata; | |
605 | } | |
606 | ||
4731d80f SS |
607 | static void dwapb_assert_reset(void *data) |
608 | { | |
609 | struct dwapb_gpio *gpio = data; | |
610 | ||
611 | reset_control_assert(gpio->rst); | |
612 | } | |
613 | ||
614 | static int dwapb_get_reset(struct dwapb_gpio *gpio) | |
615 | { | |
616 | int err; | |
617 | ||
618 | gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL); | |
7d3615ae DLM |
619 | if (IS_ERR(gpio->rst)) |
620 | return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst), | |
621 | "Cannot get reset descriptor\n"); | |
4731d80f SS |
622 | |
623 | err = reset_control_deassert(gpio->rst); | |
624 | if (err) { | |
625 | dev_err(gpio->dev, "Cannot deassert reset lane\n"); | |
626 | return err; | |
627 | } | |
628 | ||
629 | return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio); | |
630 | } | |
631 | ||
daa3f58d SS |
632 | static void dwapb_disable_clks(void *data) |
633 | { | |
634 | struct dwapb_gpio *gpio = data; | |
635 | ||
636 | clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); | |
637 | } | |
638 | ||
639 | static int dwapb_get_clks(struct dwapb_gpio *gpio) | |
640 | { | |
641 | int err; | |
642 | ||
643 | /* Optional bus and debounce clocks */ | |
644 | gpio->clks[0].id = "bus"; | |
645 | gpio->clks[1].id = "db"; | |
646 | err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS, | |
647 | gpio->clks); | |
648 | if (err) { | |
649 | dev_err(gpio->dev, "Cannot get APB/Debounce clocks\n"); | |
650 | return err; | |
651 | } | |
652 | ||
653 | err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); | |
654 | if (err) { | |
655 | dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n"); | |
656 | return err; | |
657 | } | |
658 | ||
659 | return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio); | |
660 | } | |
661 | ||
a72b8c4a HT |
662 | static const struct of_device_id dwapb_of_match[] = { |
663 | { .compatible = "snps,dw-apb-gpio", .data = (void *)0}, | |
664 | { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2}, | |
665 | { /* Sentinel */ } | |
666 | }; | |
667 | MODULE_DEVICE_TABLE(of, dwapb_of_match); | |
668 | ||
669 | static const struct acpi_device_id dwapb_acpi_match[] = { | |
670 | {"HISI0181", 0}, | |
671 | {"APMC0D07", 0}, | |
672 | {"APMC0D81", GPIO_REG_OFFSET_V2}, | |
673 | { } | |
674 | }; | |
675 | MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match); | |
676 | ||
7779b345 JI |
677 | static int dwapb_gpio_probe(struct platform_device *pdev) |
678 | { | |
3d2613c4 | 679 | unsigned int i; |
7779b345 | 680 | struct dwapb_gpio *gpio; |
7779b345 | 681 | int err; |
3d2613c4 WC |
682 | struct device *dev = &pdev->dev; |
683 | struct dwapb_platform_data *pdata = dev_get_platdata(dev); | |
3d2613c4 | 684 | |
da9df93e | 685 | if (!pdata) { |
4ba8cfa7 | 686 | pdata = dwapb_gpio_get_pdata(dev); |
3d2613c4 WC |
687 | if (IS_ERR(pdata)) |
688 | return PTR_ERR(pdata); | |
689 | } | |
7779b345 | 690 | |
da9df93e AL |
691 | if (!pdata->nports) |
692 | return -ENODEV; | |
7779b345 | 693 | |
3d2613c4 | 694 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); |
da9df93e AL |
695 | if (!gpio) |
696 | return -ENOMEM; | |
697 | ||
3d2613c4 WC |
698 | gpio->dev = &pdev->dev; |
699 | gpio->nr_ports = pdata->nports; | |
700 | ||
4731d80f SS |
701 | err = dwapb_get_reset(gpio); |
702 | if (err) | |
703 | return err; | |
07901a94 | 704 | |
3d2613c4 | 705 | gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, |
7779b345 | 706 | sizeof(*gpio->ports), GFP_KERNEL); |
da9df93e AL |
707 | if (!gpio->ports) |
708 | return -ENOMEM; | |
7779b345 | 709 | |
2a7194e9 | 710 | gpio->regs = devm_platform_ioremap_resource(pdev, 0); |
da9df93e AL |
711 | if (IS_ERR(gpio->regs)) |
712 | return PTR_ERR(gpio->regs); | |
7779b345 | 713 | |
daa3f58d SS |
714 | err = dwapb_get_clks(gpio); |
715 | if (err) | |
3ea8094c | 716 | return err; |
e6bf3773 | 717 | |
9826bbe1 | 718 | gpio->flags = (uintptr_t)device_get_match_data(dev); |
a72b8c4a | 719 | |
3d2613c4 WC |
720 | for (i = 0; i < gpio->nr_ports; i++) { |
721 | err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); | |
7779b345 | 722 | if (err) |
feeaefd3 | 723 | return err; |
7779b345 | 724 | } |
7779b345 | 725 | |
60593df6 LJ |
726 | platform_set_drvdata(pdev, gpio); |
727 | ||
7779b345 JI |
728 | return 0; |
729 | } | |
730 | ||
1e960dbb WC |
731 | #ifdef CONFIG_PM_SLEEP |
732 | static int dwapb_gpio_suspend(struct device *dev) | |
733 | { | |
deb19ac5 | 734 | struct dwapb_gpio *gpio = dev_get_drvdata(dev); |
0f4630f3 | 735 | struct gpio_chip *gc = &gpio->ports[0].gc; |
1e960dbb WC |
736 | unsigned long flags; |
737 | int i; | |
738 | ||
0f4630f3 | 739 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
1e960dbb WC |
740 | for (i = 0; i < gpio->nr_ports; i++) { |
741 | unsigned int offset; | |
742 | unsigned int idx = gpio->ports[i].idx; | |
743 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
744 | ||
89f99feb | 745 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; |
1e960dbb WC |
746 | ctx->dir = dwapb_read(gpio, offset); |
747 | ||
89f99feb | 748 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; |
1e960dbb WC |
749 | ctx->data = dwapb_read(gpio, offset); |
750 | ||
89f99feb | 751 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; |
1e960dbb WC |
752 | ctx->ext = dwapb_read(gpio, offset); |
753 | ||
754 | /* Only port A can provide interrupts */ | |
755 | if (idx == 0) { | |
756 | ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); | |
757 | ctx->int_en = dwapb_read(gpio, GPIO_INTEN); | |
758 | ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); | |
759 | ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); | |
760 | ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); | |
761 | ||
762 | /* Mask out interrupts */ | |
1afbc80c | 763 | dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); |
1e960dbb WC |
764 | } |
765 | } | |
0f4630f3 | 766 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
1e960dbb | 767 | |
5c544c92 | 768 | clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); |
e6bf3773 | 769 | |
1e960dbb WC |
770 | return 0; |
771 | } | |
772 | ||
773 | static int dwapb_gpio_resume(struct device *dev) | |
774 | { | |
deb19ac5 | 775 | struct dwapb_gpio *gpio = dev_get_drvdata(dev); |
0f4630f3 | 776 | struct gpio_chip *gc = &gpio->ports[0].gc; |
1e960dbb | 777 | unsigned long flags; |
5c544c92 | 778 | int i, err; |
1e960dbb | 779 | |
5c544c92 SS |
780 | err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); |
781 | if (err) { | |
782 | dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n"); | |
783 | return err; | |
784 | } | |
e6bf3773 | 785 | |
0f4630f3 | 786 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
1e960dbb WC |
787 | for (i = 0; i < gpio->nr_ports; i++) { |
788 | unsigned int offset; | |
789 | unsigned int idx = gpio->ports[i].idx; | |
790 | struct dwapb_context *ctx = gpio->ports[i].ctx; | |
791 | ||
89f99feb | 792 | offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; |
1e960dbb WC |
793 | dwapb_write(gpio, offset, ctx->data); |
794 | ||
89f99feb | 795 | offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; |
1e960dbb WC |
796 | dwapb_write(gpio, offset, ctx->dir); |
797 | ||
89f99feb | 798 | offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; |
1e960dbb WC |
799 | dwapb_write(gpio, offset, ctx->ext); |
800 | ||
801 | /* Only port A can provide interrupts */ | |
802 | if (idx == 0) { | |
803 | dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); | |
804 | dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); | |
805 | dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); | |
806 | dwapb_write(gpio, GPIO_INTEN, ctx->int_en); | |
807 | dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); | |
808 | ||
809 | /* Clear out spurious interrupts */ | |
810 | dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); | |
811 | } | |
812 | } | |
0f4630f3 | 813 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
1e960dbb WC |
814 | |
815 | return 0; | |
816 | } | |
817 | #endif | |
818 | ||
819 | static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend, | |
820 | dwapb_gpio_resume); | |
821 | ||
7779b345 JI |
822 | static struct platform_driver dwapb_gpio_driver = { |
823 | .driver = { | |
c58220cb | 824 | .name = DWAPB_DRIVER_NAME, |
1e960dbb | 825 | .pm = &dwapb_gpio_pm_ops, |
c59042ed AS |
826 | .of_match_table = dwapb_of_match, |
827 | .acpi_match_table = dwapb_acpi_match, | |
7779b345 JI |
828 | }, |
829 | .probe = dwapb_gpio_probe, | |
7779b345 JI |
830 | }; |
831 | ||
832 | module_platform_driver(dwapb_gpio_driver); | |
833 | ||
834 | MODULE_LICENSE("GPL"); | |
835 | MODULE_AUTHOR("Jamie Iles"); | |
836 | MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver"); | |
c58220cb | 837 | MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME); |