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Commit | Line | Data |
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aeec56e3 | 1 | /* |
c103de24 | 2 | * Generic driver for memory-mapped GPIO controllers. |
aeec56e3 AV |
3 | * |
4 | * Copyright 2008 MontaVista Software, Inc. | |
5 | * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... | |
13 | * ...`` ```````.. | |
14 | * ..The simplest form of a GPIO controller that the driver supports is`` | |
15 | * `.just a single "data" register, where GPIO state can be read and/or ` | |
16 | * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` | |
17 | * ````````` | |
18 | ___ | |
19 | _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... | |
20 | __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . | |
21 | o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` | |
22 | `....trivial..'~`.```.``` | |
23 | * ``````` | |
24 | * .```````~~~~`..`.``.``. | |
25 | * . The driver supports `... ,..```.`~~~```````````````....````.``,, | |
26 | * . big-endian notation, just`. .. A bit more sophisticated controllers , | |
27 | * . register the device with -be`. .with a pair of set/clear-bit registers , | |
28 | * `.. suffix. ```~~`````....`.` . affecting the data register and the .` | |
29 | * ``.`.``...``` ```.. output pins are also supported.` | |
30 | * ^^ `````.`````````.,``~``~``~~`````` | |
31 | * . ^^ | |
32 | * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. | |
33 | * .. The expectation is that in at least some cases . ,-~~~-, | |
34 | * .this will be used with roll-your-own ASIC/FPGA .` \ / | |
35 | * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / | |
36 | * ..````````......``````````` \o_ | |
37 | * | | |
38 | * ^^ / \ | |
39 | * | |
40 | * ...`````~~`.....``.`..........``````.`.``.```........``. | |
41 | * ` 8, 16, 32 and 64 bits registers are supported, and``. | |
42 | * . the number of GPIOs is determined by the width of ~ | |
43 | * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ | |
44 | * `.......````.``` | |
45 | */ | |
46 | ||
47 | #include <linux/init.h> | |
280df6b3 | 48 | #include <linux/err.h> |
aeec56e3 AV |
49 | #include <linux/bug.h> |
50 | #include <linux/kernel.h> | |
51 | #include <linux/module.h> | |
52 | #include <linux/spinlock.h> | |
53 | #include <linux/compiler.h> | |
54 | #include <linux/types.h> | |
55 | #include <linux/errno.h> | |
56 | #include <linux/log2.h> | |
57 | #include <linux/ioport.h> | |
58 | #include <linux/io.h> | |
59 | #include <linux/gpio.h> | |
60 | #include <linux/slab.h> | |
61 | #include <linux/platform_device.h> | |
62 | #include <linux/mod_devicetable.h> | |
63 | #include <linux/basic_mmio_gpio.h> | |
64 | ||
8467afec | 65 | static void bgpio_write8(void __iomem *reg, unsigned long data) |
aeec56e3 | 66 | { |
fd996235 | 67 | writeb(data, reg); |
aeec56e3 AV |
68 | } |
69 | ||
8467afec | 70 | static unsigned long bgpio_read8(void __iomem *reg) |
aeec56e3 | 71 | { |
fd996235 | 72 | return readb(reg); |
8467afec JI |
73 | } |
74 | ||
75 | static void bgpio_write16(void __iomem *reg, unsigned long data) | |
76 | { | |
fd996235 | 77 | writew(data, reg); |
8467afec JI |
78 | } |
79 | ||
80 | static unsigned long bgpio_read16(void __iomem *reg) | |
81 | { | |
fd996235 | 82 | return readw(reg); |
8467afec JI |
83 | } |
84 | ||
85 | static void bgpio_write32(void __iomem *reg, unsigned long data) | |
86 | { | |
fd996235 | 87 | writel(data, reg); |
8467afec JI |
88 | } |
89 | ||
90 | static unsigned long bgpio_read32(void __iomem *reg) | |
91 | { | |
fd996235 | 92 | return readl(reg); |
8467afec JI |
93 | } |
94 | ||
aeec56e3 | 95 | #if BITS_PER_LONG >= 64 |
8467afec JI |
96 | static void bgpio_write64(void __iomem *reg, unsigned long data) |
97 | { | |
fd996235 | 98 | writeq(data, reg); |
8467afec JI |
99 | } |
100 | ||
101 | static unsigned long bgpio_read64(void __iomem *reg) | |
102 | { | |
fd996235 | 103 | return readq(reg); |
aeec56e3 | 104 | } |
8467afec | 105 | #endif /* BITS_PER_LONG >= 64 */ |
aeec56e3 AV |
106 | |
107 | static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin) | |
108 | { | |
8467afec JI |
109 | return 1 << pin; |
110 | } | |
111 | ||
112 | static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc, | |
113 | unsigned int pin) | |
114 | { | |
115 | return 1 << (bgc->bits - 1 - pin); | |
aeec56e3 AV |
116 | } |
117 | ||
118 | static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) | |
119 | { | |
120 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
121 | ||
8467afec | 122 | return bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio); |
aeec56e3 AV |
123 | } |
124 | ||
125 | static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) | |
126 | { | |
127 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
8467afec | 128 | unsigned long mask = bgc->pin2mask(bgc, gpio); |
aeec56e3 AV |
129 | unsigned long flags; |
130 | ||
aeec56e3 AV |
131 | spin_lock_irqsave(&bgc->lock, flags); |
132 | ||
133 | if (val) | |
134 | bgc->data |= mask; | |
135 | else | |
136 | bgc->data &= ~mask; | |
137 | ||
8467afec | 138 | bgc->write_reg(bgc->reg_dat, bgc->data); |
aeec56e3 AV |
139 | |
140 | spin_unlock_irqrestore(&bgc->lock, flags); | |
141 | } | |
142 | ||
e027d6f9 JI |
143 | static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, |
144 | int val) | |
145 | { | |
146 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
147 | unsigned long mask = bgc->pin2mask(bgc, gpio); | |
148 | ||
149 | if (val) | |
150 | bgc->write_reg(bgc->reg_set, mask); | |
151 | else | |
152 | bgc->write_reg(bgc->reg_clr, mask); | |
153 | } | |
154 | ||
dd86a0cc JI |
155 | static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) |
156 | { | |
157 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
158 | unsigned long mask = bgc->pin2mask(bgc, gpio); | |
159 | unsigned long flags; | |
160 | ||
161 | spin_lock_irqsave(&bgc->lock, flags); | |
162 | ||
163 | if (val) | |
164 | bgc->data |= mask; | |
165 | else | |
166 | bgc->data &= ~mask; | |
167 | ||
168 | bgc->write_reg(bgc->reg_set, bgc->data); | |
169 | ||
170 | spin_unlock_irqrestore(&bgc->lock, flags); | |
171 | } | |
172 | ||
31029116 JI |
173 | static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) |
174 | { | |
175 | return 0; | |
176 | } | |
177 | ||
178 | static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, | |
179 | int val) | |
180 | { | |
181 | gc->set(gc, gpio, val); | |
182 | ||
183 | return 0; | |
184 | } | |
185 | ||
aeec56e3 AV |
186 | static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
187 | { | |
31029116 JI |
188 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
189 | unsigned long flags; | |
190 | ||
191 | spin_lock_irqsave(&bgc->lock, flags); | |
192 | ||
193 | bgc->dir &= ~bgc->pin2mask(bgc, gpio); | |
194 | bgc->write_reg(bgc->reg_dir, bgc->dir); | |
195 | ||
196 | spin_unlock_irqrestore(&bgc->lock, flags); | |
197 | ||
aeec56e3 AV |
198 | return 0; |
199 | } | |
200 | ||
201 | static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) | |
202 | { | |
31029116 JI |
203 | struct bgpio_chip *bgc = to_bgpio_chip(gc); |
204 | unsigned long flags; | |
205 | ||
206 | gc->set(gc, gpio, val); | |
207 | ||
208 | spin_lock_irqsave(&bgc->lock, flags); | |
209 | ||
210 | bgc->dir |= bgc->pin2mask(bgc, gpio); | |
211 | bgc->write_reg(bgc->reg_dir, bgc->dir); | |
212 | ||
213 | spin_unlock_irqrestore(&bgc->lock, flags); | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
218 | static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio) | |
219 | { | |
220 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
221 | unsigned long flags; | |
222 | ||
223 | spin_lock_irqsave(&bgc->lock, flags); | |
224 | ||
225 | bgc->dir |= bgc->pin2mask(bgc, gpio); | |
226 | bgc->write_reg(bgc->reg_dir, bgc->dir); | |
227 | ||
228 | spin_unlock_irqrestore(&bgc->lock, flags); | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
233 | static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val) | |
234 | { | |
235 | struct bgpio_chip *bgc = to_bgpio_chip(gc); | |
236 | unsigned long flags; | |
237 | ||
e027d6f9 JI |
238 | gc->set(gc, gpio, val); |
239 | ||
31029116 JI |
240 | spin_lock_irqsave(&bgc->lock, flags); |
241 | ||
242 | bgc->dir &= ~bgc->pin2mask(bgc, gpio); | |
243 | bgc->write_reg(bgc->reg_dir, bgc->dir); | |
244 | ||
245 | spin_unlock_irqrestore(&bgc->lock, flags); | |
246 | ||
aeec56e3 AV |
247 | return 0; |
248 | } | |
249 | ||
280df6b3 JI |
250 | static int bgpio_setup_accessors(struct device *dev, |
251 | struct bgpio_chip *bgc, | |
252 | bool be) | |
aeec56e3 | 253 | { |
8467afec JI |
254 | |
255 | switch (bgc->bits) { | |
256 | case 8: | |
257 | bgc->read_reg = bgpio_read8; | |
258 | bgc->write_reg = bgpio_write8; | |
259 | break; | |
260 | case 16: | |
261 | bgc->read_reg = bgpio_read16; | |
262 | bgc->write_reg = bgpio_write16; | |
263 | break; | |
264 | case 32: | |
265 | bgc->read_reg = bgpio_read32; | |
266 | bgc->write_reg = bgpio_write32; | |
267 | break; | |
268 | #if BITS_PER_LONG >= 64 | |
269 | case 64: | |
270 | bgc->read_reg = bgpio_read64; | |
271 | bgc->write_reg = bgpio_write64; | |
272 | break; | |
273 | #endif /* BITS_PER_LONG >= 64 */ | |
274 | default: | |
280df6b3 | 275 | dev_err(dev, "unsupported data width %u bits\n", bgc->bits); |
8467afec JI |
276 | return -EINVAL; |
277 | } | |
278 | ||
280df6b3 | 279 | bgc->pin2mask = be ? bgpio_pin2mask_be : bgpio_pin2mask; |
8467afec JI |
280 | |
281 | return 0; | |
282 | } | |
283 | ||
e027d6f9 JI |
284 | /* |
285 | * Create the device and allocate the resources. For setting GPIO's there are | |
dd86a0cc | 286 | * three supported configurations: |
e027d6f9 | 287 | * |
dd86a0cc | 288 | * - single input/output register resource (named "dat"). |
e027d6f9 | 289 | * - set/clear pair (named "set" and "clr"). |
dd86a0cc JI |
290 | * - single output register resource and single input resource ("set" and |
291 | * dat"). | |
e027d6f9 JI |
292 | * |
293 | * For the single output register, this drives a 1 by setting a bit and a zero | |
294 | * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit | |
295 | * in the set register and clears it by setting a bit in the clear register. | |
296 | * The configuration is detected by which resources are present. | |
31029116 JI |
297 | * |
298 | * For setting the GPIO direction, there are three supported configurations: | |
299 | * | |
300 | * - simple bidirection GPIO that requires no configuration. | |
301 | * - an output direction register (named "dirout") where a 1 bit | |
302 | * indicates the GPIO is an output. | |
303 | * - an input direction register (named "dirin") where a 1 bit indicates | |
304 | * the GPIO is an input. | |
e027d6f9 | 305 | */ |
280df6b3 JI |
306 | static int bgpio_setup_io(struct bgpio_chip *bgc, |
307 | void __iomem *dat, | |
308 | void __iomem *set, | |
309 | void __iomem *clr) | |
8467afec | 310 | { |
aeec56e3 | 311 | |
280df6b3 | 312 | bgc->reg_dat = dat; |
aeec56e3 | 313 | if (!bgc->reg_dat) |
280df6b3 | 314 | return -EINVAL; |
e027d6f9 | 315 | |
280df6b3 JI |
316 | if (set && clr) { |
317 | bgc->reg_set = set; | |
318 | bgc->reg_clr = clr; | |
e027d6f9 | 319 | bgc->gc.set = bgpio_set_with_clear; |
280df6b3 JI |
320 | } else if (set && !clr) { |
321 | bgc->reg_set = set; | |
dd86a0cc | 322 | bgc->gc.set = bgpio_set_set; |
e027d6f9 JI |
323 | } else { |
324 | bgc->gc.set = bgpio_set; | |
aeec56e3 AV |
325 | } |
326 | ||
dd86a0cc JI |
327 | bgc->gc.get = bgpio_get; |
328 | ||
e027d6f9 JI |
329 | return 0; |
330 | } | |
331 | ||
280df6b3 JI |
332 | static int bgpio_setup_direction(struct bgpio_chip *bgc, |
333 | void __iomem *dirout, | |
334 | void __iomem *dirin) | |
31029116 | 335 | { |
280df6b3 | 336 | if (dirout && dirin) { |
31029116 | 337 | return -EINVAL; |
280df6b3 JI |
338 | } else if (dirout) { |
339 | bgc->reg_dir = dirout; | |
31029116 JI |
340 | bgc->gc.direction_output = bgpio_dir_out; |
341 | bgc->gc.direction_input = bgpio_dir_in; | |
280df6b3 JI |
342 | } else if (dirin) { |
343 | bgc->reg_dir = dirin; | |
31029116 JI |
344 | bgc->gc.direction_output = bgpio_dir_out_inv; |
345 | bgc->gc.direction_input = bgpio_dir_in_inv; | |
346 | } else { | |
347 | bgc->gc.direction_output = bgpio_simple_dir_out; | |
348 | bgc->gc.direction_input = bgpio_simple_dir_in; | |
349 | } | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
4f5b0480 | 354 | int bgpio_remove(struct bgpio_chip *bgc) |
280df6b3 JI |
355 | { |
356 | int err = gpiochip_remove(&bgc->gc); | |
357 | ||
358 | kfree(bgc); | |
359 | ||
360 | return err; | |
361 | } | |
362 | EXPORT_SYMBOL_GPL(bgpio_remove); | |
363 | ||
4f5b0480 RK |
364 | int bgpio_init(struct bgpio_chip *bgc, struct device *dev, |
365 | unsigned long sz, void __iomem *dat, void __iomem *set, | |
366 | void __iomem *clr, void __iomem *dirout, void __iomem *dirin, | |
3e11f7b8 | 367 | unsigned long flags) |
e027d6f9 | 368 | { |
e027d6f9 | 369 | int ret; |
e027d6f9 | 370 | |
280df6b3 JI |
371 | if (!is_power_of_2(sz)) |
372 | return -EINVAL; | |
e027d6f9 | 373 | |
280df6b3 JI |
374 | bgc->bits = sz * 8; |
375 | if (bgc->bits > BITS_PER_LONG) | |
376 | return -EINVAL; | |
377 | ||
378 | spin_lock_init(&bgc->lock); | |
379 | bgc->gc.dev = dev; | |
380 | bgc->gc.label = dev_name(dev); | |
381 | bgc->gc.base = -1; | |
382 | bgc->gc.ngpio = bgc->bits; | |
383 | ||
384 | ret = bgpio_setup_io(bgc, dat, set, clr); | |
e027d6f9 JI |
385 | if (ret) |
386 | return ret; | |
aeec56e3 | 387 | |
3e11f7b8 | 388 | ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN); |
8467afec JI |
389 | if (ret) |
390 | return ret; | |
aeec56e3 | 391 | |
280df6b3 | 392 | ret = bgpio_setup_direction(bgc, dirout, dirin); |
31029116 JI |
393 | if (ret) |
394 | return ret; | |
395 | ||
8467afec | 396 | bgc->data = bgc->read_reg(bgc->reg_dat); |
3e11f7b8 SG |
397 | if (bgc->gc.set == bgpio_set_set && |
398 | !(flags & BGPIOF_UNREADABLE_REG_SET)) | |
399 | bgc->data = bgc->read_reg(bgc->reg_set); | |
400 | if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR)) | |
401 | bgc->dir = bgc->read_reg(bgc->reg_dir); | |
924e7a9f | 402 | |
280df6b3 JI |
403 | return ret; |
404 | } | |
405 | EXPORT_SYMBOL_GPL(bgpio_init); | |
aeec56e3 | 406 | |
c103de24 | 407 | #ifdef CONFIG_GPIO_GENERIC_PLATFORM |
aeec56e3 | 408 | |
280df6b3 JI |
409 | static void __iomem *bgpio_map(struct platform_device *pdev, |
410 | const char *name, | |
411 | resource_size_t sane_sz, | |
412 | int *err) | |
413 | { | |
414 | struct device *dev = &pdev->dev; | |
415 | struct resource *r; | |
416 | resource_size_t start; | |
417 | resource_size_t sz; | |
418 | void __iomem *ret; | |
419 | ||
420 | *err = 0; | |
421 | ||
422 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
423 | if (!r) | |
424 | return NULL; | |
425 | ||
426 | sz = resource_size(r); | |
427 | if (sz != sane_sz) { | |
428 | *err = -EINVAL; | |
429 | return NULL; | |
430 | } | |
431 | ||
432 | start = r->start; | |
433 | if (!devm_request_mem_region(dev, start, sz, r->name)) { | |
434 | *err = -EBUSY; | |
435 | return NULL; | |
436 | } | |
437 | ||
438 | ret = devm_ioremap(dev, start, sz); | |
439 | if (!ret) { | |
440 | *err = -ENOMEM; | |
441 | return NULL; | |
442 | } | |
aeec56e3 AV |
443 | |
444 | return ret; | |
445 | } | |
446 | ||
3836309d | 447 | static int bgpio_pdev_probe(struct platform_device *pdev) |
280df6b3 JI |
448 | { |
449 | struct device *dev = &pdev->dev; | |
450 | struct resource *r; | |
451 | void __iomem *dat; | |
452 | void __iomem *set; | |
453 | void __iomem *clr; | |
454 | void __iomem *dirout; | |
455 | void __iomem *dirin; | |
456 | unsigned long sz; | |
3e11f7b8 | 457 | unsigned long flags = 0; |
280df6b3 JI |
458 | int err; |
459 | struct bgpio_chip *bgc; | |
460 | struct bgpio_pdata *pdata = dev_get_platdata(dev); | |
461 | ||
462 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); | |
463 | if (!r) | |
464 | return -EINVAL; | |
465 | ||
466 | sz = resource_size(r); | |
467 | ||
468 | dat = bgpio_map(pdev, "dat", sz, &err); | |
469 | if (!dat) | |
470 | return err ? err : -EINVAL; | |
471 | ||
472 | set = bgpio_map(pdev, "set", sz, &err); | |
473 | if (err) | |
474 | return err; | |
475 | ||
476 | clr = bgpio_map(pdev, "clr", sz, &err); | |
477 | if (err) | |
478 | return err; | |
479 | ||
480 | dirout = bgpio_map(pdev, "dirout", sz, &err); | |
481 | if (err) | |
482 | return err; | |
483 | ||
484 | dirin = bgpio_map(pdev, "dirin", sz, &err); | |
485 | if (err) | |
486 | return err; | |
487 | ||
3e11f7b8 SG |
488 | if (!strcmp(platform_get_device_id(pdev)->name, "basic-mmio-gpio-be")) |
489 | flags |= BGPIOF_BIG_ENDIAN; | |
280df6b3 JI |
490 | |
491 | bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL); | |
492 | if (!bgc) | |
493 | return -ENOMEM; | |
494 | ||
3e11f7b8 | 495 | err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags); |
280df6b3 JI |
496 | if (err) |
497 | return err; | |
498 | ||
499 | if (pdata) { | |
500 | bgc->gc.base = pdata->base; | |
501 | if (pdata->ngpio > 0) | |
502 | bgc->gc.ngpio = pdata->ngpio; | |
503 | } | |
504 | ||
505 | platform_set_drvdata(pdev, bgc); | |
506 | ||
507 | return gpiochip_add(&bgc->gc); | |
508 | } | |
509 | ||
206210ce | 510 | static int bgpio_pdev_remove(struct platform_device *pdev) |
aeec56e3 | 511 | { |
4ddb8ae2 | 512 | struct bgpio_chip *bgc = platform_get_drvdata(pdev); |
aeec56e3 | 513 | |
280df6b3 | 514 | return bgpio_remove(bgc); |
aeec56e3 AV |
515 | } |
516 | ||
517 | static const struct platform_device_id bgpio_id_table[] = { | |
518 | { "basic-mmio-gpio", }, | |
519 | { "basic-mmio-gpio-be", }, | |
520 | {}, | |
521 | }; | |
522 | MODULE_DEVICE_TABLE(platform, bgpio_id_table); | |
523 | ||
524 | static struct platform_driver bgpio_driver = { | |
525 | .driver = { | |
526 | .name = "basic-mmio-gpio", | |
527 | }, | |
528 | .id_table = bgpio_id_table, | |
280df6b3 | 529 | .probe = bgpio_pdev_probe, |
8283c4ff | 530 | .remove = bgpio_pdev_remove, |
aeec56e3 AV |
531 | }; |
532 | ||
6f61415e | 533 | module_platform_driver(bgpio_driver); |
280df6b3 | 534 | |
c103de24 | 535 | #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ |
aeec56e3 AV |
536 | |
537 | MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); | |
538 | MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); | |
539 | MODULE_LICENSE("GPL"); |