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Commit | Line | Data |
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aeec56e3 | 1 | /* |
c103de24 | 2 | * Generic driver for memory-mapped GPIO controllers. |
aeec56e3 AV |
3 | * |
4 | * Copyright 2008 MontaVista Software, Inc. | |
5 | * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... | |
13 | * ...`` ```````.. | |
14 | * ..The simplest form of a GPIO controller that the driver supports is`` | |
15 | * `.just a single "data" register, where GPIO state can be read and/or ` | |
16 | * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` | |
17 | * ````````` | |
18 | ___ | |
19 | _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... | |
20 | __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . | |
21 | o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` | |
22 | `....trivial..'~`.```.``` | |
23 | * ``````` | |
24 | * .```````~~~~`..`.``.``. | |
25 | * . The driver supports `... ,..```.`~~~```````````````....````.``,, | |
26 | * . big-endian notation, just`. .. A bit more sophisticated controllers , | |
27 | * . register the device with -be`. .with a pair of set/clear-bit registers , | |
28 | * `.. suffix. ```~~`````....`.` . affecting the data register and the .` | |
29 | * ``.`.``...``` ```.. output pins are also supported.` | |
30 | * ^^ `````.`````````.,``~``~``~~`````` | |
31 | * . ^^ | |
32 | * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. | |
33 | * .. The expectation is that in at least some cases . ,-~~~-, | |
34 | * .this will be used with roll-your-own ASIC/FPGA .` \ / | |
35 | * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / | |
36 | * ..````````......``````````` \o_ | |
37 | * | | |
38 | * ^^ / \ | |
39 | * | |
40 | * ...`````~~`.....``.`..........``````.`.``.```........``. | |
41 | * ` 8, 16, 32 and 64 bits registers are supported, and``. | |
42 | * . the number of GPIOs is determined by the width of ~ | |
43 | * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ | |
44 | * `.......````.``` | |
45 | */ | |
46 | ||
47 | #include <linux/init.h> | |
280df6b3 | 48 | #include <linux/err.h> |
aeec56e3 AV |
49 | #include <linux/bug.h> |
50 | #include <linux/kernel.h> | |
51 | #include <linux/module.h> | |
52 | #include <linux/spinlock.h> | |
53 | #include <linux/compiler.h> | |
54 | #include <linux/types.h> | |
55 | #include <linux/errno.h> | |
56 | #include <linux/log2.h> | |
57 | #include <linux/ioport.h> | |
58 | #include <linux/io.h> | |
0f4630f3 | 59 | #include <linux/gpio/driver.h> |
aeec56e3 | 60 | #include <linux/slab.h> |
4b63739e | 61 | #include <linux/bitops.h> |
aeec56e3 AV |
62 | #include <linux/platform_device.h> |
63 | #include <linux/mod_devicetable.h> | |
aeec56e3 | 64 | |
8467afec | 65 | static void bgpio_write8(void __iomem *reg, unsigned long data) |
aeec56e3 | 66 | { |
fd996235 | 67 | writeb(data, reg); |
aeec56e3 AV |
68 | } |
69 | ||
8467afec | 70 | static unsigned long bgpio_read8(void __iomem *reg) |
aeec56e3 | 71 | { |
fd996235 | 72 | return readb(reg); |
8467afec JI |
73 | } |
74 | ||
75 | static void bgpio_write16(void __iomem *reg, unsigned long data) | |
76 | { | |
fd996235 | 77 | writew(data, reg); |
8467afec JI |
78 | } |
79 | ||
80 | static unsigned long bgpio_read16(void __iomem *reg) | |
81 | { | |
fd996235 | 82 | return readw(reg); |
8467afec JI |
83 | } |
84 | ||
85 | static void bgpio_write32(void __iomem *reg, unsigned long data) | |
86 | { | |
fd996235 | 87 | writel(data, reg); |
8467afec JI |
88 | } |
89 | ||
90 | static unsigned long bgpio_read32(void __iomem *reg) | |
91 | { | |
fd996235 | 92 | return readl(reg); |
8467afec JI |
93 | } |
94 | ||
aeec56e3 | 95 | #if BITS_PER_LONG >= 64 |
8467afec JI |
96 | static void bgpio_write64(void __iomem *reg, unsigned long data) |
97 | { | |
fd996235 | 98 | writeq(data, reg); |
8467afec JI |
99 | } |
100 | ||
101 | static unsigned long bgpio_read64(void __iomem *reg) | |
102 | { | |
fd996235 | 103 | return readq(reg); |
aeec56e3 | 104 | } |
8467afec | 105 | #endif /* BITS_PER_LONG >= 64 */ |
aeec56e3 | 106 | |
2b78f1e1 AL |
107 | static void bgpio_write16be(void __iomem *reg, unsigned long data) |
108 | { | |
109 | iowrite16be(data, reg); | |
110 | } | |
111 | ||
112 | static unsigned long bgpio_read16be(void __iomem *reg) | |
113 | { | |
114 | return ioread16be(reg); | |
115 | } | |
116 | ||
117 | static void bgpio_write32be(void __iomem *reg, unsigned long data) | |
118 | { | |
119 | iowrite32be(data, reg); | |
120 | } | |
121 | ||
122 | static unsigned long bgpio_read32be(void __iomem *reg) | |
123 | { | |
124 | return ioread32be(reg); | |
125 | } | |
126 | ||
0f4630f3 | 127 | static unsigned long bgpio_pin2mask(struct gpio_chip *gc, unsigned int pin) |
aeec56e3 | 128 | { |
4b63739e | 129 | return BIT(pin); |
8467afec JI |
130 | } |
131 | ||
0f4630f3 | 132 | static unsigned long bgpio_pin2mask_be(struct gpio_chip *gc, |
8467afec JI |
133 | unsigned int pin) |
134 | { | |
0f4630f3 | 135 | return BIT(gc->bgpio_bits - 1 - pin); |
aeec56e3 AV |
136 | } |
137 | ||
b19e7f51 VZ |
138 | static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) |
139 | { | |
0f4630f3 | 140 | unsigned long pinmask = gc->pin2mask(gc, gpio); |
b19e7f51 | 141 | |
0f4630f3 LW |
142 | if (gc->bgpio_dir & pinmask) |
143 | return !!(gc->read_reg(gc->reg_set) & pinmask); | |
b19e7f51 | 144 | else |
0f4630f3 | 145 | return !!(gc->read_reg(gc->reg_dat) & pinmask); |
b19e7f51 VZ |
146 | } |
147 | ||
aeec56e3 AV |
148 | static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) |
149 | { | |
0f4630f3 | 150 | return !!(gc->read_reg(gc->reg_dat) & gc->pin2mask(gc, gpio)); |
aeec56e3 AV |
151 | } |
152 | ||
91492a44 RV |
153 | static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) |
154 | { | |
155 | } | |
156 | ||
aeec56e3 AV |
157 | static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
158 | { | |
0f4630f3 | 159 | unsigned long mask = gc->pin2mask(gc, gpio); |
aeec56e3 AV |
160 | unsigned long flags; |
161 | ||
0f4630f3 | 162 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
aeec56e3 AV |
163 | |
164 | if (val) | |
0f4630f3 | 165 | gc->bgpio_data |= mask; |
aeec56e3 | 166 | else |
0f4630f3 | 167 | gc->bgpio_data &= ~mask; |
aeec56e3 | 168 | |
0f4630f3 | 169 | gc->write_reg(gc->reg_dat, gc->bgpio_data); |
aeec56e3 | 170 | |
0f4630f3 | 171 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
aeec56e3 AV |
172 | } |
173 | ||
e027d6f9 JI |
174 | static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, |
175 | int val) | |
176 | { | |
0f4630f3 | 177 | unsigned long mask = gc->pin2mask(gc, gpio); |
e027d6f9 JI |
178 | |
179 | if (val) | |
0f4630f3 | 180 | gc->write_reg(gc->reg_set, mask); |
e027d6f9 | 181 | else |
0f4630f3 | 182 | gc->write_reg(gc->reg_clr, mask); |
e027d6f9 JI |
183 | } |
184 | ||
dd86a0cc JI |
185 | static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) |
186 | { | |
0f4630f3 | 187 | unsigned long mask = gc->pin2mask(gc, gpio); |
dd86a0cc JI |
188 | unsigned long flags; |
189 | ||
0f4630f3 | 190 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
dd86a0cc JI |
191 | |
192 | if (val) | |
0f4630f3 | 193 | gc->bgpio_data |= mask; |
dd86a0cc | 194 | else |
0f4630f3 | 195 | gc->bgpio_data &= ~mask; |
dd86a0cc | 196 | |
0f4630f3 | 197 | gc->write_reg(gc->reg_set, gc->bgpio_data); |
dd86a0cc | 198 | |
0f4630f3 | 199 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
dd86a0cc JI |
200 | } |
201 | ||
0f4630f3 | 202 | static void bgpio_multiple_get_masks(struct gpio_chip *gc, |
73c4ceda RI |
203 | unsigned long *mask, unsigned long *bits, |
204 | unsigned long *set_mask, | |
205 | unsigned long *clear_mask) | |
206 | { | |
207 | int i; | |
208 | ||
209 | *set_mask = 0; | |
210 | *clear_mask = 0; | |
211 | ||
0f4630f3 | 212 | for (i = 0; i < gc->bgpio_bits; i++) { |
73c4ceda RI |
213 | if (*mask == 0) |
214 | break; | |
215 | if (__test_and_clear_bit(i, mask)) { | |
216 | if (test_bit(i, bits)) | |
0f4630f3 | 217 | *set_mask |= gc->pin2mask(gc, i); |
73c4ceda | 218 | else |
0f4630f3 | 219 | *clear_mask |= gc->pin2mask(gc, i); |
73c4ceda RI |
220 | } |
221 | } | |
222 | } | |
223 | ||
0f4630f3 | 224 | static void bgpio_set_multiple_single_reg(struct gpio_chip *gc, |
73c4ceda RI |
225 | unsigned long *mask, |
226 | unsigned long *bits, | |
227 | void __iomem *reg) | |
228 | { | |
229 | unsigned long flags; | |
230 | unsigned long set_mask, clear_mask; | |
231 | ||
0f4630f3 | 232 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
73c4ceda | 233 | |
0f4630f3 | 234 | bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); |
73c4ceda | 235 | |
0f4630f3 LW |
236 | gc->bgpio_data |= set_mask; |
237 | gc->bgpio_data &= ~clear_mask; | |
73c4ceda | 238 | |
0f4630f3 | 239 | gc->write_reg(reg, gc->bgpio_data); |
73c4ceda | 240 | |
0f4630f3 | 241 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
73c4ceda RI |
242 | } |
243 | ||
244 | static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, | |
245 | unsigned long *bits) | |
246 | { | |
0f4630f3 | 247 | bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); |
73c4ceda RI |
248 | } |
249 | ||
250 | static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, | |
251 | unsigned long *bits) | |
252 | { | |
0f4630f3 | 253 | bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); |
73c4ceda RI |
254 | } |
255 | ||
256 | static void bgpio_set_multiple_with_clear(struct gpio_chip *gc, | |
257 | unsigned long *mask, | |
258 | unsigned long *bits) | |
259 | { | |
73c4ceda RI |
260 | unsigned long set_mask, clear_mask; |
261 | ||
0f4630f3 | 262 | bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); |
73c4ceda RI |
263 | |
264 | if (set_mask) | |
0f4630f3 | 265 | gc->write_reg(gc->reg_set, set_mask); |
73c4ceda | 266 | if (clear_mask) |
0f4630f3 | 267 | gc->write_reg(gc->reg_clr, clear_mask); |
73c4ceda RI |
268 | } |
269 | ||
31029116 JI |
270 | static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) |
271 | { | |
272 | return 0; | |
273 | } | |
274 | ||
91492a44 RV |
275 | static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, |
276 | int val) | |
277 | { | |
278 | return -EINVAL; | |
279 | } | |
280 | ||
31029116 JI |
281 | static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, |
282 | int val) | |
283 | { | |
284 | gc->set(gc, gpio, val); | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
aeec56e3 AV |
289 | static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
290 | { | |
31029116 JI |
291 | unsigned long flags; |
292 | ||
0f4630f3 | 293 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 294 | |
0f4630f3 LW |
295 | gc->bgpio_dir &= ~gc->pin2mask(gc, gpio); |
296 | gc->write_reg(gc->reg_dir, gc->bgpio_dir); | |
31029116 | 297 | |
0f4630f3 | 298 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 | 299 | |
aeec56e3 AV |
300 | return 0; |
301 | } | |
302 | ||
db3b0fcc PZ |
303 | static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) |
304 | { | |
0f4630f3 LW |
305 | /* Return 0 if output, 1 of input */ |
306 | return !(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio)); | |
db3b0fcc PZ |
307 | } |
308 | ||
aeec56e3 AV |
309 | static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
310 | { | |
31029116 JI |
311 | unsigned long flags; |
312 | ||
313 | gc->set(gc, gpio, val); | |
314 | ||
0f4630f3 | 315 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 316 | |
0f4630f3 LW |
317 | gc->bgpio_dir |= gc->pin2mask(gc, gpio); |
318 | gc->write_reg(gc->reg_dir, gc->bgpio_dir); | |
31029116 | 319 | |
0f4630f3 | 320 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 JI |
321 | |
322 | return 0; | |
323 | } | |
324 | ||
325 | static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio) | |
326 | { | |
31029116 JI |
327 | unsigned long flags; |
328 | ||
0f4630f3 | 329 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 330 | |
0f4630f3 LW |
331 | gc->bgpio_dir |= gc->pin2mask(gc, gpio); |
332 | gc->write_reg(gc->reg_dir, gc->bgpio_dir); | |
31029116 | 333 | |
0f4630f3 | 334 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 JI |
335 | |
336 | return 0; | |
337 | } | |
338 | ||
339 | static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val) | |
340 | { | |
31029116 JI |
341 | unsigned long flags; |
342 | ||
e027d6f9 JI |
343 | gc->set(gc, gpio, val); |
344 | ||
0f4630f3 | 345 | spin_lock_irqsave(&gc->bgpio_lock, flags); |
31029116 | 346 | |
0f4630f3 LW |
347 | gc->bgpio_dir &= ~gc->pin2mask(gc, gpio); |
348 | gc->write_reg(gc->reg_dir, gc->bgpio_dir); | |
31029116 | 349 | |
0f4630f3 | 350 | spin_unlock_irqrestore(&gc->bgpio_lock, flags); |
31029116 | 351 | |
aeec56e3 AV |
352 | return 0; |
353 | } | |
354 | ||
db3b0fcc PZ |
355 | static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio) |
356 | { | |
0f4630f3 LW |
357 | /* Return 0 if output, 1 if input */ |
358 | return !!(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio)); | |
db3b0fcc PZ |
359 | } |
360 | ||
280df6b3 | 361 | static int bgpio_setup_accessors(struct device *dev, |
0f4630f3 | 362 | struct gpio_chip *gc, |
2b78f1e1 AL |
363 | bool bit_be, |
364 | bool byte_be) | |
aeec56e3 | 365 | { |
8467afec | 366 | |
0f4630f3 | 367 | switch (gc->bgpio_bits) { |
8467afec | 368 | case 8: |
0f4630f3 LW |
369 | gc->read_reg = bgpio_read8; |
370 | gc->write_reg = bgpio_write8; | |
8467afec JI |
371 | break; |
372 | case 16: | |
2b78f1e1 | 373 | if (byte_be) { |
0f4630f3 LW |
374 | gc->read_reg = bgpio_read16be; |
375 | gc->write_reg = bgpio_write16be; | |
2b78f1e1 | 376 | } else { |
0f4630f3 LW |
377 | gc->read_reg = bgpio_read16; |
378 | gc->write_reg = bgpio_write16; | |
2b78f1e1 | 379 | } |
8467afec JI |
380 | break; |
381 | case 32: | |
2b78f1e1 | 382 | if (byte_be) { |
0f4630f3 LW |
383 | gc->read_reg = bgpio_read32be; |
384 | gc->write_reg = bgpio_write32be; | |
2b78f1e1 | 385 | } else { |
0f4630f3 LW |
386 | gc->read_reg = bgpio_read32; |
387 | gc->write_reg = bgpio_write32; | |
2b78f1e1 | 388 | } |
8467afec JI |
389 | break; |
390 | #if BITS_PER_LONG >= 64 | |
391 | case 64: | |
2b78f1e1 AL |
392 | if (byte_be) { |
393 | dev_err(dev, | |
394 | "64 bit big endian byte order unsupported\n"); | |
395 | return -EINVAL; | |
396 | } else { | |
0f4630f3 LW |
397 | gc->read_reg = bgpio_read64; |
398 | gc->write_reg = bgpio_write64; | |
2b78f1e1 | 399 | } |
8467afec JI |
400 | break; |
401 | #endif /* BITS_PER_LONG >= 64 */ | |
402 | default: | |
0f4630f3 | 403 | dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits); |
8467afec JI |
404 | return -EINVAL; |
405 | } | |
406 | ||
0f4630f3 | 407 | gc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask; |
8467afec JI |
408 | |
409 | return 0; | |
410 | } | |
411 | ||
e027d6f9 JI |
412 | /* |
413 | * Create the device and allocate the resources. For setting GPIO's there are | |
dd86a0cc | 414 | * three supported configurations: |
e027d6f9 | 415 | * |
dd86a0cc | 416 | * - single input/output register resource (named "dat"). |
e027d6f9 | 417 | * - set/clear pair (named "set" and "clr"). |
dd86a0cc JI |
418 | * - single output register resource and single input resource ("set" and |
419 | * dat"). | |
e027d6f9 JI |
420 | * |
421 | * For the single output register, this drives a 1 by setting a bit and a zero | |
422 | * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit | |
423 | * in the set register and clears it by setting a bit in the clear register. | |
424 | * The configuration is detected by which resources are present. | |
31029116 JI |
425 | * |
426 | * For setting the GPIO direction, there are three supported configurations: | |
427 | * | |
428 | * - simple bidirection GPIO that requires no configuration. | |
429 | * - an output direction register (named "dirout") where a 1 bit | |
430 | * indicates the GPIO is an output. | |
431 | * - an input direction register (named "dirin") where a 1 bit indicates | |
432 | * the GPIO is an input. | |
e027d6f9 | 433 | */ |
0f4630f3 | 434 | static int bgpio_setup_io(struct gpio_chip *gc, |
280df6b3 JI |
435 | void __iomem *dat, |
436 | void __iomem *set, | |
b19e7f51 VZ |
437 | void __iomem *clr, |
438 | unsigned long flags) | |
8467afec | 439 | { |
aeec56e3 | 440 | |
0f4630f3 LW |
441 | gc->reg_dat = dat; |
442 | if (!gc->reg_dat) | |
280df6b3 | 443 | return -EINVAL; |
e027d6f9 | 444 | |
280df6b3 | 445 | if (set && clr) { |
0f4630f3 LW |
446 | gc->reg_set = set; |
447 | gc->reg_clr = clr; | |
448 | gc->set = bgpio_set_with_clear; | |
449 | gc->set_multiple = bgpio_set_multiple_with_clear; | |
280df6b3 | 450 | } else if (set && !clr) { |
0f4630f3 LW |
451 | gc->reg_set = set; |
452 | gc->set = bgpio_set_set; | |
453 | gc->set_multiple = bgpio_set_multiple_set; | |
91492a44 | 454 | } else if (flags & BGPIOF_NO_OUTPUT) { |
0f4630f3 LW |
455 | gc->set = bgpio_set_none; |
456 | gc->set_multiple = NULL; | |
e027d6f9 | 457 | } else { |
0f4630f3 LW |
458 | gc->set = bgpio_set; |
459 | gc->set_multiple = bgpio_set_multiple; | |
aeec56e3 AV |
460 | } |
461 | ||
b19e7f51 VZ |
462 | if (!(flags & BGPIOF_UNREADABLE_REG_SET) && |
463 | (flags & BGPIOF_READ_OUTPUT_REG_SET)) | |
0f4630f3 | 464 | gc->get = bgpio_get_set; |
b19e7f51 | 465 | else |
0f4630f3 | 466 | gc->get = bgpio_get; |
dd86a0cc | 467 | |
e027d6f9 JI |
468 | return 0; |
469 | } | |
470 | ||
0f4630f3 | 471 | static int bgpio_setup_direction(struct gpio_chip *gc, |
280df6b3 | 472 | void __iomem *dirout, |
91492a44 RV |
473 | void __iomem *dirin, |
474 | unsigned long flags) | |
31029116 | 475 | { |
280df6b3 | 476 | if (dirout && dirin) { |
31029116 | 477 | return -EINVAL; |
280df6b3 | 478 | } else if (dirout) { |
0f4630f3 LW |
479 | gc->reg_dir = dirout; |
480 | gc->direction_output = bgpio_dir_out; | |
481 | gc->direction_input = bgpio_dir_in; | |
482 | gc->get_direction = bgpio_get_dir; | |
280df6b3 | 483 | } else if (dirin) { |
0f4630f3 LW |
484 | gc->reg_dir = dirin; |
485 | gc->direction_output = bgpio_dir_out_inv; | |
486 | gc->direction_input = bgpio_dir_in_inv; | |
487 | gc->get_direction = bgpio_get_dir_inv; | |
31029116 | 488 | } else { |
91492a44 | 489 | if (flags & BGPIOF_NO_OUTPUT) |
0f4630f3 | 490 | gc->direction_output = bgpio_dir_out_err; |
91492a44 | 491 | else |
0f4630f3 LW |
492 | gc->direction_output = bgpio_simple_dir_out; |
493 | gc->direction_input = bgpio_simple_dir_in; | |
31029116 JI |
494 | } |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
7b42e3db AF |
499 | static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) |
500 | { | |
501 | if (gpio_pin < chip->ngpio) | |
502 | return 0; | |
503 | ||
504 | return -EINVAL; | |
505 | } | |
506 | ||
0f4630f3 | 507 | int bgpio_init(struct gpio_chip *gc, struct device *dev, |
4f5b0480 RK |
508 | unsigned long sz, void __iomem *dat, void __iomem *set, |
509 | void __iomem *clr, void __iomem *dirout, void __iomem *dirin, | |
3e11f7b8 | 510 | unsigned long flags) |
e027d6f9 | 511 | { |
e027d6f9 | 512 | int ret; |
e027d6f9 | 513 | |
280df6b3 JI |
514 | if (!is_power_of_2(sz)) |
515 | return -EINVAL; | |
e027d6f9 | 516 | |
0f4630f3 LW |
517 | gc->bgpio_bits = sz * 8; |
518 | if (gc->bgpio_bits > BITS_PER_LONG) | |
280df6b3 JI |
519 | return -EINVAL; |
520 | ||
0f4630f3 LW |
521 | spin_lock_init(&gc->bgpio_lock); |
522 | gc->parent = dev; | |
523 | gc->label = dev_name(dev); | |
524 | gc->base = -1; | |
525 | gc->ngpio = gc->bgpio_bits; | |
526 | gc->request = bgpio_request; | |
280df6b3 | 527 | |
0f4630f3 | 528 | ret = bgpio_setup_io(gc, dat, set, clr, flags); |
e027d6f9 JI |
529 | if (ret) |
530 | return ret; | |
aeec56e3 | 531 | |
0f4630f3 | 532 | ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN, |
2b78f1e1 | 533 | flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); |
8467afec JI |
534 | if (ret) |
535 | return ret; | |
aeec56e3 | 536 | |
0f4630f3 | 537 | ret = bgpio_setup_direction(gc, dirout, dirin, flags); |
31029116 JI |
538 | if (ret) |
539 | return ret; | |
540 | ||
0f4630f3 LW |
541 | gc->bgpio_data = gc->read_reg(gc->reg_dat); |
542 | if (gc->set == bgpio_set_set && | |
3e11f7b8 | 543 | !(flags & BGPIOF_UNREADABLE_REG_SET)) |
0f4630f3 LW |
544 | gc->bgpio_data = gc->read_reg(gc->reg_set); |
545 | if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR)) | |
546 | gc->bgpio_dir = gc->read_reg(gc->reg_dir); | |
924e7a9f | 547 | |
280df6b3 JI |
548 | return ret; |
549 | } | |
550 | EXPORT_SYMBOL_GPL(bgpio_init); | |
aeec56e3 | 551 | |
8f01c9d0 | 552 | #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) |
aeec56e3 | 553 | |
280df6b3 JI |
554 | static void __iomem *bgpio_map(struct platform_device *pdev, |
555 | const char *name, | |
8d240260 | 556 | resource_size_t sane_sz) |
280df6b3 | 557 | { |
280df6b3 | 558 | struct resource *r; |
280df6b3 | 559 | resource_size_t sz; |
280df6b3 JI |
560 | |
561 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); | |
8d240260 | 562 | if (!r) |
b2f68b63 | 563 | return NULL; |
280df6b3 JI |
564 | |
565 | sz = resource_size(r); | |
8d240260 HK |
566 | if (sz != sane_sz) |
567 | return IOMEM_ERR_PTR(-EINVAL); | |
280df6b3 | 568 | |
8d240260 | 569 | return devm_ioremap_resource(&pdev->dev, r); |
aeec56e3 AV |
570 | } |
571 | ||
3836309d | 572 | static int bgpio_pdev_probe(struct platform_device *pdev) |
280df6b3 JI |
573 | { |
574 | struct device *dev = &pdev->dev; | |
575 | struct resource *r; | |
576 | void __iomem *dat; | |
577 | void __iomem *set; | |
578 | void __iomem *clr; | |
579 | void __iomem *dirout; | |
580 | void __iomem *dirin; | |
581 | unsigned long sz; | |
19338530 | 582 | unsigned long flags = pdev->id_entry->driver_data; |
280df6b3 | 583 | int err; |
0f4630f3 | 584 | struct gpio_chip *gc; |
280df6b3 JI |
585 | struct bgpio_pdata *pdata = dev_get_platdata(dev); |
586 | ||
587 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); | |
588 | if (!r) | |
589 | return -EINVAL; | |
590 | ||
591 | sz = resource_size(r); | |
592 | ||
8d240260 HK |
593 | dat = bgpio_map(pdev, "dat", sz); |
594 | if (IS_ERR(dat)) | |
595 | return PTR_ERR(dat); | |
280df6b3 | 596 | |
8d240260 HK |
597 | set = bgpio_map(pdev, "set", sz); |
598 | if (IS_ERR(set)) | |
599 | return PTR_ERR(set); | |
280df6b3 | 600 | |
8d240260 HK |
601 | clr = bgpio_map(pdev, "clr", sz); |
602 | if (IS_ERR(clr)) | |
603 | return PTR_ERR(clr); | |
280df6b3 | 604 | |
8d240260 HK |
605 | dirout = bgpio_map(pdev, "dirout", sz); |
606 | if (IS_ERR(dirout)) | |
607 | return PTR_ERR(dirout); | |
280df6b3 | 608 | |
8d240260 HK |
609 | dirin = bgpio_map(pdev, "dirin", sz); |
610 | if (IS_ERR(dirin)) | |
611 | return PTR_ERR(dirin); | |
280df6b3 | 612 | |
0f4630f3 LW |
613 | gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); |
614 | if (!gc) | |
280df6b3 JI |
615 | return -ENOMEM; |
616 | ||
0f4630f3 | 617 | err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); |
280df6b3 JI |
618 | if (err) |
619 | return err; | |
620 | ||
621 | if (pdata) { | |
781f6d71 | 622 | if (pdata->label) |
0f4630f3 LW |
623 | gc->label = pdata->label; |
624 | gc->base = pdata->base; | |
280df6b3 | 625 | if (pdata->ngpio > 0) |
0f4630f3 | 626 | gc->ngpio = pdata->ngpio; |
280df6b3 JI |
627 | } |
628 | ||
0f4630f3 | 629 | platform_set_drvdata(pdev, gc); |
280df6b3 | 630 | |
c05f813b | 631 | return devm_gpiochip_add_data(&pdev->dev, gc, NULL); |
aeec56e3 AV |
632 | } |
633 | ||
634 | static const struct platform_device_id bgpio_id_table[] = { | |
19338530 AS |
635 | { |
636 | .name = "basic-mmio-gpio", | |
637 | .driver_data = 0, | |
638 | }, { | |
639 | .name = "basic-mmio-gpio-be", | |
640 | .driver_data = BGPIOF_BIG_ENDIAN, | |
641 | }, | |
642 | { } | |
aeec56e3 AV |
643 | }; |
644 | MODULE_DEVICE_TABLE(platform, bgpio_id_table); | |
645 | ||
646 | static struct platform_driver bgpio_driver = { | |
647 | .driver = { | |
648 | .name = "basic-mmio-gpio", | |
649 | }, | |
650 | .id_table = bgpio_id_table, | |
280df6b3 | 651 | .probe = bgpio_pdev_probe, |
aeec56e3 AV |
652 | }; |
653 | ||
6f61415e | 654 | module_platform_driver(bgpio_driver); |
280df6b3 | 655 | |
c103de24 | 656 | #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ |
aeec56e3 AV |
657 | |
658 | MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); | |
659 | MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); | |
660 | MODULE_LICENSE("GPL"); |