[mirror_ubuntu-hirsute-kernel.git] / drivers / gpio / gpio-gpio-mm.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * GPIO driver for the Diamond Systems GPIO-MM
 * Copyright (C) 2016 William Breathitt Gray
 *
 * This driver supports the following Diamond Systems devices: GPIO-MM and
 * GPIO-MM-12.
 */
#include <linux/bitmap.h>
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/isa.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/spinlock.h>

#define GPIOMM_EXTENT 8
#define MAX_NUM_GPIOMM max_num_isa_dev(GPIOMM_EXTENT)

static unsigned int base[MAX_NUM_GPIOMM];
static unsigned int num_gpiomm;
module_param_hw_array(base, uint, ioport, &num_gpiomm, 0);
MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");

/**
 * struct gpiomm_gpio - GPIO device private data structure
 * @chip:	instance of the gpio_chip
 * @io_state:	bit I/O state (whether bit is set to input or output)
 * @out_state:	output bits state
 * @control:	Control registers state
 * @lock:	synchronization lock to prevent I/O race conditions
 * @base:	base port address of the GPIO device
 */
struct gpiomm_gpio {
	struct gpio_chip chip;
	unsigned char io_state[6];
	unsigned char out_state[6];
	unsigned char control[2];
	spinlock_t lock;
	unsigned int base;
};

static int gpiomm_gpio_get_direction(struct gpio_chip *chip,
	unsigned int offset)
{
	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
	const unsigned int port = offset / 8;
	const unsigned int mask = BIT(offset % 8);

	if (gpiommgpio->io_state[port] & mask)
		return GPIO_LINE_DIRECTION_IN;

	return GPIO_LINE_DIRECTION_OUT;
}

static int gpiomm_gpio_direction_input(struct gpio_chip *chip,
	unsigned int offset)
{
	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
	const unsigned int io_port = offset / 8;
	const unsigned int control_port = io_port / 3;
	const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4;
	unsigned long flags;
	unsigned int control;

	spin_lock_irqsave(&gpiommgpio->lock, flags);

	/* Check if configuring Port C */
	if (io_port == 2 || io_port == 5) {
		/* Port C can be configured by nibble */
		if (offset % 8 > 3) {
			gpiommgpio->io_state[io_port] |= 0xF0;
			gpiommgpio->control[control_port] |= BIT(3);
		} else {
			gpiommgpio->io_state[io_port] |= 0x0F;
			gpiommgpio->control[control_port] |= BIT(0);
		}
	} else {
		gpiommgpio->io_state[io_port] |= 0xFF;
		if (io_port == 0 || io_port == 3)
			gpiommgpio->control[control_port] |= BIT(4);
		else
			gpiommgpio->control[control_port] |= BIT(1);
	}

	control = BIT(7) | gpiommgpio->control[control_port];
	outb(control, control_addr);

	spin_unlock_irqrestore(&gpiommgpio->lock, flags);

	return 0;
}

static int gpiomm_gpio_direction_output(struct gpio_chip *chip,
	unsigned int offset, int value)
{
	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
	const unsigned int io_port = offset / 8;
	const unsigned int control_port = io_port / 3;
	const unsigned int mask = BIT(offset % 8);
	const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4;
	const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port;
	unsigned long flags;
	unsigned int control;

	spin_lock_irqsave(&gpiommgpio->lock, flags);

	/* Check if configuring Port C */
	if (io_port == 2 || io_port == 5) {
		/* Port C can be configured by nibble */
		if (offset % 8 > 3) {
			gpiommgpio->io_state[io_port] &= 0x0F;
			gpiommgpio->control[control_port] &= ~BIT(3);
		} else {
			gpiommgpio->io_state[io_port] &= 0xF0;
			gpiommgpio->control[control_port] &= ~BIT(0);
		}
	} else {
		gpiommgpio->io_state[io_port] &= 0x00;
		if (io_port == 0 || io_port == 3)
			gpiommgpio->control[control_port] &= ~BIT(4);
		else
			gpiommgpio->control[control_port] &= ~BIT(1);
	}

	if (value)
		gpiommgpio->out_state[io_port] |= mask;
	else
		gpiommgpio->out_state[io_port] &= ~mask;

	control = BIT(7) | gpiommgpio->control[control_port];
	outb(control, control_addr);

	outb(gpiommgpio->out_state[io_port], gpiommgpio->base + out_port);

	spin_unlock_irqrestore(&gpiommgpio->lock, flags);

	return 0;
}

static int gpiomm_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
	const unsigned int port = offset / 8;
	const unsigned int mask = BIT(offset % 8);
	const unsigned int in_port = (port > 2) ? port + 1 : port;
	unsigned long flags;
	unsigned int port_state;

	spin_lock_irqsave(&gpiommgpio->lock, flags);

	/* ensure that GPIO is set for input */
	if (!(gpiommgpio->io_state[port] & mask)) {
		spin_unlock_irqrestore(&gpiommgpio->lock, flags);
		return -EINVAL;
	}

	port_state = inb(gpiommgpio->base + in_port);

	spin_unlock_irqrestore(&gpiommgpio->lock, flags);

	return !!(port_state & mask);
}

static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };

static int gpiomm_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
	unsigned long *bits)
{
	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
	unsigned long offset;
	unsigned long gpio_mask;
	unsigned int port_addr;
	unsigned long port_state;

	/* clear bits array to a clean slate */
	bitmap_zero(bits, chip->ngpio);

	for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
		port_addr = gpiommgpio->base + ports[offset / 8];
		port_state = inb(port_addr) & gpio_mask;

		bitmap_set_value8(bits, port_state, offset);
	}

	return 0;
}

static void gpiomm_gpio_set(struct gpio_chip *chip, unsigned int offset,
	int value)
{
	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
	const unsigned int port = offset / 8;
	const unsigned int mask = BIT(offset % 8);
	const unsigned int out_port = (port > 2) ? port + 1 : port;
	unsigned long flags;

	spin_lock_irqsave(&gpiommgpio->lock, flags);

	if (value)
		gpiommgpio->out_state[port] |= mask;
	else
		gpiommgpio->out_state[port] &= ~mask;

	outb(gpiommgpio->out_state[port], gpiommgpio->base + out_port);

	spin_unlock_irqrestore(&gpiommgpio->lock, flags);
}

static void gpiomm_gpio_set_multiple(struct gpio_chip *chip,
	unsigned long *mask, unsigned long *bits)
{
	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
	unsigned long offset;
	unsigned long gpio_mask;
	size_t index;
	unsigned int port_addr;
	unsigned long bitmask;
	unsigned long flags;

	for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
		index = offset / 8;
		port_addr = gpiommgpio->base + ports[index];

		bitmask = bitmap_get_value8(bits, offset) & gpio_mask;

		spin_lock_irqsave(&gpiommgpio->lock, flags);

		/* update output state data and set device gpio register */
		gpiommgpio->out_state[index] &= ~gpio_mask;
		gpiommgpio->out_state[index] |= bitmask;
		outb(gpiommgpio->out_state[index], port_addr);

		spin_unlock_irqrestore(&gpiommgpio->lock, flags);
	}
}

#define GPIOMM_NGPIO 48
static const char *gpiomm_names[GPIOMM_NGPIO] = {
	"Port 1A0", "Port 1A1", "Port 1A2", "Port 1A3", "Port 1A4", "Port 1A5",
	"Port 1A6", "Port 1A7", "Port 1B0", "Port 1B1", "Port 1B2", "Port 1B3",
	"Port 1B4", "Port 1B5", "Port 1B6", "Port 1B7", "Port 1C0", "Port 1C1",
	"Port 1C2", "Port 1C3", "Port 1C4", "Port 1C5", "Port 1C6", "Port 1C7",
	"Port 2A0", "Port 2A1", "Port 2A2", "Port 2A3", "Port 2A4", "Port 2A5",
	"Port 2A6", "Port 2A7", "Port 2B0", "Port 2B1", "Port 2B2", "Port 2B3",
	"Port 2B4", "Port 2B5", "Port 2B6", "Port 2B7", "Port 2C0", "Port 2C1",
	"Port 2C2", "Port 2C3", "Port 2C4", "Port 2C5", "Port 2C6", "Port 2C7",
};

static int gpiomm_probe(struct device *dev, unsigned int id)
{
	struct gpiomm_gpio *gpiommgpio;
	const char *const name = dev_name(dev);
	int err;

	gpiommgpio = devm_kzalloc(dev, sizeof(*gpiommgpio), GFP_KERNEL);
	if (!gpiommgpio)
		return -ENOMEM;

	if (!devm_request_region(dev, base[id], GPIOMM_EXTENT, name)) {
		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
			base[id], base[id] + GPIOMM_EXTENT);
		return -EBUSY;
	}

	gpiommgpio->chip.label = name;
	gpiommgpio->chip.parent = dev;
	gpiommgpio->chip.owner = THIS_MODULE;
	gpiommgpio->chip.base = -1;
	gpiommgpio->chip.ngpio = GPIOMM_NGPIO;
	gpiommgpio->chip.names = gpiomm_names;
	gpiommgpio->chip.get_direction = gpiomm_gpio_get_direction;
	gpiommgpio->chip.direction_input = gpiomm_gpio_direction_input;
	gpiommgpio->chip.direction_output = gpiomm_gpio_direction_output;
	gpiommgpio->chip.get = gpiomm_gpio_get;
	gpiommgpio->chip.get_multiple = gpiomm_gpio_get_multiple;
	gpiommgpio->chip.set = gpiomm_gpio_set;
	gpiommgpio->chip.set_multiple = gpiomm_gpio_set_multiple;
	gpiommgpio->base = base[id];

	spin_lock_init(&gpiommgpio->lock);

	err = devm_gpiochip_add_data(dev, &gpiommgpio->chip, gpiommgpio);
	if (err) {
		dev_err(dev, "GPIO registering failed (%d)\n", err);
		return err;
	}

	/* initialize all GPIO as output */
	outb(0x80, base[id] + 3);
	outb(0x00, base[id]);
	outb(0x00, base[id] + 1);
	outb(0x00, base[id] + 2);
	outb(0x80, base[id] + 7);
	outb(0x00, base[id] + 4);
	outb(0x00, base[id] + 5);
	outb(0x00, base[id] + 6);

	return 0;
}

static struct isa_driver gpiomm_driver = {
	.probe = gpiomm_probe,
	.driver = {
		.name = "gpio-mm"
	},
};

module_isa_driver(gpiomm_driver, num_gpiomm);

MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
MODULE_DESCRIPTION("Diamond Systems GPIO-MM GPIO driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
6ea5dcdf WBG	2	/*
	3	* GPIO driver for the Diamond Systems GPIO-MM
	4	* Copyright (C) 2016 William Breathitt Gray
	5	*
6ea5dcdf WBG	6	* This driver supports the following Diamond Systems devices: GPIO-MM and
	7	* GPIO-MM-12.
	8	*/
41b25131	9	#include <linux/bitmap.h>
6ea5dcdf WBG	10	#include <linux/bitops.h>
	11	#include <linux/device.h>
	12	#include <linux/errno.h>
	13	#include <linux/gpio/driver.h>
	14	#include <linux/io.h>
	15	#include <linux/ioport.h>
	16	#include <linux/isa.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/moduleparam.h>
	20	#include <linux/spinlock.h>
	21
	22	#define GPIOMM_EXTENT 8
	23	#define MAX_NUM_GPIOMM max_num_isa_dev(GPIOMM_EXTENT)
	24
	25	static unsigned int base[MAX_NUM_GPIOMM];
	26	static unsigned int num_gpiomm;
d759f906	27	module_param_hw_array(base, uint, ioport, &num_gpiomm, 0);
6ea5dcdf WBG	28	MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");
	29
	30	/**
	31	* struct gpiomm_gpio - GPIO device private data structure
	32	* @chip: instance of the gpio_chip
	33	* @io_state: bit I/O state (whether bit is set to input or output)
	34	* @out_state: output bits state
	35	* @control: Control registers state
	36	* @lock: synchronization lock to prevent I/O race conditions
	37	* @base: base port address of the GPIO device
	38	*/
	39	struct gpiomm_gpio {
	40	struct gpio_chip chip;
	41	unsigned char io_state[6];
	42	unsigned char out_state[6];
	43	unsigned char control[2];
	44	spinlock_t lock;
	45	unsigned int base;
	46	};
	47
	48	static int gpiomm_gpio_get_direction(struct gpio_chip *chip,
	49	unsigned int offset)
	50	{
	51	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
	52	const unsigned int port = offset / 8;
	53	const unsigned int mask = BIT(offset % 8);
	54
e42615ec MV	55	if (gpiommgpio->io_state[port] & mask)
	56	return GPIO_LINE_DIRECTION_IN;
	57
	58	return GPIO_LINE_DIRECTION_OUT;
6ea5dcdf WBG	59	}
	60
	61	static int gpiomm_gpio_direction_input(struct gpio_chip *chip,
	62	unsigned int offset)
	63	{
	64	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
	65	const unsigned int io_port = offset / 8;
	66	const unsigned int control_port = io_port / 3;
	67	const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4;
	68	unsigned long flags;
	69	unsigned int control;
	70
	71	spin_lock_irqsave(&gpiommgpio->lock, flags);
	72
	73	/* Check if configuring Port C */
	74	if (io_port == 2 \|\| io_port == 5) {
	75	/* Port C can be configured by nibble */
	76	if (offset % 8 > 3) {
	77	gpiommgpio->io_state[io_port] \|= 0xF0;
	78	gpiommgpio->control[control_port] \|= BIT(3);
	79	} else {
	80	gpiommgpio->io_state[io_port] \|= 0x0F;
	81	gpiommgpio->control[control_port] \|= BIT(0);
	82	}
	83	} else {
	84	gpiommgpio->io_state[io_port] \|= 0xFF;
	85	if (io_port == 0 \|\| io_port == 3)
	86	gpiommgpio->control[control_port] \|= BIT(4);
	87	else
	88	gpiommgpio->control[control_port] \|= BIT(1);
	89	}
	90
	91	control = BIT(7) \| gpiommgpio->control[control_port];
	92	outb(control, control_addr);
	93
	94	spin_unlock_irqrestore(&gpiommgpio->lock, flags);
	95
	96	return 0;
	97	}
	98
	99	static int gpiomm_gpio_direction_output(struct gpio_chip *chip,
	100	unsigned int offset, int value)
	101	{
	102	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
	103	const unsigned int io_port = offset / 8;
	104	const unsigned int control_port = io_port / 3;
	105	const unsigned int mask = BIT(offset % 8);
	106	const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4;
	107	const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port;
	108	unsigned long flags;
	109	unsigned int control;
	110
	111	spin_lock_irqsave(&gpiommgpio->lock, flags);
	112
	113	/* Check if configuring Port C */
	114	if (io_port == 2 \|\| io_port == 5) {
	115	/* Port C can be configured by nibble */
	116	if (offset % 8 > 3) {
	117	gpiommgpio->io_state[io_port] &= 0x0F;
	118	gpiommgpio->control[control_port] &= ~BIT(3);
	119	} else {
	120	gpiommgpio->io_state[io_port] &= 0xF0;
	121	gpiommgpio->control[control_port] &= ~BIT(0);
	122	}
123	} else {
124	gpiommgpio->io_state[io_port] &= 0x00;
125	if (io_port == 0 \|\| io_port == 3)
126	gpiommgpio->control[control_port] &= ~BIT(4);
127	else
128	gpiommgpio->control[control_port] &= ~BIT(1);
129	}
130
131	if (value)
132	gpiommgpio->out_state[io_port] \|= mask;
133	else
134	gpiommgpio->out_state[io_port] &= ~mask;
135
136	control = BIT(7) \| gpiommgpio->control[control_port];
137	outb(control, control_addr);
138
139	outb(gpiommgpio->out_state[io_port], gpiommgpio->base + out_port);
140
141	spin_unlock_irqrestore(&gpiommgpio->lock, flags);
142
143	return 0;
144	}
145
146	static int gpiomm_gpio_get(struct gpio_chip *chip, unsigned int offset)
147	{
148	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
149	const unsigned int port = offset / 8;
150	const unsigned int mask = BIT(offset % 8);
151	const unsigned int in_port = (port > 2) ? port + 1 : port;
152	unsigned long flags;
153	unsigned int port_state;
154
155	spin_lock_irqsave(&gpiommgpio->lock, flags);
156
157	/* ensure that GPIO is set for input */
158	if (!(gpiommgpio->io_state[port] & mask)) {
159	spin_unlock_irqrestore(&gpiommgpio->lock, flags);
160	return -EINVAL;
161	}
162
163	port_state = inb(gpiommgpio->base + in_port);
164
165	spin_unlock_irqrestore(&gpiommgpio->lock, flags);
166
167	return !!(port_state & mask);
168	}
169
b0f49e9b WBG	170	static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
b0f49e9b WBG	171
41b25131 WBG	172	static int gpiomm_gpio_get_multiple(struct gpio_chip chip, unsigned long mask,
	173	unsigned long *bits)
	174	{
	175	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
b0f49e9b WBG	176	unsigned long offset;
	177	unsigned long gpio_mask;
	178	unsigned int port_addr;
41b25131 WBG	179	unsigned long port_state;
	180
	181	/* clear bits array to a clean slate */
	182	bitmap_zero(bits, chip->ngpio);
	183
b0f49e9b WBG	184	for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
	185	port_addr = gpiommgpio->base + ports[offset / 8];
	186	port_state = inb(port_addr) & gpio_mask;
41b25131	187
b0f49e9b	188	bitmap_set_value8(bits, port_state, offset);
41b25131 WBG	189	}
	190
	191	return 0;
	192	}
	193
6ea5dcdf WBG	194	static void gpiomm_gpio_set(struct gpio_chip *chip, unsigned int offset,
	195	int value)
	196	{
	197	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
	198	const unsigned int port = offset / 8;
	199	const unsigned int mask = BIT(offset % 8);
	200	const unsigned int out_port = (port > 2) ? port + 1 : port;
	201	unsigned long flags;
	202
	203	spin_lock_irqsave(&gpiommgpio->lock, flags);
	204
	205	if (value)
	206	gpiommgpio->out_state[port] \|= mask;
	207	else
	208	gpiommgpio->out_state[port] &= ~mask;
	209
	210	outb(gpiommgpio->out_state[port], gpiommgpio->base + out_port);
	211
	212	spin_unlock_irqrestore(&gpiommgpio->lock, flags);
	213	}
	214
65502a12 WBG	215	static void gpiomm_gpio_set_multiple(struct gpio_chip *chip,
	216	unsigned long mask, unsigned long bits)
	217	{
	218	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
b0f49e9b WBG	219	unsigned long offset;
	220	unsigned long gpio_mask;
	221	size_t index;
	222	unsigned int port_addr;
	223	unsigned long bitmask;
65502a12 WBG	224	unsigned long flags;
65502a12 WBG	225
b0f49e9b WBG	226	for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
	227	index = offset / 8;
	228	port_addr = gpiommgpio->base + ports[index];
65502a12	229
b0f49e9b	230	bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
65502a12 WBG	231
	232	spin_lock_irqsave(&gpiommgpio->lock, flags);
	233
	234	/* update output state data and set device gpio register */
b0f49e9b WBG	235	gpiommgpio->out_state[index] &= ~gpio_mask;
	236	gpiommgpio->out_state[index] \|= bitmask;
	237	outb(gpiommgpio->out_state[index], port_addr);
65502a12 WBG	238
65502a12 WBG	239	spin_unlock_irqrestore(&gpiommgpio->lock, flags);
65502a12 WBG	240	}
	241	}
	242
210b4bde WBG	243	#define GPIOMM_NGPIO 48
	244	static const char *gpiomm_names[GPIOMM_NGPIO] = {
	245	"Port 1A0", "Port 1A1", "Port 1A2", "Port 1A3", "Port 1A4", "Port 1A5",
	246	"Port 1A6", "Port 1A7", "Port 1B0", "Port 1B1", "Port 1B2", "Port 1B3",
	247	"Port 1B4", "Port 1B5", "Port 1B6", "Port 1B7", "Port 1C0", "Port 1C1",
	248	"Port 1C2", "Port 1C3", "Port 1C4", "Port 1C5", "Port 1C6", "Port 1C7",
	249	"Port 2A0", "Port 2A1", "Port 2A2", "Port 2A3", "Port 2A4", "Port 2A5",
	250	"Port 2A6", "Port 2A7", "Port 2B0", "Port 2B1", "Port 2B2", "Port 2B3",
	251	"Port 2B4", "Port 2B5", "Port 2B6", "Port 2B7", "Port 2C0", "Port 2C1",
	252	"Port 2C2", "Port 2C3", "Port 2C4", "Port 2C5", "Port 2C6", "Port 2C7",
	253	};
	254
6ea5dcdf WBG	255	static int gpiomm_probe(struct device *dev, unsigned int id)
	256	{
	257	struct gpiomm_gpio *gpiommgpio;
	258	const char *const name = dev_name(dev);
	259	int err;
	260
	261	gpiommgpio = devm_kzalloc(dev, sizeof(*gpiommgpio), GFP_KERNEL);
	262	if (!gpiommgpio)
	263	return -ENOMEM;
	264
	265	if (!devm_request_region(dev, base[id], GPIOMM_EXTENT, name)) {
	266	dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
	267	base[id], base[id] + GPIOMM_EXTENT);
	268	return -EBUSY;
	269	}
	270
	271	gpiommgpio->chip.label = name;
	272	gpiommgpio->chip.parent = dev;
	273	gpiommgpio->chip.owner = THIS_MODULE;
	274	gpiommgpio->chip.base = -1;
210b4bde WBG	275	gpiommgpio->chip.ngpio = GPIOMM_NGPIO;
210b4bde WBG	276	gpiommgpio->chip.names = gpiomm_names;
6ea5dcdf WBG	277	gpiommgpio->chip.get_direction = gpiomm_gpio_get_direction;
	278	gpiommgpio->chip.direction_input = gpiomm_gpio_direction_input;
	279	gpiommgpio->chip.direction_output = gpiomm_gpio_direction_output;
	280	gpiommgpio->chip.get = gpiomm_gpio_get;
41b25131	281	gpiommgpio->chip.get_multiple = gpiomm_gpio_get_multiple;
6ea5dcdf	282	gpiommgpio->chip.set = gpiomm_gpio_set;
65502a12	283	gpiommgpio->chip.set_multiple = gpiomm_gpio_set_multiple;
6ea5dcdf WBG	284	gpiommgpio->base = base[id];
	285
	286	spin_lock_init(&gpiommgpio->lock);
	287
2141b0a1	288	err = devm_gpiochip_add_data(dev, &gpiommgpio->chip, gpiommgpio);
6ea5dcdf WBG	289	if (err) {
	290	dev_err(dev, "GPIO registering failed (%d)\n", err);
	291	return err;
	292	}
	293
	294	/* initialize all GPIO as output */
	295	outb(0x80, base[id] + 3);
	296	outb(0x00, base[id]);
	297	outb(0x00, base[id] + 1);
	298	outb(0x00, base[id] + 2);
	299	outb(0x80, base[id] + 7);
	300	outb(0x00, base[id] + 4);
	301	outb(0x00, base[id] + 5);
	302	outb(0x00, base[id] + 6);
	303
	304	return 0;
	305	}
	306
6ea5dcdf WBG	307	static struct isa_driver gpiomm_driver = {
	308	.probe = gpiomm_probe,
	309	.driver = {
	310	.name = "gpio-mm"
	311	},
6ea5dcdf WBG	312	};
	313
	314	module_isa_driver(gpiomm_driver, num_gpiomm);
	315
	316	MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
	317	MODULE_DESCRIPTION("Diamond Systems GPIO-MM GPIO driver");
	318	MODULE_LICENSE("GPL v2");