[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-intel-mid.c

/*
 * Intel MID GPIO driver
 *
 * Copyright (c) 2008-2014,2016 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/* Supports:
 * Moorestown platform Langwell chip.
 * Medfield platform Penwell chip.
 * Clovertrail platform Cloverview chip.
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/stddef.h>

#define INTEL_MID_IRQ_TYPE_EDGE		(1 << 0)
#define INTEL_MID_IRQ_TYPE_LEVEL	(1 << 1)

/*
 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
 * registers to control them, so we only define the order here instead of a
 * structure, to get a bit offset for a pin (use GPDR as an example):
 *
 * nreg = ngpio / 32;
 * reg = offset / 32;
 * bit = offset % 32;
 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
 *
 * so the bit of reg_addr is to control pin offset's GPDR feature
*/

enum GPIO_REG {
	GPLR = 0,	/* pin level read-only */
	GPDR,		/* pin direction */
	GPSR,		/* pin set */
	GPCR,		/* pin clear */
	GRER,		/* rising edge detect */
	GFER,		/* falling edge detect */
	GEDR,		/* edge detect result */
	GAFR,		/* alt function */
};

/* intel_mid gpio driver data */
struct intel_mid_gpio_ddata {
	u16 ngpio;		/* number of gpio pins */
	u32 chip_irq_type;	/* chip interrupt type */
};

struct intel_mid_gpio {
	struct gpio_chip		chip;
	void __iomem			*reg_base;
	spinlock_t			lock;
	struct pci_dev			*pdev;
};

static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
			      enum GPIO_REG reg_type)
{
	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 32;

	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
}

static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
				   enum GPIO_REG reg_type)
{
	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 16;

	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
}

static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	u32 value = readl(gafr);
	int shift = (offset % 16) << 1, af = (value >> shift) & 3;

	if (af) {
		value &= ~(3 << shift);
		writel(value, gafr);
	}
	return 0;
}

static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gplr = gpio_reg(chip, offset, GPLR);

	return !!(readl(gplr) & BIT(offset % 32));
}

static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	void __iomem *gpsr, *gpcr;

	if (value) {
		gpsr = gpio_reg(chip, offset, GPSR);
		writel(BIT(offset % 32), gpsr);
	} else {
		gpcr = gpio_reg(chip, offset, GPCR);
		writel(BIT(offset % 32), gpcr);
	}
}

static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	u32 value;
	unsigned long flags;

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	value = readl(gpdr);
	value &= ~BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static int intel_gpio_direction_output(struct gpio_chip *chip,
			unsigned offset, int value)
{
	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	unsigned long flags;

	intel_gpio_set(chip, offset, value);

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	value = readl(gpdr);
	value |= BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static int intel_mid_irq_type(struct irq_data *d, unsigned type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct intel_mid_gpio *priv = gpiochip_get_data(gc);
	u32 gpio = irqd_to_hwirq(d);
	unsigned long flags;
	u32 value;
	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);

	if (gpio >= priv->chip.ngpio)
		return -EINVAL;

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	if (type & IRQ_TYPE_EDGE_RISING)
		value = readl(grer) | BIT(gpio % 32);
	else
		value = readl(grer) & (~BIT(gpio % 32));
	writel(value, grer);

	if (type & IRQ_TYPE_EDGE_FALLING)
		value = readl(gfer) | BIT(gpio % 32);
	else
		value = readl(gfer) & (~BIT(gpio % 32));
	writel(value, gfer);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static void intel_mid_irq_unmask(struct irq_data *d)
{
}

static void intel_mid_irq_mask(struct irq_data *d)
{
}

static struct irq_chip intel_mid_irqchip = {
	.name		= "INTEL_MID-GPIO",
	.irq_mask	= intel_mid_irq_mask,
	.irq_unmask	= intel_mid_irq_unmask,
	.irq_set_type	= intel_mid_irq_type,
};

static const struct intel_mid_gpio_ddata gpio_lincroft = {
	.ngpio = 64,
};

static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct intel_mid_gpio_ddata gpio_penwell_core = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
};

static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct pci_device_id intel_gpio_ids[] = {
	{
		/* Lincroft */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
		.driver_data = (kernel_ulong_t)&gpio_lincroft,
	},
	{
		/* Penwell AON */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
		.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
	},
	{
		/* Penwell Core */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
		.driver_data = (kernel_ulong_t)&gpio_penwell_core,
	},
	{
		/* Cloverview Aon */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
		.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
	},
	{
		/* Cloverview Core */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
		.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
	},
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, intel_gpio_ids);

static void intel_mid_irq_handler(struct irq_desc *desc)
{
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct intel_mid_gpio *priv = gpiochip_get_data(gc);
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, gpio, mask;
	unsigned long pending;
	void __iomem *gedr;

	/* check GPIO controller to check which pin triggered the interrupt */
	for (base = 0; base < priv->chip.ngpio; base += 32) {
		gedr = gpio_reg(&priv->chip, base, GEDR);
		while ((pending = readl(gedr))) {
			gpio = __ffs(pending);
			mask = BIT(gpio);
			/* Clear before handling so we can't lose an edge */
			writel(mask, gedr);
			generic_handle_irq(irq_find_mapping(gc->irqdomain,
							    base + gpio));
		}
	}

	chip->irq_eoi(data);
}

static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
{
	void __iomem *reg;
	unsigned base;

	for (base = 0; base < priv->chip.ngpio; base += 32) {
		/* Clear the rising-edge detect register */
		reg = gpio_reg(&priv->chip, base, GRER);
		writel(0, reg);
		/* Clear the falling-edge detect register */
		reg = gpio_reg(&priv->chip, base, GFER);
		writel(0, reg);
		/* Clear the edge detect status register */
		reg = gpio_reg(&priv->chip, base, GEDR);
		writel(~0, reg);
	}
}

static int __maybe_unused intel_gpio_runtime_idle(struct device *dev)
{
	int err = pm_schedule_suspend(dev, 500);
	return err ?: -EBUSY;
}

static const struct dev_pm_ops intel_gpio_pm_ops = {
	SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
};

static int intel_gpio_probe(struct pci_dev *pdev,
			  const struct pci_device_id *id)
{
	void __iomem *base;
	struct intel_mid_gpio *priv;
	u32 gpio_base;
	u32 irq_base;
	int retval;
	struct intel_mid_gpio_ddata *ddata =
				(struct intel_mid_gpio_ddata *)id->driver_data;

	retval = pcim_enable_device(pdev);
	if (retval)
		return retval;

	retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
	if (retval) {
		dev_err(&pdev->dev, "I/O memory mapping error\n");
		return retval;
	}

	base = pcim_iomap_table(pdev)[1];

	irq_base = readl(base);
	gpio_base = readl(sizeof(u32) + base);

	/* release the IO mapping, since we already get the info from bar1 */
	pcim_iounmap_regions(pdev, 1 << 1);

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		dev_err(&pdev->dev, "can't allocate chip data\n");
		return -ENOMEM;
	}

	priv->reg_base = pcim_iomap_table(pdev)[0];
	priv->chip.label = dev_name(&pdev->dev);
	priv->chip.parent = &pdev->dev;
	priv->chip.request = intel_gpio_request;
	priv->chip.direction_input = intel_gpio_direction_input;
	priv->chip.direction_output = intel_gpio_direction_output;
	priv->chip.get = intel_gpio_get;
	priv->chip.set = intel_gpio_set;
	priv->chip.base = gpio_base;
	priv->chip.ngpio = ddata->ngpio;
	priv->chip.can_sleep = false;
	priv->pdev = pdev;

	spin_lock_init(&priv->lock);

	pci_set_drvdata(pdev, priv);
	retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
	if (retval) {
		dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
		return retval;
	}

	retval = gpiochip_irqchip_add(&priv->chip,
				      &intel_mid_irqchip,
				      irq_base,
				      handle_simple_irq,
				      IRQ_TYPE_NONE);
	if (retval) {
		dev_err(&pdev->dev,
			"could not connect irqchip to gpiochip\n");
		return retval;
	}

	intel_mid_irq_init_hw(priv);

	gpiochip_set_chained_irqchip(&priv->chip,
				     &intel_mid_irqchip,
				     pdev->irq,
				     intel_mid_irq_handler);

	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_allow(&pdev->dev);

	return 0;
}

static struct pci_driver intel_gpio_driver = {
	.name		= "intel_mid_gpio",
	.id_table	= intel_gpio_ids,
	.probe		= intel_gpio_probe,
	.driver		= {
		.pm	= &intel_gpio_pm_ops,
	},
};

builtin_pci_driver(intel_gpio_driver);
Commit	Line	Data
c103de24	1	/*
a0bbf032	2	* Intel MID GPIO driver
c103de24	3	*
3cabe87b	4	* Copyright (c) 2008-2014,2016 Intel Corporation.
8bf02617 AD	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
8bf02617 AD	14	*/
	15
	16	/* Supports:
	17	* Moorestown platform Langwell chip.
8081c84c	18	* Medfield platform Penwell chip.
f89a768f	19	* Clovertrail platform Cloverview chip.
8bf02617 AD	20	*/
8bf02617 AD	21
8bf02617	22	#include <linux/delay.h>
8bf02617	23	#include <linux/init.h>
3cabe87b	24	#include <linux/interrupt.h>
8bf02617	25	#include <linux/io.h>
3f7dbfd8	26	#include <linux/gpio/driver.h>
3cabe87b AS	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
	29	#include <linux/pci.h>
	30	#include <linux/platform_device.h>
7812803a	31	#include <linux/pm_runtime.h>
3cabe87b AS	32	#include <linux/slab.h>
3cabe87b AS	33	#include <linux/stddef.h>
8bf02617	34
f89a768f DC	35	#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
f89a768f DC	36	#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
d56d6b3d	37
8081c84c AD	38	/*
	39	* Langwell chip has 64 pins and thus there are 2 32bit registers to control
	40	* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
	41	* registers to control them, so we only define the order here instead of a
	42	* structure, to get a bit offset for a pin (use GPDR as an example):
	43	*
	44	* nreg = ngpio / 32;
	45	* reg = offset / 32;
	46	* bit = offset % 32;
	47	* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
	48	*
	49	* so the bit of reg_addr is to control pin offset's GPDR feature
	50	*/
	51
	52	enum GPIO_REG {
	53	GPLR = 0, /* pin level read-only */
	54	GPDR, /* pin direction */
	55	GPSR, /* pin set */
	56	GPCR, /* pin clear */
	57	GRER, /* rising edge detect */
	58	GFER, /* falling edge detect */
	59	GEDR, /* edge detect result */
8c0f7b10	60	GAFR, /* alt function */
8bf02617 AD	61	};
8bf02617 AD	62
f89a768f DC	63	/* intel_mid gpio driver data */
f89a768f DC	64	struct intel_mid_gpio_ddata {
d56d6b3d	65	u16 ngpio; /* number of gpio pins */
d56d6b3d DC	66	u32 chip_irq_type; /* chip interrupt type */
	67	};
	68
f89a768f	69	struct intel_mid_gpio {
8bf02617	70	struct gpio_chip chip;
64c8cbc1	71	void __iomem *reg_base;
8bf02617	72	spinlock_t lock;
7812803a	73	struct pci_dev *pdev;
8bf02617 AD	74	};
8bf02617 AD	75
8081c84c	76	static void __iomem gpio_reg(struct gpio_chip chip, unsigned offset,
611a485b	77	enum GPIO_REG reg_type)
8bf02617	78	{
5c77c021	79	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
8081c84c	80	unsigned nreg = chip->ngpio / 32;
8bf02617	81	u8 reg = offset / 32;
8081c84c	82
f89a768f	83	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
8081c84c AD	84	}
8081c84c AD	85
8c0f7b10 AH	86	static void __iomem gpio_reg_2bit(struct gpio_chip chip, unsigned offset,
	87	enum GPIO_REG reg_type)
	88	{
5c77c021	89	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
8c0f7b10 AH	90	unsigned nreg = chip->ngpio / 32;
8c0f7b10 AH	91	u8 reg = offset / 16;
8c0f7b10	92
f89a768f	93	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
8c0f7b10 AH	94	}
8c0f7b10 AH	95
f89a768f	96	static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
8c0f7b10 AH	97	{
	98	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	99	u32 value = readl(gafr);
	100	int shift = (offset % 16) << 1, af = (value >> shift) & 3;
	101
	102	if (af) {
	103	value &= ~(3 << shift);
	104	writel(value, gafr);
	105	}
	106	return 0;
	107	}
	108
f89a768f	109	static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
8081c84c AD	110	{
8081c84c AD	111	void __iomem *gplr = gpio_reg(chip, offset, GPLR);
8bf02617	112
4c628f3d	113	return !!(readl(gplr) & BIT(offset % 32));
8bf02617 AD	114	}
8bf02617 AD	115
f89a768f	116	static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
8bf02617	117	{
8bf02617 AD	118	void __iomem gpsr, gpcr;
	119
	120	if (value) {
8081c84c	121	gpsr = gpio_reg(chip, offset, GPSR);
8bf02617 AD	122	writel(BIT(offset % 32), gpsr);
8bf02617 AD	123	} else {
8081c84c	124	gpcr = gpio_reg(chip, offset, GPCR);
8bf02617 AD	125	writel(BIT(offset % 32), gpcr);
	126	}
	127	}
	128
f89a768f	129	static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
8bf02617	130	{
5c77c021	131	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
8081c84c	132	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617 AD	133	u32 value;
8bf02617 AD	134	unsigned long flags;
8bf02617	135
f89a768f DC	136	if (priv->pdev)
f89a768f DC	137	pm_runtime_get(&priv->pdev->dev);
7812803a	138
f89a768f	139	spin_lock_irqsave(&priv->lock, flags);
8bf02617 AD	140	value = readl(gpdr);
	141	value &= ~BIT(offset % 32);
	142	writel(value, gpdr);
f89a768f	143	spin_unlock_irqrestore(&priv->lock, flags);
7812803a	144
f89a768f DC	145	if (priv->pdev)
f89a768f DC	146	pm_runtime_put(&priv->pdev->dev);
7812803a	147
8bf02617 AD	148	return 0;
	149	}
	150
f89a768f	151	static int intel_gpio_direction_output(struct gpio_chip *chip,
8bf02617 AD	152	unsigned offset, int value)
8bf02617 AD	153	{
5c77c021	154	struct intel_mid_gpio *priv = gpiochip_get_data(chip);
8081c84c	155	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617	156	unsigned long flags;
8bf02617	157
f89a768f	158	intel_gpio_set(chip, offset, value);
7812803a	159
f89a768f DC	160	if (priv->pdev)
f89a768f DC	161	pm_runtime_get(&priv->pdev->dev);
7812803a	162
f89a768f	163	spin_lock_irqsave(&priv->lock, flags);
8bf02617	164	value = readl(gpdr);
6eab04a8	165	value \|= BIT(offset % 32);
8bf02617	166	writel(value, gpdr);
f89a768f	167	spin_unlock_irqrestore(&priv->lock, flags);
7812803a	168
f89a768f DC	169	if (priv->pdev)
f89a768f DC	170	pm_runtime_put(&priv->pdev->dev);
7812803a	171
8bf02617 AD	172	return 0;
	173	}
	174
f89a768f	175	static int intel_mid_irq_type(struct irq_data *d, unsigned type)
8bf02617	176	{
3f7dbfd8	177	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
5c77c021	178	struct intel_mid_gpio *priv = gpiochip_get_data(gc);
465f2bd4	179	u32 gpio = irqd_to_hwirq(d);
8bf02617 AD	180	unsigned long flags;
8bf02617 AD	181	u32 value;
f89a768f DC	182	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
f89a768f DC	183	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
8bf02617	184
f89a768f	185	if (gpio >= priv->chip.ngpio)
8bf02617	186	return -EINVAL;
7812803a	187
f89a768f DC	188	if (priv->pdev)
f89a768f DC	189	pm_runtime_get(&priv->pdev->dev);
7812803a	190
f89a768f	191	spin_lock_irqsave(&priv->lock, flags);
8bf02617 AD	192	if (type & IRQ_TYPE_EDGE_RISING)
	193	value = readl(grer) \| BIT(gpio % 32);
	194	else
	195	value = readl(grer) & (~BIT(gpio % 32));
	196	writel(value, grer);
	197
	198	if (type & IRQ_TYPE_EDGE_FALLING)
	199	value = readl(gfer) \| BIT(gpio % 32);
	200	else
	201	value = readl(gfer) & (~BIT(gpio % 32));
	202	writel(value, gfer);
f89a768f	203	spin_unlock_irqrestore(&priv->lock, flags);
8bf02617	204
f89a768f DC	205	if (priv->pdev)
f89a768f DC	206	pm_runtime_put(&priv->pdev->dev);
7812803a	207
8bf02617	208	return 0;
fd0574cb	209	}
8bf02617	210
f89a768f	211	static void intel_mid_irq_unmask(struct irq_data *d)
8bf02617	212	{
fd0574cb	213	}
8bf02617	214
f89a768f	215	static void intel_mid_irq_mask(struct irq_data *d)
8bf02617	216	{
fd0574cb	217	}
8bf02617	218
f89a768f DC	219	static struct irq_chip intel_mid_irqchip = {
	220	.name = "INTEL_MID-GPIO",
	221	.irq_mask = intel_mid_irq_mask,
	222	.irq_unmask = intel_mid_irq_unmask,
	223	.irq_set_type = intel_mid_irq_type,
8bf02617 AD	224	};
8bf02617 AD	225
f89a768f	226	static const struct intel_mid_gpio_ddata gpio_lincroft = {
d56d6b3d DC	227	.ngpio = 64,
	228	};
	229
f89a768f	230	static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
d56d6b3d	231	.ngpio = 96,
f89a768f	232	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	233	};
d56d6b3d DC	234
f89a768f	235	static const struct intel_mid_gpio_ddata gpio_penwell_core = {
d56d6b3d	236	.ngpio = 96,
f89a768f	237	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	238	};
d56d6b3d DC	239
f89a768f	240	static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
d56d6b3d	241	.ngpio = 96,
f89a768f	242	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE \| INTEL_MID_IRQ_TYPE_LEVEL,
d56d6b3d DC	243	};
d56d6b3d DC	244
f89a768f	245	static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
d56d6b3d	246	.ngpio = 96,
f89a768f	247	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	248	};
d56d6b3d DC	249
14f4a883	250	static const struct pci_device_id intel_gpio_ids[] = {
d56d6b3d DC	251	{
	252	/* Lincroft */
	253	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
	254	.driver_data = (kernel_ulong_t)&gpio_lincroft,
	255	},
	256	{
	257	/* Penwell AON */
	258	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
	259	.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
	260	},
	261	{
	262	/* Penwell Core */
	263	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
	264	.driver_data = (kernel_ulong_t)&gpio_penwell_core,
	265	},
	266	{
	267	/* Cloverview Aon */
	268	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
	269	.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
	270	},
	271	{
	272	/* Cloverview Core */
	273	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
	274	.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
	275	},
d56d6b3d	276	{ 0 }
8bf02617	277	};
f89a768f	278	MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
8bf02617	279
bd0b9ac4	280	static void intel_mid_irq_handler(struct irq_desc *desc)
8bf02617	281	{
3f7dbfd8	282	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
5c77c021	283	struct intel_mid_gpio *priv = gpiochip_get_data(gc);
20e2aa91	284	struct irq_data *data = irq_desc_get_irq_data(desc);
20e2aa91	285	struct irq_chip *chip = irq_data_get_irq_chip(data);
84bead6c	286	u32 base, gpio, mask;
732063b9	287	unsigned long pending;
8bf02617	288	void __iomem *gedr;
8bf02617 AD	289
8bf02617 AD	290	/* check GPIO controller to check which pin triggered the interrupt */
f89a768f DC	291	for (base = 0; base < priv->chip.ngpio; base += 32) {
f89a768f DC	292	gedr = gpio_reg(&priv->chip, base, GEDR);
c8f925b6	293	while ((pending = readl(gedr))) {
2345b20f	294	gpio = __ffs(pending);
84bead6c	295	mask = BIT(gpio);
84bead6c TG	296	/* Clear before handling so we can't lose an edge */
84bead6c TG	297	writel(mask, gedr);
3f7dbfd8	298	generic_handle_irq(irq_find_mapping(gc->irqdomain,
465f2bd4	299	base + gpio));
732063b9	300	}
8bf02617	301	}
0766d20f	302
20e2aa91	303	chip->irq_eoi(data);
8bf02617 AD	304	}
8bf02617 AD	305
f89a768f	306	static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
f5f93117 MW	307	{
	308	void __iomem *reg;
	309	unsigned base;
	310
f89a768f	311	for (base = 0; base < priv->chip.ngpio; base += 32) {
f5f93117	312	/* Clear the rising-edge detect register */
f89a768f	313	reg = gpio_reg(&priv->chip, base, GRER);
f5f93117 MW	314	writel(0, reg);
f5f93117 MW	315	/* Clear the falling-edge detect register */
f89a768f	316	reg = gpio_reg(&priv->chip, base, GFER);
f5f93117 MW	317	writel(0, reg);
f5f93117 MW	318	/* Clear the edge detect status register */
f89a768f	319	reg = gpio_reg(&priv->chip, base, GEDR);
f5f93117 MW	320	writel(~0, reg);
	321	}
	322	}
	323
fbc2a294	324	static int __maybe_unused intel_gpio_runtime_idle(struct device *dev)
7812803a	325	{
84a34575	326	int err = pm_schedule_suspend(dev, 500);
84a34575	327	return err ?: -EBUSY;
7812803a KCA	328	}
7812803a KCA	329
f89a768f DC	330	static const struct dev_pm_ops intel_gpio_pm_ops = {
f89a768f DC	331	SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
7812803a KCA	332	};
7812803a KCA	333
f89a768f	334	static int intel_gpio_probe(struct pci_dev *pdev,
64c8cbc1	335	const struct pci_device_id *id)
8bf02617	336	{
64c8cbc1	337	void __iomem *base;
f89a768f	338	struct intel_mid_gpio *priv;
8bf02617	339	u32 gpio_base;
2519f9ab	340	u32 irq_base;
d6a2b7ba	341	int retval;
f89a768f DC	342	struct intel_mid_gpio_ddata *ddata =
f89a768f DC	343	(struct intel_mid_gpio_ddata *)id->driver_data;
8bf02617	344
786e07ec	345	retval = pcim_enable_device(pdev);
8bf02617	346	if (retval)
8302c741	347	return retval;
8bf02617	348
786e07ec	349	retval = pcim_iomap_regions(pdev, 1 << 0 \| 1 << 1, pci_name(pdev));
8bf02617	350	if (retval) {
786e07ec AS	351	dev_err(&pdev->dev, "I/O memory mapping error\n");
786e07ec AS	352	return retval;
8bf02617	353	}
64c8cbc1	354
786e07ec AS	355	base = pcim_iomap_table(pdev)[1];
786e07ec AS	356
64c8cbc1 AS	357	irq_base = readl(base);
	358	gpio_base = readl(sizeof(u32) + base);
	359
8bf02617	360	/* release the IO mapping, since we already get the info from bar1 */
786e07ec	361	pcim_iounmap_regions(pdev, 1 << 1);
8bf02617	362
f89a768f DC	363	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
f89a768f DC	364	if (!priv) {
8aca119f	365	dev_err(&pdev->dev, "can't allocate chip data\n");
786e07ec	366	return -ENOMEM;
8bf02617	367	}
b3e35af2	368
f89a768f DC	369	priv->reg_base = pcim_iomap_table(pdev)[0];
f89a768f DC	370	priv->chip.label = dev_name(&pdev->dev);
58383c78	371	priv->chip.parent = &pdev->dev;
f89a768f DC	372	priv->chip.request = intel_gpio_request;
	373	priv->chip.direction_input = intel_gpio_direction_input;
	374	priv->chip.direction_output = intel_gpio_direction_output;
	375	priv->chip.get = intel_gpio_get;
	376	priv->chip.set = intel_gpio_set;
f89a768f DC	377	priv->chip.base = gpio_base;
f89a768f DC	378	priv->chip.ngpio = ddata->ngpio;
9fb1f39e	379	priv->chip.can_sleep = false;
f89a768f DC	380	priv->pdev = pdev;
	381
	382	spin_lock_init(&priv->lock);
	383
f89a768f	384	pci_set_drvdata(pdev, priv);
dd3b204a	385	retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
8bf02617	386	if (retval) {
8aca119f	387	dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
786e07ec	388	return retval;
8bf02617	389	}
f5f93117	390
3f7dbfd8 LW	391	retval = gpiochip_irqchip_add(&priv->chip,
	392	&intel_mid_irqchip,
	393	irq_base,
	394	handle_simple_irq,
	395	IRQ_TYPE_NONE);
	396	if (retval) {
	397	dev_err(&pdev->dev,
	398	"could not connect irqchip to gpiochip\n");
	399	return retval;
	400	}
	401
f89a768f	402	intel_mid_irq_init_hw(priv);
f5f93117	403
3f7dbfd8 LW	404	gpiochip_set_chained_irqchip(&priv->chip,
	405	&intel_mid_irqchip,
	406	pdev->irq,
	407	intel_mid_irq_handler);
8bf02617	408
7812803a KCA	409	pm_runtime_put_noidle(&pdev->dev);
	410	pm_runtime_allow(&pdev->dev);
	411
8302c741	412	return 0;
8bf02617 AD	413	}
8bf02617 AD	414
f89a768f DC	415	static struct pci_driver intel_gpio_driver = {
	416	.name = "intel_mid_gpio",
	417	.id_table = intel_gpio_ids,
	418	.probe = intel_gpio_probe,
7812803a	419	.driver = {
f89a768f	420	.pm = &intel_gpio_pm_ops,
7812803a	421	},
8bf02617 AD	422	};
8bf02617 AD	423
5261bee8	424	builtin_pci_driver(intel_gpio_driver);