[mirror_ubuntu-zesty-kernel.git] / drivers / gpio / gpio-intel-mid.c

/*
 * Intel MID GPIO driver
 *
 * Copyright (c) 2008-2014 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/* Supports:
 * Moorestown platform Langwell chip.
 * Medfield platform Penwell chip.
 * Clovertrail platform Cloverview chip.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>

#define INTEL_MID_IRQ_TYPE_EDGE		(1 << 0)
#define INTEL_MID_IRQ_TYPE_LEVEL	(1 << 1)

/*
 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
 * registers to control them, so we only define the order here instead of a
 * structure, to get a bit offset for a pin (use GPDR as an example):
 *
 * nreg = ngpio / 32;
 * reg = offset / 32;
 * bit = offset % 32;
 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
 *
 * so the bit of reg_addr is to control pin offset's GPDR feature
*/

enum GPIO_REG {
	GPLR = 0,	/* pin level read-only */
	GPDR,		/* pin direction */
	GPSR,		/* pin set */
	GPCR,		/* pin clear */
	GRER,		/* rising edge detect */
	GFER,		/* falling edge detect */
	GEDR,		/* edge detect result */
	GAFR,		/* alt function */
};

/* intel_mid gpio driver data */
struct intel_mid_gpio_ddata {
	u16 ngpio;		/* number of gpio pins */
	u32 chip_irq_type;	/* chip interrupt type */
};

struct intel_mid_gpio {
	struct gpio_chip		chip;
	void __iomem			*reg_base;
	spinlock_t			lock;
	struct pci_dev			*pdev;
};

static inline struct intel_mid_gpio *to_intel_gpio_priv(struct gpio_chip *gc)
{
	return container_of(gc, struct intel_mid_gpio, chip);
}

static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
			      enum GPIO_REG reg_type)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 32;

	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
}

static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
				   enum GPIO_REG reg_type)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 16;

	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
}

static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	u32 value = readl(gafr);
	int shift = (offset % 16) << 1, af = (value >> shift) & 3;

	if (af) {
		value &= ~(3 << shift);
		writel(value, gafr);
	}
	return 0;
}

static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gplr = gpio_reg(chip, offset, GPLR);

	return readl(gplr) & BIT(offset % 32);
}

static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	void __iomem *gpsr, *gpcr;

	if (value) {
		gpsr = gpio_reg(chip, offset, GPSR);
		writel(BIT(offset % 32), gpsr);
	} else {
		gpcr = gpio_reg(chip, offset, GPCR);
		writel(BIT(offset % 32), gpcr);
	}
}

static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	u32 value;
	unsigned long flags;

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	value = readl(gpdr);
	value &= ~BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static int intel_gpio_direction_output(struct gpio_chip *chip,
			unsigned offset, int value)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	unsigned long flags;

	intel_gpio_set(chip, offset, value);

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	value = readl(gpdr);
	value |= BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static int intel_mid_irq_type(struct irq_data *d, unsigned type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct intel_mid_gpio *priv = to_intel_gpio_priv(gc);
	u32 gpio = irqd_to_hwirq(d);
	unsigned long flags;
	u32 value;
	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);

	if (gpio >= priv->chip.ngpio)
		return -EINVAL;

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	if (type & IRQ_TYPE_EDGE_RISING)
		value = readl(grer) | BIT(gpio % 32);
	else
		value = readl(grer) & (~BIT(gpio % 32));
	writel(value, grer);

	if (type & IRQ_TYPE_EDGE_FALLING)
		value = readl(gfer) | BIT(gpio % 32);
	else
		value = readl(gfer) & (~BIT(gpio % 32));
	writel(value, gfer);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static void intel_mid_irq_unmask(struct irq_data *d)
{
}

static void intel_mid_irq_mask(struct irq_data *d)
{
}

static struct irq_chip intel_mid_irqchip = {
	.name		= "INTEL_MID-GPIO",
	.irq_mask	= intel_mid_irq_mask,
	.irq_unmask	= intel_mid_irq_unmask,
	.irq_set_type	= intel_mid_irq_type,
};

static const struct intel_mid_gpio_ddata gpio_lincroft = {
	.ngpio = 64,
};

static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct intel_mid_gpio_ddata gpio_penwell_core = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
};

static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct pci_device_id intel_gpio_ids[] = {
	{
		/* Lincroft */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
		.driver_data = (kernel_ulong_t)&gpio_lincroft,
	},
	{
		/* Penwell AON */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
		.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
	},
	{
		/* Penwell Core */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
		.driver_data = (kernel_ulong_t)&gpio_penwell_core,
	},
	{
		/* Cloverview Aon */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
		.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
	},
	{
		/* Cloverview Core */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
		.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
	},
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, intel_gpio_ids);

static void intel_mid_irq_handler(struct irq_desc *desc)
{
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct intel_mid_gpio *priv = to_intel_gpio_priv(gc);
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, gpio, mask;
	unsigned long pending;
	void __iomem *gedr;

	/* check GPIO controller to check which pin triggered the interrupt */
	for (base = 0; base < priv->chip.ngpio; base += 32) {
		gedr = gpio_reg(&priv->chip, base, GEDR);
		while ((pending = readl(gedr))) {
			gpio = __ffs(pending);
			mask = BIT(gpio);
			/* Clear before handling so we can't lose an edge */
			writel(mask, gedr);
			generic_handle_irq(irq_find_mapping(gc->irqdomain,
							    base + gpio));
		}
	}

	chip->irq_eoi(data);
}

static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
{
	void __iomem *reg;
	unsigned base;

	for (base = 0; base < priv->chip.ngpio; base += 32) {
		/* Clear the rising-edge detect register */
		reg = gpio_reg(&priv->chip, base, GRER);
		writel(0, reg);
		/* Clear the falling-edge detect register */
		reg = gpio_reg(&priv->chip, base, GFER);
		writel(0, reg);
		/* Clear the edge detect status register */
		reg = gpio_reg(&priv->chip, base, GEDR);
		writel(~0, reg);
	}
}

static int intel_gpio_runtime_idle(struct device *dev)
{
	int err = pm_schedule_suspend(dev, 500);
	return err ?: -EBUSY;
}

static const struct dev_pm_ops intel_gpio_pm_ops = {
	SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
};

static int intel_gpio_probe(struct pci_dev *pdev,
			  const struct pci_device_id *id)
{
	void __iomem *base;
	struct intel_mid_gpio *priv;
	u32 gpio_base;
	u32 irq_base;
	int retval;
	struct intel_mid_gpio_ddata *ddata =
				(struct intel_mid_gpio_ddata *)id->driver_data;

	retval = pcim_enable_device(pdev);
	if (retval)
		return retval;

	retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
	if (retval) {
		dev_err(&pdev->dev, "I/O memory mapping error\n");
		return retval;
	}

	base = pcim_iomap_table(pdev)[1];

	irq_base = readl(base);
	gpio_base = readl(sizeof(u32) + base);

	/* release the IO mapping, since we already get the info from bar1 */
	pcim_iounmap_regions(pdev, 1 << 1);

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		dev_err(&pdev->dev, "can't allocate chip data\n");
		return -ENOMEM;
	}

	priv->reg_base = pcim_iomap_table(pdev)[0];
	priv->chip.label = dev_name(&pdev->dev);
	priv->chip.dev = &pdev->dev;
	priv->chip.request = intel_gpio_request;
	priv->chip.direction_input = intel_gpio_direction_input;
	priv->chip.direction_output = intel_gpio_direction_output;
	priv->chip.get = intel_gpio_get;
	priv->chip.set = intel_gpio_set;
	priv->chip.base = gpio_base;
	priv->chip.ngpio = ddata->ngpio;
	priv->chip.can_sleep = false;
	priv->pdev = pdev;

	spin_lock_init(&priv->lock);

	pci_set_drvdata(pdev, priv);
	retval = gpiochip_add(&priv->chip);
	if (retval) {
		dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
		return retval;
	}

	retval = gpiochip_irqchip_add(&priv->chip,
				      &intel_mid_irqchip,
				      irq_base,
				      handle_simple_irq,
				      IRQ_TYPE_NONE);
	if (retval) {
		dev_err(&pdev->dev,
			"could not connect irqchip to gpiochip\n");
		return retval;
	}

	intel_mid_irq_init_hw(priv);

	gpiochip_set_chained_irqchip(&priv->chip,
				     &intel_mid_irqchip,
				     pdev->irq,
				     intel_mid_irq_handler);

	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_allow(&pdev->dev);

	return 0;
}

static struct pci_driver intel_gpio_driver = {
	.name		= "intel_mid_gpio",
	.id_table	= intel_gpio_ids,
	.probe		= intel_gpio_probe,
	.driver		= {
		.pm	= &intel_gpio_pm_ops,
	},
};

static int __init intel_gpio_init(void)
{
	return pci_register_driver(&intel_gpio_driver);
}

device_initcall(intel_gpio_init);
Commit	Line	Data
c103de24	1	/*
a0bbf032	2	* Intel MID GPIO driver
c103de24	3	*
a0bbf032	4	* Copyright (c) 2008-2014 Intel Corporation.
8bf02617 AD	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
8bf02617 AD	14	*/
	15
	16	/* Supports:
	17	* Moorestown platform Langwell chip.
8081c84c	18	* Medfield platform Penwell chip.
f89a768f	19	* Clovertrail platform Cloverview chip.
8bf02617 AD	20	*/
	21
	22	#include <linux/module.h>
	23	#include <linux/pci.h>
72b4379e	24	#include <linux/platform_device.h>
8bf02617 AD	25	#include <linux/kernel.h>
	26	#include <linux/delay.h>
	27	#include <linux/stddef.h>
	28	#include <linux/interrupt.h>
	29	#include <linux/init.h>
8bf02617	30	#include <linux/io.h>
3f7dbfd8	31	#include <linux/gpio/driver.h>
5a0e3ad6	32	#include <linux/slab.h>
7812803a	33	#include <linux/pm_runtime.h>
8bf02617	34
f89a768f DC	35	#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
f89a768f DC	36	#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
d56d6b3d	37
8081c84c AD	38	/*
	39	* Langwell chip has 64 pins and thus there are 2 32bit registers to control
	40	* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
	41	* registers to control them, so we only define the order here instead of a
	42	* structure, to get a bit offset for a pin (use GPDR as an example):
	43	*
	44	* nreg = ngpio / 32;
	45	* reg = offset / 32;
	46	* bit = offset % 32;
	47	* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
	48	*
	49	* so the bit of reg_addr is to control pin offset's GPDR feature
	50	*/
	51
	52	enum GPIO_REG {
	53	GPLR = 0, /* pin level read-only */
	54	GPDR, /* pin direction */
	55	GPSR, /* pin set */
	56	GPCR, /* pin clear */
	57	GRER, /* rising edge detect */
	58	GFER, /* falling edge detect */
	59	GEDR, /* edge detect result */
8c0f7b10	60	GAFR, /* alt function */
8bf02617 AD	61	};
8bf02617 AD	62
f89a768f DC	63	/* intel_mid gpio driver data */
f89a768f DC	64	struct intel_mid_gpio_ddata {
d56d6b3d	65	u16 ngpio; /* number of gpio pins */
d56d6b3d DC	66	u32 chip_irq_type; /* chip interrupt type */
	67	};
	68
f89a768f	69	struct intel_mid_gpio {
8bf02617	70	struct gpio_chip chip;
64c8cbc1	71	void __iomem *reg_base;
8bf02617	72	spinlock_t lock;
7812803a	73	struct pci_dev *pdev;
8bf02617 AD	74	};
8bf02617 AD	75
3f7dbfd8 LW	76	static inline struct intel_mid_gpio to_intel_gpio_priv(struct gpio_chip gc)
	77	{
	78	return container_of(gc, struct intel_mid_gpio, chip);
	79	}
46ebfbc3	80
8081c84c	81	static void __iomem gpio_reg(struct gpio_chip chip, unsigned offset,
611a485b	82	enum GPIO_REG reg_type)
8bf02617	83	{
f89a768f	84	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
8081c84c	85	unsigned nreg = chip->ngpio / 32;
8bf02617	86	u8 reg = offset / 32;
8081c84c	87
f89a768f	88	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
8081c84c AD	89	}
8081c84c AD	90
8c0f7b10 AH	91	static void __iomem gpio_reg_2bit(struct gpio_chip chip, unsigned offset,
	92	enum GPIO_REG reg_type)
	93	{
f89a768f	94	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
8c0f7b10 AH	95	unsigned nreg = chip->ngpio / 32;
8c0f7b10 AH	96	u8 reg = offset / 16;
8c0f7b10	97
f89a768f	98	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
8c0f7b10 AH	99	}
8c0f7b10 AH	100
f89a768f	101	static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
8c0f7b10 AH	102	{
	103	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	104	u32 value = readl(gafr);
	105	int shift = (offset % 16) << 1, af = (value >> shift) & 3;
	106
	107	if (af) {
	108	value &= ~(3 << shift);
	109	writel(value, gafr);
	110	}
	111	return 0;
	112	}
	113
f89a768f	114	static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
8081c84c AD	115	{
8081c84c AD	116	void __iomem *gplr = gpio_reg(chip, offset, GPLR);
8bf02617	117
8bf02617 AD	118	return readl(gplr) & BIT(offset % 32);
	119	}
	120
f89a768f	121	static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
8bf02617	122	{
8bf02617 AD	123	void __iomem gpsr, gpcr;
	124
	125	if (value) {
8081c84c	126	gpsr = gpio_reg(chip, offset, GPSR);
8bf02617 AD	127	writel(BIT(offset % 32), gpsr);
8bf02617 AD	128	} else {
8081c84c	129	gpcr = gpio_reg(chip, offset, GPCR);
8bf02617 AD	130	writel(BIT(offset % 32), gpcr);
	131	}
	132	}
	133
f89a768f	134	static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
8bf02617	135	{
f89a768f	136	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
8081c84c	137	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617 AD	138	u32 value;
8bf02617 AD	139	unsigned long flags;
8bf02617	140
f89a768f DC	141	if (priv->pdev)
f89a768f DC	142	pm_runtime_get(&priv->pdev->dev);
7812803a	143
f89a768f	144	spin_lock_irqsave(&priv->lock, flags);
8bf02617 AD	145	value = readl(gpdr);
	146	value &= ~BIT(offset % 32);
	147	writel(value, gpdr);
f89a768f	148	spin_unlock_irqrestore(&priv->lock, flags);
7812803a	149
f89a768f DC	150	if (priv->pdev)
f89a768f DC	151	pm_runtime_put(&priv->pdev->dev);
7812803a	152
8bf02617 AD	153	return 0;
	154	}
	155
f89a768f	156	static int intel_gpio_direction_output(struct gpio_chip *chip,
8bf02617 AD	157	unsigned offset, int value)
8bf02617 AD	158	{
f89a768f	159	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
8081c84c	160	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617	161	unsigned long flags;
8bf02617	162
f89a768f	163	intel_gpio_set(chip, offset, value);
7812803a	164
f89a768f DC	165	if (priv->pdev)
f89a768f DC	166	pm_runtime_get(&priv->pdev->dev);
7812803a	167
f89a768f	168	spin_lock_irqsave(&priv->lock, flags);
8bf02617	169	value = readl(gpdr);
6eab04a8	170	value \|= BIT(offset % 32);
8bf02617	171	writel(value, gpdr);
f89a768f	172	spin_unlock_irqrestore(&priv->lock, flags);
7812803a	173
f89a768f DC	174	if (priv->pdev)
f89a768f DC	175	pm_runtime_put(&priv->pdev->dev);
7812803a	176
8bf02617 AD	177	return 0;
	178	}
	179
f89a768f	180	static int intel_mid_irq_type(struct irq_data *d, unsigned type)
8bf02617	181	{
3f7dbfd8 LW	182	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
3f7dbfd8 LW	183	struct intel_mid_gpio *priv = to_intel_gpio_priv(gc);
465f2bd4	184	u32 gpio = irqd_to_hwirq(d);
8bf02617 AD	185	unsigned long flags;
8bf02617 AD	186	u32 value;
f89a768f DC	187	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
f89a768f DC	188	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
8bf02617	189
f89a768f	190	if (gpio >= priv->chip.ngpio)
8bf02617	191	return -EINVAL;
7812803a	192
f89a768f DC	193	if (priv->pdev)
f89a768f DC	194	pm_runtime_get(&priv->pdev->dev);
7812803a	195
f89a768f	196	spin_lock_irqsave(&priv->lock, flags);
8bf02617 AD	197	if (type & IRQ_TYPE_EDGE_RISING)
	198	value = readl(grer) \| BIT(gpio % 32);
	199	else
	200	value = readl(grer) & (~BIT(gpio % 32));
	201	writel(value, grer);
	202
	203	if (type & IRQ_TYPE_EDGE_FALLING)
	204	value = readl(gfer) \| BIT(gpio % 32);
	205	else
	206	value = readl(gfer) & (~BIT(gpio % 32));
	207	writel(value, gfer);
f89a768f	208	spin_unlock_irqrestore(&priv->lock, flags);
8bf02617	209
f89a768f DC	210	if (priv->pdev)
f89a768f DC	211	pm_runtime_put(&priv->pdev->dev);
7812803a	212
8bf02617	213	return 0;
fd0574cb	214	}
8bf02617	215
f89a768f	216	static void intel_mid_irq_unmask(struct irq_data *d)
8bf02617	217	{
fd0574cb	218	}
8bf02617	219
f89a768f	220	static void intel_mid_irq_mask(struct irq_data *d)
8bf02617	221	{
fd0574cb	222	}
8bf02617	223
f89a768f DC	224	static struct irq_chip intel_mid_irqchip = {
	225	.name = "INTEL_MID-GPIO",
	226	.irq_mask = intel_mid_irq_mask,
	227	.irq_unmask = intel_mid_irq_unmask,
	228	.irq_set_type = intel_mid_irq_type,
8bf02617 AD	229	};
8bf02617 AD	230
f89a768f	231	static const struct intel_mid_gpio_ddata gpio_lincroft = {
d56d6b3d DC	232	.ngpio = 64,
	233	};
	234
f89a768f	235	static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
d56d6b3d	236	.ngpio = 96,
f89a768f	237	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	238	};
d56d6b3d DC	239
f89a768f	240	static const struct intel_mid_gpio_ddata gpio_penwell_core = {
d56d6b3d	241	.ngpio = 96,
f89a768f	242	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	243	};
d56d6b3d DC	244
f89a768f	245	static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
d56d6b3d	246	.ngpio = 96,
f89a768f	247	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE \| INTEL_MID_IRQ_TYPE_LEVEL,
d56d6b3d DC	248	};
d56d6b3d DC	249
f89a768f	250	static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
d56d6b3d	251	.ngpio = 96,
f89a768f	252	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	253	};
d56d6b3d DC	254
14f4a883	255	static const struct pci_device_id intel_gpio_ids[] = {
d56d6b3d DC	256	{
	257	/* Lincroft */
	258	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
	259	.driver_data = (kernel_ulong_t)&gpio_lincroft,
	260	},
	261	{
	262	/* Penwell AON */
	263	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
	264	.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
	265	},
	266	{
	267	/* Penwell Core */
	268	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
	269	.driver_data = (kernel_ulong_t)&gpio_penwell_core,
	270	},
	271	{
	272	/* Cloverview Aon */
	273	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
	274	.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
	275	},
	276	{
	277	/* Cloverview Core */
	278	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
	279	.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
	280	},
d56d6b3d	281	{ 0 }
8bf02617	282	};
f89a768f	283	MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
8bf02617	284
bd0b9ac4	285	static void intel_mid_irq_handler(struct irq_desc *desc)
8bf02617	286	{
3f7dbfd8 LW	287	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
3f7dbfd8 LW	288	struct intel_mid_gpio *priv = to_intel_gpio_priv(gc);
20e2aa91	289	struct irq_data *data = irq_desc_get_irq_data(desc);
20e2aa91	290	struct irq_chip *chip = irq_data_get_irq_chip(data);
84bead6c	291	u32 base, gpio, mask;
732063b9	292	unsigned long pending;
8bf02617	293	void __iomem *gedr;
8bf02617 AD	294
8bf02617 AD	295	/* check GPIO controller to check which pin triggered the interrupt */
f89a768f DC	296	for (base = 0; base < priv->chip.ngpio; base += 32) {
f89a768f DC	297	gedr = gpio_reg(&priv->chip, base, GEDR);
c8f925b6	298	while ((pending = readl(gedr))) {
2345b20f	299	gpio = __ffs(pending);
84bead6c	300	mask = BIT(gpio);
84bead6c TG	301	/* Clear before handling so we can't lose an edge */
84bead6c TG	302	writel(mask, gedr);
3f7dbfd8	303	generic_handle_irq(irq_find_mapping(gc->irqdomain,
465f2bd4	304	base + gpio));
732063b9	305	}
8bf02617	306	}
0766d20f	307
20e2aa91	308	chip->irq_eoi(data);
8bf02617 AD	309	}
8bf02617 AD	310
f89a768f	311	static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
f5f93117 MW	312	{
	313	void __iomem *reg;
	314	unsigned base;
	315
f89a768f	316	for (base = 0; base < priv->chip.ngpio; base += 32) {
f5f93117	317	/* Clear the rising-edge detect register */
f89a768f	318	reg = gpio_reg(&priv->chip, base, GRER);
f5f93117 MW	319	writel(0, reg);
f5f93117 MW	320	/* Clear the falling-edge detect register */
f89a768f	321	reg = gpio_reg(&priv->chip, base, GFER);
f5f93117 MW	322	writel(0, reg);
f5f93117 MW	323	/* Clear the edge detect status register */
f89a768f	324	reg = gpio_reg(&priv->chip, base, GEDR);
f5f93117 MW	325	writel(~0, reg);
	326	}
	327	}
	328
f89a768f	329	static int intel_gpio_runtime_idle(struct device *dev)
7812803a	330	{
84a34575	331	int err = pm_schedule_suspend(dev, 500);
84a34575	332	return err ?: -EBUSY;
7812803a KCA	333	}
7812803a KCA	334
f89a768f DC	335	static const struct dev_pm_ops intel_gpio_pm_ops = {
f89a768f DC	336	SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
7812803a KCA	337	};
7812803a KCA	338
f89a768f	339	static int intel_gpio_probe(struct pci_dev *pdev,
64c8cbc1	340	const struct pci_device_id *id)
8bf02617	341	{
64c8cbc1	342	void __iomem *base;
f89a768f	343	struct intel_mid_gpio *priv;
8bf02617	344	u32 gpio_base;
2519f9ab	345	u32 irq_base;
d6a2b7ba	346	int retval;
f89a768f DC	347	struct intel_mid_gpio_ddata *ddata =
f89a768f DC	348	(struct intel_mid_gpio_ddata *)id->driver_data;
8bf02617	349
786e07ec	350	retval = pcim_enable_device(pdev);
8bf02617	351	if (retval)
8302c741	352	return retval;
8bf02617	353
786e07ec	354	retval = pcim_iomap_regions(pdev, 1 << 0 \| 1 << 1, pci_name(pdev));
8bf02617	355	if (retval) {
786e07ec AS	356	dev_err(&pdev->dev, "I/O memory mapping error\n");
786e07ec AS	357	return retval;
8bf02617	358	}
64c8cbc1	359
786e07ec AS	360	base = pcim_iomap_table(pdev)[1];
786e07ec AS	361
64c8cbc1 AS	362	irq_base = readl(base);
	363	gpio_base = readl(sizeof(u32) + base);
	364
8bf02617	365	/* release the IO mapping, since we already get the info from bar1 */
786e07ec	366	pcim_iounmap_regions(pdev, 1 << 1);
8bf02617	367
f89a768f DC	368	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
f89a768f DC	369	if (!priv) {
8aca119f	370	dev_err(&pdev->dev, "can't allocate chip data\n");
786e07ec	371	return -ENOMEM;
8bf02617	372	}
b3e35af2	373
f89a768f DC	374	priv->reg_base = pcim_iomap_table(pdev)[0];
f89a768f DC	375	priv->chip.label = dev_name(&pdev->dev);
aa6baa7e	376	priv->chip.dev = &pdev->dev;
f89a768f DC	377	priv->chip.request = intel_gpio_request;
	378	priv->chip.direction_input = intel_gpio_direction_input;
	379	priv->chip.direction_output = intel_gpio_direction_output;
	380	priv->chip.get = intel_gpio_get;
	381	priv->chip.set = intel_gpio_set;
f89a768f DC	382	priv->chip.base = gpio_base;
f89a768f DC	383	priv->chip.ngpio = ddata->ngpio;
9fb1f39e	384	priv->chip.can_sleep = false;
f89a768f DC	385	priv->pdev = pdev;
	386
	387	spin_lock_init(&priv->lock);
	388
f89a768f DC	389	pci_set_drvdata(pdev, priv);
f89a768f DC	390	retval = gpiochip_add(&priv->chip);
8bf02617	391	if (retval) {
8aca119f	392	dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
786e07ec	393	return retval;
8bf02617	394	}
f5f93117	395
3f7dbfd8 LW	396	retval = gpiochip_irqchip_add(&priv->chip,
	397	&intel_mid_irqchip,
	398	irq_base,
	399	handle_simple_irq,
	400	IRQ_TYPE_NONE);
	401	if (retval) {
	402	dev_err(&pdev->dev,
	403	"could not connect irqchip to gpiochip\n");
	404	return retval;
	405	}
	406
f89a768f	407	intel_mid_irq_init_hw(priv);
f5f93117	408
3f7dbfd8 LW	409	gpiochip_set_chained_irqchip(&priv->chip,
	410	&intel_mid_irqchip,
	411	pdev->irq,
	412	intel_mid_irq_handler);
8bf02617	413
7812803a KCA	414	pm_runtime_put_noidle(&pdev->dev);
	415	pm_runtime_allow(&pdev->dev);
	416
8302c741	417	return 0;
8bf02617 AD	418	}
8bf02617 AD	419
f89a768f DC	420	static struct pci_driver intel_gpio_driver = {
	421	.name = "intel_mid_gpio",
	422	.id_table = intel_gpio_ids,
	423	.probe = intel_gpio_probe,
7812803a	424	.driver = {
f89a768f	425	.pm = &intel_gpio_pm_ops,
7812803a	426	},
8bf02617 AD	427	};
8bf02617 AD	428
f89a768f	429	static int __init intel_gpio_init(void)
8bf02617	430	{
f89a768f	431	return pci_register_driver(&intel_gpio_driver);
8bf02617 AD	432	}
8bf02617 AD	433
f89a768f	434	device_initcall(intel_gpio_init);