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Commit | Line | Data |
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c103de24 | 1 | /* |
a0bbf032 | 2 | * Intel MID GPIO driver |
c103de24 | 3 | * |
3cabe87b | 4 | * Copyright (c) 2008-2014,2016 Intel Corporation. |
8bf02617 AD |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
8bf02617 AD |
14 | */ |
15 | ||
16 | /* Supports: | |
17 | * Moorestown platform Langwell chip. | |
8081c84c | 18 | * Medfield platform Penwell chip. |
f89a768f | 19 | * Clovertrail platform Cloverview chip. |
8bf02617 AD |
20 | */ |
21 | ||
8bf02617 | 22 | #include <linux/delay.h> |
ddc53c40 | 23 | #include <linux/gpio/driver.h> |
8bf02617 | 24 | #include <linux/init.h> |
3cabe87b | 25 | #include <linux/interrupt.h> |
8bf02617 | 26 | #include <linux/io.h> |
3cabe87b | 27 | #include <linux/kernel.h> |
3cabe87b AS |
28 | #include <linux/pci.h> |
29 | #include <linux/platform_device.h> | |
7812803a | 30 | #include <linux/pm_runtime.h> |
3cabe87b AS |
31 | #include <linux/slab.h> |
32 | #include <linux/stddef.h> | |
8bf02617 | 33 | |
f89a768f DC |
34 | #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0) |
35 | #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1) | |
d56d6b3d | 36 | |
8081c84c AD |
37 | /* |
38 | * Langwell chip has 64 pins and thus there are 2 32bit registers to control | |
39 | * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit | |
40 | * registers to control them, so we only define the order here instead of a | |
41 | * structure, to get a bit offset for a pin (use GPDR as an example): | |
42 | * | |
43 | * nreg = ngpio / 32; | |
44 | * reg = offset / 32; | |
45 | * bit = offset % 32; | |
46 | * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4; | |
47 | * | |
48 | * so the bit of reg_addr is to control pin offset's GPDR feature | |
49 | */ | |
50 | ||
51 | enum GPIO_REG { | |
52 | GPLR = 0, /* pin level read-only */ | |
53 | GPDR, /* pin direction */ | |
54 | GPSR, /* pin set */ | |
55 | GPCR, /* pin clear */ | |
56 | GRER, /* rising edge detect */ | |
57 | GFER, /* falling edge detect */ | |
58 | GEDR, /* edge detect result */ | |
8c0f7b10 | 59 | GAFR, /* alt function */ |
8bf02617 AD |
60 | }; |
61 | ||
f89a768f DC |
62 | /* intel_mid gpio driver data */ |
63 | struct intel_mid_gpio_ddata { | |
d56d6b3d | 64 | u16 ngpio; /* number of gpio pins */ |
d56d6b3d DC |
65 | u32 chip_irq_type; /* chip interrupt type */ |
66 | }; | |
67 | ||
f89a768f | 68 | struct intel_mid_gpio { |
8bf02617 | 69 | struct gpio_chip chip; |
64c8cbc1 | 70 | void __iomem *reg_base; |
8bf02617 | 71 | spinlock_t lock; |
7812803a | 72 | struct pci_dev *pdev; |
8bf02617 AD |
73 | }; |
74 | ||
8081c84c | 75 | static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, |
611a485b | 76 | enum GPIO_REG reg_type) |
8bf02617 | 77 | { |
5c77c021 | 78 | struct intel_mid_gpio *priv = gpiochip_get_data(chip); |
8081c84c | 79 | unsigned nreg = chip->ngpio / 32; |
8bf02617 | 80 | u8 reg = offset / 32; |
8081c84c | 81 | |
f89a768f | 82 | return priv->reg_base + reg_type * nreg * 4 + reg * 4; |
8081c84c AD |
83 | } |
84 | ||
8c0f7b10 AH |
85 | static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset, |
86 | enum GPIO_REG reg_type) | |
87 | { | |
5c77c021 | 88 | struct intel_mid_gpio *priv = gpiochip_get_data(chip); |
8c0f7b10 AH |
89 | unsigned nreg = chip->ngpio / 32; |
90 | u8 reg = offset / 16; | |
8c0f7b10 | 91 | |
f89a768f | 92 | return priv->reg_base + reg_type * nreg * 4 + reg * 4; |
8c0f7b10 AH |
93 | } |
94 | ||
f89a768f | 95 | static int intel_gpio_request(struct gpio_chip *chip, unsigned offset) |
8c0f7b10 AH |
96 | { |
97 | void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR); | |
98 | u32 value = readl(gafr); | |
99 | int shift = (offset % 16) << 1, af = (value >> shift) & 3; | |
100 | ||
101 | if (af) { | |
102 | value &= ~(3 << shift); | |
103 | writel(value, gafr); | |
104 | } | |
105 | return 0; | |
106 | } | |
107 | ||
f89a768f | 108 | static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) |
8081c84c AD |
109 | { |
110 | void __iomem *gplr = gpio_reg(chip, offset, GPLR); | |
8bf02617 | 111 | |
4c628f3d | 112 | return !!(readl(gplr) & BIT(offset % 32)); |
8bf02617 AD |
113 | } |
114 | ||
f89a768f | 115 | static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
8bf02617 | 116 | { |
8bf02617 AD |
117 | void __iomem *gpsr, *gpcr; |
118 | ||
119 | if (value) { | |
8081c84c | 120 | gpsr = gpio_reg(chip, offset, GPSR); |
8bf02617 AD |
121 | writel(BIT(offset % 32), gpsr); |
122 | } else { | |
8081c84c | 123 | gpcr = gpio_reg(chip, offset, GPCR); |
8bf02617 AD |
124 | writel(BIT(offset % 32), gpcr); |
125 | } | |
126 | } | |
127 | ||
f89a768f | 128 | static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
8bf02617 | 129 | { |
5c77c021 | 130 | struct intel_mid_gpio *priv = gpiochip_get_data(chip); |
8081c84c | 131 | void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
8bf02617 AD |
132 | u32 value; |
133 | unsigned long flags; | |
8bf02617 | 134 | |
f89a768f DC |
135 | if (priv->pdev) |
136 | pm_runtime_get(&priv->pdev->dev); | |
7812803a | 137 | |
f89a768f | 138 | spin_lock_irqsave(&priv->lock, flags); |
8bf02617 AD |
139 | value = readl(gpdr); |
140 | value &= ~BIT(offset % 32); | |
141 | writel(value, gpdr); | |
f89a768f | 142 | spin_unlock_irqrestore(&priv->lock, flags); |
7812803a | 143 | |
f89a768f DC |
144 | if (priv->pdev) |
145 | pm_runtime_put(&priv->pdev->dev); | |
7812803a | 146 | |
8bf02617 AD |
147 | return 0; |
148 | } | |
149 | ||
f89a768f | 150 | static int intel_gpio_direction_output(struct gpio_chip *chip, |
8bf02617 AD |
151 | unsigned offset, int value) |
152 | { | |
5c77c021 | 153 | struct intel_mid_gpio *priv = gpiochip_get_data(chip); |
8081c84c | 154 | void __iomem *gpdr = gpio_reg(chip, offset, GPDR); |
8bf02617 | 155 | unsigned long flags; |
8bf02617 | 156 | |
f89a768f | 157 | intel_gpio_set(chip, offset, value); |
7812803a | 158 | |
f89a768f DC |
159 | if (priv->pdev) |
160 | pm_runtime_get(&priv->pdev->dev); | |
7812803a | 161 | |
f89a768f | 162 | spin_lock_irqsave(&priv->lock, flags); |
8bf02617 | 163 | value = readl(gpdr); |
6eab04a8 | 164 | value |= BIT(offset % 32); |
8bf02617 | 165 | writel(value, gpdr); |
f89a768f | 166 | spin_unlock_irqrestore(&priv->lock, flags); |
7812803a | 167 | |
f89a768f DC |
168 | if (priv->pdev) |
169 | pm_runtime_put(&priv->pdev->dev); | |
7812803a | 170 | |
8bf02617 AD |
171 | return 0; |
172 | } | |
173 | ||
f89a768f | 174 | static int intel_mid_irq_type(struct irq_data *d, unsigned type) |
8bf02617 | 175 | { |
3f7dbfd8 | 176 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
5c77c021 | 177 | struct intel_mid_gpio *priv = gpiochip_get_data(gc); |
465f2bd4 | 178 | u32 gpio = irqd_to_hwirq(d); |
8bf02617 AD |
179 | unsigned long flags; |
180 | u32 value; | |
f89a768f DC |
181 | void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); |
182 | void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); | |
8bf02617 | 183 | |
f89a768f | 184 | if (gpio >= priv->chip.ngpio) |
8bf02617 | 185 | return -EINVAL; |
7812803a | 186 | |
f89a768f DC |
187 | if (priv->pdev) |
188 | pm_runtime_get(&priv->pdev->dev); | |
7812803a | 189 | |
f89a768f | 190 | spin_lock_irqsave(&priv->lock, flags); |
8bf02617 AD |
191 | if (type & IRQ_TYPE_EDGE_RISING) |
192 | value = readl(grer) | BIT(gpio % 32); | |
193 | else | |
194 | value = readl(grer) & (~BIT(gpio % 32)); | |
195 | writel(value, grer); | |
196 | ||
197 | if (type & IRQ_TYPE_EDGE_FALLING) | |
198 | value = readl(gfer) | BIT(gpio % 32); | |
199 | else | |
200 | value = readl(gfer) & (~BIT(gpio % 32)); | |
201 | writel(value, gfer); | |
f89a768f | 202 | spin_unlock_irqrestore(&priv->lock, flags); |
8bf02617 | 203 | |
f89a768f DC |
204 | if (priv->pdev) |
205 | pm_runtime_put(&priv->pdev->dev); | |
7812803a | 206 | |
8bf02617 | 207 | return 0; |
fd0574cb | 208 | } |
8bf02617 | 209 | |
f89a768f | 210 | static void intel_mid_irq_unmask(struct irq_data *d) |
8bf02617 | 211 | { |
fd0574cb | 212 | } |
8bf02617 | 213 | |
f89a768f | 214 | static void intel_mid_irq_mask(struct irq_data *d) |
8bf02617 | 215 | { |
fd0574cb | 216 | } |
8bf02617 | 217 | |
f89a768f DC |
218 | static struct irq_chip intel_mid_irqchip = { |
219 | .name = "INTEL_MID-GPIO", | |
220 | .irq_mask = intel_mid_irq_mask, | |
221 | .irq_unmask = intel_mid_irq_unmask, | |
222 | .irq_set_type = intel_mid_irq_type, | |
8bf02617 AD |
223 | }; |
224 | ||
f89a768f | 225 | static const struct intel_mid_gpio_ddata gpio_lincroft = { |
d56d6b3d DC |
226 | .ngpio = 64, |
227 | }; | |
228 | ||
f89a768f | 229 | static const struct intel_mid_gpio_ddata gpio_penwell_aon = { |
d56d6b3d | 230 | .ngpio = 96, |
f89a768f | 231 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
d56d6b3d DC |
232 | }; |
233 | ||
f89a768f | 234 | static const struct intel_mid_gpio_ddata gpio_penwell_core = { |
d56d6b3d | 235 | .ngpio = 96, |
f89a768f | 236 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
d56d6b3d DC |
237 | }; |
238 | ||
f89a768f | 239 | static const struct intel_mid_gpio_ddata gpio_cloverview_aon = { |
d56d6b3d | 240 | .ngpio = 96, |
f89a768f | 241 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL, |
d56d6b3d DC |
242 | }; |
243 | ||
f89a768f | 244 | static const struct intel_mid_gpio_ddata gpio_cloverview_core = { |
d56d6b3d | 245 | .ngpio = 96, |
f89a768f | 246 | .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE, |
d56d6b3d DC |
247 | }; |
248 | ||
14f4a883 | 249 | static const struct pci_device_id intel_gpio_ids[] = { |
d56d6b3d DC |
250 | { |
251 | /* Lincroft */ | |
252 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), | |
253 | .driver_data = (kernel_ulong_t)&gpio_lincroft, | |
254 | }, | |
255 | { | |
256 | /* Penwell AON */ | |
257 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), | |
258 | .driver_data = (kernel_ulong_t)&gpio_penwell_aon, | |
259 | }, | |
260 | { | |
261 | /* Penwell Core */ | |
262 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), | |
263 | .driver_data = (kernel_ulong_t)&gpio_penwell_core, | |
264 | }, | |
265 | { | |
266 | /* Cloverview Aon */ | |
267 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), | |
268 | .driver_data = (kernel_ulong_t)&gpio_cloverview_aon, | |
269 | }, | |
270 | { | |
271 | /* Cloverview Core */ | |
272 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), | |
273 | .driver_data = (kernel_ulong_t)&gpio_cloverview_core, | |
274 | }, | |
ddc53c40 | 275 | { } |
8bf02617 | 276 | }; |
8bf02617 | 277 | |
bd0b9ac4 | 278 | static void intel_mid_irq_handler(struct irq_desc *desc) |
8bf02617 | 279 | { |
3f7dbfd8 | 280 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
5c77c021 | 281 | struct intel_mid_gpio *priv = gpiochip_get_data(gc); |
20e2aa91 | 282 | struct irq_data *data = irq_desc_get_irq_data(desc); |
20e2aa91 | 283 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
84bead6c | 284 | u32 base, gpio, mask; |
732063b9 | 285 | unsigned long pending; |
8bf02617 | 286 | void __iomem *gedr; |
8bf02617 AD |
287 | |
288 | /* check GPIO controller to check which pin triggered the interrupt */ | |
f89a768f DC |
289 | for (base = 0; base < priv->chip.ngpio; base += 32) { |
290 | gedr = gpio_reg(&priv->chip, base, GEDR); | |
c8f925b6 | 291 | while ((pending = readl(gedr))) { |
2345b20f | 292 | gpio = __ffs(pending); |
84bead6c | 293 | mask = BIT(gpio); |
84bead6c TG |
294 | /* Clear before handling so we can't lose an edge */ |
295 | writel(mask, gedr); | |
f0fbe7bc | 296 | generic_handle_irq(irq_find_mapping(gc->irq.domain, |
465f2bd4 | 297 | base + gpio)); |
732063b9 | 298 | } |
8bf02617 | 299 | } |
0766d20f | 300 | |
20e2aa91 | 301 | chip->irq_eoi(data); |
8bf02617 AD |
302 | } |
303 | ||
f89a768f | 304 | static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv) |
f5f93117 MW |
305 | { |
306 | void __iomem *reg; | |
307 | unsigned base; | |
308 | ||
f89a768f | 309 | for (base = 0; base < priv->chip.ngpio; base += 32) { |
f5f93117 | 310 | /* Clear the rising-edge detect register */ |
f89a768f | 311 | reg = gpio_reg(&priv->chip, base, GRER); |
f5f93117 MW |
312 | writel(0, reg); |
313 | /* Clear the falling-edge detect register */ | |
f89a768f | 314 | reg = gpio_reg(&priv->chip, base, GFER); |
f5f93117 MW |
315 | writel(0, reg); |
316 | /* Clear the edge detect status register */ | |
f89a768f | 317 | reg = gpio_reg(&priv->chip, base, GEDR); |
f5f93117 MW |
318 | writel(~0, reg); |
319 | } | |
320 | } | |
321 | ||
fbc2a294 | 322 | static int __maybe_unused intel_gpio_runtime_idle(struct device *dev) |
7812803a | 323 | { |
84a34575 | 324 | int err = pm_schedule_suspend(dev, 500); |
325 | return err ?: -EBUSY; | |
7812803a KCA |
326 | } |
327 | ||
f89a768f DC |
328 | static const struct dev_pm_ops intel_gpio_pm_ops = { |
329 | SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle) | |
7812803a KCA |
330 | }; |
331 | ||
f89a768f | 332 | static int intel_gpio_probe(struct pci_dev *pdev, |
64c8cbc1 | 333 | const struct pci_device_id *id) |
8bf02617 | 334 | { |
64c8cbc1 | 335 | void __iomem *base; |
f89a768f | 336 | struct intel_mid_gpio *priv; |
8bf02617 | 337 | u32 gpio_base; |
2519f9ab | 338 | u32 irq_base; |
d6a2b7ba | 339 | int retval; |
f89a768f DC |
340 | struct intel_mid_gpio_ddata *ddata = |
341 | (struct intel_mid_gpio_ddata *)id->driver_data; | |
8bf02617 | 342 | |
786e07ec | 343 | retval = pcim_enable_device(pdev); |
8bf02617 | 344 | if (retval) |
8302c741 | 345 | return retval; |
8bf02617 | 346 | |
786e07ec | 347 | retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev)); |
8bf02617 | 348 | if (retval) { |
786e07ec AS |
349 | dev_err(&pdev->dev, "I/O memory mapping error\n"); |
350 | return retval; | |
8bf02617 | 351 | } |
64c8cbc1 | 352 | |
786e07ec AS |
353 | base = pcim_iomap_table(pdev)[1]; |
354 | ||
64c8cbc1 AS |
355 | irq_base = readl(base); |
356 | gpio_base = readl(sizeof(u32) + base); | |
357 | ||
8bf02617 | 358 | /* release the IO mapping, since we already get the info from bar1 */ |
786e07ec | 359 | pcim_iounmap_regions(pdev, 1 << 1); |
8bf02617 | 360 | |
f89a768f | 361 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
75f8f5af | 362 | if (!priv) |
786e07ec | 363 | return -ENOMEM; |
b3e35af2 | 364 | |
f89a768f DC |
365 | priv->reg_base = pcim_iomap_table(pdev)[0]; |
366 | priv->chip.label = dev_name(&pdev->dev); | |
58383c78 | 367 | priv->chip.parent = &pdev->dev; |
f89a768f DC |
368 | priv->chip.request = intel_gpio_request; |
369 | priv->chip.direction_input = intel_gpio_direction_input; | |
370 | priv->chip.direction_output = intel_gpio_direction_output; | |
371 | priv->chip.get = intel_gpio_get; | |
372 | priv->chip.set = intel_gpio_set; | |
f89a768f DC |
373 | priv->chip.base = gpio_base; |
374 | priv->chip.ngpio = ddata->ngpio; | |
9fb1f39e | 375 | priv->chip.can_sleep = false; |
f89a768f DC |
376 | priv->pdev = pdev; |
377 | ||
378 | spin_lock_init(&priv->lock); | |
379 | ||
f89a768f | 380 | pci_set_drvdata(pdev, priv); |
dd3b204a | 381 | retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); |
8bf02617 | 382 | if (retval) { |
8aca119f | 383 | dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); |
786e07ec | 384 | return retval; |
8bf02617 | 385 | } |
f5f93117 | 386 | |
3f7dbfd8 LW |
387 | retval = gpiochip_irqchip_add(&priv->chip, |
388 | &intel_mid_irqchip, | |
389 | irq_base, | |
390 | handle_simple_irq, | |
391 | IRQ_TYPE_NONE); | |
392 | if (retval) { | |
393 | dev_err(&pdev->dev, | |
394 | "could not connect irqchip to gpiochip\n"); | |
395 | return retval; | |
396 | } | |
397 | ||
f89a768f | 398 | intel_mid_irq_init_hw(priv); |
f5f93117 | 399 | |
3f7dbfd8 LW |
400 | gpiochip_set_chained_irqchip(&priv->chip, |
401 | &intel_mid_irqchip, | |
402 | pdev->irq, | |
403 | intel_mid_irq_handler); | |
8bf02617 | 404 | |
7812803a KCA |
405 | pm_runtime_put_noidle(&pdev->dev); |
406 | pm_runtime_allow(&pdev->dev); | |
407 | ||
8302c741 | 408 | return 0; |
8bf02617 AD |
409 | } |
410 | ||
f89a768f DC |
411 | static struct pci_driver intel_gpio_driver = { |
412 | .name = "intel_mid_gpio", | |
413 | .id_table = intel_gpio_ids, | |
414 | .probe = intel_gpio_probe, | |
7812803a | 415 | .driver = { |
f89a768f | 416 | .pm = &intel_gpio_pm_ops, |
7812803a | 417 | }, |
8bf02617 AD |
418 | }; |
419 | ||
5261bee8 | 420 | builtin_pci_driver(intel_gpio_driver); |