[mirror_ubuntu-zesty-kernel.git] / drivers / gpio / gpio-intel-mid.c

/*
 * Moorestown platform Langwell chip GPIO driver
 *
 * Copyright (c) 2008, 2009, 2013, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* Supports:
 * Moorestown platform Langwell chip.
 * Medfield platform Penwell chip.
 * Clovertrail platform Cloverview chip.
 * Merrifield platform Tangier chip.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/irqdomain.h>

#define INTEL_MID_IRQ_TYPE_EDGE		(1 << 0)
#define INTEL_MID_IRQ_TYPE_LEVEL	(1 << 1)

/*
 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
 * registers to control them, so we only define the order here instead of a
 * structure, to get a bit offset for a pin (use GPDR as an example):
 *
 * nreg = ngpio / 32;
 * reg = offset / 32;
 * bit = offset % 32;
 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
 *
 * so the bit of reg_addr is to control pin offset's GPDR feature
*/

enum GPIO_REG {
	GPLR = 0,	/* pin level read-only */
	GPDR,		/* pin direction */
	GPSR,		/* pin set */
	GPCR,		/* pin clear */
	GRER,		/* rising edge detect */
	GFER,		/* falling edge detect */
	GEDR,		/* edge detect result */
	GAFR,		/* alt function */
};

/* intel_mid gpio driver data */
struct intel_mid_gpio_ddata {
	u16 ngpio;		/* number of gpio pins */
	u32 gplr_offset;	/* offset of first GPLR register from base */
	u32 flis_base;		/* base address of FLIS registers */
	u32 flis_len;		/* length of FLIS registers */
	u32 (*get_flis_offset)(int gpio);
	u32 chip_irq_type;	/* chip interrupt type */
};

struct intel_mid_gpio {
	struct gpio_chip		chip;
	void __iomem			*reg_base;
	spinlock_t			lock;
	struct pci_dev			*pdev;
	struct irq_domain		*domain;
};

#define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip)

static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
			      enum GPIO_REG reg_type)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 32;

	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
}

static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
				   enum GPIO_REG reg_type)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 16;

	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
}

static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	u32 value = readl(gafr);
	int shift = (offset % 16) << 1, af = (value >> shift) & 3;

	if (af) {
		value &= ~(3 << shift);
		writel(value, gafr);
	}
	return 0;
}

static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gplr = gpio_reg(chip, offset, GPLR);

	return readl(gplr) & BIT(offset % 32);
}

static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	void __iomem *gpsr, *gpcr;

	if (value) {
		gpsr = gpio_reg(chip, offset, GPSR);
		writel(BIT(offset % 32), gpsr);
	} else {
		gpcr = gpio_reg(chip, offset, GPCR);
		writel(BIT(offset % 32), gpcr);
	}
}

static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	u32 value;
	unsigned long flags;

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	value = readl(gpdr);
	value &= ~BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static int intel_gpio_direction_output(struct gpio_chip *chip,
			unsigned offset, int value)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	unsigned long flags;

	intel_gpio_set(chip, offset, value);

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	value = readl(gpdr);
	value |= BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
	return irq_create_mapping(priv->domain, offset);
}

static int intel_mid_irq_type(struct irq_data *d, unsigned type)
{
	struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
	u32 gpio = irqd_to_hwirq(d);
	unsigned long flags;
	u32 value;
	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);

	if (gpio >= priv->chip.ngpio)
		return -EINVAL;

	if (priv->pdev)
		pm_runtime_get(&priv->pdev->dev);

	spin_lock_irqsave(&priv->lock, flags);
	if (type & IRQ_TYPE_EDGE_RISING)
		value = readl(grer) | BIT(gpio % 32);
	else
		value = readl(grer) & (~BIT(gpio % 32));
	writel(value, grer);

	if (type & IRQ_TYPE_EDGE_FALLING)
		value = readl(gfer) | BIT(gpio % 32);
	else
		value = readl(gfer) & (~BIT(gpio % 32));
	writel(value, gfer);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (priv->pdev)
		pm_runtime_put(&priv->pdev->dev);

	return 0;
}

static void intel_mid_irq_unmask(struct irq_data *d)
{
}

static void intel_mid_irq_mask(struct irq_data *d)
{
}

static struct irq_chip intel_mid_irqchip = {
	.name		= "INTEL_MID-GPIO",
	.irq_mask	= intel_mid_irq_mask,
	.irq_unmask	= intel_mid_irq_unmask,
	.irq_set_type	= intel_mid_irq_type,
};

static const struct intel_mid_gpio_ddata gpio_lincroft = {
	.ngpio = 64,
};

static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct intel_mid_gpio_ddata gpio_penwell_core = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
};

static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
	.ngpio = 96,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct intel_mid_gpio_ddata gpio_tangier = {
	.ngpio = 192,
	.gplr_offset = 4,
	.flis_base = 0xff0c0000,
	.flis_len = 0x8000,
	.get_flis_offset = NULL,
	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
};

static const struct pci_device_id intel_gpio_ids[] = {
	{
		/* Lincroft */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
		.driver_data = (kernel_ulong_t)&gpio_lincroft,
	},
	{
		/* Penwell AON */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
		.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
	},
	{
		/* Penwell Core */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
		.driver_data = (kernel_ulong_t)&gpio_penwell_core,
	},
	{
		/* Cloverview Aon */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
		.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
	},
	{
		/* Cloverview Core */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
		.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
	},
	{
		/* Tangier */
		PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
		.driver_data = (kernel_ulong_t)&gpio_tangier,
	},
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, intel_gpio_ids);

static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, gpio, mask;
	unsigned long pending;
	void __iomem *gedr;

	/* check GPIO controller to check which pin triggered the interrupt */
	for (base = 0; base < priv->chip.ngpio; base += 32) {
		gedr = gpio_reg(&priv->chip, base, GEDR);
		while ((pending = readl(gedr))) {
			gpio = __ffs(pending);
			mask = BIT(gpio);
			/* Clear before handling so we can't lose an edge */
			writel(mask, gedr);
			generic_handle_irq(irq_find_mapping(priv->domain,
							    base + gpio));
		}
	}

	chip->irq_eoi(data);
}

static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
{
	void __iomem *reg;
	unsigned base;

	for (base = 0; base < priv->chip.ngpio; base += 32) {
		/* Clear the rising-edge detect register */
		reg = gpio_reg(&priv->chip, base, GRER);
		writel(0, reg);
		/* Clear the falling-edge detect register */
		reg = gpio_reg(&priv->chip, base, GFER);
		writel(0, reg);
		/* Clear the edge detect status register */
		reg = gpio_reg(&priv->chip, base, GEDR);
		writel(~0, reg);
	}
}

static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq,
			    irq_hw_number_t hwirq)
{
	struct intel_mid_gpio *priv = d->host_data;

	irq_set_chip_and_handler(irq, &intel_mid_irqchip, handle_simple_irq);
	irq_set_chip_data(irq, priv);
	irq_set_irq_type(irq, IRQ_TYPE_NONE);

	return 0;
}

static const struct irq_domain_ops intel_gpio_irq_ops = {
	.map = intel_gpio_irq_map,
	.xlate = irq_domain_xlate_twocell,
};

static int intel_gpio_runtime_idle(struct device *dev)
{
	pm_schedule_suspend(dev, 500);
	return -EBUSY;
}

static const struct dev_pm_ops intel_gpio_pm_ops = {
	SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
};

static int intel_gpio_probe(struct pci_dev *pdev,
			  const struct pci_device_id *id)
{
	void __iomem *base;
	struct intel_mid_gpio *priv;
	u32 gpio_base;
	u32 irq_base;
	int retval;
	struct intel_mid_gpio_ddata *ddata =
				(struct intel_mid_gpio_ddata *)id->driver_data;

	retval = pcim_enable_device(pdev);
	if (retval)
		return retval;

	retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
	if (retval) {
		dev_err(&pdev->dev, "I/O memory mapping error\n");
		return retval;
	}

	base = pcim_iomap_table(pdev)[1];

	irq_base = readl(base);
	gpio_base = readl(sizeof(u32) + base);

	/* release the IO mapping, since we already get the info from bar1 */
	pcim_iounmap_regions(pdev, 1 << 1);

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		dev_err(&pdev->dev, "can't allocate chip data\n");
		return -ENOMEM;
	}

	priv->reg_base = pcim_iomap_table(pdev)[0];
	priv->chip.label = dev_name(&pdev->dev);
	priv->chip.request = intel_gpio_request;
	priv->chip.direction_input = intel_gpio_direction_input;
	priv->chip.direction_output = intel_gpio_direction_output;
	priv->chip.get = intel_gpio_get;
	priv->chip.set = intel_gpio_set;
	priv->chip.to_irq = intel_gpio_to_irq;
	priv->chip.base = gpio_base;
	priv->chip.ngpio = ddata->ngpio;
	priv->chip.can_sleep = 0;
	priv->pdev = pdev;

	spin_lock_init(&priv->lock);

	priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
					irq_base, &intel_gpio_irq_ops, priv);
	if (!priv->domain)
		return -ENOMEM;

	pci_set_drvdata(pdev, priv);
	retval = gpiochip_add(&priv->chip);
	if (retval) {
		dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
		return retval;
	}

	intel_mid_irq_init_hw(priv);

	irq_set_handler_data(pdev->irq, priv);
	irq_set_chained_handler(pdev->irq, intel_mid_irq_handler);

	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_allow(&pdev->dev);

	return 0;
}

static struct pci_driver intel_gpio_driver = {
	.name		= "intel_mid_gpio",
	.id_table	= intel_gpio_ids,
	.probe		= intel_gpio_probe,
	.driver		= {
		.pm	= &intel_gpio_pm_ops,
	},
};

static int __init intel_gpio_init(void)
{
	return pci_register_driver(&intel_gpio_driver);
}

device_initcall(intel_gpio_init);
Commit	Line	Data
c103de24 GL	1	/*
	2	* Moorestown platform Langwell chip GPIO driver
	3	*
611a485b	4	* Copyright (c) 2008, 2009, 2013, Intel Corporation.
8bf02617 AD	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*/
	19
	20	/* Supports:
	21	* Moorestown platform Langwell chip.
8081c84c	22	* Medfield platform Penwell chip.
f89a768f DC	23	* Clovertrail platform Cloverview chip.
f89a768f DC	24	* Merrifield platform Tangier chip.
8bf02617 AD	25	*/
	26
	27	#include <linux/module.h>
	28	#include <linux/pci.h>
72b4379e	29	#include <linux/platform_device.h>
8bf02617 AD	30	#include <linux/kernel.h>
	31	#include <linux/delay.h>
	32	#include <linux/stddef.h>
	33	#include <linux/interrupt.h>
	34	#include <linux/init.h>
	35	#include <linux/irq.h>
	36	#include <linux/io.h>
	37	#include <linux/gpio.h>
5a0e3ad6	38	#include <linux/slab.h>
7812803a	39	#include <linux/pm_runtime.h>
465f2bd4	40	#include <linux/irqdomain.h>
8bf02617	41
f89a768f DC	42	#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
f89a768f DC	43	#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
d56d6b3d	44
8081c84c AD	45	/*
	46	* Langwell chip has 64 pins and thus there are 2 32bit registers to control
	47	* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
	48	* registers to control them, so we only define the order here instead of a
	49	* structure, to get a bit offset for a pin (use GPDR as an example):
	50	*
	51	* nreg = ngpio / 32;
	52	* reg = offset / 32;
	53	* bit = offset % 32;
	54	* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
	55	*
	56	* so the bit of reg_addr is to control pin offset's GPDR feature
	57	*/
	58
	59	enum GPIO_REG {
	60	GPLR = 0, /* pin level read-only */
	61	GPDR, /* pin direction */
	62	GPSR, /* pin set */
	63	GPCR, /* pin clear */
	64	GRER, /* rising edge detect */
	65	GFER, /* falling edge detect */
	66	GEDR, /* edge detect result */
8c0f7b10	67	GAFR, /* alt function */
8bf02617 AD	68	};
8bf02617 AD	69
f89a768f DC	70	/* intel_mid gpio driver data */
f89a768f DC	71	struct intel_mid_gpio_ddata {
d56d6b3d DC	72	u16 ngpio; /* number of gpio pins */
	73	u32 gplr_offset; /* offset of first GPLR register from base */
	74	u32 flis_base; /* base address of FLIS registers */
	75	u32 flis_len; /* length of FLIS registers */
	76	u32 (*get_flis_offset)(int gpio);
	77	u32 chip_irq_type; /* chip interrupt type */
	78	};
	79
f89a768f	80	struct intel_mid_gpio {
8bf02617	81	struct gpio_chip chip;
64c8cbc1	82	void __iomem *reg_base;
8bf02617	83	spinlock_t lock;
7812803a	84	struct pci_dev *pdev;
465f2bd4	85	struct irq_domain *domain;
8bf02617 AD	86	};
8bf02617 AD	87
f89a768f	88	#define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip)
46ebfbc3	89
8081c84c	90	static void __iomem gpio_reg(struct gpio_chip chip, unsigned offset,
611a485b	91	enum GPIO_REG reg_type)
8bf02617	92	{
f89a768f	93	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
8081c84c	94	unsigned nreg = chip->ngpio / 32;
8bf02617	95	u8 reg = offset / 32;
8081c84c	96
f89a768f	97	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
8081c84c AD	98	}
8081c84c AD	99
8c0f7b10 AH	100	static void __iomem gpio_reg_2bit(struct gpio_chip chip, unsigned offset,
	101	enum GPIO_REG reg_type)
	102	{
f89a768f	103	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
8c0f7b10 AH	104	unsigned nreg = chip->ngpio / 32;
8c0f7b10 AH	105	u8 reg = offset / 16;
8c0f7b10	106
f89a768f	107	return priv->reg_base + reg_type * nreg * 4 + reg * 4;
8c0f7b10 AH	108	}
8c0f7b10 AH	109
f89a768f	110	static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
8c0f7b10 AH	111	{
	112	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	113	u32 value = readl(gafr);
	114	int shift = (offset % 16) << 1, af = (value >> shift) & 3;
	115
	116	if (af) {
	117	value &= ~(3 << shift);
	118	writel(value, gafr);
	119	}
	120	return 0;
	121	}
	122
f89a768f	123	static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
8081c84c AD	124	{
8081c84c AD	125	void __iomem *gplr = gpio_reg(chip, offset, GPLR);
8bf02617	126
8bf02617 AD	127	return readl(gplr) & BIT(offset % 32);
	128	}
	129
f89a768f	130	static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
8bf02617	131	{
8bf02617 AD	132	void __iomem gpsr, gpcr;
	133
	134	if (value) {
8081c84c	135	gpsr = gpio_reg(chip, offset, GPSR);
8bf02617 AD	136	writel(BIT(offset % 32), gpsr);
8bf02617 AD	137	} else {
8081c84c	138	gpcr = gpio_reg(chip, offset, GPCR);
8bf02617 AD	139	writel(BIT(offset % 32), gpcr);
	140	}
	141	}
	142
f89a768f	143	static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
8bf02617	144	{
f89a768f	145	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
8081c84c	146	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617 AD	147	u32 value;
8bf02617 AD	148	unsigned long flags;
8bf02617	149
f89a768f DC	150	if (priv->pdev)
f89a768f DC	151	pm_runtime_get(&priv->pdev->dev);
7812803a	152
f89a768f	153	spin_lock_irqsave(&priv->lock, flags);
8bf02617 AD	154	value = readl(gpdr);
	155	value &= ~BIT(offset % 32);
	156	writel(value, gpdr);
f89a768f	157	spin_unlock_irqrestore(&priv->lock, flags);
7812803a	158
f89a768f DC	159	if (priv->pdev)
f89a768f DC	160	pm_runtime_put(&priv->pdev->dev);
7812803a	161
8bf02617 AD	162	return 0;
	163	}
	164
f89a768f	165	static int intel_gpio_direction_output(struct gpio_chip *chip,
8bf02617 AD	166	unsigned offset, int value)
8bf02617 AD	167	{
f89a768f	168	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
8081c84c	169	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617	170	unsigned long flags;
8bf02617	171
f89a768f	172	intel_gpio_set(chip, offset, value);
7812803a	173
f89a768f DC	174	if (priv->pdev)
f89a768f DC	175	pm_runtime_get(&priv->pdev->dev);
7812803a	176
f89a768f	177	spin_lock_irqsave(&priv->lock, flags);
8bf02617	178	value = readl(gpdr);
6eab04a8	179	value \|= BIT(offset % 32);
8bf02617	180	writel(value, gpdr);
f89a768f	181	spin_unlock_irqrestore(&priv->lock, flags);
7812803a	182
f89a768f DC	183	if (priv->pdev)
f89a768f DC	184	pm_runtime_put(&priv->pdev->dev);
7812803a	185
8bf02617 AD	186	return 0;
	187	}
	188
f89a768f	189	static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
8bf02617	190	{
f89a768f DC	191	struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
f89a768f DC	192	return irq_create_mapping(priv->domain, offset);
8bf02617 AD	193	}
8bf02617 AD	194
f89a768f	195	static int intel_mid_irq_type(struct irq_data *d, unsigned type)
8bf02617	196	{
f89a768f	197	struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
465f2bd4	198	u32 gpio = irqd_to_hwirq(d);
8bf02617 AD	199	unsigned long flags;
8bf02617 AD	200	u32 value;
f89a768f DC	201	void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
f89a768f DC	202	void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
8bf02617	203
f89a768f	204	if (gpio >= priv->chip.ngpio)
8bf02617	205	return -EINVAL;
7812803a	206
f89a768f DC	207	if (priv->pdev)
f89a768f DC	208	pm_runtime_get(&priv->pdev->dev);
7812803a	209
f89a768f	210	spin_lock_irqsave(&priv->lock, flags);
8bf02617 AD	211	if (type & IRQ_TYPE_EDGE_RISING)
	212	value = readl(grer) \| BIT(gpio % 32);
	213	else
	214	value = readl(grer) & (~BIT(gpio % 32));
	215	writel(value, grer);
	216
	217	if (type & IRQ_TYPE_EDGE_FALLING)
	218	value = readl(gfer) \| BIT(gpio % 32);
	219	else
	220	value = readl(gfer) & (~BIT(gpio % 32));
	221	writel(value, gfer);
f89a768f	222	spin_unlock_irqrestore(&priv->lock, flags);
8bf02617	223
f89a768f DC	224	if (priv->pdev)
f89a768f DC	225	pm_runtime_put(&priv->pdev->dev);
7812803a	226
8bf02617	227	return 0;
fd0574cb	228	}
8bf02617	229
f89a768f	230	static void intel_mid_irq_unmask(struct irq_data *d)
8bf02617	231	{
fd0574cb	232	}
8bf02617	233
f89a768f	234	static void intel_mid_irq_mask(struct irq_data *d)
8bf02617	235	{
fd0574cb	236	}
8bf02617	237
f89a768f DC	238	static struct irq_chip intel_mid_irqchip = {
	239	.name = "INTEL_MID-GPIO",
	240	.irq_mask = intel_mid_irq_mask,
	241	.irq_unmask = intel_mid_irq_unmask,
	242	.irq_set_type = intel_mid_irq_type,
8bf02617 AD	243	};
8bf02617 AD	244
f89a768f	245	static const struct intel_mid_gpio_ddata gpio_lincroft = {
d56d6b3d DC	246	.ngpio = 64,
	247	};
	248
f89a768f	249	static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
d56d6b3d	250	.ngpio = 96,
f89a768f	251	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	252	};
d56d6b3d DC	253
f89a768f	254	static const struct intel_mid_gpio_ddata gpio_penwell_core = {
d56d6b3d	255	.ngpio = 96,
f89a768f	256	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	257	};
d56d6b3d DC	258
f89a768f	259	static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
d56d6b3d	260	.ngpio = 96,
f89a768f	261	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE \| INTEL_MID_IRQ_TYPE_LEVEL,
d56d6b3d DC	262	};
d56d6b3d DC	263
f89a768f	264	static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
d56d6b3d	265	.ngpio = 96,
f89a768f	266	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	267	};
d56d6b3d DC	268
f89a768f	269	static const struct intel_mid_gpio_ddata gpio_tangier = {
d56d6b3d DC	270	.ngpio = 192,
	271	.gplr_offset = 4,
	272	.flis_base = 0xff0c0000,
	273	.flis_len = 0x8000,
	274	.get_flis_offset = NULL,
f89a768f	275	.chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
d56d6b3d DC	276	};
d56d6b3d DC	277
14f4a883	278	static const struct pci_device_id intel_gpio_ids[] = {
d56d6b3d DC	279	{
	280	/* Lincroft */
	281	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
	282	.driver_data = (kernel_ulong_t)&gpio_lincroft,
	283	},
	284	{
	285	/* Penwell AON */
	286	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
	287	.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
	288	},
	289	{
	290	/* Penwell Core */
	291	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
	292	.driver_data = (kernel_ulong_t)&gpio_penwell_core,
	293	},
	294	{
	295	/* Cloverview Aon */
	296	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
	297	.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
	298	},
	299	{
	300	/* Cloverview Core */
	301	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
	302	.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
	303	},
	304	{
	305	/* Tangier */
	306	PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
	307	.driver_data = (kernel_ulong_t)&gpio_tangier,
	308	},
	309	{ 0 }
8bf02617	310	};
f89a768f	311	MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
8bf02617	312
f89a768f	313	static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
8bf02617	314	{
20e2aa91	315	struct irq_data *data = irq_desc_get_irq_data(desc);
f89a768f	316	struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data);
20e2aa91	317	struct irq_chip *chip = irq_data_get_irq_chip(data);
84bead6c	318	u32 base, gpio, mask;
732063b9	319	unsigned long pending;
8bf02617	320	void __iomem *gedr;
8bf02617 AD	321
8bf02617 AD	322	/* check GPIO controller to check which pin triggered the interrupt */
f89a768f DC	323	for (base = 0; base < priv->chip.ngpio; base += 32) {
f89a768f DC	324	gedr = gpio_reg(&priv->chip, base, GEDR);
c8f925b6	325	while ((pending = readl(gedr))) {
2345b20f	326	gpio = __ffs(pending);
84bead6c	327	mask = BIT(gpio);
84bead6c TG	328	/* Clear before handling so we can't lose an edge */
84bead6c TG	329	writel(mask, gedr);
f89a768f	330	generic_handle_irq(irq_find_mapping(priv->domain,
465f2bd4	331	base + gpio));
732063b9	332	}
8bf02617	333	}
0766d20f	334
20e2aa91	335	chip->irq_eoi(data);
8bf02617 AD	336	}
8bf02617 AD	337
f89a768f	338	static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
f5f93117 MW	339	{
	340	void __iomem *reg;
	341	unsigned base;
	342
f89a768f	343	for (base = 0; base < priv->chip.ngpio; base += 32) {
f5f93117	344	/* Clear the rising-edge detect register */
f89a768f	345	reg = gpio_reg(&priv->chip, base, GRER);
f5f93117 MW	346	writel(0, reg);
f5f93117 MW	347	/* Clear the falling-edge detect register */
f89a768f	348	reg = gpio_reg(&priv->chip, base, GFER);
f5f93117 MW	349	writel(0, reg);
f5f93117 MW	350	/* Clear the edge detect status register */
f89a768f	351	reg = gpio_reg(&priv->chip, base, GEDR);
f5f93117 MW	352	writel(~0, reg);
	353	}
	354	}
	355
ba519dd4 LW	356	static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq,
ba519dd4 LW	357	irq_hw_number_t hwirq)
465f2bd4	358	{
f89a768f	359	struct intel_mid_gpio *priv = d->host_data;
465f2bd4	360
e5428a68	361	irq_set_chip_and_handler(irq, &intel_mid_irqchip, handle_simple_irq);
ba519dd4 LW	362	irq_set_chip_data(irq, priv);
ba519dd4 LW	363	irq_set_irq_type(irq, IRQ_TYPE_NONE);
465f2bd4 MW	364
	365	return 0;
	366	}
	367
f89a768f DC	368	static const struct irq_domain_ops intel_gpio_irq_ops = {
f89a768f DC	369	.map = intel_gpio_irq_map,
465f2bd4 MW	370	.xlate = irq_domain_xlate_twocell,
	371	};
	372
f89a768f	373	static int intel_gpio_runtime_idle(struct device *dev)
7812803a	374	{
45f0a85c	375	pm_schedule_suspend(dev, 500);
7812803a KCA	376	return -EBUSY;
	377	}
	378
f89a768f DC	379	static const struct dev_pm_ops intel_gpio_pm_ops = {
f89a768f DC	380	SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
7812803a KCA	381	};
7812803a KCA	382
f89a768f	383	static int intel_gpio_probe(struct pci_dev *pdev,
64c8cbc1	384	const struct pci_device_id *id)
8bf02617	385	{
64c8cbc1	386	void __iomem *base;
f89a768f	387	struct intel_mid_gpio *priv;
8bf02617	388	u32 gpio_base;
2519f9ab	389	u32 irq_base;
d6a2b7ba	390	int retval;
f89a768f DC	391	struct intel_mid_gpio_ddata *ddata =
f89a768f DC	392	(struct intel_mid_gpio_ddata *)id->driver_data;
8bf02617	393
786e07ec	394	retval = pcim_enable_device(pdev);
8bf02617	395	if (retval)
8302c741	396	return retval;
8bf02617	397
786e07ec	398	retval = pcim_iomap_regions(pdev, 1 << 0 \| 1 << 1, pci_name(pdev));
8bf02617	399	if (retval) {
786e07ec AS	400	dev_err(&pdev->dev, "I/O memory mapping error\n");
786e07ec AS	401	return retval;
8bf02617	402	}
64c8cbc1	403
786e07ec AS	404	base = pcim_iomap_table(pdev)[1];
786e07ec AS	405
64c8cbc1 AS	406	irq_base = readl(base);
	407	gpio_base = readl(sizeof(u32) + base);
	408
8bf02617	409	/* release the IO mapping, since we already get the info from bar1 */
786e07ec	410	pcim_iounmap_regions(pdev, 1 << 1);
8bf02617	411
f89a768f DC	412	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
f89a768f DC	413	if (!priv) {
8aca119f	414	dev_err(&pdev->dev, "can't allocate chip data\n");
786e07ec	415	return -ENOMEM;
8bf02617	416	}
b3e35af2	417
f89a768f DC	418	priv->reg_base = pcim_iomap_table(pdev)[0];
	419	priv->chip.label = dev_name(&pdev->dev);
	420	priv->chip.request = intel_gpio_request;
	421	priv->chip.direction_input = intel_gpio_direction_input;
	422	priv->chip.direction_output = intel_gpio_direction_output;
	423	priv->chip.get = intel_gpio_get;
	424	priv->chip.set = intel_gpio_set;
	425	priv->chip.to_irq = intel_gpio_to_irq;
	426	priv->chip.base = gpio_base;
	427	priv->chip.ngpio = ddata->ngpio;
	428	priv->chip.can_sleep = 0;
	429	priv->pdev = pdev;
	430
	431	spin_lock_init(&priv->lock);
	432
	433	priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
	434	irq_base, &intel_gpio_irq_ops, priv);
	435	if (!priv->domain)
786e07ec	436	return -ENOMEM;
2519f9ab	437
f89a768f DC	438	pci_set_drvdata(pdev, priv);
f89a768f DC	439	retval = gpiochip_add(&priv->chip);
8bf02617	440	if (retval) {
8aca119f	441	dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
786e07ec	442	return retval;
8bf02617	443	}
f5f93117	444
f89a768f	445	intel_mid_irq_init_hw(priv);
f5f93117	446
f89a768f DC	447	irq_set_handler_data(pdev->irq, priv);
f89a768f DC	448	irq_set_chained_handler(pdev->irq, intel_mid_irq_handler);
8bf02617	449
7812803a KCA	450	pm_runtime_put_noidle(&pdev->dev);
	451	pm_runtime_allow(&pdev->dev);
	452
8302c741	453	return 0;
8bf02617 AD	454	}
8bf02617 AD	455
f89a768f DC	456	static struct pci_driver intel_gpio_driver = {
	457	.name = "intel_mid_gpio",
	458	.id_table = intel_gpio_ids,
	459	.probe = intel_gpio_probe,
7812803a	460	.driver = {
f89a768f	461	.pm = &intel_gpio_pm_ops,
7812803a	462	},
8bf02617 AD	463	};
8bf02617 AD	464
f89a768f	465	static int __init intel_gpio_init(void)
8bf02617	466	{
f89a768f	467	return pci_register_driver(&intel_gpio_driver);
8bf02617 AD	468	}
8bf02617 AD	469
f89a768f	470	device_initcall(intel_gpio_init);