[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-langwell.c

/*
 * Moorestown platform Langwell chip GPIO driver
 *
 * Copyright (c) 2008, 2009, 2013, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* Supports:
 * Moorestown platform Langwell chip.
 * Medfield platform Penwell chip.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/irqdomain.h>

/*
 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
 * registers to control them, so we only define the order here instead of a
 * structure, to get a bit offset for a pin (use GPDR as an example):
 *
 * nreg = ngpio / 32;
 * reg = offset / 32;
 * bit = offset % 32;
 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
 *
 * so the bit of reg_addr is to control pin offset's GPDR feature
*/

enum GPIO_REG {
	GPLR = 0,	/* pin level read-only */
	GPDR,		/* pin direction */
	GPSR,		/* pin set */
	GPCR,		/* pin clear */
	GRER,		/* rising edge detect */
	GFER,		/* falling edge detect */
	GEDR,		/* edge detect result */
	GAFR,		/* alt function */
};

struct lnw_gpio {
	struct gpio_chip		chip;
	void __iomem			*reg_base;
	spinlock_t			lock;
	struct pci_dev			*pdev;
	struct irq_domain		*domain;
};

#define to_lnw_priv(chip)	container_of(chip, struct lnw_gpio, chip)

static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
			      enum GPIO_REG reg_type)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 32;

	return lnw->reg_base + reg_type * nreg * 4 + reg * 4;
}

static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
				   enum GPIO_REG reg_type)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 16;

	return lnw->reg_base + reg_type * nreg * 4 + reg * 4;
}

static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	u32 value = readl(gafr);
	int shift = (offset % 16) << 1, af = (value >> shift) & 3;

	if (af) {
		value &= ~(3 << shift);
		writel(value, gafr);
	}
	return 0;
}

static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gplr = gpio_reg(chip, offset, GPLR);

	return readl(gplr) & BIT(offset % 32);
}

static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	void __iomem *gpsr, *gpcr;

	if (value) {
		gpsr = gpio_reg(chip, offset, GPSR);
		writel(BIT(offset % 32), gpsr);
	} else {
		gpcr = gpio_reg(chip, offset, GPCR);
		writel(BIT(offset % 32), gpcr);
	}
}

static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	u32 value;
	unsigned long flags;

	if (lnw->pdev)
		pm_runtime_get(&lnw->pdev->dev);

	spin_lock_irqsave(&lnw->lock, flags);
	value = readl(gpdr);
	value &= ~BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&lnw->lock, flags);

	if (lnw->pdev)
		pm_runtime_put(&lnw->pdev->dev);

	return 0;
}

static int lnw_gpio_direction_output(struct gpio_chip *chip,
			unsigned offset, int value)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	unsigned long flags;

	lnw_gpio_set(chip, offset, value);

	if (lnw->pdev)
		pm_runtime_get(&lnw->pdev->dev);

	spin_lock_irqsave(&lnw->lock, flags);
	value = readl(gpdr);
	value |= BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&lnw->lock, flags);

	if (lnw->pdev)
		pm_runtime_put(&lnw->pdev->dev);

	return 0;
}

static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	return irq_create_mapping(lnw->domain, offset);
}

static int lnw_irq_type(struct irq_data *d, unsigned type)
{
	struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
	u32 gpio = irqd_to_hwirq(d);
	unsigned long flags;
	u32 value;
	void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
	void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);

	if (gpio >= lnw->chip.ngpio)
		return -EINVAL;

	if (lnw->pdev)
		pm_runtime_get(&lnw->pdev->dev);

	spin_lock_irqsave(&lnw->lock, flags);
	if (type & IRQ_TYPE_EDGE_RISING)
		value = readl(grer) | BIT(gpio % 32);
	else
		value = readl(grer) & (~BIT(gpio % 32));
	writel(value, grer);

	if (type & IRQ_TYPE_EDGE_FALLING)
		value = readl(gfer) | BIT(gpio % 32);
	else
		value = readl(gfer) & (~BIT(gpio % 32));
	writel(value, gfer);
	spin_unlock_irqrestore(&lnw->lock, flags);

	if (lnw->pdev)
		pm_runtime_put(&lnw->pdev->dev);

	return 0;
}

static void lnw_irq_unmask(struct irq_data *d)
{
}

static void lnw_irq_mask(struct irq_data *d)
{
}

static struct irq_chip lnw_irqchip = {
	.name		= "LNW-GPIO",
	.irq_mask	= lnw_irq_mask,
	.irq_unmask	= lnw_irq_unmask,
	.irq_set_type	= lnw_irq_type,
};

static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = {   /* pin number */
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), .driver_data = 96 },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), .driver_data = 96 },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);

static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, gpio, mask;
	unsigned long pending;
	void __iomem *gedr;

	/* check GPIO controller to check which pin triggered the interrupt */
	for (base = 0; base < lnw->chip.ngpio; base += 32) {
		gedr = gpio_reg(&lnw->chip, base, GEDR);
		while ((pending = readl(gedr))) {
			gpio = __ffs(pending);
			mask = BIT(gpio);
			/* Clear before handling so we can't lose an edge */
			writel(mask, gedr);
			generic_handle_irq(irq_find_mapping(lnw->domain,
							    base + gpio));
		}
	}

	chip->irq_eoi(data);
}

static void lnw_irq_init_hw(struct lnw_gpio *lnw)
{
	void __iomem *reg;
	unsigned base;

	for (base = 0; base < lnw->chip.ngpio; base += 32) {
		/* Clear the rising-edge detect register */
		reg = gpio_reg(&lnw->chip, base, GRER);
		writel(0, reg);
		/* Clear the falling-edge detect register */
		reg = gpio_reg(&lnw->chip, base, GFER);
		writel(0, reg);
		/* Clear the edge detect status register */
		reg = gpio_reg(&lnw->chip, base, GEDR);
		writel(~0, reg);
	}
}

static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
			    irq_hw_number_t hw)
{
	struct lnw_gpio *lnw = d->host_data;

	irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
				      "demux");
	irq_set_chip_data(virq, lnw);
	irq_set_irq_type(virq, IRQ_TYPE_NONE);

	return 0;
}

static const struct irq_domain_ops lnw_gpio_irq_ops = {
	.map = lnw_gpio_irq_map,
	.xlate = irq_domain_xlate_twocell,
};

static int lnw_gpio_runtime_idle(struct device *dev)
{
	pm_schedule_suspend(dev, 500);
	return -EBUSY;
}

static const struct dev_pm_ops lnw_gpio_pm_ops = {
	SET_RUNTIME_PM_OPS(NULL, NULL, lnw_gpio_runtime_idle)
};

static int lnw_gpio_probe(struct pci_dev *pdev,
			  const struct pci_device_id *id)
{
	void __iomem *base;
	struct lnw_gpio *lnw;
	u32 gpio_base;
	u32 irq_base;
	int retval;
	int ngpio = id->driver_data;

	retval = pcim_enable_device(pdev);
	if (retval)
		return retval;

	retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
	if (retval) {
		dev_err(&pdev->dev, "I/O memory mapping error\n");
		return retval;
	}

	base = pcim_iomap_table(pdev)[1];

	irq_base = readl(base);
	gpio_base = readl(sizeof(u32) + base);

	/* release the IO mapping, since we already get the info from bar1 */
	pcim_iounmap_regions(pdev, 1 << 1);

	lnw = devm_kzalloc(&pdev->dev, sizeof(*lnw), GFP_KERNEL);
	if (!lnw) {
		dev_err(&pdev->dev, "can't allocate chip data\n");
		return -ENOMEM;
	}

	lnw->reg_base = pcim_iomap_table(pdev)[0];
	lnw->chip.label = dev_name(&pdev->dev);
	lnw->chip.request = lnw_gpio_request;
	lnw->chip.direction_input = lnw_gpio_direction_input;
	lnw->chip.direction_output = lnw_gpio_direction_output;
	lnw->chip.get = lnw_gpio_get;
	lnw->chip.set = lnw_gpio_set;
	lnw->chip.to_irq = lnw_gpio_to_irq;
	lnw->chip.base = gpio_base;
	lnw->chip.ngpio = ngpio;
	lnw->chip.can_sleep = 0;
	lnw->pdev = pdev;

	spin_lock_init(&lnw->lock);

	lnw->domain = irq_domain_add_simple(pdev->dev.of_node, ngpio, irq_base,
					    &lnw_gpio_irq_ops, lnw);
	if (!lnw->domain)
		return -ENOMEM;

	pci_set_drvdata(pdev, lnw);
	retval = gpiochip_add(&lnw->chip);
	if (retval) {
		dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
		return retval;
	}

	lnw_irq_init_hw(lnw);

	irq_set_handler_data(pdev->irq, lnw);
	irq_set_chained_handler(pdev->irq, lnw_irq_handler);

	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_allow(&pdev->dev);

	return 0;
}

static struct pci_driver lnw_gpio_driver = {
	.name		= "langwell_gpio",
	.id_table	= lnw_gpio_ids,
	.probe		= lnw_gpio_probe,
	.driver		= {
		.pm	= &lnw_gpio_pm_ops,
	},
};

static int __init lnw_gpio_init(void)
{
	return pci_register_driver(&lnw_gpio_driver);
}

device_initcall(lnw_gpio_init);
Commit	Line	Data
c103de24 GL	1	/*
	2	* Moorestown platform Langwell chip GPIO driver
	3	*
611a485b	4	* Copyright (c) 2008, 2009, 2013, Intel Corporation.
8bf02617 AD	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*/
	19
	20	/* Supports:
	21	* Moorestown platform Langwell chip.
8081c84c	22	* Medfield platform Penwell chip.
8bf02617 AD	23	*/
	24
	25	#include <linux/module.h>
	26	#include <linux/pci.h>
72b4379e	27	#include <linux/platform_device.h>
8bf02617 AD	28	#include <linux/kernel.h>
	29	#include <linux/delay.h>
	30	#include <linux/stddef.h>
	31	#include <linux/interrupt.h>
	32	#include <linux/init.h>
	33	#include <linux/irq.h>
	34	#include <linux/io.h>
	35	#include <linux/gpio.h>
5a0e3ad6	36	#include <linux/slab.h>
7812803a	37	#include <linux/pm_runtime.h>
465f2bd4	38	#include <linux/irqdomain.h>
8bf02617	39
8081c84c AD	40	/*
	41	* Langwell chip has 64 pins and thus there are 2 32bit registers to control
	42	* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
	43	* registers to control them, so we only define the order here instead of a
	44	* structure, to get a bit offset for a pin (use GPDR as an example):
	45	*
	46	* nreg = ngpio / 32;
	47	* reg = offset / 32;
	48	* bit = offset % 32;
	49	* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
	50	*
	51	* so the bit of reg_addr is to control pin offset's GPDR feature
	52	*/
	53
	54	enum GPIO_REG {
	55	GPLR = 0, /* pin level read-only */
	56	GPDR, /* pin direction */
	57	GPSR, /* pin set */
	58	GPCR, /* pin clear */
	59	GRER, /* rising edge detect */
	60	GFER, /* falling edge detect */
	61	GEDR, /* edge detect result */
8c0f7b10	62	GAFR, /* alt function */
8bf02617 AD	63	};
	64
	65	struct lnw_gpio {
	66	struct gpio_chip chip;
64c8cbc1	67	void __iomem *reg_base;
8bf02617	68	spinlock_t lock;
7812803a	69	struct pci_dev *pdev;
465f2bd4	70	struct irq_domain *domain;
8bf02617 AD	71	};
8bf02617 AD	72
46ebfbc3 DC	73	#define to_lnw_priv(chip) container_of(chip, struct lnw_gpio, chip)
46ebfbc3 DC	74
8081c84c	75	static void __iomem gpio_reg(struct gpio_chip chip, unsigned offset,
611a485b	76	enum GPIO_REG reg_type)
8bf02617	77	{
46ebfbc3	78	struct lnw_gpio *lnw = to_lnw_priv(chip);
8081c84c	79	unsigned nreg = chip->ngpio / 32;
8bf02617	80	u8 reg = offset / 32;
8081c84c	81
611a485b	82	return lnw->reg_base + reg_type * nreg * 4 + reg * 4;
8081c84c AD	83	}
8081c84c AD	84
8c0f7b10 AH	85	static void __iomem gpio_reg_2bit(struct gpio_chip chip, unsigned offset,
	86	enum GPIO_REG reg_type)
	87	{
46ebfbc3	88	struct lnw_gpio *lnw = to_lnw_priv(chip);
8c0f7b10 AH	89	unsigned nreg = chip->ngpio / 32;
8c0f7b10 AH	90	u8 reg = offset / 16;
8c0f7b10	91
611a485b	92	return lnw->reg_base + reg_type * nreg * 4 + reg * 4;
8c0f7b10 AH	93	}
	94
	95	static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
	96	{
	97	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	98	u32 value = readl(gafr);
	99	int shift = (offset % 16) << 1, af = (value >> shift) & 3;
	100
	101	if (af) {
	102	value &= ~(3 << shift);
	103	writel(value, gafr);
	104	}
	105	return 0;
	106	}
	107
8081c84c AD	108	static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
	109	{
	110	void __iomem *gplr = gpio_reg(chip, offset, GPLR);
8bf02617	111
8bf02617 AD	112	return readl(gplr) & BIT(offset % 32);
	113	}
	114
	115	static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	116	{
8bf02617 AD	117	void __iomem gpsr, gpcr;
	118
	119	if (value) {
8081c84c	120	gpsr = gpio_reg(chip, offset, GPSR);
8bf02617 AD	121	writel(BIT(offset % 32), gpsr);
8bf02617 AD	122	} else {
8081c84c	123	gpcr = gpio_reg(chip, offset, GPCR);
8bf02617 AD	124	writel(BIT(offset % 32), gpcr);
	125	}
	126	}
	127
	128	static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	129	{
46ebfbc3	130	struct lnw_gpio *lnw = to_lnw_priv(chip);
8081c84c	131	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617 AD	132	u32 value;
8bf02617 AD	133	unsigned long flags;
8bf02617	134
7812803a KCA	135	if (lnw->pdev)
	136	pm_runtime_get(&lnw->pdev->dev);
	137
8bf02617 AD	138	spin_lock_irqsave(&lnw->lock, flags);
	139	value = readl(gpdr);
	140	value &= ~BIT(offset % 32);
	141	writel(value, gpdr);
	142	spin_unlock_irqrestore(&lnw->lock, flags);
7812803a KCA	143
	144	if (lnw->pdev)
	145	pm_runtime_put(&lnw->pdev->dev);
	146
8bf02617 AD	147	return 0;
	148	}
	149
	150	static int lnw_gpio_direction_output(struct gpio_chip *chip,
	151	unsigned offset, int value)
	152	{
46ebfbc3	153	struct lnw_gpio *lnw = to_lnw_priv(chip);
8081c84c	154	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617	155	unsigned long flags;
8bf02617 AD	156
8bf02617 AD	157	lnw_gpio_set(chip, offset, value);
7812803a KCA	158
	159	if (lnw->pdev)
	160	pm_runtime_get(&lnw->pdev->dev);
	161
8bf02617 AD	162	spin_lock_irqsave(&lnw->lock, flags);
8bf02617 AD	163	value = readl(gpdr);
6eab04a8	164	value \|= BIT(offset % 32);
8bf02617 AD	165	writel(value, gpdr);
8bf02617 AD	166	spin_unlock_irqrestore(&lnw->lock, flags);
7812803a KCA	167
	168	if (lnw->pdev)
	169	pm_runtime_put(&lnw->pdev->dev);
	170
8bf02617 AD	171	return 0;
	172	}
	173
	174	static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	175	{
46ebfbc3	176	struct lnw_gpio *lnw = to_lnw_priv(chip);
465f2bd4	177	return irq_create_mapping(lnw->domain, offset);
8bf02617 AD	178	}
8bf02617 AD	179
5ffd72c6	180	static int lnw_irq_type(struct irq_data *d, unsigned type)
8bf02617	181	{
5ffd72c6	182	struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
465f2bd4	183	u32 gpio = irqd_to_hwirq(d);
8bf02617 AD	184	unsigned long flags;
8bf02617 AD	185	u32 value;
8081c84c AD	186	void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
8081c84c AD	187	void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
8bf02617	188
4efec627	189	if (gpio >= lnw->chip.ngpio)
8bf02617	190	return -EINVAL;
7812803a KCA	191
	192	if (lnw->pdev)
	193	pm_runtime_get(&lnw->pdev->dev);
	194
8bf02617 AD	195	spin_lock_irqsave(&lnw->lock, flags);
	196	if (type & IRQ_TYPE_EDGE_RISING)
	197	value = readl(grer) \| BIT(gpio % 32);
	198	else
	199	value = readl(grer) & (~BIT(gpio % 32));
	200	writel(value, grer);
	201
	202	if (type & IRQ_TYPE_EDGE_FALLING)
	203	value = readl(gfer) \| BIT(gpio % 32);
	204	else
	205	value = readl(gfer) & (~BIT(gpio % 32));
	206	writel(value, gfer);
	207	spin_unlock_irqrestore(&lnw->lock, flags);
	208
7812803a KCA	209	if (lnw->pdev)
	210	pm_runtime_put(&lnw->pdev->dev);
	211
8bf02617	212	return 0;
fd0574cb	213	}
8bf02617	214
5ffd72c6	215	static void lnw_irq_unmask(struct irq_data *d)
8bf02617	216	{
fd0574cb	217	}
8bf02617	218
5ffd72c6	219	static void lnw_irq_mask(struct irq_data *d)
8bf02617	220	{
fd0574cb	221	}
8bf02617 AD	222
	223	static struct irq_chip lnw_irqchip = {
	224	.name = "LNW-GPIO",
5ffd72c6 LB	225	.irq_mask = lnw_irq_mask,
	226	.irq_unmask = lnw_irq_unmask,
	227	.irq_set_type = lnw_irq_type,
8bf02617 AD	228	};
8bf02617 AD	229
8081c84c AD	230	static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
	231	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
	232	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
	233	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
936cb1b1 DC	234	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), .driver_data = 96 },
936cb1b1 DC	235	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), .driver_data = 96 },
8bf02617 AD	236	{ 0, }
	237	};
	238	MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
	239
	240	static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
	241	{
20e2aa91 TG	242	struct irq_data *data = irq_desc_get_irq_data(desc);
	243	struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
	244	struct irq_chip *chip = irq_data_get_irq_chip(data);
84bead6c	245	u32 base, gpio, mask;
732063b9	246	unsigned long pending;
8bf02617	247	void __iomem *gedr;
8bf02617 AD	248
8bf02617 AD	249	/* check GPIO controller to check which pin triggered the interrupt */
8081c84c AD	250	for (base = 0; base < lnw->chip.ngpio; base += 32) {
8081c84c AD	251	gedr = gpio_reg(&lnw->chip, base, GEDR);
c8f925b6	252	while ((pending = readl(gedr))) {
2345b20f	253	gpio = __ffs(pending);
84bead6c	254	mask = BIT(gpio);
84bead6c TG	255	/* Clear before handling so we can't lose an edge */
84bead6c TG	256	writel(mask, gedr);
465f2bd4 MW	257	generic_handle_irq(irq_find_mapping(lnw->domain,
465f2bd4 MW	258	base + gpio));
732063b9	259	}
8bf02617	260	}
0766d20f	261
20e2aa91	262	chip->irq_eoi(data);
8bf02617 AD	263	}
8bf02617 AD	264
f5f93117 MW	265	static void lnw_irq_init_hw(struct lnw_gpio *lnw)
	266	{
	267	void __iomem *reg;
	268	unsigned base;
	269
	270	for (base = 0; base < lnw->chip.ngpio; base += 32) {
	271	/* Clear the rising-edge detect register */
	272	reg = gpio_reg(&lnw->chip, base, GRER);
	273	writel(0, reg);
	274	/* Clear the falling-edge detect register */
	275	reg = gpio_reg(&lnw->chip, base, GFER);
	276	writel(0, reg);
	277	/* Clear the edge detect status register */
	278	reg = gpio_reg(&lnw->chip, base, GEDR);
	279	writel(~0, reg);
	280	}
	281	}
	282
465f2bd4 MW	283	static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
	284	irq_hw_number_t hw)
	285	{
	286	struct lnw_gpio *lnw = d->host_data;
	287
	288	irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
	289	"demux");
	290	irq_set_chip_data(virq, lnw);
	291	irq_set_irq_type(virq, IRQ_TYPE_NONE);
	292
	293	return 0;
	294	}
	295
	296	static const struct irq_domain_ops lnw_gpio_irq_ops = {
	297	.map = lnw_gpio_irq_map,
	298	.xlate = irq_domain_xlate_twocell,
	299	};
	300
7812803a KCA	301	static int lnw_gpio_runtime_idle(struct device *dev)
7812803a KCA	302	{
45f0a85c	303	pm_schedule_suspend(dev, 500);
7812803a KCA	304	return -EBUSY;
	305	}
	306
7812803a	307	static const struct dev_pm_ops lnw_gpio_pm_ops = {
46ebfbc3	308	SET_RUNTIME_PM_OPS(NULL, NULL, lnw_gpio_runtime_idle)
7812803a KCA	309	};
7812803a KCA	310
3836309d	311	static int lnw_gpio_probe(struct pci_dev *pdev,
64c8cbc1	312	const struct pci_device_id *id)
8bf02617	313	{
64c8cbc1	314	void __iomem *base;
8bf02617	315	struct lnw_gpio *lnw;
8bf02617	316	u32 gpio_base;
2519f9ab	317	u32 irq_base;
d6a2b7ba	318	int retval;
b3e35af2	319	int ngpio = id->driver_data;
8bf02617	320
786e07ec	321	retval = pcim_enable_device(pdev);
8bf02617	322	if (retval)
8302c741	323	return retval;
8bf02617	324
786e07ec	325	retval = pcim_iomap_regions(pdev, 1 << 0 \| 1 << 1, pci_name(pdev));
8bf02617	326	if (retval) {
786e07ec AS	327	dev_err(&pdev->dev, "I/O memory mapping error\n");
786e07ec AS	328	return retval;
8bf02617	329	}
64c8cbc1	330
786e07ec AS	331	base = pcim_iomap_table(pdev)[1];
786e07ec AS	332
64c8cbc1 AS	333	irq_base = readl(base);
	334	gpio_base = readl(sizeof(u32) + base);
	335
8bf02617	336	/* release the IO mapping, since we already get the info from bar1 */
786e07ec	337	pcim_iounmap_regions(pdev, 1 << 1);
8bf02617	338
46ebfbc3	339	lnw = devm_kzalloc(&pdev->dev, sizeof(*lnw), GFP_KERNEL);
8bf02617	340	if (!lnw) {
8aca119f	341	dev_err(&pdev->dev, "can't allocate chip data\n");
786e07ec	342	return -ENOMEM;
8bf02617	343	}
b3e35af2	344
786e07ec	345	lnw->reg_base = pcim_iomap_table(pdev)[0];
8bf02617	346	lnw->chip.label = dev_name(&pdev->dev);
8c0f7b10	347	lnw->chip.request = lnw_gpio_request;
8bf02617 AD	348	lnw->chip.direction_input = lnw_gpio_direction_input;
	349	lnw->chip.direction_output = lnw_gpio_direction_output;
	350	lnw->chip.get = lnw_gpio_get;
	351	lnw->chip.set = lnw_gpio_set;
	352	lnw->chip.to_irq = lnw_gpio_to_irq;
	353	lnw->chip.base = gpio_base;
b3e35af2	354	lnw->chip.ngpio = ngpio;
8bf02617	355	lnw->chip.can_sleep = 0;
7812803a	356	lnw->pdev = pdev;
2519f9ab	357
aeb168f7 AS	358	spin_lock_init(&lnw->lock);
aeb168f7 AS	359
2519f9ab DC	360	lnw->domain = irq_domain_add_simple(pdev->dev.of_node, ngpio, irq_base,
2519f9ab DC	361	&lnw_gpio_irq_ops, lnw);
786e07ec AS	362	if (!lnw->domain)
786e07ec AS	363	return -ENOMEM;
2519f9ab	364
8bf02617 AD	365	pci_set_drvdata(pdev, lnw);
	366	retval = gpiochip_add(&lnw->chip);
	367	if (retval) {
8aca119f	368	dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
786e07ec	369	return retval;
8bf02617	370	}
f5f93117 MW	371
	372	lnw_irq_init_hw(lnw);
	373
674db906 TG	374	irq_set_handler_data(pdev->irq, lnw);
674db906 TG	375	irq_set_chained_handler(pdev->irq, lnw_irq_handler);
8bf02617	376
7812803a KCA	377	pm_runtime_put_noidle(&pdev->dev);
	378	pm_runtime_allow(&pdev->dev);
	379
8302c741	380	return 0;
8bf02617 AD	381	}
	382
	383	static struct pci_driver lnw_gpio_driver = {
	384	.name = "langwell_gpio",
	385	.id_table = lnw_gpio_ids,
	386	.probe = lnw_gpio_probe,
7812803a KCA	387	.driver = {
	388	.pm = &lnw_gpio_pm_ops,
	389	},
8bf02617 AD	390	};
	391
	392	static int __init lnw_gpio_init(void)
	393	{
10b20a93	394	return pci_register_driver(&lnw_gpio_driver);
8bf02617 AD	395	}
	396
	397	device_initcall(lnw_gpio_init);