[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-langwell.c

/*
 * Moorestown platform Langwell chip GPIO driver
 *
 * Copyright (c) 2008 - 2009,  Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* Supports:
 * Moorestown platform Langwell chip.
 * Medfield platform Penwell chip.
 * Whitney point.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/irqdomain.h>

/*
 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
 * registers to control them, so we only define the order here instead of a
 * structure, to get a bit offset for a pin (use GPDR as an example):
 *
 * nreg = ngpio / 32;
 * reg = offset / 32;
 * bit = offset % 32;
 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
 *
 * so the bit of reg_addr is to control pin offset's GPDR feature
*/

enum GPIO_REG {
	GPLR = 0,	/* pin level read-only */
	GPDR,		/* pin direction */
	GPSR,		/* pin set */
	GPCR,		/* pin clear */
	GRER,		/* rising edge detect */
	GFER,		/* falling edge detect */
	GEDR,		/* edge detect result */
	GAFR,		/* alt function */
};

struct lnw_gpio {
	struct gpio_chip		chip;
	void __iomem			*reg_base;
	spinlock_t			lock;
	struct pci_dev			*pdev;
	struct irq_domain		*domain;
};

#define to_lnw_priv(chip)	container_of(chip, struct lnw_gpio, chip)

static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
			enum GPIO_REG reg_type)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 32;
	void __iomem *ptr;

	ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
	return ptr;
}

static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
				   enum GPIO_REG reg_type)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 16;
	void __iomem *ptr;

	ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
	return ptr;
}

static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	u32 value = readl(gafr);
	int shift = (offset % 16) << 1, af = (value >> shift) & 3;

	if (af) {
		value &= ~(3 << shift);
		writel(value, gafr);
	}
	return 0;
}

static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gplr = gpio_reg(chip, offset, GPLR);

	return readl(gplr) & BIT(offset % 32);
}

static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	void __iomem *gpsr, *gpcr;

	if (value) {
		gpsr = gpio_reg(chip, offset, GPSR);
		writel(BIT(offset % 32), gpsr);
	} else {
		gpcr = gpio_reg(chip, offset, GPCR);
		writel(BIT(offset % 32), gpcr);
	}
}

static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	u32 value;
	unsigned long flags;

	if (lnw->pdev)
		pm_runtime_get(&lnw->pdev->dev);

	spin_lock_irqsave(&lnw->lock, flags);
	value = readl(gpdr);
	value &= ~BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&lnw->lock, flags);

	if (lnw->pdev)
		pm_runtime_put(&lnw->pdev->dev);

	return 0;
}

static int lnw_gpio_direction_output(struct gpio_chip *chip,
			unsigned offset, int value)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	unsigned long flags;

	lnw_gpio_set(chip, offset, value);

	if (lnw->pdev)
		pm_runtime_get(&lnw->pdev->dev);

	spin_lock_irqsave(&lnw->lock, flags);
	value = readl(gpdr);
	value |= BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&lnw->lock, flags);

	if (lnw->pdev)
		pm_runtime_put(&lnw->pdev->dev);

	return 0;
}

static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct lnw_gpio *lnw = to_lnw_priv(chip);
	return irq_create_mapping(lnw->domain, offset);
}

static int lnw_irq_type(struct irq_data *d, unsigned type)
{
	struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
	u32 gpio = irqd_to_hwirq(d);
	unsigned long flags;
	u32 value;
	void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
	void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);

	if (gpio >= lnw->chip.ngpio)
		return -EINVAL;

	if (lnw->pdev)
		pm_runtime_get(&lnw->pdev->dev);

	spin_lock_irqsave(&lnw->lock, flags);
	if (type & IRQ_TYPE_EDGE_RISING)
		value = readl(grer) | BIT(gpio % 32);
	else
		value = readl(grer) & (~BIT(gpio % 32));
	writel(value, grer);

	if (type & IRQ_TYPE_EDGE_FALLING)
		value = readl(gfer) | BIT(gpio % 32);
	else
		value = readl(gfer) & (~BIT(gpio % 32));
	writel(value, gfer);
	spin_unlock_irqrestore(&lnw->lock, flags);

	if (lnw->pdev)
		pm_runtime_put(&lnw->pdev->dev);

	return 0;
}

static void lnw_irq_unmask(struct irq_data *d)
{
}

static void lnw_irq_mask(struct irq_data *d)
{
}

static struct irq_chip lnw_irqchip = {
	.name		= "LNW-GPIO",
	.irq_mask	= lnw_irq_mask,
	.irq_unmask	= lnw_irq_unmask,
	.irq_set_type	= lnw_irq_type,
};

static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = {   /* pin number */
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), .driver_data = 96 },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), .driver_data = 96 },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);

static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, gpio, mask;
	unsigned long pending;
	void __iomem *gedr;

	/* check GPIO controller to check which pin triggered the interrupt */
	for (base = 0; base < lnw->chip.ngpio; base += 32) {
		gedr = gpio_reg(&lnw->chip, base, GEDR);
		while ((pending = readl(gedr))) {
			gpio = __ffs(pending);
			mask = BIT(gpio);
			/* Clear before handling so we can't lose an edge */
			writel(mask, gedr);
			generic_handle_irq(irq_find_mapping(lnw->domain,
							    base + gpio));
		}
	}

	chip->irq_eoi(data);
}

static void lnw_irq_init_hw(struct lnw_gpio *lnw)
{
	void __iomem *reg;
	unsigned base;

	for (base = 0; base < lnw->chip.ngpio; base += 32) {
		/* Clear the rising-edge detect register */
		reg = gpio_reg(&lnw->chip, base, GRER);
		writel(0, reg);
		/* Clear the falling-edge detect register */
		reg = gpio_reg(&lnw->chip, base, GFER);
		writel(0, reg);
		/* Clear the edge detect status register */
		reg = gpio_reg(&lnw->chip, base, GEDR);
		writel(~0, reg);
	}
}

static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
			    irq_hw_number_t hw)
{
	struct lnw_gpio *lnw = d->host_data;

	irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
				      "demux");
	irq_set_chip_data(virq, lnw);
	irq_set_irq_type(virq, IRQ_TYPE_NONE);

	return 0;
}

static const struct irq_domain_ops lnw_gpio_irq_ops = {
	.map = lnw_gpio_irq_map,
	.xlate = irq_domain_xlate_twocell,
};

static int lnw_gpio_runtime_idle(struct device *dev)
{
	int err = pm_schedule_suspend(dev, 500);

	if (!err)
		return 0;

	return -EBUSY;
}

static const struct dev_pm_ops lnw_gpio_pm_ops = {
	SET_RUNTIME_PM_OPS(NULL, NULL, lnw_gpio_runtime_idle)
};

static int lnw_gpio_probe(struct pci_dev *pdev,
			  const struct pci_device_id *id)
{
	void __iomem *base;
	struct lnw_gpio *lnw;
	u32 gpio_base;
	u32 irq_base;
	int retval;
	int ngpio = id->driver_data;

	retval = pcim_enable_device(pdev);
	if (retval)
		return retval;

	retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
	if (retval) {
		dev_err(&pdev->dev, "I/O memory mapping error\n");
		return retval;
	}

	base = pcim_iomap_table(pdev)[1];

	irq_base = readl(base);
	gpio_base = readl(sizeof(u32) + base);

	/* release the IO mapping, since we already get the info from bar1 */
	pcim_iounmap_regions(pdev, 1 << 1);

	lnw = devm_kzalloc(&pdev->dev, sizeof(*lnw), GFP_KERNEL);
	if (!lnw) {
		dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
		return -ENOMEM;
	}

	lnw->reg_base = pcim_iomap_table(pdev)[0];
	lnw->chip.label = dev_name(&pdev->dev);
	lnw->chip.request = lnw_gpio_request;
	lnw->chip.direction_input = lnw_gpio_direction_input;
	lnw->chip.direction_output = lnw_gpio_direction_output;
	lnw->chip.get = lnw_gpio_get;
	lnw->chip.set = lnw_gpio_set;
	lnw->chip.to_irq = lnw_gpio_to_irq;
	lnw->chip.base = gpio_base;
	lnw->chip.ngpio = ngpio;
	lnw->chip.can_sleep = 0;
	lnw->pdev = pdev;

	spin_lock_init(&lnw->lock);

	lnw->domain = irq_domain_add_simple(pdev->dev.of_node, ngpio, irq_base,
					    &lnw_gpio_irq_ops, lnw);
	if (!lnw->domain)
		return -ENOMEM;

	pci_set_drvdata(pdev, lnw);
	retval = gpiochip_add(&lnw->chip);
	if (retval) {
		dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
		return retval;
	}

	lnw_irq_init_hw(lnw);

	irq_set_handler_data(pdev->irq, lnw);
	irq_set_chained_handler(pdev->irq, lnw_irq_handler);

	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_allow(&pdev->dev);

	return 0;
}

static struct pci_driver lnw_gpio_driver = {
	.name		= "langwell_gpio",
	.id_table	= lnw_gpio_ids,
	.probe		= lnw_gpio_probe,
	.driver		= {
		.pm	= &lnw_gpio_pm_ops,
	},
};


static int wp_gpio_probe(struct platform_device *pdev)
{
	struct lnw_gpio *lnw;
	struct gpio_chip *gc;
	struct resource *rc;
	int retval;

	lnw = devm_kzalloc(&pdev->dev, sizeof(struct lnw_gpio), GFP_KERNEL);
	if (!lnw) {
		dev_err(&pdev->dev,
			"can't allocate whitneypoint_gpio chip data\n");
		return -ENOMEM;
	}

	rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	lnw->reg_base = devm_ioremap_resource(&pdev->dev, rc);
	if (IS_ERR(lnw->reg_base))
		return PTR_ERR(lnw->reg_base);

	spin_lock_init(&lnw->lock);
	gc = &lnw->chip;
	gc->label = dev_name(&pdev->dev);
	gc->owner = THIS_MODULE;
	gc->direction_input = lnw_gpio_direction_input;
	gc->direction_output = lnw_gpio_direction_output;
	gc->get = lnw_gpio_get;
	gc->set = lnw_gpio_set;
	gc->to_irq = NULL;
	gc->base = 0;
	gc->ngpio = 64;
	gc->can_sleep = 0;
	retval = gpiochip_add(gc);
	if (retval) {
		dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
								retval);
		return retval;
	}
	platform_set_drvdata(pdev, lnw);
	return 0;
}

static int wp_gpio_remove(struct platform_device *pdev)
{
	struct lnw_gpio *lnw = platform_get_drvdata(pdev);
	int err;
	err = gpiochip_remove(&lnw->chip);
	if (err)
		dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
	return 0;
}

static struct platform_driver wp_gpio_driver = {
	.probe		= wp_gpio_probe,
	.remove		= wp_gpio_remove,
	.driver		= {
		.name	= "wp_gpio",
		.owner	= THIS_MODULE,
	},
};

static int __init lnw_gpio_init(void)
{
	int ret;
	ret =  pci_register_driver(&lnw_gpio_driver);
	if (ret < 0)
		return ret;
	ret = platform_driver_register(&wp_gpio_driver);
	if (ret < 0)
		pci_unregister_driver(&lnw_gpio_driver);
	return ret;
}

device_initcall(lnw_gpio_init);
Commit	Line	Data
c103de24 GL	1	/*
	2	* Moorestown platform Langwell chip GPIO driver
	3	*
8bf02617 AD	4	* Copyright (c) 2008 - 2009, Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*/
	19
	20	/* Supports:
	21	* Moorestown platform Langwell chip.
8081c84c	22	* Medfield platform Penwell chip.
72b4379e	23	* Whitney point.
8bf02617 AD	24	*/
	25
	26	#include <linux/module.h>
	27	#include <linux/pci.h>
72b4379e	28	#include <linux/platform_device.h>
8bf02617 AD	29	#include <linux/kernel.h>
	30	#include <linux/delay.h>
	31	#include <linux/stddef.h>
	32	#include <linux/interrupt.h>
	33	#include <linux/init.h>
	34	#include <linux/irq.h>
	35	#include <linux/io.h>
	36	#include <linux/gpio.h>
5a0e3ad6	37	#include <linux/slab.h>
7812803a	38	#include <linux/pm_runtime.h>
465f2bd4	39	#include <linux/irqdomain.h>
8bf02617	40
8081c84c AD	41	/*
	42	* Langwell chip has 64 pins and thus there are 2 32bit registers to control
	43	* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
	44	* registers to control them, so we only define the order here instead of a
	45	* structure, to get a bit offset for a pin (use GPDR as an example):
	46	*
	47	* nreg = ngpio / 32;
	48	* reg = offset / 32;
	49	* bit = offset % 32;
	50	* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
	51	*
	52	* so the bit of reg_addr is to control pin offset's GPDR feature
	53	*/
	54
	55	enum GPIO_REG {
	56	GPLR = 0, /* pin level read-only */
	57	GPDR, /* pin direction */
	58	GPSR, /* pin set */
	59	GPCR, /* pin clear */
	60	GRER, /* rising edge detect */
	61	GFER, /* falling edge detect */
	62	GEDR, /* edge detect result */
8c0f7b10	63	GAFR, /* alt function */
8bf02617 AD	64	};
	65
	66	struct lnw_gpio {
	67	struct gpio_chip chip;
64c8cbc1	68	void __iomem *reg_base;
8bf02617	69	spinlock_t lock;
7812803a	70	struct pci_dev *pdev;
465f2bd4	71	struct irq_domain *domain;
8bf02617 AD	72	};
8bf02617 AD	73
46ebfbc3 DC	74	#define to_lnw_priv(chip) container_of(chip, struct lnw_gpio, chip)
46ebfbc3 DC	75
8081c84c AD	76	static void __iomem gpio_reg(struct gpio_chip chip, unsigned offset,
8081c84c AD	77	enum GPIO_REG reg_type)
8bf02617	78	{
46ebfbc3	79	struct lnw_gpio *lnw = to_lnw_priv(chip);
8081c84c	80	unsigned nreg = chip->ngpio / 32;
8bf02617	81	u8 reg = offset / 32;
8081c84c AD	82	void __iomem *ptr;
	83
	84	ptr = (void __iomem )(lnw->reg_base + reg_type nreg * 4 + reg * 4);
	85	return ptr;
	86	}
	87
8c0f7b10 AH	88	static void __iomem gpio_reg_2bit(struct gpio_chip chip, unsigned offset,
	89	enum GPIO_REG reg_type)
	90	{
46ebfbc3	91	struct lnw_gpio *lnw = to_lnw_priv(chip);
8c0f7b10 AH	92	unsigned nreg = chip->ngpio / 32;
	93	u8 reg = offset / 16;
	94	void __iomem *ptr;
	95
	96	ptr = (void __iomem )(lnw->reg_base + reg_type nreg * 4 + reg * 4);
	97	return ptr;
	98	}
	99
	100	static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
	101	{
	102	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	103	u32 value = readl(gafr);
	104	int shift = (offset % 16) << 1, af = (value >> shift) & 3;
	105
	106	if (af) {
	107	value &= ~(3 << shift);
	108	writel(value, gafr);
	109	}
	110	return 0;
	111	}
	112
8081c84c AD	113	static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
	114	{
	115	void __iomem *gplr = gpio_reg(chip, offset, GPLR);
8bf02617	116
8bf02617 AD	117	return readl(gplr) & BIT(offset % 32);
	118	}
	119
	120	static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	121	{
8bf02617 AD	122	void __iomem gpsr, gpcr;
	123
	124	if (value) {
8081c84c	125	gpsr = gpio_reg(chip, offset, GPSR);
8bf02617 AD	126	writel(BIT(offset % 32), gpsr);
8bf02617 AD	127	} else {
8081c84c	128	gpcr = gpio_reg(chip, offset, GPCR);
8bf02617 AD	129	writel(BIT(offset % 32), gpcr);
	130	}
	131	}
	132
	133	static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	134	{
46ebfbc3	135	struct lnw_gpio *lnw = to_lnw_priv(chip);
8081c84c	136	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617 AD	137	u32 value;
8bf02617 AD	138	unsigned long flags;
8bf02617	139
7812803a KCA	140	if (lnw->pdev)
	141	pm_runtime_get(&lnw->pdev->dev);
	142
8bf02617 AD	143	spin_lock_irqsave(&lnw->lock, flags);
	144	value = readl(gpdr);
	145	value &= ~BIT(offset % 32);
	146	writel(value, gpdr);
	147	spin_unlock_irqrestore(&lnw->lock, flags);
7812803a KCA	148
	149	if (lnw->pdev)
	150	pm_runtime_put(&lnw->pdev->dev);
	151
8bf02617 AD	152	return 0;
	153	}
	154
	155	static int lnw_gpio_direction_output(struct gpio_chip *chip,
	156	unsigned offset, int value)
	157	{
46ebfbc3	158	struct lnw_gpio *lnw = to_lnw_priv(chip);
8081c84c	159	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617	160	unsigned long flags;
8bf02617 AD	161
8bf02617 AD	162	lnw_gpio_set(chip, offset, value);
7812803a KCA	163
	164	if (lnw->pdev)
	165	pm_runtime_get(&lnw->pdev->dev);
	166
8bf02617 AD	167	spin_lock_irqsave(&lnw->lock, flags);
8bf02617 AD	168	value = readl(gpdr);
6eab04a8	169	value \|= BIT(offset % 32);
8bf02617 AD	170	writel(value, gpdr);
8bf02617 AD	171	spin_unlock_irqrestore(&lnw->lock, flags);
7812803a KCA	172
	173	if (lnw->pdev)
	174	pm_runtime_put(&lnw->pdev->dev);
	175
8bf02617 AD	176	return 0;
	177	}
	178
	179	static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	180	{
46ebfbc3	181	struct lnw_gpio *lnw = to_lnw_priv(chip);
465f2bd4	182	return irq_create_mapping(lnw->domain, offset);
8bf02617 AD	183	}
8bf02617 AD	184
5ffd72c6	185	static int lnw_irq_type(struct irq_data *d, unsigned type)
8bf02617	186	{
5ffd72c6	187	struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
465f2bd4	188	u32 gpio = irqd_to_hwirq(d);
8bf02617 AD	189	unsigned long flags;
8bf02617 AD	190	u32 value;
8081c84c AD	191	void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
8081c84c AD	192	void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
8bf02617	193
4efec627	194	if (gpio >= lnw->chip.ngpio)
8bf02617	195	return -EINVAL;
7812803a KCA	196
	197	if (lnw->pdev)
	198	pm_runtime_get(&lnw->pdev->dev);
	199
8bf02617 AD	200	spin_lock_irqsave(&lnw->lock, flags);
	201	if (type & IRQ_TYPE_EDGE_RISING)
	202	value = readl(grer) \| BIT(gpio % 32);
	203	else
	204	value = readl(grer) & (~BIT(gpio % 32));
	205	writel(value, grer);
	206
	207	if (type & IRQ_TYPE_EDGE_FALLING)
	208	value = readl(gfer) \| BIT(gpio % 32);
	209	else
	210	value = readl(gfer) & (~BIT(gpio % 32));
	211	writel(value, gfer);
	212	spin_unlock_irqrestore(&lnw->lock, flags);
	213
7812803a KCA	214	if (lnw->pdev)
	215	pm_runtime_put(&lnw->pdev->dev);
	216
8bf02617	217	return 0;
fd0574cb	218	}
8bf02617	219
5ffd72c6	220	static void lnw_irq_unmask(struct irq_data *d)
8bf02617	221	{
fd0574cb	222	}
8bf02617	223
5ffd72c6	224	static void lnw_irq_mask(struct irq_data *d)
8bf02617	225	{
fd0574cb	226	}
8bf02617 AD	227
	228	static struct irq_chip lnw_irqchip = {
	229	.name = "LNW-GPIO",
5ffd72c6 LB	230	.irq_mask = lnw_irq_mask,
	231	.irq_unmask = lnw_irq_unmask,
	232	.irq_set_type = lnw_irq_type,
8bf02617 AD	233	};
8bf02617 AD	234
8081c84c AD	235	static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
	236	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
	237	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
	238	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
936cb1b1 DC	239	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), .driver_data = 96 },
936cb1b1 DC	240	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), .driver_data = 96 },
8bf02617 AD	241	{ 0, }
	242	};
	243	MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
	244
	245	static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
	246	{
20e2aa91 TG	247	struct irq_data *data = irq_desc_get_irq_data(desc);
	248	struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
	249	struct irq_chip *chip = irq_data_get_irq_chip(data);
84bead6c	250	u32 base, gpio, mask;
732063b9	251	unsigned long pending;
8bf02617	252	void __iomem *gedr;
8bf02617 AD	253
8bf02617 AD	254	/* check GPIO controller to check which pin triggered the interrupt */
8081c84c AD	255	for (base = 0; base < lnw->chip.ngpio; base += 32) {
8081c84c AD	256	gedr = gpio_reg(&lnw->chip, base, GEDR);
c8f925b6	257	while ((pending = readl(gedr))) {
2345b20f	258	gpio = __ffs(pending);
84bead6c	259	mask = BIT(gpio);
84bead6c TG	260	/* Clear before handling so we can't lose an edge */
84bead6c TG	261	writel(mask, gedr);
465f2bd4 MW	262	generic_handle_irq(irq_find_mapping(lnw->domain,
465f2bd4 MW	263	base + gpio));
732063b9	264	}
8bf02617	265	}
0766d20f	266
20e2aa91	267	chip->irq_eoi(data);
8bf02617 AD	268	}
8bf02617 AD	269
f5f93117 MW	270	static void lnw_irq_init_hw(struct lnw_gpio *lnw)
	271	{
	272	void __iomem *reg;
	273	unsigned base;
	274
	275	for (base = 0; base < lnw->chip.ngpio; base += 32) {
	276	/* Clear the rising-edge detect register */
	277	reg = gpio_reg(&lnw->chip, base, GRER);
	278	writel(0, reg);
	279	/* Clear the falling-edge detect register */
	280	reg = gpio_reg(&lnw->chip, base, GFER);
	281	writel(0, reg);
	282	/* Clear the edge detect status register */
	283	reg = gpio_reg(&lnw->chip, base, GEDR);
	284	writel(~0, reg);
	285	}
	286	}
	287
465f2bd4 MW	288	static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
	289	irq_hw_number_t hw)
	290	{
	291	struct lnw_gpio *lnw = d->host_data;
	292
	293	irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
	294	"demux");
	295	irq_set_chip_data(virq, lnw);
	296	irq_set_irq_type(virq, IRQ_TYPE_NONE);
	297
	298	return 0;
	299	}
	300
	301	static const struct irq_domain_ops lnw_gpio_irq_ops = {
	302	.map = lnw_gpio_irq_map,
	303	.xlate = irq_domain_xlate_twocell,
	304	};
	305
7812803a KCA	306	static int lnw_gpio_runtime_idle(struct device *dev)
	307	{
	308	int err = pm_schedule_suspend(dev, 500);
	309
	310	if (!err)
	311	return 0;
	312
	313	return -EBUSY;
	314	}
	315
7812803a	316	static const struct dev_pm_ops lnw_gpio_pm_ops = {
46ebfbc3	317	SET_RUNTIME_PM_OPS(NULL, NULL, lnw_gpio_runtime_idle)
7812803a KCA	318	};
7812803a KCA	319
3836309d	320	static int lnw_gpio_probe(struct pci_dev *pdev,
64c8cbc1	321	const struct pci_device_id *id)
8bf02617	322	{
64c8cbc1	323	void __iomem *base;
8bf02617	324	struct lnw_gpio *lnw;
8bf02617	325	u32 gpio_base;
2519f9ab	326	u32 irq_base;
d6a2b7ba	327	int retval;
b3e35af2	328	int ngpio = id->driver_data;
8bf02617	329
786e07ec	330	retval = pcim_enable_device(pdev);
8bf02617	331	if (retval)
8302c741	332	return retval;
8bf02617	333
786e07ec	334	retval = pcim_iomap_regions(pdev, 1 << 0 \| 1 << 1, pci_name(pdev));
8bf02617	335	if (retval) {
786e07ec AS	336	dev_err(&pdev->dev, "I/O memory mapping error\n");
786e07ec AS	337	return retval;
8bf02617	338	}
64c8cbc1	339
786e07ec AS	340	base = pcim_iomap_table(pdev)[1];
786e07ec AS	341
64c8cbc1 AS	342	irq_base = readl(base);
	343	gpio_base = readl(sizeof(u32) + base);
	344
8bf02617	345	/* release the IO mapping, since we already get the info from bar1 */
786e07ec	346	pcim_iounmap_regions(pdev, 1 << 1);
8bf02617	347
46ebfbc3	348	lnw = devm_kzalloc(&pdev->dev, sizeof(*lnw), GFP_KERNEL);
8bf02617 AD	349	if (!lnw) {
8bf02617 AD	350	dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
786e07ec	351	return -ENOMEM;
8bf02617	352	}
b3e35af2	353
786e07ec	354	lnw->reg_base = pcim_iomap_table(pdev)[0];
8bf02617	355	lnw->chip.label = dev_name(&pdev->dev);
8c0f7b10	356	lnw->chip.request = lnw_gpio_request;
8bf02617 AD	357	lnw->chip.direction_input = lnw_gpio_direction_input;
	358	lnw->chip.direction_output = lnw_gpio_direction_output;
	359	lnw->chip.get = lnw_gpio_get;
	360	lnw->chip.set = lnw_gpio_set;
	361	lnw->chip.to_irq = lnw_gpio_to_irq;
	362	lnw->chip.base = gpio_base;
b3e35af2	363	lnw->chip.ngpio = ngpio;
8bf02617	364	lnw->chip.can_sleep = 0;
7812803a	365	lnw->pdev = pdev;
2519f9ab	366
aeb168f7 AS	367	spin_lock_init(&lnw->lock);
aeb168f7 AS	368
2519f9ab DC	369	lnw->domain = irq_domain_add_simple(pdev->dev.of_node, ngpio, irq_base,
2519f9ab DC	370	&lnw_gpio_irq_ops, lnw);
786e07ec AS	371	if (!lnw->domain)
786e07ec AS	372	return -ENOMEM;
2519f9ab	373
8bf02617 AD	374	pci_set_drvdata(pdev, lnw);
	375	retval = gpiochip_add(&lnw->chip);
	376	if (retval) {
	377	dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
786e07ec	378	return retval;
8bf02617	379	}
f5f93117 MW	380
	381	lnw_irq_init_hw(lnw);
	382
674db906 TG	383	irq_set_handler_data(pdev->irq, lnw);
674db906 TG	384	irq_set_chained_handler(pdev->irq, lnw_irq_handler);
8bf02617	385
7812803a KCA	386	pm_runtime_put_noidle(&pdev->dev);
	387	pm_runtime_allow(&pdev->dev);
	388
8302c741	389	return 0;
8bf02617 AD	390	}
	391
	392	static struct pci_driver lnw_gpio_driver = {
	393	.name = "langwell_gpio",
	394	.id_table = lnw_gpio_ids,
	395	.probe = lnw_gpio_probe,
7812803a KCA	396	.driver = {
	397	.pm = &lnw_gpio_pm_ops,
	398	},
8bf02617 AD	399	};
8bf02617 AD	400
72b4379e	401
3836309d	402	static int wp_gpio_probe(struct platform_device *pdev)
72b4379e AC	403	{
	404	struct lnw_gpio *lnw;
	405	struct gpio_chip *gc;
	406	struct resource *rc;
786e07ec	407	int retval;
72b4379e	408
786e07ec	409	lnw = devm_kzalloc(&pdev->dev, sizeof(struct lnw_gpio), GFP_KERNEL);
72b4379e AC	410	if (!lnw) {
	411	dev_err(&pdev->dev,
	412	"can't allocate whitneypoint_gpio chip data\n");
	413	return -ENOMEM;
	414	}
786e07ec AS	415
	416	rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	417	lnw->reg_base = devm_ioremap_resource(&pdev->dev, rc);
	418	if (IS_ERR(lnw->reg_base))
	419	return PTR_ERR(lnw->reg_base);
	420
72b4379e AC	421	spin_lock_init(&lnw->lock);
	422	gc = &lnw->chip;
	423	gc->label = dev_name(&pdev->dev);
	424	gc->owner = THIS_MODULE;
	425	gc->direction_input = lnw_gpio_direction_input;
	426	gc->direction_output = lnw_gpio_direction_output;
	427	gc->get = lnw_gpio_get;
	428	gc->set = lnw_gpio_set;
	429	gc->to_irq = NULL;
	430	gc->base = 0;
	431	gc->ngpio = 64;
	432	gc->can_sleep = 0;
	433	retval = gpiochip_add(gc);
	434	if (retval) {
	435	dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
	436	retval);
786e07ec	437	return retval;
72b4379e AC	438	}
	439	platform_set_drvdata(pdev, lnw);
	440	return 0;
72b4379e AC	441	}
72b4379e AC	442
206210ce	443	static int wp_gpio_remove(struct platform_device *pdev)
72b4379e AC	444	{
	445	struct lnw_gpio *lnw = platform_get_drvdata(pdev);
	446	int err;
	447	err = gpiochip_remove(&lnw->chip);
	448	if (err)
	449	dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
72b4379e AC	450	return 0;
	451	}
	452
	453	static struct platform_driver wp_gpio_driver = {
	454	.probe = wp_gpio_probe,
8283c4ff	455	.remove = wp_gpio_remove,
72b4379e AC	456	.driver = {
	457	.name = "wp_gpio",
	458	.owner = THIS_MODULE,
	459	},
	460	};
	461
8bf02617 AD	462	static int __init lnw_gpio_init(void)
8bf02617 AD	463	{
72b4379e AC	464	int ret;
	465	ret = pci_register_driver(&lnw_gpio_driver);
	466	if (ret < 0)
	467	return ret;
	468	ret = platform_driver_register(&wp_gpio_driver);
	469	if (ret < 0)
	470	pci_unregister_driver(&lnw_gpio_driver);
	471	return ret;
8bf02617 AD	472	}
	473
	474	device_initcall(lnw_gpio_init);