[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-lpc32xx.c

/*
 * GPIO driver for LPC32xx SoC
 *
 * Author: Kevin Wells <kevin.wells@nxp.com>
 *
 * Copyright (C) 2010 NXP Semiconductors
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/module.h>

#include <mach/hardware.h>
#include <mach/platform.h>

#define LPC32XX_GPIO_P3_INP_STATE		_GPREG(0x000)
#define LPC32XX_GPIO_P3_OUTP_SET		_GPREG(0x004)
#define LPC32XX_GPIO_P3_OUTP_CLR		_GPREG(0x008)
#define LPC32XX_GPIO_P3_OUTP_STATE		_GPREG(0x00C)
#define LPC32XX_GPIO_P2_DIR_SET			_GPREG(0x010)
#define LPC32XX_GPIO_P2_DIR_CLR			_GPREG(0x014)
#define LPC32XX_GPIO_P2_DIR_STATE		_GPREG(0x018)
#define LPC32XX_GPIO_P2_INP_STATE		_GPREG(0x01C)
#define LPC32XX_GPIO_P2_OUTP_SET		_GPREG(0x020)
#define LPC32XX_GPIO_P2_OUTP_CLR		_GPREG(0x024)
#define LPC32XX_GPIO_P2_MUX_SET			_GPREG(0x028)
#define LPC32XX_GPIO_P2_MUX_CLR			_GPREG(0x02C)
#define LPC32XX_GPIO_P2_MUX_STATE		_GPREG(0x030)
#define LPC32XX_GPIO_P0_INP_STATE		_GPREG(0x040)
#define LPC32XX_GPIO_P0_OUTP_SET		_GPREG(0x044)
#define LPC32XX_GPIO_P0_OUTP_CLR		_GPREG(0x048)
#define LPC32XX_GPIO_P0_OUTP_STATE		_GPREG(0x04C)
#define LPC32XX_GPIO_P0_DIR_SET			_GPREG(0x050)
#define LPC32XX_GPIO_P0_DIR_CLR			_GPREG(0x054)
#define LPC32XX_GPIO_P0_DIR_STATE		_GPREG(0x058)
#define LPC32XX_GPIO_P1_INP_STATE		_GPREG(0x060)
#define LPC32XX_GPIO_P1_OUTP_SET		_GPREG(0x064)
#define LPC32XX_GPIO_P1_OUTP_CLR		_GPREG(0x068)
#define LPC32XX_GPIO_P1_OUTP_STATE		_GPREG(0x06C)
#define LPC32XX_GPIO_P1_DIR_SET			_GPREG(0x070)
#define LPC32XX_GPIO_P1_DIR_CLR			_GPREG(0x074)
#define LPC32XX_GPIO_P1_DIR_STATE		_GPREG(0x078)

#define GPIO012_PIN_TO_BIT(x)			(1 << (x))
#define GPIO3_PIN_TO_BIT(x)			(1 << ((x) + 25))
#define GPO3_PIN_TO_BIT(x)			(1 << (x))
#define GPIO012_PIN_IN_SEL(x, y)		(((x) >> (y)) & 1)
#define GPIO3_PIN_IN_SHIFT(x)			((x) == 5 ? 24 : 10 + (x))
#define GPIO3_PIN_IN_SEL(x, y)			(((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
#define GPIO3_PIN5_IN_SEL(x)			(((x) >> 24) & 1)
#define GPI3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)
#define GPO3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)

#define LPC32XX_GPIO_P0_MAX	8
#define LPC32XX_GPIO_P1_MAX	24
#define LPC32XX_GPIO_P2_MAX	13
#define LPC32XX_GPIO_P3_MAX	6
#define LPC32XX_GPI_P3_MAX	29
#define LPC32XX_GPO_P3_MAX	24

#define LPC32XX_GPIO_P0_GRP	0
#define LPC32XX_GPIO_P1_GRP	(LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
#define LPC32XX_GPIO_P2_GRP	(LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
#define LPC32XX_GPIO_P3_GRP	(LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
#define LPC32XX_GPI_P3_GRP	(LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
#define LPC32XX_GPO_P3_GRP	(LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)

struct gpio_regs {
	void __iomem *inp_state;
	void __iomem *outp_state;
	void __iomem *outp_set;
	void __iomem *outp_clr;
	void __iomem *dir_set;
	void __iomem *dir_clr;
};

/*
 * GPIO names
 */
static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
	"p0.0", "p0.1", "p0.2", "p0.3",
	"p0.4", "p0.5", "p0.6", "p0.7"
};

static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
	"p1.0", "p1.1", "p1.2", "p1.3",
	"p1.4", "p1.5", "p1.6", "p1.7",
	"p1.8", "p1.9", "p1.10", "p1.11",
	"p1.12", "p1.13", "p1.14", "p1.15",
	"p1.16", "p1.17", "p1.18", "p1.19",
	"p1.20", "p1.21", "p1.22", "p1.23",
};

static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
	"p2.0", "p2.1", "p2.2", "p2.3",
	"p2.4", "p2.5", "p2.6", "p2.7",
	"p2.8", "p2.9", "p2.10", "p2.11",
	"p2.12"
};

static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
	"gpio00", "gpio01", "gpio02", "gpio03",
	"gpio04", "gpio05"
};

static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
	"gpi00", "gpi01", "gpi02", "gpi03",
	"gpi04", "gpi05", "gpi06", "gpi07",
	"gpi08", "gpi09",  NULL,    NULL,
	 NULL,    NULL,    NULL,   "gpi15",
	"gpi16", "gpi17", "gpi18", "gpi19",
	"gpi20", "gpi21", "gpi22", "gpi23",
	"gpi24", "gpi25", "gpi26", "gpi27",
	"gpi28"
};

static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
	"gpo00", "gpo01", "gpo02", "gpo03",
	"gpo04", "gpo05", "gpo06", "gpo07",
	"gpo08", "gpo09", "gpo10", "gpo11",
	"gpo12", "gpo13", "gpo14", "gpo15",
	"gpo16", "gpo17", "gpo18", "gpo19",
	"gpo20", "gpo21", "gpo22", "gpo23"
};

static struct gpio_regs gpio_grp_regs_p0 = {
	.inp_state	= LPC32XX_GPIO_P0_INP_STATE,
	.outp_set	= LPC32XX_GPIO_P0_OUTP_SET,
	.outp_clr	= LPC32XX_GPIO_P0_OUTP_CLR,
	.dir_set	= LPC32XX_GPIO_P0_DIR_SET,
	.dir_clr	= LPC32XX_GPIO_P0_DIR_CLR,
};

static struct gpio_regs gpio_grp_regs_p1 = {
	.inp_state	= LPC32XX_GPIO_P1_INP_STATE,
	.outp_set	= LPC32XX_GPIO_P1_OUTP_SET,
	.outp_clr	= LPC32XX_GPIO_P1_OUTP_CLR,
	.dir_set	= LPC32XX_GPIO_P1_DIR_SET,
	.dir_clr	= LPC32XX_GPIO_P1_DIR_CLR,
};

static struct gpio_regs gpio_grp_regs_p2 = {
	.inp_state	= LPC32XX_GPIO_P2_INP_STATE,
	.outp_set	= LPC32XX_GPIO_P2_OUTP_SET,
	.outp_clr	= LPC32XX_GPIO_P2_OUTP_CLR,
	.dir_set	= LPC32XX_GPIO_P2_DIR_SET,
	.dir_clr	= LPC32XX_GPIO_P2_DIR_CLR,
};

static struct gpio_regs gpio_grp_regs_p3 = {
	.inp_state	= LPC32XX_GPIO_P3_INP_STATE,
	.outp_state	= LPC32XX_GPIO_P3_OUTP_STATE,
	.outp_set	= LPC32XX_GPIO_P3_OUTP_SET,
	.outp_clr	= LPC32XX_GPIO_P3_OUTP_CLR,
	.dir_set	= LPC32XX_GPIO_P2_DIR_SET,
	.dir_clr	= LPC32XX_GPIO_P2_DIR_CLR,
};

struct lpc32xx_gpio_chip {
	struct gpio_chip	chip;
	struct gpio_regs	*gpio_grp;
};

static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
	unsigned pin, int input)
{
	if (input)
		__raw_writel(GPIO012_PIN_TO_BIT(pin),
			group->gpio_grp->dir_clr);
	else
		__raw_writel(GPIO012_PIN_TO_BIT(pin),
			group->gpio_grp->dir_set);
}

static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
	unsigned pin, int input)
{
	u32 u = GPIO3_PIN_TO_BIT(pin);

	if (input)
		__raw_writel(u, group->gpio_grp->dir_clr);
	else
		__raw_writel(u, group->gpio_grp->dir_set);
}

static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
	unsigned pin, int high)
{
	if (high)
		__raw_writel(GPIO012_PIN_TO_BIT(pin),
			group->gpio_grp->outp_set);
	else
		__raw_writel(GPIO012_PIN_TO_BIT(pin),
			group->gpio_grp->outp_clr);
}

static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
	unsigned pin, int high)
{
	u32 u = GPIO3_PIN_TO_BIT(pin);

	if (high)
		__raw_writel(u, group->gpio_grp->outp_set);
	else
		__raw_writel(u, group->gpio_grp->outp_clr);
}

static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
	unsigned pin, int high)
{
	if (high)
		__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
	else
		__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
}

static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
	unsigned pin)
{
	return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
		pin);
}

static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
	unsigned pin)
{
	int state = __raw_readl(group->gpio_grp->inp_state);

	/*
	 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
	 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
	 */
	return GPIO3_PIN_IN_SEL(state, pin);
}

static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
	unsigned pin)
{
	return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
}

static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
	unsigned pin)
{
	return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
}

/*
 * GPIO primitives.
 */
static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
	unsigned pin)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpio_dir_p012(group, pin, 1);

	return 0;
}

static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
	unsigned pin)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpio_dir_p3(group, pin, 1);

	return 0;
}

static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
	unsigned pin)
{
	return 0;
}

static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	return !!__get_gpio_state_p012(group, pin);
}

static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	return !!__get_gpio_state_p3(group, pin);
}

static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	return !!__get_gpi_state_p3(group, pin);
}

static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
	int value)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpio_level_p012(group, pin, value);
	__set_gpio_dir_p012(group, pin, 0);

	return 0;
}

static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
	int value)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpio_level_p3(group, pin, value);
	__set_gpio_dir_p3(group, pin, 0);

	return 0;
}

static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
	int value)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpo_level_p3(group, pin, value);
	return 0;
}

static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
	int value)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpio_level_p012(group, pin, value);
}

static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
	int value)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpio_level_p3(group, pin, value);
}

static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
	int value)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	__set_gpo_level_p3(group, pin, value);
}

static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
{
	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);

	return !!__get_gpo_state_p3(group, pin);
}

static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
{
	if (pin < chip->ngpio)
		return 0;

	return -EINVAL;
}

static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
{
	return -ENXIO;
}

static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
{
	return -ENXIO;
}

static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
{
	return -ENXIO;
}

static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
	{
		.chip = {
			.label			= "gpio_p0",
			.direction_input	= lpc32xx_gpio_dir_input_p012,
			.get			= lpc32xx_gpio_get_value_p012,
			.direction_output	= lpc32xx_gpio_dir_output_p012,
			.set			= lpc32xx_gpio_set_value_p012,
			.request		= lpc32xx_gpio_request,
			.to_irq			= lpc32xx_gpio_to_irq_p01,
			.base			= LPC32XX_GPIO_P0_GRP,
			.ngpio			= LPC32XX_GPIO_P0_MAX,
			.names			= gpio_p0_names,
			.can_sleep		= false,
		},
		.gpio_grp = &gpio_grp_regs_p0,
	},
	{
		.chip = {
			.label			= "gpio_p1",
			.direction_input	= lpc32xx_gpio_dir_input_p012,
			.get			= lpc32xx_gpio_get_value_p012,
			.direction_output	= lpc32xx_gpio_dir_output_p012,
			.set			= lpc32xx_gpio_set_value_p012,
			.request		= lpc32xx_gpio_request,
			.to_irq			= lpc32xx_gpio_to_irq_p01,
			.base			= LPC32XX_GPIO_P1_GRP,
			.ngpio			= LPC32XX_GPIO_P1_MAX,
			.names			= gpio_p1_names,
			.can_sleep		= false,
		},
		.gpio_grp = &gpio_grp_regs_p1,
	},
	{
		.chip = {
			.label			= "gpio_p2",
			.direction_input	= lpc32xx_gpio_dir_input_p012,
			.get			= lpc32xx_gpio_get_value_p012,
			.direction_output	= lpc32xx_gpio_dir_output_p012,
			.set			= lpc32xx_gpio_set_value_p012,
			.request		= lpc32xx_gpio_request,
			.base			= LPC32XX_GPIO_P2_GRP,
			.ngpio			= LPC32XX_GPIO_P2_MAX,
			.names			= gpio_p2_names,
			.can_sleep		= false,
		},
		.gpio_grp = &gpio_grp_regs_p2,
	},
	{
		.chip = {
			.label			= "gpio_p3",
			.direction_input	= lpc32xx_gpio_dir_input_p3,
			.get			= lpc32xx_gpio_get_value_p3,
			.direction_output	= lpc32xx_gpio_dir_output_p3,
			.set			= lpc32xx_gpio_set_value_p3,
			.request		= lpc32xx_gpio_request,
			.to_irq			= lpc32xx_gpio_to_irq_gpio_p3,
			.base			= LPC32XX_GPIO_P3_GRP,
			.ngpio			= LPC32XX_GPIO_P3_MAX,
			.names			= gpio_p3_names,
			.can_sleep		= false,
		},
		.gpio_grp = &gpio_grp_regs_p3,
	},
	{
		.chip = {
			.label			= "gpi_p3",
			.direction_input	= lpc32xx_gpio_dir_in_always,
			.get			= lpc32xx_gpi_get_value,
			.request		= lpc32xx_gpio_request,
			.to_irq			= lpc32xx_gpio_to_irq_gpi_p3,
			.base			= LPC32XX_GPI_P3_GRP,
			.ngpio			= LPC32XX_GPI_P3_MAX,
			.names			= gpi_p3_names,
			.can_sleep		= false,
		},
		.gpio_grp = &gpio_grp_regs_p3,
	},
	{
		.chip = {
			.label			= "gpo_p3",
			.direction_output	= lpc32xx_gpio_dir_out_always,
			.set			= lpc32xx_gpo_set_value,
			.get			= lpc32xx_gpo_get_value,
			.request		= lpc32xx_gpio_request,
			.base			= LPC32XX_GPO_P3_GRP,
			.ngpio			= LPC32XX_GPO_P3_MAX,
			.names			= gpo_p3_names,
			.can_sleep		= false,
		},
		.gpio_grp = &gpio_grp_regs_p3,
	},
};

static int lpc32xx_of_xlate(struct gpio_chip *gc,
			    const struct of_phandle_args *gpiospec, u32 *flags)
{
	/* Is this the correct bank? */
	u32 bank = gpiospec->args[0];
	if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) ||
	    (gc != &lpc32xx_gpiochip[bank].chip)))
		return -EINVAL;

	if (flags)
		*flags = gpiospec->args[2];
	return gpiospec->args[1];
}

static int lpc32xx_gpio_probe(struct platform_device *pdev)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
		if (pdev->dev.of_node) {
			lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
			lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
			lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
		}
		devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
				  &lpc32xx_gpiochip[i]);
	}

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id lpc32xx_gpio_of_match[] = {
	{ .compatible = "nxp,lpc3220-gpio", },
	{ },
};
#endif

static struct platform_driver lpc32xx_gpio_driver = {
	.driver		= {
		.name	= "lpc32xx-gpio",
		.of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
	},
	.probe		= lpc32xx_gpio_probe,
};

module_platform_driver(lpc32xx_gpio_driver);
Commit	Line	Data
c4a0208f	1	/*
da03d740	2	* GPIO driver for LPC32xx SoC
c4a0208f KW	3	*
	4	* Author: Kevin Wells <kevin.wells@nxp.com>
	5	*
	6	* Copyright (C) 2010 NXP Semiconductors
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/io.h>
	22	#include <linux/errno.h>
	23	#include <linux/gpio.h>
831cbd7a	24	#include <linux/of.h>
e92935e1 RS	25	#include <linux/of_gpio.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/module.h>
c4a0208f KW	28
	29	#include <mach/hardware.h>
	30	#include <mach/platform.h>
c4a0208f KW	31
	32	#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
	33	#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
	34	#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
	35	#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
	36	#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
	37	#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
	38	#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
	39	#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
	40	#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
	41	#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
	42	#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
	43	#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
	44	#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
	45	#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
	46	#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
	47	#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
	48	#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
	49	#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
	50	#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
	51	#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
	52	#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
	53	#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
	54	#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
	55	#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
	56	#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
	57	#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
	58	#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
	59
	60	#define GPIO012_PIN_TO_BIT(x) (1 << (x))
	61	#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
	62	#define GPO3_PIN_TO_BIT(x) (1 << (x))
	63	#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
	64	#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
8e5fb37b	65	#define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
c4a0208f KW	66	#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
c4a0208f KW	67	#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
46158aad	68	#define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
c4a0208f	69
14bf873e VZ	70	#define LPC32XX_GPIO_P0_MAX 8
	71	#define LPC32XX_GPIO_P1_MAX 24
	72	#define LPC32XX_GPIO_P2_MAX 13
	73	#define LPC32XX_GPIO_P3_MAX 6
	74	#define LPC32XX_GPI_P3_MAX 29
	75	#define LPC32XX_GPO_P3_MAX 24
	76
	77	#define LPC32XX_GPIO_P0_GRP 0
	78	#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
	79	#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
	80	#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
	81	#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
	82	#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
	83
c4a0208f KW	84	struct gpio_regs {
c4a0208f KW	85	void __iomem *inp_state;
46158aad	86	void __iomem *outp_state;
c4a0208f KW	87	void __iomem *outp_set;
	88	void __iomem *outp_clr;
	89	void __iomem *dir_set;
	90	void __iomem *dir_clr;
	91	};
	92
	93	/*
	94	* GPIO names
	95	*/
	96	static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
	97	"p0.0", "p0.1", "p0.2", "p0.3",
	98	"p0.4", "p0.5", "p0.6", "p0.7"
	99	};
	100
	101	static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
	102	"p1.0", "p1.1", "p1.2", "p1.3",
	103	"p1.4", "p1.5", "p1.6", "p1.7",
	104	"p1.8", "p1.9", "p1.10", "p1.11",
	105	"p1.12", "p1.13", "p1.14", "p1.15",
	106	"p1.16", "p1.17", "p1.18", "p1.19",
	107	"p1.20", "p1.21", "p1.22", "p1.23",
	108	};
	109
	110	static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
	111	"p2.0", "p2.1", "p2.2", "p2.3",
	112	"p2.4", "p2.5", "p2.6", "p2.7",
	113	"p2.8", "p2.9", "p2.10", "p2.11",
	114	"p2.12"
	115	};
	116
	117	static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
95120d5d	118	"gpio00", "gpio01", "gpio02", "gpio03",
c4a0208f KW	119	"gpio04", "gpio05"
	120	};
	121
	122	static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
	123	"gpi00", "gpi01", "gpi02", "gpi03",
	124	"gpi04", "gpi05", "gpi06", "gpi07",
	125	"gpi08", "gpi09", NULL, NULL,
	126	NULL, NULL, NULL, "gpi15",
	127	"gpi16", "gpi17", "gpi18", "gpi19",
	128	"gpi20", "gpi21", "gpi22", "gpi23",
71fde000 RS	129	"gpi24", "gpi25", "gpi26", "gpi27",
71fde000 RS	130	"gpi28"
c4a0208f KW	131	};
	132
	133	static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
	134	"gpo00", "gpo01", "gpo02", "gpo03",
	135	"gpo04", "gpo05", "gpo06", "gpo07",
	136	"gpo08", "gpo09", "gpo10", "gpo11",
	137	"gpo12", "gpo13", "gpo14", "gpo15",
	138	"gpo16", "gpo17", "gpo18", "gpo19",
	139	"gpo20", "gpo21", "gpo22", "gpo23"
	140	};
	141
	142	static struct gpio_regs gpio_grp_regs_p0 = {
	143	.inp_state = LPC32XX_GPIO_P0_INP_STATE,
	144	.outp_set = LPC32XX_GPIO_P0_OUTP_SET,
	145	.outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
	146	.dir_set = LPC32XX_GPIO_P0_DIR_SET,
	147	.dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
	148	};
	149
	150	static struct gpio_regs gpio_grp_regs_p1 = {
	151	.inp_state = LPC32XX_GPIO_P1_INP_STATE,
	152	.outp_set = LPC32XX_GPIO_P1_OUTP_SET,
	153	.outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
	154	.dir_set = LPC32XX_GPIO_P1_DIR_SET,
	155	.dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
	156	};
	157
	158	static struct gpio_regs gpio_grp_regs_p2 = {
	159	.inp_state = LPC32XX_GPIO_P2_INP_STATE,
	160	.outp_set = LPC32XX_GPIO_P2_OUTP_SET,
	161	.outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
	162	.dir_set = LPC32XX_GPIO_P2_DIR_SET,
	163	.dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
	164	};
	165
	166	static struct gpio_regs gpio_grp_regs_p3 = {
	167	.inp_state = LPC32XX_GPIO_P3_INP_STATE,
46158aad	168	.outp_state = LPC32XX_GPIO_P3_OUTP_STATE,
c4a0208f KW	169	.outp_set = LPC32XX_GPIO_P3_OUTP_SET,
	170	.outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
	171	.dir_set = LPC32XX_GPIO_P2_DIR_SET,
	172	.dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
	173	};
	174
	175	struct lpc32xx_gpio_chip {
	176	struct gpio_chip chip;
	177	struct gpio_regs *gpio_grp;
	178	};
	179
c4a0208f KW	180	static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
	181	unsigned pin, int input)
	182	{
	183	if (input)
	184	__raw_writel(GPIO012_PIN_TO_BIT(pin),
	185	group->gpio_grp->dir_clr);
	186	else
	187	__raw_writel(GPIO012_PIN_TO_BIT(pin),
	188	group->gpio_grp->dir_set);
	189	}
	190
	191	static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
	192	unsigned pin, int input)
	193	{
	194	u32 u = GPIO3_PIN_TO_BIT(pin);
	195
	196	if (input)
	197	__raw_writel(u, group->gpio_grp->dir_clr);
	198	else
	199	__raw_writel(u, group->gpio_grp->dir_set);
	200	}
	201
	202	static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
	203	unsigned pin, int high)
	204	{
	205	if (high)
	206	__raw_writel(GPIO012_PIN_TO_BIT(pin),
	207	group->gpio_grp->outp_set);
	208	else
	209	__raw_writel(GPIO012_PIN_TO_BIT(pin),
	210	group->gpio_grp->outp_clr);
	211	}
	212
	213	static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
	214	unsigned pin, int high)
	215	{
	216	u32 u = GPIO3_PIN_TO_BIT(pin);
	217
	218	if (high)
	219	__raw_writel(u, group->gpio_grp->outp_set);
	220	else
	221	__raw_writel(u, group->gpio_grp->outp_clr);
	222	}
	223
	224	static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
	225	unsigned pin, int high)
	226	{
	227	if (high)
	228	__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
	229	else
	230	__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
	231	}
	232
	233	static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
	234	unsigned pin)
	235	{
	236	return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
	237	pin);
	238	}
	239
	240	static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
	241	unsigned pin)
	242	{
	243	int state = __raw_readl(group->gpio_grp->inp_state);
244
245	/*
246	* P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
247	* to bits 10..14, while GPIOP3-5 is mapped to bit 24.
248	*/
249	return GPIO3_PIN_IN_SEL(state, pin);
250	}
251
252	static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
253	unsigned pin)
254	{
255	return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
256	}
257
46158aad RS	258	static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
	259	unsigned pin)
	260	{
	261	return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
	262	}
	263
c4a0208f	264	/*
7fd2bf3d	265	* GPIO primitives.
c4a0208f KW	266	*/
	267	static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
	268	unsigned pin)
	269	{
a9bc97e4	270	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f KW	271
	272	__set_gpio_dir_p012(group, pin, 1);
	273
	274	return 0;
	275	}
	276
	277	static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
	278	unsigned pin)
	279	{
a9bc97e4	280	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f KW	281
	282	__set_gpio_dir_p3(group, pin, 1);
	283
	284	return 0;
	285	}
	286
	287	static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
	288	unsigned pin)
	289	{
	290	return 0;
	291	}
	292
	293	static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
	294	{
a9bc97e4	295	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f	296
2e6d8456	297	return !!__get_gpio_state_p012(group, pin);
c4a0208f KW	298	}
	299
	300	static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
	301	{
a9bc97e4	302	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f	303
2e6d8456	304	return !!__get_gpio_state_p3(group, pin);
c4a0208f KW	305	}
	306
	307	static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
	308	{
a9bc97e4	309	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f	310
2e6d8456	311	return !!__get_gpi_state_p3(group, pin);
c4a0208f KW	312	}
	313
	314	static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
	315	int value)
	316	{
a9bc97e4	317	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f	318
b1268d37	319	__set_gpio_level_p012(group, pin, value);
c4a0208f KW	320	__set_gpio_dir_p012(group, pin, 0);
	321
	322	return 0;
	323	}
	324
	325	static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
	326	int value)
	327	{
a9bc97e4	328	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f	329
b1268d37	330	__set_gpio_level_p3(group, pin, value);
c4a0208f KW	331	__set_gpio_dir_p3(group, pin, 0);
	332
	333	return 0;
	334	}
	335
	336	static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
	337	int value)
	338	{
a9bc97e4	339	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
b1268d37 RS	340
b1268d37 RS	341	__set_gpo_level_p3(group, pin, value);
c4a0208f KW	342	return 0;
	343	}
	344
	345	static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
	346	int value)
	347	{
a9bc97e4	348	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f KW	349
	350	__set_gpio_level_p012(group, pin, value);
	351	}
	352
	353	static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
	354	int value)
	355	{
a9bc97e4	356	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f KW	357
	358	__set_gpio_level_p3(group, pin, value);
	359	}
	360
	361	static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
	362	int value)
	363	{
a9bc97e4	364	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
c4a0208f KW	365
	366	__set_gpo_level_p3(group, pin, value);
	367	}
	368
46158aad RS	369	static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
46158aad RS	370	{
a9bc97e4	371	struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
46158aad	372
2e6d8456	373	return !!__get_gpo_state_p3(group, pin);
46158aad RS	374	}
46158aad RS	375
c4a0208f KW	376	static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
	377	{
	378	if (pin < chip->ngpio)
	379	return 0;
	380
	381	return -EINVAL;
	382	}
	383
0bdfeddc RS	384	static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
0bdfeddc RS	385	{
320a6480	386	return -ENXIO;
0bdfeddc RS	387	}
0bdfeddc RS	388
0bdfeddc RS	389	static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
0bdfeddc RS	390	{
0bdfeddc RS	391	return -ENXIO;
	392	}
	393
0bdfeddc RS	394	static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
0bdfeddc RS	395	{
0bdfeddc RS	396	return -ENXIO;
	397	}
	398
c4a0208f KW	399	static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
	400	{
	401	.chip = {
	402	.label = "gpio_p0",
	403	.direction_input = lpc32xx_gpio_dir_input_p012,
	404	.get = lpc32xx_gpio_get_value_p012,
	405	.direction_output = lpc32xx_gpio_dir_output_p012,
	406	.set = lpc32xx_gpio_set_value_p012,
	407	.request = lpc32xx_gpio_request,
0bdfeddc	408	.to_irq = lpc32xx_gpio_to_irq_p01,
c4a0208f KW	409	.base = LPC32XX_GPIO_P0_GRP,
	410	.ngpio = LPC32XX_GPIO_P0_MAX,
	411	.names = gpio_p0_names,
9fb1f39e	412	.can_sleep = false,
c4a0208f KW	413	},
	414	.gpio_grp = &gpio_grp_regs_p0,
	415	},
	416	{
	417	.chip = {
	418	.label = "gpio_p1",
	419	.direction_input = lpc32xx_gpio_dir_input_p012,
	420	.get = lpc32xx_gpio_get_value_p012,
	421	.direction_output = lpc32xx_gpio_dir_output_p012,
	422	.set = lpc32xx_gpio_set_value_p012,
	423	.request = lpc32xx_gpio_request,
0bdfeddc	424	.to_irq = lpc32xx_gpio_to_irq_p01,
c4a0208f KW	425	.base = LPC32XX_GPIO_P1_GRP,
	426	.ngpio = LPC32XX_GPIO_P1_MAX,
	427	.names = gpio_p1_names,
9fb1f39e	428	.can_sleep = false,
c4a0208f KW	429	},
	430	.gpio_grp = &gpio_grp_regs_p1,
	431	},
	432	{
	433	.chip = {
	434	.label = "gpio_p2",
	435	.direction_input = lpc32xx_gpio_dir_input_p012,
	436	.get = lpc32xx_gpio_get_value_p012,
	437	.direction_output = lpc32xx_gpio_dir_output_p012,
	438	.set = lpc32xx_gpio_set_value_p012,
	439	.request = lpc32xx_gpio_request,
	440	.base = LPC32XX_GPIO_P2_GRP,
	441	.ngpio = LPC32XX_GPIO_P2_MAX,
	442	.names = gpio_p2_names,
9fb1f39e	443	.can_sleep = false,
c4a0208f KW	444	},
	445	.gpio_grp = &gpio_grp_regs_p2,
	446	},
	447	{
	448	.chip = {
	449	.label = "gpio_p3",
	450	.direction_input = lpc32xx_gpio_dir_input_p3,
	451	.get = lpc32xx_gpio_get_value_p3,
	452	.direction_output = lpc32xx_gpio_dir_output_p3,
	453	.set = lpc32xx_gpio_set_value_p3,
	454	.request = lpc32xx_gpio_request,
0bdfeddc	455	.to_irq = lpc32xx_gpio_to_irq_gpio_p3,
c4a0208f KW	456	.base = LPC32XX_GPIO_P3_GRP,
	457	.ngpio = LPC32XX_GPIO_P3_MAX,
	458	.names = gpio_p3_names,
9fb1f39e	459	.can_sleep = false,
c4a0208f KW	460	},
	461	.gpio_grp = &gpio_grp_regs_p3,
	462	},
	463	{
	464	.chip = {
	465	.label = "gpi_p3",
	466	.direction_input = lpc32xx_gpio_dir_in_always,
	467	.get = lpc32xx_gpi_get_value,
	468	.request = lpc32xx_gpio_request,
0bdfeddc	469	.to_irq = lpc32xx_gpio_to_irq_gpi_p3,
c4a0208f KW	470	.base = LPC32XX_GPI_P3_GRP,
	471	.ngpio = LPC32XX_GPI_P3_MAX,
	472	.names = gpi_p3_names,
9fb1f39e	473	.can_sleep = false,
c4a0208f KW	474	},
	475	.gpio_grp = &gpio_grp_regs_p3,
	476	},
	477	{
	478	.chip = {
	479	.label = "gpo_p3",
	480	.direction_output = lpc32xx_gpio_dir_out_always,
	481	.set = lpc32xx_gpo_set_value,
46158aad	482	.get = lpc32xx_gpo_get_value,
c4a0208f KW	483	.request = lpc32xx_gpio_request,
	484	.base = LPC32XX_GPO_P3_GRP,
	485	.ngpio = LPC32XX_GPO_P3_MAX,
	486	.names = gpo_p3_names,
9fb1f39e	487	.can_sleep = false,
c4a0208f KW	488	},
	489	.gpio_grp = &gpio_grp_regs_p3,
	490	},
	491	};
	492
e92935e1 RS	493	static int lpc32xx_of_xlate(struct gpio_chip *gc,
	494	const struct of_phandle_args gpiospec, u32 flags)
	495	{
	496	/* Is this the correct bank? */
	497	u32 bank = gpiospec->args[0];
fdc7a9f8	498	if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) \|\|
e92935e1 RS	499	(gc != &lpc32xx_gpiochip[bank].chip)))
	500	return -EINVAL;
	501
	502	if (flags)
	503	*flags = gpiospec->args[2];
	504	return gpiospec->args[1];
	505	}
	506
3836309d	507	static int lpc32xx_gpio_probe(struct platform_device *pdev)
c4a0208f KW	508	{
	509	int i;
	510
e92935e1 RS	511	for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
	512	if (pdev->dev.of_node) {
	513	lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
	514	lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
	515	lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
	516	}
69c0a0a5	517	devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
a9bc97e4	518	&lpc32xx_gpiochip[i]);
e92935e1 RS	519	}
	520
	521	return 0;
c4a0208f	522	}
e92935e1 RS	523
e92935e1 RS	524	#ifdef CONFIG_OF
e95c7c45	525	static const struct of_device_id lpc32xx_gpio_of_match[] = {
e92935e1 RS	526	{ .compatible = "nxp,lpc3220-gpio", },
	527	{ },
	528	};
	529	#endif
	530
	531	static struct platform_driver lpc32xx_gpio_driver = {
	532	.driver = {
	533	.name = "lpc32xx-gpio",
e92935e1 RS	534	.of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
	535	},
	536	.probe = lpc32xx_gpio_probe,
	537	};
	538
	539	module_platform_driver(lpc32xx_gpio_driver);