[mirror_ubuntu-hirsute-kernel.git] / drivers / gpio / gpio-mb86s7x.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *  linux/drivers/gpio/gpio-mb86s7x.c
 *
 *  Copyright (C) 2015 Fujitsu Semiconductor Limited
 *  Copyright (C) 2015 Linaro Ltd.
 */

#include <linux/acpi.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/of_device.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/slab.h>

#include "gpiolib.h"
#include "gpiolib-acpi.h"

/*
 * Only first 8bits of a register correspond to each pin,
 * so there are 4 registers for 32 pins.
 */
#define PDR(x)	(0x0 + x / 8 * 4)
#define DDR(x)	(0x10 + x / 8 * 4)
#define PFR(x)	(0x20 + x / 8 * 4)

#define OFFSET(x)	BIT((x) % 8)

struct mb86s70_gpio_chip {
	struct gpio_chip gc;
	void __iomem *base;
	struct clk *clk;
	spinlock_t lock;
};

static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio)
{
	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&gchip->lock, flags);

	val = readl(gchip->base + PFR(gpio));
	val &= ~OFFSET(gpio);
	writel(val, gchip->base + PFR(gpio));

	spin_unlock_irqrestore(&gchip->lock, flags);

	return 0;
}

static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio)
{
	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&gchip->lock, flags);

	val = readl(gchip->base + PFR(gpio));
	val |= OFFSET(gpio);
	writel(val, gchip->base + PFR(gpio));

	spin_unlock_irqrestore(&gchip->lock, flags);
}

static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
{
	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char val;

	spin_lock_irqsave(&gchip->lock, flags);

	val = readl(gchip->base + DDR(gpio));
	val &= ~OFFSET(gpio);
	writel(val, gchip->base + DDR(gpio));

	spin_unlock_irqrestore(&gchip->lock, flags);

	return 0;
}

static int mb86s70_gpio_direction_output(struct gpio_chip *gc,
					 unsigned gpio, int value)
{
	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char val;

	spin_lock_irqsave(&gchip->lock, flags);

	val = readl(gchip->base + PDR(gpio));
	if (value)
		val |= OFFSET(gpio);
	else
		val &= ~OFFSET(gpio);
	writel(val, gchip->base + PDR(gpio));

	val = readl(gchip->base + DDR(gpio));
	val |= OFFSET(gpio);
	writel(val, gchip->base + DDR(gpio));

	spin_unlock_irqrestore(&gchip->lock, flags);

	return 0;
}

static int mb86s70_gpio_get(struct gpio_chip *gc, unsigned gpio)
{
	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);

	return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio));
}

static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value)
{
	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char val;

	spin_lock_irqsave(&gchip->lock, flags);

	val = readl(gchip->base + PDR(gpio));
	if (value)
		val |= OFFSET(gpio);
	else
		val &= ~OFFSET(gpio);
	writel(val, gchip->base + PDR(gpio));

	spin_unlock_irqrestore(&gchip->lock, flags);
}

static int mb86s70_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
{
	int irq, index;

	for (index = 0;; index++) {
		irq = platform_get_irq(to_platform_device(gc->parent), index);
		if (irq < 0)
			return irq;
		if (irq == 0)
			break;
		if (irq_get_irq_data(irq)->hwirq == offset)
			return irq;
	}
	return -EINVAL;
}

static int mb86s70_gpio_probe(struct platform_device *pdev)
{
	struct mb86s70_gpio_chip *gchip;
	int ret;

	gchip = devm_kzalloc(&pdev->dev, sizeof(*gchip), GFP_KERNEL);
	if (gchip == NULL)
		return -ENOMEM;

	platform_set_drvdata(pdev, gchip);

	gchip->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(gchip->base))
		return PTR_ERR(gchip->base);

	gchip->clk = devm_clk_get_optional(&pdev->dev, NULL);
	if (IS_ERR(gchip->clk))
		return PTR_ERR(gchip->clk);

	ret = clk_prepare_enable(gchip->clk);
	if (ret)
		return ret;

	spin_lock_init(&gchip->lock);

	gchip->gc.direction_output = mb86s70_gpio_direction_output;
	gchip->gc.direction_input = mb86s70_gpio_direction_input;
	gchip->gc.request = mb86s70_gpio_request;
	gchip->gc.free = mb86s70_gpio_free;
	gchip->gc.get = mb86s70_gpio_get;
	gchip->gc.set = mb86s70_gpio_set;
	gchip->gc.to_irq = mb86s70_gpio_to_irq;
	gchip->gc.label = dev_name(&pdev->dev);
	gchip->gc.ngpio = 32;
	gchip->gc.owner = THIS_MODULE;
	gchip->gc.parent = &pdev->dev;
	gchip->gc.base = -1;

	ret = gpiochip_add_data(&gchip->gc, gchip);
	if (ret) {
		dev_err(&pdev->dev, "couldn't register gpio driver\n");
		clk_disable_unprepare(gchip->clk);
		return ret;
	}

	acpi_gpiochip_request_interrupts(&gchip->gc);

	return 0;
}

static int mb86s70_gpio_remove(struct platform_device *pdev)
{
	struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev);

	acpi_gpiochip_free_interrupts(&gchip->gc);
	gpiochip_remove(&gchip->gc);
	clk_disable_unprepare(gchip->clk);

	return 0;
}

static const struct of_device_id mb86s70_gpio_dt_ids[] = {
	{ .compatible = "fujitsu,mb86s70-gpio" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids);

#ifdef CONFIG_ACPI
static const struct acpi_device_id mb86s70_gpio_acpi_ids[] = {
	{ "SCX0007" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(acpi, mb86s70_gpio_acpi_ids);
#endif

static struct platform_driver mb86s70_gpio_driver = {
	.driver = {
		.name = "mb86s70-gpio",
		.of_match_table = mb86s70_gpio_dt_ids,
		.acpi_match_table = ACPI_PTR(mb86s70_gpio_acpi_ids),
	},
	.probe = mb86s70_gpio_probe,
	.remove = mb86s70_gpio_remove,
};
module_platform_driver(mb86s70_gpio_driver);

MODULE_DESCRIPTION("MB86S7x GPIO Driver");
MODULE_ALIAS("platform:mb86s70-gpio");
MODULE_LICENSE("GPL");
Commit	Line	Data
8e8e69d6	1	// SPDX-License-Identifier: GPL-2.0-only
0da094d8 JB	2	/*
	3	* linux/drivers/gpio/gpio-mb86s7x.c
	4	*
	5	* Copyright (C) 2015 Fujitsu Semiconductor Limited
	6	* Copyright (C) 2015 Linaro Ltd.
0da094d8 JB	7	*/
0da094d8 JB	8
f3d705d5	9	#include <linux/acpi.h>
0da094d8 JB	10	#include <linux/io.h>
	11	#include <linux/init.h>
	12	#include <linux/clk.h>
e1289dba	13	#include <linux/module.h>
0da094d8 JB	14	#include <linux/err.h>
	15	#include <linux/errno.h>
	16	#include <linux/ioport.h>
	17	#include <linux/of_device.h>
	18	#include <linux/gpio/driver.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/spinlock.h>
	21	#include <linux/slab.h>
	22
f3d705d5	23	#include "gpiolib.h"
77cb907a	24	#include "gpiolib-acpi.h"
f3d705d5	25
0da094d8 JB	26	/*
	27	* Only first 8bits of a register correspond to each pin,
	28	* so there are 4 registers for 32 pins.
	29	*/
	30	#define PDR(x) (0x0 + x / 8 * 4)
	31	#define DDR(x) (0x10 + x / 8 * 4)
	32	#define PFR(x) (0x20 + x / 8 * 4)
	33
	34	#define OFFSET(x) BIT((x) % 8)
	35
	36	struct mb86s70_gpio_chip {
	37	struct gpio_chip gc;
	38	void __iomem *base;
	39	struct clk *clk;
	40	spinlock_t lock;
	41	};
	42
0da094d8 JB	43	static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio)
0da094d8 JB	44	{
01f76b26	45	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
0da094d8 JB	46	unsigned long flags;
	47	u32 val;
	48
	49	spin_lock_irqsave(&gchip->lock, flags);
	50
	51	val = readl(gchip->base + PFR(gpio));
	52	val &= ~OFFSET(gpio);
	53	writel(val, gchip->base + PFR(gpio));
	54
	55	spin_unlock_irqrestore(&gchip->lock, flags);
	56
	57	return 0;
	58	}
	59
	60	static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio)
	61	{
01f76b26	62	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
0da094d8 JB	63	unsigned long flags;
	64	u32 val;
	65
	66	spin_lock_irqsave(&gchip->lock, flags);
	67
	68	val = readl(gchip->base + PFR(gpio));
	69	val \|= OFFSET(gpio);
	70	writel(val, gchip->base + PFR(gpio));
	71
	72	spin_unlock_irqrestore(&gchip->lock, flags);
	73	}
	74
	75	static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
	76	{
01f76b26	77	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
0da094d8 JB	78	unsigned long flags;
	79	unsigned char val;
	80
	81	spin_lock_irqsave(&gchip->lock, flags);
	82
	83	val = readl(gchip->base + DDR(gpio));
	84	val &= ~OFFSET(gpio);
	85	writel(val, gchip->base + DDR(gpio));
	86
	87	spin_unlock_irqrestore(&gchip->lock, flags);
	88
	89	return 0;
	90	}
	91
	92	static int mb86s70_gpio_direction_output(struct gpio_chip *gc,
	93	unsigned gpio, int value)
	94	{
01f76b26	95	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
0da094d8 JB	96	unsigned long flags;
	97	unsigned char val;
	98
	99	spin_lock_irqsave(&gchip->lock, flags);
	100
	101	val = readl(gchip->base + PDR(gpio));
	102	if (value)
	103	val \|= OFFSET(gpio);
	104	else
	105	val &= ~OFFSET(gpio);
	106	writel(val, gchip->base + PDR(gpio));
	107
	108	val = readl(gchip->base + DDR(gpio));
	109	val \|= OFFSET(gpio);
	110	writel(val, gchip->base + DDR(gpio));
	111
	112	spin_unlock_irqrestore(&gchip->lock, flags);
	113
	114	return 0;
	115	}
	116
	117	static int mb86s70_gpio_get(struct gpio_chip *gc, unsigned gpio)
	118	{
01f76b26	119	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
0da094d8 JB	120
	121	return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio));
	122	}
	123
	124	static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value)
	125	{
01f76b26	126	struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
0da094d8 JB	127	unsigned long flags;
	128	unsigned char val;
	129
	130	spin_lock_irqsave(&gchip->lock, flags);
	131
	132	val = readl(gchip->base + PDR(gpio));
	133	if (value)
	134	val \|= OFFSET(gpio);
	135	else
	136	val &= ~OFFSET(gpio);
	137	writel(val, gchip->base + PDR(gpio));
	138
	139	spin_unlock_irqrestore(&gchip->lock, flags);
	140	}
	141
f3d705d5 AB	142	static int mb86s70_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
	143	{
	144	int irq, index;
	145
	146	for (index = 0;; index++) {
	147	irq = platform_get_irq(to_platform_device(gc->parent), index);
db67aa33 AS	148	if (irq < 0)
	149	return irq;
	150	if (irq == 0)
f3d705d5 AB	151	break;
	152	if (irq_get_irq_data(irq)->hwirq == offset)
	153	return irq;
	154	}
	155	return -EINVAL;
	156	}
	157
0da094d8 JB	158	static int mb86s70_gpio_probe(struct platform_device *pdev)
	159	{
	160	struct mb86s70_gpio_chip *gchip;
0da094d8 JB	161	int ret;
	162
	163	gchip = devm_kzalloc(&pdev->dev, sizeof(*gchip), GFP_KERNEL);
	164	if (gchip == NULL)
	165	return -ENOMEM;
	166
	167	platform_set_drvdata(pdev, gchip);
	168
329e23f9	169	gchip->base = devm_platform_ioremap_resource(pdev, 0);
0da094d8 JB	170	if (IS_ERR(gchip->base))
	171	return PTR_ERR(gchip->base);
	172
672de527 AS	173	gchip->clk = devm_clk_get_optional(&pdev->dev, NULL);
	174	if (IS_ERR(gchip->clk))
	175	return PTR_ERR(gchip->clk);
	176
	177	ret = clk_prepare_enable(gchip->clk);
	178	if (ret)
	179	return ret;
0da094d8 JB	180
	181	spin_lock_init(&gchip->lock);
	182
	183	gchip->gc.direction_output = mb86s70_gpio_direction_output;
	184	gchip->gc.direction_input = mb86s70_gpio_direction_input;
	185	gchip->gc.request = mb86s70_gpio_request;
	186	gchip->gc.free = mb86s70_gpio_free;
	187	gchip->gc.get = mb86s70_gpio_get;
	188	gchip->gc.set = mb86s70_gpio_set;
db67aa33	189	gchip->gc.to_irq = mb86s70_gpio_to_irq;
0da094d8 JB	190	gchip->gc.label = dev_name(&pdev->dev);
	191	gchip->gc.ngpio = 32;
	192	gchip->gc.owner = THIS_MODULE;
58383c78	193	gchip->gc.parent = &pdev->dev;
0da094d8 JB	194	gchip->gc.base = -1;
0da094d8 JB	195
01f76b26	196	ret = gpiochip_add_data(&gchip->gc, gchip);
0da094d8 JB	197	if (ret) {
	198	dev_err(&pdev->dev, "couldn't register gpio driver\n");
	199	clk_disable_unprepare(gchip->clk);
f3d705d5	200	return ret;
0da094d8 JB	201	}
0da094d8 JB	202
db67aa33	203	acpi_gpiochip_request_interrupts(&gchip->gc);
f3d705d5 AB	204
f3d705d5 AB	205	return 0;
0da094d8 JB	206	}
	207
	208	static int mb86s70_gpio_remove(struct platform_device *pdev)
	209	{
	210	struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev);
	211
db67aa33	212	acpi_gpiochip_free_interrupts(&gchip->gc);
0da094d8 JB	213	gpiochip_remove(&gchip->gc);
	214	clk_disable_unprepare(gchip->clk);
	215
	216	return 0;
	217	}
	218
	219	static const struct of_device_id mb86s70_gpio_dt_ids[] = {
	220	{ .compatible = "fujitsu,mb86s70-gpio" },
	221	{ /* sentinel */ }
	222	};
e1289dba	223	MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids);
0da094d8	224
f3d705d5 AB	225	#ifdef CONFIG_ACPI
	226	static const struct acpi_device_id mb86s70_gpio_acpi_ids[] = {
	227	{ "SCX0007" },
	228	{ /* sentinel */ }
	229	};
	230	MODULE_DEVICE_TABLE(acpi, mb86s70_gpio_acpi_ids);
	231	#endif
	232
0da094d8 JB	233	static struct platform_driver mb86s70_gpio_driver = {
	234	.driver = {
	235	.name = "mb86s70-gpio",
	236	.of_match_table = mb86s70_gpio_dt_ids,
f3d705d5	237	.acpi_match_table = ACPI_PTR(mb86s70_gpio_acpi_ids),
0da094d8 JB	238	},
	239	.probe = mb86s70_gpio_probe,
	240	.remove = mb86s70_gpio_remove,
	241	};
e1289dba	242	module_platform_driver(mb86s70_gpio_driver);
0da094d8	243
e1289dba AB	244	MODULE_DESCRIPTION("MB86S7x GPIO Driver");
	245	MODULE_ALIAS("platform:mb86s70-gpio");
	246	MODULE_LICENSE("GPL");