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Merge branch 'x86/urgent' into x86/platform, to pick up fixes
[mirror_ubuntu-bionic-kernel.git] / drivers / gpio / gpio-mcp23s08.c
CommitLineData
e58b9e27 1/*
4e47f91b
LP
2 * MCP23S08 SPI/I2C GPIO gpio expander driver
3 *
4 * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are
5 * supported.
6 * For the I2C versions of the chips (mcp23008 and mcp23017) generation of
7 * interrupts is also supported.
8 * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is
9 * also capable of generating interrupts, but the linux driver does not
10 * support that yet.
e58b9e27
DB
11 */
12
13#include <linux/kernel.h>
14#include <linux/device.h>
e58b9e27 15#include <linux/mutex.h>
bb207ef1 16#include <linux/module.h>
d120c17f 17#include <linux/gpio.h>
752ad5e8 18#include <linux/i2c.h>
e58b9e27
DB
19#include <linux/spi/spi.h>
20#include <linux/spi/mcp23s08.h>
5a0e3ad6 21#include <linux/slab.h>
0b7bb77f 22#include <asm/byteorder.h>
4e47f91b
LP
23#include <linux/interrupt.h>
24#include <linux/of_irq.h>
97ddb1c8 25#include <linux/of_device.h>
e58b9e27 26
0b7bb77f
PK
27/**
28 * MCP types supported by driver
29 */
30#define MCP_TYPE_S08 0
31#define MCP_TYPE_S17 1
752ad5e8
PK
32#define MCP_TYPE_008 2
33#define MCP_TYPE_017 3
28c5a41e 34#define MCP_TYPE_S18 4
e58b9e27
DB
35
36/* Registers are all 8 bits wide.
37 *
38 * The mcp23s17 has twice as many bits, and can be configured to work
39 * with either 16 bit registers or with two adjacent 8 bit banks.
e58b9e27
DB
40 */
41#define MCP_IODIR 0x00 /* init/reset: all ones */
42#define MCP_IPOL 0x01
43#define MCP_GPINTEN 0x02
44#define MCP_DEFVAL 0x03
45#define MCP_INTCON 0x04
46#define MCP_IOCON 0x05
4e47f91b 47# define IOCON_MIRROR (1 << 6)
e58b9e27
DB
48# define IOCON_SEQOP (1 << 5)
49# define IOCON_HAEN (1 << 3)
50# define IOCON_ODR (1 << 2)
51# define IOCON_INTPOL (1 << 1)
3539699c 52# define IOCON_INTCC (1)
e58b9e27
DB
53#define MCP_GPPU 0x06
54#define MCP_INTF 0x07
55#define MCP_INTCAP 0x08
56#define MCP_GPIO 0x09
57#define MCP_OLAT 0x0a
58
0b7bb77f
PK
59struct mcp23s08;
60
61struct mcp23s08_ops {
62 int (*read)(struct mcp23s08 *mcp, unsigned reg);
63 int (*write)(struct mcp23s08 *mcp, unsigned reg, unsigned val);
64 int (*read_regs)(struct mcp23s08 *mcp, unsigned reg,
65 u16 *vals, unsigned n);
66};
67
e58b9e27 68struct mcp23s08 {
e58b9e27 69 u8 addr;
a4e63554 70 bool irq_active_high;
e58b9e27 71
0b7bb77f 72 u16 cache[11];
4e47f91b
LP
73 u16 irq_rise;
74 u16 irq_fall;
75 int irq;
76 bool irq_controller;
e58b9e27
DB
77 /* lock protects the cached values */
78 struct mutex lock;
4e47f91b 79 struct mutex irq_lock;
e58b9e27
DB
80
81 struct gpio_chip chip;
82
0b7bb77f 83 const struct mcp23s08_ops *ops;
d62b98f3 84 void *data; /* ops specific data */
e58b9e27
DB
85};
86
0b7bb77f 87/* A given spi_device can represent up to eight mcp23sxx chips
8f1cc3b1
DB
88 * sharing the same chipselect but using different addresses
89 * (e.g. chips #0 and #3 might be populated, but not #1 or $2).
90 * Driver data holds all the per-chip data.
91 */
92struct mcp23s08_driver_data {
93 unsigned ngpio;
0b7bb77f 94 struct mcp23s08 *mcp[8];
8f1cc3b1
DB
95 struct mcp23s08 chip[];
96};
97
752ad5e8
PK
98/*----------------------------------------------------------------------*/
99
cbf24fad 100#if IS_ENABLED(CONFIG_I2C)
752ad5e8
PK
101
102static int mcp23008_read(struct mcp23s08 *mcp, unsigned reg)
103{
104 return i2c_smbus_read_byte_data(mcp->data, reg);
105}
106
107static int mcp23008_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
108{
109 return i2c_smbus_write_byte_data(mcp->data, reg, val);
110}
111
112static int
113mcp23008_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
114{
115 while (n--) {
116 int ret = mcp23008_read(mcp, reg++);
117 if (ret < 0)
118 return ret;
119 *vals++ = ret;
120 }
121
122 return 0;
123}
124
125static int mcp23017_read(struct mcp23s08 *mcp, unsigned reg)
126{
127 return i2c_smbus_read_word_data(mcp->data, reg << 1);
128}
129
130static int mcp23017_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
131{
132 return i2c_smbus_write_word_data(mcp->data, reg << 1, val);
133}
134
135static int
136mcp23017_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
137{
138 while (n--) {
139 int ret = mcp23017_read(mcp, reg++);
140 if (ret < 0)
141 return ret;
142 *vals++ = ret;
143 }
144
145 return 0;
146}
147
148static const struct mcp23s08_ops mcp23008_ops = {
149 .read = mcp23008_read,
150 .write = mcp23008_write,
151 .read_regs = mcp23008_read_regs,
152};
153
154static const struct mcp23s08_ops mcp23017_ops = {
155 .read = mcp23017_read,
156 .write = mcp23017_write,
157 .read_regs = mcp23017_read_regs,
158};
159
160#endif /* CONFIG_I2C */
161
162/*----------------------------------------------------------------------*/
163
d62b98f3
PK
164#ifdef CONFIG_SPI_MASTER
165
e58b9e27
DB
166static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg)
167{
168 u8 tx[2], rx[1];
169 int status;
170
171 tx[0] = mcp->addr | 0x01;
172 tx[1] = reg;
33bc8411 173 status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx));
e58b9e27
DB
174 return (status < 0) ? status : rx[0];
175}
176
0b7bb77f 177static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
e58b9e27
DB
178{
179 u8 tx[3];
180
181 tx[0] = mcp->addr;
182 tx[1] = reg;
183 tx[2] = val;
33bc8411 184 return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0);
e58b9e27
DB
185}
186
187static int
0b7bb77f 188mcp23s08_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
e58b9e27 189{
0b7bb77f
PK
190 u8 tx[2], *tmp;
191 int status;
e58b9e27 192
33bc8411 193 if ((n + reg) > sizeof(mcp->cache))
e58b9e27
DB
194 return -EINVAL;
195 tx[0] = mcp->addr | 0x01;
196 tx[1] = reg;
0b7bb77f
PK
197
198 tmp = (u8 *)vals;
33bc8411 199 status = spi_write_then_read(mcp->data, tx, sizeof(tx), tmp, n);
0b7bb77f
PK
200 if (status >= 0) {
201 while (n--)
202 vals[n] = tmp[n]; /* expand to 16bit */
203 }
204 return status;
205}
206
207static int mcp23s17_read(struct mcp23s08 *mcp, unsigned reg)
208{
209 u8 tx[2], rx[2];
210 int status;
211
212 tx[0] = mcp->addr | 0x01;
213 tx[1] = reg << 1;
33bc8411 214 status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx));
0b7bb77f
PK
215 return (status < 0) ? status : (rx[0] | (rx[1] << 8));
216}
217
218static int mcp23s17_write(struct mcp23s08 *mcp, unsigned reg, unsigned val)
219{
220 u8 tx[4];
221
222 tx[0] = mcp->addr;
223 tx[1] = reg << 1;
224 tx[2] = val;
225 tx[3] = val >> 8;
33bc8411 226 return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0);
0b7bb77f
PK
227}
228
229static int
230mcp23s17_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n)
231{
232 u8 tx[2];
233 int status;
234
33bc8411 235 if ((n + reg) > sizeof(mcp->cache))
0b7bb77f
PK
236 return -EINVAL;
237 tx[0] = mcp->addr | 0x01;
238 tx[1] = reg << 1;
239
33bc8411 240 status = spi_write_then_read(mcp->data, tx, sizeof(tx),
0b7bb77f
PK
241 (u8 *)vals, n * 2);
242 if (status >= 0) {
243 while (n--)
244 vals[n] = __le16_to_cpu((__le16)vals[n]);
245 }
246
247 return status;
e58b9e27
DB
248}
249
0b7bb77f
PK
250static const struct mcp23s08_ops mcp23s08_ops = {
251 .read = mcp23s08_read,
252 .write = mcp23s08_write,
253 .read_regs = mcp23s08_read_regs,
254};
255
256static const struct mcp23s08_ops mcp23s17_ops = {
257 .read = mcp23s17_read,
258 .write = mcp23s17_write,
259 .read_regs = mcp23s17_read_regs,
260};
261
d62b98f3 262#endif /* CONFIG_SPI_MASTER */
0b7bb77f 263
e58b9e27
DB
264/*----------------------------------------------------------------------*/
265
266static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
267{
9e03cf0b 268 struct mcp23s08 *mcp = gpiochip_get_data(chip);
e58b9e27
DB
269 int status;
270
271 mutex_lock(&mcp->lock);
272 mcp->cache[MCP_IODIR] |= (1 << offset);
0b7bb77f 273 status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
e58b9e27
DB
274 mutex_unlock(&mcp->lock);
275 return status;
276}
277
278static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
279{
9e03cf0b 280 struct mcp23s08 *mcp = gpiochip_get_data(chip);
e58b9e27
DB
281 int status;
282
283 mutex_lock(&mcp->lock);
284
285 /* REVISIT reading this clears any IRQ ... */
0b7bb77f 286 status = mcp->ops->read(mcp, MCP_GPIO);
e58b9e27
DB
287 if (status < 0)
288 status = 0;
289 else {
290 mcp->cache[MCP_GPIO] = status;
291 status = !!(status & (1 << offset));
292 }
293 mutex_unlock(&mcp->lock);
294 return status;
295}
296
297static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value)
298{
0b7bb77f 299 unsigned olat = mcp->cache[MCP_OLAT];
e58b9e27
DB
300
301 if (value)
302 olat |= mask;
303 else
304 olat &= ~mask;
305 mcp->cache[MCP_OLAT] = olat;
0b7bb77f 306 return mcp->ops->write(mcp, MCP_OLAT, olat);
e58b9e27
DB
307}
308
309static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
310{
9e03cf0b 311 struct mcp23s08 *mcp = gpiochip_get_data(chip);
0b7bb77f 312 unsigned mask = 1 << offset;
e58b9e27
DB
313
314 mutex_lock(&mcp->lock);
315 __mcp23s08_set(mcp, mask, value);
316 mutex_unlock(&mcp->lock);
317}
318
319static int
320mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
321{
9e03cf0b 322 struct mcp23s08 *mcp = gpiochip_get_data(chip);
0b7bb77f 323 unsigned mask = 1 << offset;
e58b9e27
DB
324 int status;
325
326 mutex_lock(&mcp->lock);
327 status = __mcp23s08_set(mcp, mask, value);
328 if (status == 0) {
329 mcp->cache[MCP_IODIR] &= ~mask;
0b7bb77f 330 status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
e58b9e27
DB
331 }
332 mutex_unlock(&mcp->lock);
333 return status;
334}
335
4e47f91b
LP
336/*----------------------------------------------------------------------*/
337static irqreturn_t mcp23s08_irq(int irq, void *data)
338{
339 struct mcp23s08 *mcp = data;
340 int intcap, intf, i;
341 unsigned int child_irq;
342
343 mutex_lock(&mcp->lock);
344 intf = mcp->ops->read(mcp, MCP_INTF);
345 if (intf < 0) {
346 mutex_unlock(&mcp->lock);
347 return IRQ_HANDLED;
348 }
349
350 mcp->cache[MCP_INTF] = intf;
351
352 intcap = mcp->ops->read(mcp, MCP_INTCAP);
353 if (intcap < 0) {
354 mutex_unlock(&mcp->lock);
355 return IRQ_HANDLED;
356 }
357
358 mcp->cache[MCP_INTCAP] = intcap;
359 mutex_unlock(&mcp->lock);
360
361
362 for (i = 0; i < mcp->chip.ngpio; i++) {
363 if ((BIT(i) & mcp->cache[MCP_INTF]) &&
364 ((BIT(i) & intcap & mcp->irq_rise) ||
16fe1ad2
AS
365 (mcp->irq_fall & ~intcap & BIT(i)) ||
366 (BIT(i) & mcp->cache[MCP_INTCON]))) {
dad3d272 367 child_irq = irq_find_mapping(mcp->chip.irqdomain, i);
4e47f91b
LP
368 handle_nested_irq(child_irq);
369 }
370 }
371
372 return IRQ_HANDLED;
373}
374
4e47f91b
LP
375static void mcp23s08_irq_mask(struct irq_data *data)
376{
dad3d272
PR
377 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
378 struct mcp23s08 *mcp = gpiochip_get_data(gc);
4e47f91b
LP
379 unsigned int pos = data->hwirq;
380
381 mcp->cache[MCP_GPINTEN] &= ~BIT(pos);
382}
383
384static void mcp23s08_irq_unmask(struct irq_data *data)
385{
dad3d272
PR
386 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
387 struct mcp23s08 *mcp = gpiochip_get_data(gc);
4e47f91b
LP
388 unsigned int pos = data->hwirq;
389
390 mcp->cache[MCP_GPINTEN] |= BIT(pos);
391}
392
393static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
394{
dad3d272
PR
395 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
396 struct mcp23s08 *mcp = gpiochip_get_data(gc);
4e47f91b
LP
397 unsigned int pos = data->hwirq;
398 int status = 0;
399
400 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
401 mcp->cache[MCP_INTCON] &= ~BIT(pos);
402 mcp->irq_rise |= BIT(pos);
403 mcp->irq_fall |= BIT(pos);
404 } else if (type & IRQ_TYPE_EDGE_RISING) {
405 mcp->cache[MCP_INTCON] &= ~BIT(pos);
406 mcp->irq_rise |= BIT(pos);
407 mcp->irq_fall &= ~BIT(pos);
408 } else if (type & IRQ_TYPE_EDGE_FALLING) {
409 mcp->cache[MCP_INTCON] &= ~BIT(pos);
410 mcp->irq_rise &= ~BIT(pos);
411 mcp->irq_fall |= BIT(pos);
16fe1ad2
AS
412 } else if (type & IRQ_TYPE_LEVEL_HIGH) {
413 mcp->cache[MCP_INTCON] |= BIT(pos);
414 mcp->cache[MCP_DEFVAL] &= ~BIT(pos);
415 } else if (type & IRQ_TYPE_LEVEL_LOW) {
416 mcp->cache[MCP_INTCON] |= BIT(pos);
417 mcp->cache[MCP_DEFVAL] |= BIT(pos);
4e47f91b
LP
418 } else
419 return -EINVAL;
420
421 return status;
422}
423
424static void mcp23s08_irq_bus_lock(struct irq_data *data)
425{
dad3d272
PR
426 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
427 struct mcp23s08 *mcp = gpiochip_get_data(gc);
4e47f91b
LP
428
429 mutex_lock(&mcp->irq_lock);
430}
431
432static void mcp23s08_irq_bus_unlock(struct irq_data *data)
433{
dad3d272
PR
434 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
435 struct mcp23s08 *mcp = gpiochip_get_data(gc);
4e47f91b
LP
436
437 mutex_lock(&mcp->lock);
438 mcp->ops->write(mcp, MCP_GPINTEN, mcp->cache[MCP_GPINTEN]);
439 mcp->ops->write(mcp, MCP_DEFVAL, mcp->cache[MCP_DEFVAL]);
440 mcp->ops->write(mcp, MCP_INTCON, mcp->cache[MCP_INTCON]);
441 mutex_unlock(&mcp->lock);
442 mutex_unlock(&mcp->irq_lock);
443}
444
4e47f91b
LP
445static struct irq_chip mcp23s08_irq_chip = {
446 .name = "gpio-mcp23xxx",
447 .irq_mask = mcp23s08_irq_mask,
448 .irq_unmask = mcp23s08_irq_unmask,
449 .irq_set_type = mcp23s08_irq_set_type,
450 .irq_bus_lock = mcp23s08_irq_bus_lock,
451 .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
4e47f91b
LP
452};
453
454static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
455{
456 struct gpio_chip *chip = &mcp->chip;
dad3d272 457 int err;
a4e63554 458 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
4e47f91b
LP
459
460 mutex_init(&mcp->irq_lock);
461
a4e63554
AS
462 if (mcp->irq_active_high)
463 irqflags |= IRQF_TRIGGER_HIGH;
464 else
465 irqflags |= IRQF_TRIGGER_LOW;
466
58383c78
LW
467 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
468 mcp23s08_irq,
469 irqflags, dev_name(chip->parent), mcp);
4e47f91b 470 if (err != 0) {
58383c78 471 dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
4e47f91b
LP
472 mcp->irq, err);
473 return err;
474 }
475
d245b3f9
LW
476 err = gpiochip_irqchip_add_nested(chip,
477 &mcp23s08_irq_chip,
478 0,
479 handle_simple_irq,
480 IRQ_TYPE_NONE);
dad3d272
PR
481 if (err) {
482 dev_err(chip->parent,
483 "could not connect irqchip to gpiochip: %d\n", err);
484 return err;
4e47f91b 485 }
4e47f91b 486
d245b3f9
LW
487 gpiochip_set_nested_irqchip(chip,
488 &mcp23s08_irq_chip,
489 mcp->irq);
4e47f91b 490
dad3d272 491 return 0;
4e47f91b
LP
492}
493
e58b9e27
DB
494/*----------------------------------------------------------------------*/
495
496#ifdef CONFIG_DEBUG_FS
497
498#include <linux/seq_file.h>
499
500/*
501 * This shows more info than the generic gpio dump code:
502 * pullups, deglitching, open drain drive.
503 */
504static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip)
505{
506 struct mcp23s08 *mcp;
507 char bank;
1d1c1d9b 508 int t;
e58b9e27
DB
509 unsigned mask;
510
9e03cf0b 511 mcp = gpiochip_get_data(chip);
e58b9e27
DB
512
513 /* NOTE: we only handle one bank for now ... */
0b7bb77f 514 bank = '0' + ((mcp->addr >> 1) & 0x7);
e58b9e27
DB
515
516 mutex_lock(&mcp->lock);
0b7bb77f 517 t = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache));
e58b9e27
DB
518 if (t < 0) {
519 seq_printf(s, " I/O ERROR %d\n", t);
520 goto done;
521 }
522
0b7bb77f 523 for (t = 0, mask = 1; t < chip->ngpio; t++, mask <<= 1) {
e58b9e27
DB
524 const char *label;
525
526 label = gpiochip_is_requested(chip, t);
527 if (!label)
528 continue;
529
530 seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s",
531 chip->base + t, bank, t, label,
532 (mcp->cache[MCP_IODIR] & mask) ? "in " : "out",
533 (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo",
eb1567f7 534 (mcp->cache[MCP_GPPU] & mask) ? "up" : " ");
e58b9e27 535 /* NOTE: ignoring the irq-related registers */
33bc8411 536 seq_puts(s, "\n");
e58b9e27
DB
537 }
538done:
539 mutex_unlock(&mcp->lock);
540}
541
542#else
543#define mcp23s08_dbg_show NULL
544#endif
545
546/*----------------------------------------------------------------------*/
547
d62b98f3 548static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
4e47f91b 549 void *data, unsigned addr, unsigned type,
3af0dbd5 550 struct mcp23s08_platform_data *pdata, int cs)
e58b9e27 551{
d62b98f3 552 int status;
4e47f91b 553 bool mirror = false;
e58b9e27 554
e58b9e27
DB
555 mutex_init(&mcp->lock);
556
d62b98f3
PK
557 mcp->data = data;
558 mcp->addr = addr;
a4e63554 559 mcp->irq_active_high = false;
e58b9e27 560
e58b9e27
DB
561 mcp->chip.direction_input = mcp23s08_direction_input;
562 mcp->chip.get = mcp23s08_get;
563 mcp->chip.direction_output = mcp23s08_direction_output;
564 mcp->chip.set = mcp23s08_set;
565 mcp->chip.dbg_show = mcp23s08_dbg_show;
60f749f8 566#ifdef CONFIG_OF_GPIO
97ddb1c8
LP
567 mcp->chip.of_gpio_n_cells = 2;
568 mcp->chip.of_node = dev->of_node;
569#endif
e58b9e27 570
d62b98f3
PK
571 switch (type) {
572#ifdef CONFIG_SPI_MASTER
573 case MCP_TYPE_S08:
0b7bb77f
PK
574 mcp->ops = &mcp23s08_ops;
575 mcp->chip.ngpio = 8;
576 mcp->chip.label = "mcp23s08";
d62b98f3
PK
577 break;
578
579 case MCP_TYPE_S17:
580 mcp->ops = &mcp23s17_ops;
581 mcp->chip.ngpio = 16;
582 mcp->chip.label = "mcp23s17";
583 break;
28c5a41e
PR
584
585 case MCP_TYPE_S18:
586 mcp->ops = &mcp23s17_ops;
587 mcp->chip.ngpio = 16;
588 mcp->chip.label = "mcp23s18";
589 break;
d62b98f3
PK
590#endif /* CONFIG_SPI_MASTER */
591
cbf24fad 592#if IS_ENABLED(CONFIG_I2C)
752ad5e8
PK
593 case MCP_TYPE_008:
594 mcp->ops = &mcp23008_ops;
595 mcp->chip.ngpio = 8;
596 mcp->chip.label = "mcp23008";
597 break;
598
599 case MCP_TYPE_017:
600 mcp->ops = &mcp23017_ops;
601 mcp->chip.ngpio = 16;
602 mcp->chip.label = "mcp23017";
603 break;
604#endif /* CONFIG_I2C */
605
d62b98f3
PK
606 default:
607 dev_err(dev, "invalid device type (%d)\n", type);
608 return -EINVAL;
0b7bb77f 609 }
d62b98f3 610
3af0dbd5 611 mcp->chip.base = pdata->base;
9fb1f39e 612 mcp->chip.can_sleep = true;
58383c78 613 mcp->chip.parent = dev;
d72cbed0 614 mcp->chip.owner = THIS_MODULE;
e58b9e27 615
8f1cc3b1
DB
616 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
617 * and MCP_IOCON.HAEN = 1, so we work with all chips.
618 */
4e47f91b 619
0b7bb77f 620 status = mcp->ops->read(mcp, MCP_IOCON);
e58b9e27
DB
621 if (status < 0)
622 goto fail;
4e47f91b 623
3af0dbd5 624 mcp->irq_controller = pdata->irq_controller;
a4e63554 625 if (mcp->irq && mcp->irq_controller) {
170680ab 626 mcp->irq_active_high =
58383c78 627 of_property_read_bool(mcp->chip.parent->of_node,
170680ab 628 "microchip,irq-active-high");
4e47f91b 629
28c5a41e 630 mirror = pdata->mirror;
a4e63554
AS
631 }
632
633 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
634 mcp->irq_active_high) {
0b7bb77f
PK
635 /* mcp23s17 has IOCON twice, make sure they are in sync */
636 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
637 status |= IOCON_HAEN | (IOCON_HAEN << 8);
a4e63554
AS
638 if (mcp->irq_active_high)
639 status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
640 else
641 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
642
4e47f91b
LP
643 if (mirror)
644 status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
645
3539699c
PR
646 if (type == MCP_TYPE_S18)
647 status |= IOCON_INTCC | (IOCON_INTCC << 8);
648
0b7bb77f 649 status = mcp->ops->write(mcp, MCP_IOCON, status);
e58b9e27
DB
650 if (status < 0)
651 goto fail;
652 }
653
654 /* configure ~100K pullups */
3af0dbd5 655 status = mcp->ops->write(mcp, MCP_GPPU, pdata->chip[cs].pullups);
e58b9e27
DB
656 if (status < 0)
657 goto fail;
658
0b7bb77f 659 status = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache));
e58b9e27
DB
660 if (status < 0)
661 goto fail;
662
663 /* disable inverter on input */
664 if (mcp->cache[MCP_IPOL] != 0) {
665 mcp->cache[MCP_IPOL] = 0;
0b7bb77f
PK
666 status = mcp->ops->write(mcp, MCP_IPOL, 0);
667 if (status < 0)
668 goto fail;
e58b9e27
DB
669 }
670
671 /* disable irqs */
672 if (mcp->cache[MCP_GPINTEN] != 0) {
673 mcp->cache[MCP_GPINTEN] = 0;
0b7bb77f 674 status = mcp->ops->write(mcp, MCP_GPINTEN, 0);
8f1cc3b1
DB
675 if (status < 0)
676 goto fail;
e58b9e27
DB
677 }
678
9e03cf0b 679 status = gpiochip_add_data(&mcp->chip, mcp);
4e47f91b
LP
680 if (status < 0)
681 goto fail;
682
683 if (mcp->irq && mcp->irq_controller) {
684 status = mcp23s08_irq_setup(mcp);
685 if (status) {
4e47f91b
LP
686 goto fail;
687 }
688 }
8f1cc3b1
DB
689fail:
690 if (status < 0)
d62b98f3
PK
691 dev_dbg(dev, "can't setup chip %d, --> %d\n",
692 addr, status);
8f1cc3b1
DB
693 return status;
694}
695
752ad5e8
PK
696/*----------------------------------------------------------------------*/
697
97ddb1c8
LP
698#ifdef CONFIG_OF
699#ifdef CONFIG_SPI_MASTER
ac791804 700static const struct of_device_id mcp23s08_spi_of_match[] = {
97ddb1c8 701 {
45971686
LP
702 .compatible = "microchip,mcp23s08",
703 .data = (void *) MCP_TYPE_S08,
97ddb1c8
LP
704 },
705 {
45971686
LP
706 .compatible = "microchip,mcp23s17",
707 .data = (void *) MCP_TYPE_S17,
708 },
28c5a41e
PR
709 {
710 .compatible = "microchip,mcp23s18",
711 .data = (void *) MCP_TYPE_S18,
712 },
45971686
LP
713/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
714 {
715 .compatible = "mcp,mcp23s08",
716 .data = (void *) MCP_TYPE_S08,
717 },
718 {
719 .compatible = "mcp,mcp23s17",
720 .data = (void *) MCP_TYPE_S17,
97ddb1c8
LP
721 },
722 { },
723};
724MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match);
725#endif
726
727#if IS_ENABLED(CONFIG_I2C)
ac791804 728static const struct of_device_id mcp23s08_i2c_of_match[] = {
97ddb1c8 729 {
45971686
LP
730 .compatible = "microchip,mcp23008",
731 .data = (void *) MCP_TYPE_008,
97ddb1c8
LP
732 },
733 {
45971686
LP
734 .compatible = "microchip,mcp23017",
735 .data = (void *) MCP_TYPE_017,
736 },
737/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
738 {
739 .compatible = "mcp,mcp23008",
740 .data = (void *) MCP_TYPE_008,
741 },
742 {
743 .compatible = "mcp,mcp23017",
744 .data = (void *) MCP_TYPE_017,
97ddb1c8
LP
745 },
746 { },
747};
748MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match);
749#endif
750#endif /* CONFIG_OF */
751
752
cbf24fad 753#if IS_ENABLED(CONFIG_I2C)
752ad5e8 754
3836309d 755static int mcp230xx_probe(struct i2c_client *client,
752ad5e8
PK
756 const struct i2c_device_id *id)
757{
3af0dbd5 758 struct mcp23s08_platform_data *pdata, local_pdata;
752ad5e8 759 struct mcp23s08 *mcp;
3af0dbd5 760 int status;
97ddb1c8
LP
761 const struct of_device_id *match;
762
763 match = of_match_device(of_match_ptr(mcp23s08_i2c_of_match),
764 &client->dev);
3af0dbd5
SZ
765 if (match) {
766 pdata = &local_pdata;
767 pdata->base = -1;
768 pdata->chip[0].pullups = 0;
769 pdata->irq_controller = of_property_read_bool(
770 client->dev.of_node,
771 "interrupt-controller");
772 pdata->mirror = of_property_read_bool(client->dev.of_node,
773 "microchip,irq-mirror");
4e47f91b 774 client->irq = irq_of_parse_and_map(client->dev.of_node, 0);
97ddb1c8 775 } else {
3af0dbd5 776 pdata = dev_get_platdata(&client->dev);
b184c388
SZ
777 if (!pdata) {
778 pdata = devm_kzalloc(&client->dev,
779 sizeof(struct mcp23s08_platform_data),
780 GFP_KERNEL);
aaf2b3af
IY
781 if (!pdata)
782 return -ENOMEM;
b184c388 783 pdata->base = -1;
97ddb1c8 784 }
752ad5e8
PK
785 }
786
33bc8411 787 mcp = kzalloc(sizeof(*mcp), GFP_KERNEL);
752ad5e8
PK
788 if (!mcp)
789 return -ENOMEM;
790
4e47f91b 791 mcp->irq = client->irq;
752ad5e8 792 status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr,
3af0dbd5 793 id->driver_data, pdata, 0);
752ad5e8
PK
794 if (status)
795 goto fail;
796
797 i2c_set_clientdata(client, mcp);
798
799 return 0;
800
801fail:
802 kfree(mcp);
803
804 return status;
805}
806
206210ce 807static int mcp230xx_remove(struct i2c_client *client)
752ad5e8
PK
808{
809 struct mcp23s08 *mcp = i2c_get_clientdata(client);
752ad5e8 810
9f5132ae 811 gpiochip_remove(&mcp->chip);
812 kfree(mcp);
752ad5e8 813
9f5132ae 814 return 0;
752ad5e8
PK
815}
816
817static const struct i2c_device_id mcp230xx_id[] = {
818 { "mcp23008", MCP_TYPE_008 },
819 { "mcp23017", MCP_TYPE_017 },
820 { },
821};
822MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
823
824static struct i2c_driver mcp230xx_driver = {
825 .driver = {
826 .name = "mcp230xx",
97ddb1c8 827 .of_match_table = of_match_ptr(mcp23s08_i2c_of_match),
752ad5e8
PK
828 },
829 .probe = mcp230xx_probe,
8283c4ff 830 .remove = mcp230xx_remove,
752ad5e8
PK
831 .id_table = mcp230xx_id,
832};
833
834static int __init mcp23s08_i2c_init(void)
835{
836 return i2c_add_driver(&mcp230xx_driver);
837}
838
839static void mcp23s08_i2c_exit(void)
840{
841 i2c_del_driver(&mcp230xx_driver);
842}
843
844#else
845
846static int __init mcp23s08_i2c_init(void) { return 0; }
847static void mcp23s08_i2c_exit(void) { }
848
849#endif /* CONFIG_I2C */
850
851/*----------------------------------------------------------------------*/
852
d62b98f3
PK
853#ifdef CONFIG_SPI_MASTER
854
8f1cc3b1
DB
855static int mcp23s08_probe(struct spi_device *spi)
856{
3af0dbd5 857 struct mcp23s08_platform_data *pdata, local_pdata;
8f1cc3b1 858 unsigned addr;
596a1c5f 859 int chips = 0;
8f1cc3b1 860 struct mcp23s08_driver_data *data;
0b7bb77f 861 int status, type;
3af0dbd5 862 unsigned ngpio = 0;
97ddb1c8
LP
863 const struct of_device_id *match;
864 u32 spi_present_mask = 0;
865
866 match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev);
867 if (match) {
de755c33 868 type = (int)(uintptr_t)match->data;
97ddb1c8 869 status = of_property_read_u32(spi->dev.of_node,
45971686 870 "microchip,spi-present-mask", &spi_present_mask);
97ddb1c8 871 if (status) {
45971686
LP
872 status = of_property_read_u32(spi->dev.of_node,
873 "mcp,spi-present-mask", &spi_present_mask);
874 if (status) {
875 dev_err(&spi->dev,
876 "DT has no spi-present-mask\n");
877 return -ENODEV;
878 }
97ddb1c8
LP
879 }
880 if ((spi_present_mask <= 0) || (spi_present_mask >= 256)) {
881 dev_err(&spi->dev, "invalid spi-present-mask\n");
882 return -ENODEV;
883 }
8f1cc3b1 884
3af0dbd5
SZ
885 pdata = &local_pdata;
886 pdata->base = -1;
99e4b98d 887 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
3af0dbd5 888 pdata->chip[addr].pullups = 0;
3e3bed91
MS
889 if (spi_present_mask & (1 << addr))
890 chips++;
99e4b98d 891 }
3af0dbd5
SZ
892 pdata->irq_controller = of_property_read_bool(
893 spi->dev.of_node,
894 "interrupt-controller");
895 pdata->mirror = of_property_read_bool(spi->dev.of_node,
896 "microchip,irq-mirror");
97ddb1c8
LP
897 } else {
898 type = spi_get_device_id(spi)->driver_data;
e56aee18 899 pdata = dev_get_platdata(&spi->dev);
b184c388
SZ
900 if (!pdata) {
901 pdata = devm_kzalloc(&spi->dev,
902 sizeof(struct mcp23s08_platform_data),
903 GFP_KERNEL);
904 pdata->base = -1;
0b7bb77f 905 }
97ddb1c8
LP
906
907 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
908 if (!pdata->chip[addr].is_present)
909 continue;
910 chips++;
911 if ((type == MCP_TYPE_S08) && (addr > 3)) {
912 dev_err(&spi->dev,
913 "mcp23s08 only supports address 0..3\n");
914 return -EINVAL;
915 }
916 spi_present_mask |= 1 << addr;
97ddb1c8 917 }
8f1cc3b1 918 }
8f1cc3b1 919
99e4b98d
MW
920 if (!chips)
921 return -ENODEV;
922
7898b31e
VB
923 data = devm_kzalloc(&spi->dev,
924 sizeof(*data) + chips * sizeof(struct mcp23s08),
925 GFP_KERNEL);
8f1cc3b1
DB
926 if (!data)
927 return -ENOMEM;
7898b31e 928
8f1cc3b1
DB
929 spi_set_drvdata(spi, data);
930
a231b88c
AS
931 spi->irq = irq_of_parse_and_map(spi->dev.of_node, 0);
932
0b7bb77f 933 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
97ddb1c8 934 if (!(spi_present_mask & (1 << addr)))
8f1cc3b1
DB
935 continue;
936 chips--;
937 data->mcp[addr] = &data->chip[chips];
a231b88c 938 data->mcp[addr]->irq = spi->irq;
d62b98f3 939 status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi,
3af0dbd5
SZ
940 0x40 | (addr << 1), type, pdata,
941 addr);
8f1cc3b1
DB
942 if (status < 0)
943 goto fail;
0b7bb77f 944
3af0dbd5 945 if (pdata->base != -1)
28c5a41e
PR
946 pdata->base += data->mcp[addr]->chip.ngpio;
947 ngpio += data->mcp[addr]->chip.ngpio;
8f1cc3b1 948 }
97ddb1c8 949 data->ngpio = ngpio;
e58b9e27
DB
950
951 /* NOTE: these chips have a relatively sane IRQ framework, with
952 * per-signal masking and level/edge triggering. It's not yet
953 * handled here...
954 */
955
e58b9e27
DB
956 return 0;
957
958fail:
0b7bb77f 959 for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
8f1cc3b1
DB
960
961 if (!data->mcp[addr])
962 continue;
9f5132ae 963 gpiochip_remove(&data->mcp[addr]->chip);
8f1cc3b1 964 }
e58b9e27
DB
965 return status;
966}
967
968static int mcp23s08_remove(struct spi_device *spi)
969{
8f1cc3b1 970 struct mcp23s08_driver_data *data = spi_get_drvdata(spi);
8f1cc3b1 971 unsigned addr;
e58b9e27 972
0b7bb77f 973 for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
8f1cc3b1
DB
974
975 if (!data->mcp[addr])
976 continue;
977
9f5132ae 978 gpiochip_remove(&data->mcp[addr]->chip);
8f1cc3b1 979 }
c4941e07 980
9f5132ae 981 return 0;
e58b9e27
DB
982}
983
0b7bb77f
PK
984static const struct spi_device_id mcp23s08_ids[] = {
985 { "mcp23s08", MCP_TYPE_S08 },
986 { "mcp23s17", MCP_TYPE_S17 },
28c5a41e 987 { "mcp23s18", MCP_TYPE_S18 },
0b7bb77f
PK
988 { },
989};
990MODULE_DEVICE_TABLE(spi, mcp23s08_ids);
991
e58b9e27
DB
992static struct spi_driver mcp23s08_driver = {
993 .probe = mcp23s08_probe,
994 .remove = mcp23s08_remove,
0b7bb77f 995 .id_table = mcp23s08_ids,
e58b9e27
DB
996 .driver = {
997 .name = "mcp23s08",
97ddb1c8 998 .of_match_table = of_match_ptr(mcp23s08_spi_of_match),
e58b9e27
DB
999 },
1000};
1001
d62b98f3
PK
1002static int __init mcp23s08_spi_init(void)
1003{
1004 return spi_register_driver(&mcp23s08_driver);
1005}
1006
1007static void mcp23s08_spi_exit(void)
1008{
1009 spi_unregister_driver(&mcp23s08_driver);
1010}
1011
1012#else
1013
1014static int __init mcp23s08_spi_init(void) { return 0; }
1015static void mcp23s08_spi_exit(void) { }
1016
1017#endif /* CONFIG_SPI_MASTER */
1018
e58b9e27
DB
1019/*----------------------------------------------------------------------*/
1020
1021static int __init mcp23s08_init(void)
1022{
752ad5e8
PK
1023 int ret;
1024
1025 ret = mcp23s08_spi_init();
1026 if (ret)
1027 goto spi_fail;
1028
1029 ret = mcp23s08_i2c_init();
1030 if (ret)
1031 goto i2c_fail;
1032
1033 return 0;
1034
1035 i2c_fail:
1036 mcp23s08_spi_exit();
1037 spi_fail:
1038 return ret;
e58b9e27 1039}
752ad5e8 1040/* register after spi/i2c postcore initcall and before
673c0c00
DB
1041 * subsys initcalls that may rely on these GPIOs
1042 */
1043subsys_initcall(mcp23s08_init);
e58b9e27
DB
1044
1045static void __exit mcp23s08_exit(void)
1046{
d62b98f3 1047 mcp23s08_spi_exit();
752ad5e8 1048 mcp23s08_i2c_exit();
e58b9e27
DB
1049}
1050module_exit(mcp23s08_exit);
1051
1052MODULE_LICENSE("GPL");