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[mirror_ubuntu-bionic-kernel.git] / drivers / gpio / gpio-mcp23s08.c
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e58b9e27 1/*
4e47f91b
LP
2 * MCP23S08 SPI/I2C GPIO gpio expander driver
3 *
4 * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are
5 * supported.
6 * For the I2C versions of the chips (mcp23008 and mcp23017) generation of
7 * interrupts is also supported.
8 * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is
9 * also capable of generating interrupts, but the linux driver does not
10 * support that yet.
e58b9e27
DB
11 */
12
13#include <linux/kernel.h>
14#include <linux/device.h>
e58b9e27 15#include <linux/mutex.h>
bb207ef1 16#include <linux/module.h>
d120c17f 17#include <linux/gpio.h>
752ad5e8 18#include <linux/i2c.h>
e58b9e27
DB
19#include <linux/spi/spi.h>
20#include <linux/spi/mcp23s08.h>
5a0e3ad6 21#include <linux/slab.h>
0b7bb77f 22#include <asm/byteorder.h>
4e47f91b
LP
23#include <linux/interrupt.h>
24#include <linux/of_irq.h>
97ddb1c8 25#include <linux/of_device.h>
3d84fdb3 26#include <linux/regmap.h>
e58b9e27 27
0b7bb77f
PK
28/**
29 * MCP types supported by driver
30 */
31#define MCP_TYPE_S08 0
32#define MCP_TYPE_S17 1
752ad5e8
PK
33#define MCP_TYPE_008 2
34#define MCP_TYPE_017 3
28c5a41e 35#define MCP_TYPE_S18 4
e58b9e27
DB
36
37/* Registers are all 8 bits wide.
38 *
39 * The mcp23s17 has twice as many bits, and can be configured to work
40 * with either 16 bit registers or with two adjacent 8 bit banks.
e58b9e27
DB
41 */
42#define MCP_IODIR 0x00 /* init/reset: all ones */
43#define MCP_IPOL 0x01
44#define MCP_GPINTEN 0x02
45#define MCP_DEFVAL 0x03
46#define MCP_INTCON 0x04
47#define MCP_IOCON 0x05
4e47f91b 48# define IOCON_MIRROR (1 << 6)
e58b9e27
DB
49# define IOCON_SEQOP (1 << 5)
50# define IOCON_HAEN (1 << 3)
51# define IOCON_ODR (1 << 2)
52# define IOCON_INTPOL (1 << 1)
3539699c 53# define IOCON_INTCC (1)
e58b9e27
DB
54#define MCP_GPPU 0x06
55#define MCP_INTF 0x07
56#define MCP_INTCAP 0x08
57#define MCP_GPIO 0x09
58#define MCP_OLAT 0x0a
59
0b7bb77f
PK
60struct mcp23s08;
61
e58b9e27 62struct mcp23s08 {
e58b9e27 63 u8 addr;
a4e63554 64 bool irq_active_high;
3d84fdb3 65 bool reg_shift;
e58b9e27 66
0b7bb77f 67 u16 cache[11];
4e47f91b
LP
68 u16 irq_rise;
69 u16 irq_fall;
70 int irq;
71 bool irq_controller;
e58b9e27
DB
72 /* lock protects the cached values */
73 struct mutex lock;
4e47f91b 74 struct mutex irq_lock;
e58b9e27
DB
75
76 struct gpio_chip chip;
77
3d84fdb3
SR
78 struct regmap *regmap;
79 struct device *dev;
8f1cc3b1
DB
80};
81
3d84fdb3
SR
82static const struct regmap_config mcp23x08_regmap = {
83 .reg_bits = 8,
84 .val_bits = 8,
752ad5e8 85
3d84fdb3
SR
86 .reg_stride = 1,
87 .max_register = MCP_OLAT,
752ad5e8
PK
88};
89
3d84fdb3
SR
90static const struct regmap_config mcp23x17_regmap = {
91 .reg_bits = 8,
92 .val_bits = 16,
752ad5e8 93
3d84fdb3
SR
94 .reg_stride = 2,
95 .max_register = MCP_OLAT << 1,
96 .val_format_endian = REGMAP_ENDIAN_LITTLE,
97};
752ad5e8
PK
98
99/*----------------------------------------------------------------------*/
100
d62b98f3
PK
101#ifdef CONFIG_SPI_MASTER
102
3d84fdb3 103static int mcp23sxx_spi_write(void *context, const void *data, size_t count)
e58b9e27 104{
3d84fdb3
SR
105 struct mcp23s08 *mcp = context;
106 struct spi_device *spi = to_spi_device(mcp->dev);
107 struct spi_message m;
108 struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, },
109 { .tx_buf = data, .len = count, }, };
e58b9e27 110
3d84fdb3
SR
111 spi_message_init(&m);
112 spi_message_add_tail(&t[0], &m);
113 spi_message_add_tail(&t[1], &m);
114
115 return spi_sync(spi, &m);
e58b9e27
DB
116}
117
3d84fdb3
SR
118static int mcp23sxx_spi_gather_write(void *context,
119 const void *reg, size_t reg_size,
120 const void *val, size_t val_size)
e58b9e27 121{
3d84fdb3
SR
122 struct mcp23s08 *mcp = context;
123 struct spi_device *spi = to_spi_device(mcp->dev);
124 struct spi_message m;
125 struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, },
126 { .tx_buf = reg, .len = reg_size, },
127 { .tx_buf = val, .len = val_size, }, };
128
129 spi_message_init(&m);
130 spi_message_add_tail(&t[0], &m);
131 spi_message_add_tail(&t[1], &m);
132 spi_message_add_tail(&t[2], &m);
133
134 return spi_sync(spi, &m);
e58b9e27
DB
135}
136
3d84fdb3
SR
137static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size,
138 void *val, size_t val_size)
e58b9e27 139{
3d84fdb3
SR
140 struct mcp23s08 *mcp = context;
141 struct spi_device *spi = to_spi_device(mcp->dev);
142 u8 tx[2];
e58b9e27 143
3d84fdb3 144 if (reg_size != 1)
e58b9e27 145 return -EINVAL;
3d84fdb3 146
e58b9e27 147 tx[0] = mcp->addr | 0x01;
3d84fdb3 148 tx[1] = *((u8 *) reg);
0b7bb77f 149
3d84fdb3 150 return spi_write_then_read(spi, tx, sizeof(tx), val, val_size);
0b7bb77f
PK
151}
152
3d84fdb3
SR
153static const struct regmap_bus mcp23sxx_spi_regmap = {
154 .write = mcp23sxx_spi_write,
155 .gather_write = mcp23sxx_spi_gather_write,
156 .read = mcp23sxx_spi_read,
157};
0b7bb77f 158
3d84fdb3 159#endif /* CONFIG_SPI_MASTER */
0b7bb77f 160
3d84fdb3 161static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
0b7bb77f 162{
3d84fdb3 163 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
0b7bb77f
PK
164}
165
3d84fdb3 166static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
0b7bb77f 167{
3d84fdb3
SR
168 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
169}
0b7bb77f 170
3d84fdb3
SR
171static int mcp_update_cache(struct mcp23s08 *mcp)
172{
173 int ret, reg, i;
0b7bb77f 174
3d84fdb3
SR
175 for (i = 0; i < ARRAY_SIZE(mcp->cache); i++) {
176 ret = mcp_read(mcp, i, &reg);
177 if (ret < 0)
178 return ret;
179 mcp->cache[i] = reg;
0b7bb77f
PK
180 }
181
3d84fdb3 182 return 0;
e58b9e27
DB
183}
184
3d84fdb3 185/*----------------------------------------------------------------------*/
0b7bb77f 186
3d84fdb3
SR
187/* A given spi_device can represent up to eight mcp23sxx chips
188 * sharing the same chipselect but using different addresses
189 * (e.g. chips #0 and #3 might be populated, but not #1 or $2).
190 * Driver data holds all the per-chip data.
191 */
192struct mcp23s08_driver_data {
193 unsigned ngpio;
194 struct mcp23s08 *mcp[8];
195 struct mcp23s08 chip[];
0b7bb77f
PK
196};
197
e58b9e27
DB
198
199static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
200{
9e03cf0b 201 struct mcp23s08 *mcp = gpiochip_get_data(chip);
e58b9e27
DB
202 int status;
203
204 mutex_lock(&mcp->lock);
205 mcp->cache[MCP_IODIR] |= (1 << offset);
3d84fdb3 206 status = mcp_write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
e58b9e27
DB
207 mutex_unlock(&mcp->lock);
208 return status;
209}
210
211static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
212{
9e03cf0b 213 struct mcp23s08 *mcp = gpiochip_get_data(chip);
3d84fdb3 214 int status, ret;
e58b9e27
DB
215
216 mutex_lock(&mcp->lock);
217
218 /* REVISIT reading this clears any IRQ ... */
3d84fdb3
SR
219 ret = mcp_read(mcp, MCP_GPIO, &status);
220 if (ret < 0)
e58b9e27
DB
221 status = 0;
222 else {
223 mcp->cache[MCP_GPIO] = status;
224 status = !!(status & (1 << offset));
225 }
226 mutex_unlock(&mcp->lock);
227 return status;
228}
229
230static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value)
231{
0b7bb77f 232 unsigned olat = mcp->cache[MCP_OLAT];
e58b9e27
DB
233
234 if (value)
235 olat |= mask;
236 else
237 olat &= ~mask;
238 mcp->cache[MCP_OLAT] = olat;
3d84fdb3 239 return mcp_write(mcp, MCP_OLAT, olat);
e58b9e27
DB
240}
241
242static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
243{
9e03cf0b 244 struct mcp23s08 *mcp = gpiochip_get_data(chip);
0b7bb77f 245 unsigned mask = 1 << offset;
e58b9e27
DB
246
247 mutex_lock(&mcp->lock);
248 __mcp23s08_set(mcp, mask, value);
249 mutex_unlock(&mcp->lock);
250}
251
252static int
253mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
254{
9e03cf0b 255 struct mcp23s08 *mcp = gpiochip_get_data(chip);
0b7bb77f 256 unsigned mask = 1 << offset;
e58b9e27
DB
257 int status;
258
259 mutex_lock(&mcp->lock);
260 status = __mcp23s08_set(mcp, mask, value);
261 if (status == 0) {
262 mcp->cache[MCP_IODIR] &= ~mask;
3d84fdb3 263 status = mcp_write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]);
e58b9e27
DB
264 }
265 mutex_unlock(&mcp->lock);
266 return status;
267}
268
4e47f91b
LP
269/*----------------------------------------------------------------------*/
270static irqreturn_t mcp23s08_irq(int irq, void *data)
271{
272 struct mcp23s08 *mcp = data;
273 int intcap, intf, i;
274 unsigned int child_irq;
275
276 mutex_lock(&mcp->lock);
3d84fdb3 277 if (mcp_read(mcp, MCP_INTF, &intf) < 0) {
4e47f91b
LP
278 mutex_unlock(&mcp->lock);
279 return IRQ_HANDLED;
280 }
281
282 mcp->cache[MCP_INTF] = intf;
283
3d84fdb3 284 if (mcp_read(mcp, MCP_INTCAP, &intcap) < 0) {
4e47f91b
LP
285 mutex_unlock(&mcp->lock);
286 return IRQ_HANDLED;
287 }
288
289 mcp->cache[MCP_INTCAP] = intcap;
290 mutex_unlock(&mcp->lock);
291
292
293 for (i = 0; i < mcp->chip.ngpio; i++) {
294 if ((BIT(i) & mcp->cache[MCP_INTF]) &&
295 ((BIT(i) & intcap & mcp->irq_rise) ||
16fe1ad2
AS
296 (mcp->irq_fall & ~intcap & BIT(i)) ||
297 (BIT(i) & mcp->cache[MCP_INTCON]))) {
dad3d272 298 child_irq = irq_find_mapping(mcp->chip.irqdomain, i);
4e47f91b
LP
299 handle_nested_irq(child_irq);
300 }
301 }
302
303 return IRQ_HANDLED;
304}
305
4e47f91b
LP
306static void mcp23s08_irq_mask(struct irq_data *data)
307{
dad3d272
PR
308 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
309 struct mcp23s08 *mcp = gpiochip_get_data(gc);
4e47f91b
LP
310 unsigned int pos = data->hwirq;
311
312 mcp->cache[MCP_GPINTEN] &= ~BIT(pos);
313}
314
315static void mcp23s08_irq_unmask(struct irq_data *data)
316{
dad3d272
PR
317 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
318 struct mcp23s08 *mcp = gpiochip_get_data(gc);
4e47f91b
LP
319 unsigned int pos = data->hwirq;
320
321 mcp->cache[MCP_GPINTEN] |= BIT(pos);
322}
323
324static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
325{
dad3d272
PR
326 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
327 struct mcp23s08 *mcp = gpiochip_get_data(gc);
4e47f91b
LP
328 unsigned int pos = data->hwirq;
329 int status = 0;
330
331 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
332 mcp->cache[MCP_INTCON] &= ~BIT(pos);
333 mcp->irq_rise |= BIT(pos);
334 mcp->irq_fall |= BIT(pos);
335 } else if (type & IRQ_TYPE_EDGE_RISING) {
336 mcp->cache[MCP_INTCON] &= ~BIT(pos);
337 mcp->irq_rise |= BIT(pos);
338 mcp->irq_fall &= ~BIT(pos);
339 } else if (type & IRQ_TYPE_EDGE_FALLING) {
340 mcp->cache[MCP_INTCON] &= ~BIT(pos);
341 mcp->irq_rise &= ~BIT(pos);
342 mcp->irq_fall |= BIT(pos);
16fe1ad2
AS
343 } else if (type & IRQ_TYPE_LEVEL_HIGH) {
344 mcp->cache[MCP_INTCON] |= BIT(pos);
345 mcp->cache[MCP_DEFVAL] &= ~BIT(pos);
346 } else if (type & IRQ_TYPE_LEVEL_LOW) {
347 mcp->cache[MCP_INTCON] |= BIT(pos);
348 mcp->cache[MCP_DEFVAL] |= BIT(pos);
4e47f91b
LP
349 } else
350 return -EINVAL;
351
352 return status;
353}
354
355static void mcp23s08_irq_bus_lock(struct irq_data *data)
356{
dad3d272
PR
357 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
358 struct mcp23s08 *mcp = gpiochip_get_data(gc);
4e47f91b
LP
359
360 mutex_lock(&mcp->irq_lock);
361}
362
363static void mcp23s08_irq_bus_unlock(struct irq_data *data)
364{
dad3d272
PR
365 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
366 struct mcp23s08 *mcp = gpiochip_get_data(gc);
4e47f91b
LP
367
368 mutex_lock(&mcp->lock);
3d84fdb3
SR
369 mcp_write(mcp, MCP_GPINTEN, mcp->cache[MCP_GPINTEN]);
370 mcp_write(mcp, MCP_DEFVAL, mcp->cache[MCP_DEFVAL]);
371 mcp_write(mcp, MCP_INTCON, mcp->cache[MCP_INTCON]);
4e47f91b
LP
372 mutex_unlock(&mcp->lock);
373 mutex_unlock(&mcp->irq_lock);
374}
375
4e47f91b
LP
376static struct irq_chip mcp23s08_irq_chip = {
377 .name = "gpio-mcp23xxx",
378 .irq_mask = mcp23s08_irq_mask,
379 .irq_unmask = mcp23s08_irq_unmask,
380 .irq_set_type = mcp23s08_irq_set_type,
381 .irq_bus_lock = mcp23s08_irq_bus_lock,
382 .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
4e47f91b
LP
383};
384
385static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
386{
387 struct gpio_chip *chip = &mcp->chip;
dad3d272 388 int err;
a4e63554 389 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
4e47f91b
LP
390
391 mutex_init(&mcp->irq_lock);
392
a4e63554
AS
393 if (mcp->irq_active_high)
394 irqflags |= IRQF_TRIGGER_HIGH;
395 else
396 irqflags |= IRQF_TRIGGER_LOW;
397
58383c78
LW
398 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
399 mcp23s08_irq,
400 irqflags, dev_name(chip->parent), mcp);
4e47f91b 401 if (err != 0) {
58383c78 402 dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
4e47f91b
LP
403 mcp->irq, err);
404 return err;
405 }
406
d245b3f9
LW
407 err = gpiochip_irqchip_add_nested(chip,
408 &mcp23s08_irq_chip,
409 0,
410 handle_simple_irq,
411 IRQ_TYPE_NONE);
dad3d272
PR
412 if (err) {
413 dev_err(chip->parent,
414 "could not connect irqchip to gpiochip: %d\n", err);
415 return err;
4e47f91b 416 }
4e47f91b 417
d245b3f9
LW
418 gpiochip_set_nested_irqchip(chip,
419 &mcp23s08_irq_chip,
420 mcp->irq);
4e47f91b 421
dad3d272 422 return 0;
4e47f91b
LP
423}
424
e58b9e27
DB
425/*----------------------------------------------------------------------*/
426
427#ifdef CONFIG_DEBUG_FS
428
429#include <linux/seq_file.h>
430
431/*
432 * This shows more info than the generic gpio dump code:
433 * pullups, deglitching, open drain drive.
434 */
435static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip)
436{
437 struct mcp23s08 *mcp;
438 char bank;
1d1c1d9b 439 int t;
e58b9e27
DB
440 unsigned mask;
441
9e03cf0b 442 mcp = gpiochip_get_data(chip);
e58b9e27
DB
443
444 /* NOTE: we only handle one bank for now ... */
0b7bb77f 445 bank = '0' + ((mcp->addr >> 1) & 0x7);
e58b9e27
DB
446
447 mutex_lock(&mcp->lock);
3d84fdb3 448 t = mcp_update_cache(mcp);
e58b9e27
DB
449 if (t < 0) {
450 seq_printf(s, " I/O ERROR %d\n", t);
451 goto done;
452 }
453
0b7bb77f 454 for (t = 0, mask = 1; t < chip->ngpio; t++, mask <<= 1) {
e58b9e27
DB
455 const char *label;
456
457 label = gpiochip_is_requested(chip, t);
458 if (!label)
459 continue;
460
461 seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s",
462 chip->base + t, bank, t, label,
463 (mcp->cache[MCP_IODIR] & mask) ? "in " : "out",
464 (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo",
eb1567f7 465 (mcp->cache[MCP_GPPU] & mask) ? "up" : " ");
e58b9e27 466 /* NOTE: ignoring the irq-related registers */
33bc8411 467 seq_puts(s, "\n");
e58b9e27
DB
468 }
469done:
470 mutex_unlock(&mcp->lock);
471}
472
473#else
474#define mcp23s08_dbg_show NULL
475#endif
476
477/*----------------------------------------------------------------------*/
478
d62b98f3 479static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
4e47f91b 480 void *data, unsigned addr, unsigned type,
3af0dbd5 481 struct mcp23s08_platform_data *pdata, int cs)
e58b9e27 482{
3d84fdb3 483 int status, ret;
4e47f91b 484 bool mirror = false;
e58b9e27 485
e58b9e27
DB
486 mutex_init(&mcp->lock);
487
3d84fdb3 488 mcp->dev = dev;
d62b98f3 489 mcp->addr = addr;
a4e63554 490 mcp->irq_active_high = false;
e58b9e27 491
e58b9e27
DB
492 mcp->chip.direction_input = mcp23s08_direction_input;
493 mcp->chip.get = mcp23s08_get;
494 mcp->chip.direction_output = mcp23s08_direction_output;
495 mcp->chip.set = mcp23s08_set;
496 mcp->chip.dbg_show = mcp23s08_dbg_show;
60f749f8 497#ifdef CONFIG_OF_GPIO
97ddb1c8
LP
498 mcp->chip.of_gpio_n_cells = 2;
499 mcp->chip.of_node = dev->of_node;
500#endif
e58b9e27 501
d62b98f3
PK
502 switch (type) {
503#ifdef CONFIG_SPI_MASTER
504 case MCP_TYPE_S08:
3d84fdb3
SR
505 mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp,
506 &mcp23x08_regmap);
507 mcp->reg_shift = 0;
0b7bb77f
PK
508 mcp->chip.ngpio = 8;
509 mcp->chip.label = "mcp23s08";
d62b98f3
PK
510 break;
511
512 case MCP_TYPE_S17:
3d84fdb3
SR
513 mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp,
514 &mcp23x17_regmap);
515 mcp->reg_shift = 1;
d62b98f3
PK
516 mcp->chip.ngpio = 16;
517 mcp->chip.label = "mcp23s17";
518 break;
28c5a41e
PR
519
520 case MCP_TYPE_S18:
3d84fdb3
SR
521 mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp,
522 &mcp23x17_regmap);
523 mcp->reg_shift = 1;
28c5a41e
PR
524 mcp->chip.ngpio = 16;
525 mcp->chip.label = "mcp23s18";
526 break;
d62b98f3
PK
527#endif /* CONFIG_SPI_MASTER */
528
cbf24fad 529#if IS_ENABLED(CONFIG_I2C)
752ad5e8 530 case MCP_TYPE_008:
3d84fdb3
SR
531 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap);
532 mcp->reg_shift = 0;
752ad5e8
PK
533 mcp->chip.ngpio = 8;
534 mcp->chip.label = "mcp23008";
535 break;
536
537 case MCP_TYPE_017:
3d84fdb3
SR
538 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap);
539 mcp->reg_shift = 1;
752ad5e8
PK
540 mcp->chip.ngpio = 16;
541 mcp->chip.label = "mcp23017";
542 break;
543#endif /* CONFIG_I2C */
544
d62b98f3
PK
545 default:
546 dev_err(dev, "invalid device type (%d)\n", type);
547 return -EINVAL;
0b7bb77f 548 }
d62b98f3 549
3d84fdb3
SR
550 if (IS_ERR(mcp->regmap))
551 return PTR_ERR(mcp->regmap);
552
3af0dbd5 553 mcp->chip.base = pdata->base;
9fb1f39e 554 mcp->chip.can_sleep = true;
58383c78 555 mcp->chip.parent = dev;
d72cbed0 556 mcp->chip.owner = THIS_MODULE;
e58b9e27 557
8f1cc3b1
DB
558 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
559 * and MCP_IOCON.HAEN = 1, so we work with all chips.
560 */
4e47f91b 561
3d84fdb3
SR
562 ret = mcp_read(mcp, MCP_IOCON, &status);
563 if (ret < 0)
e58b9e27 564 goto fail;
4e47f91b 565
3af0dbd5 566 mcp->irq_controller = pdata->irq_controller;
a4e63554 567 if (mcp->irq && mcp->irq_controller) {
170680ab 568 mcp->irq_active_high =
58383c78 569 of_property_read_bool(mcp->chip.parent->of_node,
170680ab 570 "microchip,irq-active-high");
4e47f91b 571
28c5a41e 572 mirror = pdata->mirror;
a4e63554
AS
573 }
574
575 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
576 mcp->irq_active_high) {
0b7bb77f
PK
577 /* mcp23s17 has IOCON twice, make sure they are in sync */
578 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
579 status |= IOCON_HAEN | (IOCON_HAEN << 8);
a4e63554
AS
580 if (mcp->irq_active_high)
581 status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
582 else
583 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
584
4e47f91b
LP
585 if (mirror)
586 status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
587
3539699c
PR
588 if (type == MCP_TYPE_S18)
589 status |= IOCON_INTCC | (IOCON_INTCC << 8);
590
3d84fdb3
SR
591 ret = mcp_write(mcp, MCP_IOCON, status);
592 if (ret < 0)
e58b9e27
DB
593 goto fail;
594 }
595
596 /* configure ~100K pullups */
3d84fdb3
SR
597 ret = mcp_write(mcp, MCP_GPPU, pdata->chip[cs].pullups);
598 if (ret < 0)
e58b9e27
DB
599 goto fail;
600
3d84fdb3
SR
601 ret = mcp_update_cache(mcp);
602 if (ret < 0)
e58b9e27
DB
603 goto fail;
604
605 /* disable inverter on input */
606 if (mcp->cache[MCP_IPOL] != 0) {
607 mcp->cache[MCP_IPOL] = 0;
3d84fdb3
SR
608 ret = mcp_write(mcp, MCP_IPOL, 0);
609 if (ret < 0)
0b7bb77f 610 goto fail;
e58b9e27
DB
611 }
612
613 /* disable irqs */
614 if (mcp->cache[MCP_GPINTEN] != 0) {
615 mcp->cache[MCP_GPINTEN] = 0;
3d84fdb3
SR
616 ret = mcp_write(mcp, MCP_GPINTEN, 0);
617 if (ret < 0)
8f1cc3b1 618 goto fail;
e58b9e27
DB
619 }
620
3d84fdb3
SR
621 ret = gpiochip_add_data(&mcp->chip, mcp);
622 if (ret < 0)
4e47f91b
LP
623 goto fail;
624
625 if (mcp->irq && mcp->irq_controller) {
3d84fdb3
SR
626 ret = mcp23s08_irq_setup(mcp);
627 if (ret)
4e47f91b 628 goto fail;
4e47f91b 629 }
8f1cc3b1 630fail:
3d84fdb3
SR
631 if (ret < 0)
632 dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret);
633 return ret;
8f1cc3b1
DB
634}
635
752ad5e8
PK
636/*----------------------------------------------------------------------*/
637
97ddb1c8
LP
638#ifdef CONFIG_OF
639#ifdef CONFIG_SPI_MASTER
ac791804 640static const struct of_device_id mcp23s08_spi_of_match[] = {
97ddb1c8 641 {
45971686
LP
642 .compatible = "microchip,mcp23s08",
643 .data = (void *) MCP_TYPE_S08,
97ddb1c8
LP
644 },
645 {
45971686
LP
646 .compatible = "microchip,mcp23s17",
647 .data = (void *) MCP_TYPE_S17,
648 },
28c5a41e
PR
649 {
650 .compatible = "microchip,mcp23s18",
651 .data = (void *) MCP_TYPE_S18,
652 },
45971686
LP
653/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
654 {
655 .compatible = "mcp,mcp23s08",
656 .data = (void *) MCP_TYPE_S08,
657 },
658 {
659 .compatible = "mcp,mcp23s17",
660 .data = (void *) MCP_TYPE_S17,
97ddb1c8
LP
661 },
662 { },
663};
664MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match);
665#endif
666
667#if IS_ENABLED(CONFIG_I2C)
ac791804 668static const struct of_device_id mcp23s08_i2c_of_match[] = {
97ddb1c8 669 {
45971686
LP
670 .compatible = "microchip,mcp23008",
671 .data = (void *) MCP_TYPE_008,
97ddb1c8
LP
672 },
673 {
45971686
LP
674 .compatible = "microchip,mcp23017",
675 .data = (void *) MCP_TYPE_017,
676 },
677/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
678 {
679 .compatible = "mcp,mcp23008",
680 .data = (void *) MCP_TYPE_008,
681 },
682 {
683 .compatible = "mcp,mcp23017",
684 .data = (void *) MCP_TYPE_017,
97ddb1c8
LP
685 },
686 { },
687};
688MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match);
689#endif
690#endif /* CONFIG_OF */
691
692
cbf24fad 693#if IS_ENABLED(CONFIG_I2C)
752ad5e8 694
3836309d 695static int mcp230xx_probe(struct i2c_client *client,
752ad5e8
PK
696 const struct i2c_device_id *id)
697{
3af0dbd5 698 struct mcp23s08_platform_data *pdata, local_pdata;
752ad5e8 699 struct mcp23s08 *mcp;
3af0dbd5 700 int status;
97ddb1c8
LP
701 const struct of_device_id *match;
702
703 match = of_match_device(of_match_ptr(mcp23s08_i2c_of_match),
704 &client->dev);
3af0dbd5
SZ
705 if (match) {
706 pdata = &local_pdata;
707 pdata->base = -1;
708 pdata->chip[0].pullups = 0;
709 pdata->irq_controller = of_property_read_bool(
710 client->dev.of_node,
711 "interrupt-controller");
712 pdata->mirror = of_property_read_bool(client->dev.of_node,
713 "microchip,irq-mirror");
4e47f91b 714 client->irq = irq_of_parse_and_map(client->dev.of_node, 0);
97ddb1c8 715 } else {
3af0dbd5 716 pdata = dev_get_platdata(&client->dev);
b184c388
SZ
717 if (!pdata) {
718 pdata = devm_kzalloc(&client->dev,
719 sizeof(struct mcp23s08_platform_data),
720 GFP_KERNEL);
aaf2b3af
IY
721 if (!pdata)
722 return -ENOMEM;
b184c388 723 pdata->base = -1;
97ddb1c8 724 }
752ad5e8
PK
725 }
726
33bc8411 727 mcp = kzalloc(sizeof(*mcp), GFP_KERNEL);
752ad5e8
PK
728 if (!mcp)
729 return -ENOMEM;
730
4e47f91b 731 mcp->irq = client->irq;
752ad5e8 732 status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr,
3af0dbd5 733 id->driver_data, pdata, 0);
752ad5e8
PK
734 if (status)
735 goto fail;
736
737 i2c_set_clientdata(client, mcp);
738
739 return 0;
740
741fail:
742 kfree(mcp);
743
744 return status;
745}
746
206210ce 747static int mcp230xx_remove(struct i2c_client *client)
752ad5e8
PK
748{
749 struct mcp23s08 *mcp = i2c_get_clientdata(client);
752ad5e8 750
9f5132ae 751 gpiochip_remove(&mcp->chip);
752 kfree(mcp);
752ad5e8 753
9f5132ae 754 return 0;
752ad5e8
PK
755}
756
757static const struct i2c_device_id mcp230xx_id[] = {
758 { "mcp23008", MCP_TYPE_008 },
759 { "mcp23017", MCP_TYPE_017 },
760 { },
761};
762MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
763
764static struct i2c_driver mcp230xx_driver = {
765 .driver = {
766 .name = "mcp230xx",
97ddb1c8 767 .of_match_table = of_match_ptr(mcp23s08_i2c_of_match),
752ad5e8
PK
768 },
769 .probe = mcp230xx_probe,
8283c4ff 770 .remove = mcp230xx_remove,
752ad5e8
PK
771 .id_table = mcp230xx_id,
772};
773
774static int __init mcp23s08_i2c_init(void)
775{
776 return i2c_add_driver(&mcp230xx_driver);
777}
778
779static void mcp23s08_i2c_exit(void)
780{
781 i2c_del_driver(&mcp230xx_driver);
782}
783
784#else
785
786static int __init mcp23s08_i2c_init(void) { return 0; }
787static void mcp23s08_i2c_exit(void) { }
788
789#endif /* CONFIG_I2C */
790
791/*----------------------------------------------------------------------*/
792
d62b98f3
PK
793#ifdef CONFIG_SPI_MASTER
794
8f1cc3b1
DB
795static int mcp23s08_probe(struct spi_device *spi)
796{
3af0dbd5 797 struct mcp23s08_platform_data *pdata, local_pdata;
8f1cc3b1 798 unsigned addr;
596a1c5f 799 int chips = 0;
8f1cc3b1 800 struct mcp23s08_driver_data *data;
0b7bb77f 801 int status, type;
3af0dbd5 802 unsigned ngpio = 0;
97ddb1c8
LP
803 const struct of_device_id *match;
804 u32 spi_present_mask = 0;
805
806 match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev);
807 if (match) {
de755c33 808 type = (int)(uintptr_t)match->data;
97ddb1c8 809 status = of_property_read_u32(spi->dev.of_node,
45971686 810 "microchip,spi-present-mask", &spi_present_mask);
97ddb1c8 811 if (status) {
45971686
LP
812 status = of_property_read_u32(spi->dev.of_node,
813 "mcp,spi-present-mask", &spi_present_mask);
814 if (status) {
815 dev_err(&spi->dev,
816 "DT has no spi-present-mask\n");
817 return -ENODEV;
818 }
97ddb1c8
LP
819 }
820 if ((spi_present_mask <= 0) || (spi_present_mask >= 256)) {
821 dev_err(&spi->dev, "invalid spi-present-mask\n");
822 return -ENODEV;
823 }
8f1cc3b1 824
3af0dbd5
SZ
825 pdata = &local_pdata;
826 pdata->base = -1;
99e4b98d 827 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
3af0dbd5 828 pdata->chip[addr].pullups = 0;
3e3bed91
MS
829 if (spi_present_mask & (1 << addr))
830 chips++;
99e4b98d 831 }
3af0dbd5
SZ
832 pdata->irq_controller = of_property_read_bool(
833 spi->dev.of_node,
834 "interrupt-controller");
835 pdata->mirror = of_property_read_bool(spi->dev.of_node,
836 "microchip,irq-mirror");
97ddb1c8
LP
837 } else {
838 type = spi_get_device_id(spi)->driver_data;
e56aee18 839 pdata = dev_get_platdata(&spi->dev);
b184c388
SZ
840 if (!pdata) {
841 pdata = devm_kzalloc(&spi->dev,
842 sizeof(struct mcp23s08_platform_data),
843 GFP_KERNEL);
844 pdata->base = -1;
0b7bb77f 845 }
97ddb1c8
LP
846
847 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
848 if (!pdata->chip[addr].is_present)
849 continue;
850 chips++;
851 if ((type == MCP_TYPE_S08) && (addr > 3)) {
852 dev_err(&spi->dev,
853 "mcp23s08 only supports address 0..3\n");
854 return -EINVAL;
855 }
856 spi_present_mask |= 1 << addr;
97ddb1c8 857 }
8f1cc3b1 858 }
8f1cc3b1 859
99e4b98d
MW
860 if (!chips)
861 return -ENODEV;
862
7898b31e
VB
863 data = devm_kzalloc(&spi->dev,
864 sizeof(*data) + chips * sizeof(struct mcp23s08),
865 GFP_KERNEL);
8f1cc3b1
DB
866 if (!data)
867 return -ENOMEM;
7898b31e 868
8f1cc3b1
DB
869 spi_set_drvdata(spi, data);
870
a231b88c
AS
871 spi->irq = irq_of_parse_and_map(spi->dev.of_node, 0);
872
0b7bb77f 873 for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) {
97ddb1c8 874 if (!(spi_present_mask & (1 << addr)))
8f1cc3b1
DB
875 continue;
876 chips--;
877 data->mcp[addr] = &data->chip[chips];
a231b88c 878 data->mcp[addr]->irq = spi->irq;
d62b98f3 879 status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi,
3af0dbd5
SZ
880 0x40 | (addr << 1), type, pdata,
881 addr);
8f1cc3b1
DB
882 if (status < 0)
883 goto fail;
0b7bb77f 884
3af0dbd5 885 if (pdata->base != -1)
28c5a41e
PR
886 pdata->base += data->mcp[addr]->chip.ngpio;
887 ngpio += data->mcp[addr]->chip.ngpio;
8f1cc3b1 888 }
97ddb1c8 889 data->ngpio = ngpio;
e58b9e27
DB
890
891 /* NOTE: these chips have a relatively sane IRQ framework, with
892 * per-signal masking and level/edge triggering. It's not yet
893 * handled here...
894 */
895
e58b9e27
DB
896 return 0;
897
898fail:
0b7bb77f 899 for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
8f1cc3b1
DB
900
901 if (!data->mcp[addr])
902 continue;
9f5132ae 903 gpiochip_remove(&data->mcp[addr]->chip);
8f1cc3b1 904 }
e58b9e27
DB
905 return status;
906}
907
908static int mcp23s08_remove(struct spi_device *spi)
909{
8f1cc3b1 910 struct mcp23s08_driver_data *data = spi_get_drvdata(spi);
8f1cc3b1 911 unsigned addr;
e58b9e27 912
0b7bb77f 913 for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) {
8f1cc3b1
DB
914
915 if (!data->mcp[addr])
916 continue;
917
9f5132ae 918 gpiochip_remove(&data->mcp[addr]->chip);
8f1cc3b1 919 }
c4941e07 920
9f5132ae 921 return 0;
e58b9e27
DB
922}
923
0b7bb77f
PK
924static const struct spi_device_id mcp23s08_ids[] = {
925 { "mcp23s08", MCP_TYPE_S08 },
926 { "mcp23s17", MCP_TYPE_S17 },
28c5a41e 927 { "mcp23s18", MCP_TYPE_S18 },
0b7bb77f
PK
928 { },
929};
930MODULE_DEVICE_TABLE(spi, mcp23s08_ids);
931
e58b9e27
DB
932static struct spi_driver mcp23s08_driver = {
933 .probe = mcp23s08_probe,
934 .remove = mcp23s08_remove,
0b7bb77f 935 .id_table = mcp23s08_ids,
e58b9e27
DB
936 .driver = {
937 .name = "mcp23s08",
97ddb1c8 938 .of_match_table = of_match_ptr(mcp23s08_spi_of_match),
e58b9e27
DB
939 },
940};
941
d62b98f3
PK
942static int __init mcp23s08_spi_init(void)
943{
944 return spi_register_driver(&mcp23s08_driver);
945}
946
947static void mcp23s08_spi_exit(void)
948{
949 spi_unregister_driver(&mcp23s08_driver);
950}
951
952#else
953
954static int __init mcp23s08_spi_init(void) { return 0; }
955static void mcp23s08_spi_exit(void) { }
956
957#endif /* CONFIG_SPI_MASTER */
958
e58b9e27
DB
959/*----------------------------------------------------------------------*/
960
961static int __init mcp23s08_init(void)
962{
752ad5e8
PK
963 int ret;
964
965 ret = mcp23s08_spi_init();
966 if (ret)
967 goto spi_fail;
968
969 ret = mcp23s08_i2c_init();
970 if (ret)
971 goto i2c_fail;
972
973 return 0;
974
975 i2c_fail:
976 mcp23s08_spi_exit();
977 spi_fail:
978 return ret;
e58b9e27 979}
752ad5e8 980/* register after spi/i2c postcore initcall and before
673c0c00
DB
981 * subsys initcalls that may rely on these GPIOs
982 */
983subsys_initcall(mcp23s08_init);
e58b9e27
DB
984
985static void __exit mcp23s08_exit(void)
986{
d62b98f3 987 mcp23s08_spi_exit();
752ad5e8 988 mcp23s08_i2c_exit();
e58b9e27
DB
989}
990module_exit(mcp23s08_exit);
991
992MODULE_LICENSE("GPL");