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e58b9e27 | 1 | /* |
4e47f91b LP |
2 | * MCP23S08 SPI/I2C GPIO gpio expander driver |
3 | * | |
4 | * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are | |
5 | * supported. | |
6 | * For the I2C versions of the chips (mcp23008 and mcp23017) generation of | |
7 | * interrupts is also supported. | |
8 | * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is | |
9 | * also capable of generating interrupts, but the linux driver does not | |
10 | * support that yet. | |
e58b9e27 DB |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/device.h> | |
e58b9e27 | 15 | #include <linux/mutex.h> |
bb207ef1 | 16 | #include <linux/module.h> |
d120c17f | 17 | #include <linux/gpio.h> |
752ad5e8 | 18 | #include <linux/i2c.h> |
e58b9e27 DB |
19 | #include <linux/spi/spi.h> |
20 | #include <linux/spi/mcp23s08.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
0b7bb77f | 22 | #include <asm/byteorder.h> |
4e47f91b LP |
23 | #include <linux/interrupt.h> |
24 | #include <linux/of_irq.h> | |
97ddb1c8 | 25 | #include <linux/of_device.h> |
e58b9e27 | 26 | |
0b7bb77f PK |
27 | /** |
28 | * MCP types supported by driver | |
29 | */ | |
30 | #define MCP_TYPE_S08 0 | |
31 | #define MCP_TYPE_S17 1 | |
752ad5e8 PK |
32 | #define MCP_TYPE_008 2 |
33 | #define MCP_TYPE_017 3 | |
e58b9e27 DB |
34 | |
35 | /* Registers are all 8 bits wide. | |
36 | * | |
37 | * The mcp23s17 has twice as many bits, and can be configured to work | |
38 | * with either 16 bit registers or with two adjacent 8 bit banks. | |
e58b9e27 DB |
39 | */ |
40 | #define MCP_IODIR 0x00 /* init/reset: all ones */ | |
41 | #define MCP_IPOL 0x01 | |
42 | #define MCP_GPINTEN 0x02 | |
43 | #define MCP_DEFVAL 0x03 | |
44 | #define MCP_INTCON 0x04 | |
45 | #define MCP_IOCON 0x05 | |
4e47f91b | 46 | # define IOCON_MIRROR (1 << 6) |
e58b9e27 DB |
47 | # define IOCON_SEQOP (1 << 5) |
48 | # define IOCON_HAEN (1 << 3) | |
49 | # define IOCON_ODR (1 << 2) | |
50 | # define IOCON_INTPOL (1 << 1) | |
51 | #define MCP_GPPU 0x06 | |
52 | #define MCP_INTF 0x07 | |
53 | #define MCP_INTCAP 0x08 | |
54 | #define MCP_GPIO 0x09 | |
55 | #define MCP_OLAT 0x0a | |
56 | ||
0b7bb77f PK |
57 | struct mcp23s08; |
58 | ||
59 | struct mcp23s08_ops { | |
60 | int (*read)(struct mcp23s08 *mcp, unsigned reg); | |
61 | int (*write)(struct mcp23s08 *mcp, unsigned reg, unsigned val); | |
62 | int (*read_regs)(struct mcp23s08 *mcp, unsigned reg, | |
63 | u16 *vals, unsigned n); | |
64 | }; | |
65 | ||
e58b9e27 | 66 | struct mcp23s08 { |
e58b9e27 DB |
67 | u8 addr; |
68 | ||
0b7bb77f | 69 | u16 cache[11]; |
4e47f91b LP |
70 | u16 irq_rise; |
71 | u16 irq_fall; | |
72 | int irq; | |
73 | bool irq_controller; | |
e58b9e27 DB |
74 | /* lock protects the cached values */ |
75 | struct mutex lock; | |
4e47f91b LP |
76 | struct mutex irq_lock; |
77 | struct irq_domain *irq_domain; | |
e58b9e27 DB |
78 | |
79 | struct gpio_chip chip; | |
80 | ||
0b7bb77f | 81 | const struct mcp23s08_ops *ops; |
d62b98f3 | 82 | void *data; /* ops specific data */ |
e58b9e27 DB |
83 | }; |
84 | ||
0b7bb77f | 85 | /* A given spi_device can represent up to eight mcp23sxx chips |
8f1cc3b1 DB |
86 | * sharing the same chipselect but using different addresses |
87 | * (e.g. chips #0 and #3 might be populated, but not #1 or $2). | |
88 | * Driver data holds all the per-chip data. | |
89 | */ | |
90 | struct mcp23s08_driver_data { | |
91 | unsigned ngpio; | |
0b7bb77f | 92 | struct mcp23s08 *mcp[8]; |
8f1cc3b1 DB |
93 | struct mcp23s08 chip[]; |
94 | }; | |
95 | ||
4e47f91b LP |
96 | /* This lock class tells lockdep that GPIO irqs are in a different |
97 | * category than their parents, so it won't report false recursion. | |
98 | */ | |
99 | static struct lock_class_key gpio_lock_class; | |
100 | ||
752ad5e8 PK |
101 | /*----------------------------------------------------------------------*/ |
102 | ||
cbf24fad | 103 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 PK |
104 | |
105 | static int mcp23008_read(struct mcp23s08 *mcp, unsigned reg) | |
106 | { | |
107 | return i2c_smbus_read_byte_data(mcp->data, reg); | |
108 | } | |
109 | ||
110 | static int mcp23008_write(struct mcp23s08 *mcp, unsigned reg, unsigned val) | |
111 | { | |
112 | return i2c_smbus_write_byte_data(mcp->data, reg, val); | |
113 | } | |
114 | ||
115 | static int | |
116 | mcp23008_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n) | |
117 | { | |
118 | while (n--) { | |
119 | int ret = mcp23008_read(mcp, reg++); | |
120 | if (ret < 0) | |
121 | return ret; | |
122 | *vals++ = ret; | |
123 | } | |
124 | ||
125 | return 0; | |
126 | } | |
127 | ||
128 | static int mcp23017_read(struct mcp23s08 *mcp, unsigned reg) | |
129 | { | |
130 | return i2c_smbus_read_word_data(mcp->data, reg << 1); | |
131 | } | |
132 | ||
133 | static int mcp23017_write(struct mcp23s08 *mcp, unsigned reg, unsigned val) | |
134 | { | |
135 | return i2c_smbus_write_word_data(mcp->data, reg << 1, val); | |
136 | } | |
137 | ||
138 | static int | |
139 | mcp23017_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n) | |
140 | { | |
141 | while (n--) { | |
142 | int ret = mcp23017_read(mcp, reg++); | |
143 | if (ret < 0) | |
144 | return ret; | |
145 | *vals++ = ret; | |
146 | } | |
147 | ||
148 | return 0; | |
149 | } | |
150 | ||
151 | static const struct mcp23s08_ops mcp23008_ops = { | |
152 | .read = mcp23008_read, | |
153 | .write = mcp23008_write, | |
154 | .read_regs = mcp23008_read_regs, | |
155 | }; | |
156 | ||
157 | static const struct mcp23s08_ops mcp23017_ops = { | |
158 | .read = mcp23017_read, | |
159 | .write = mcp23017_write, | |
160 | .read_regs = mcp23017_read_regs, | |
161 | }; | |
162 | ||
163 | #endif /* CONFIG_I2C */ | |
164 | ||
165 | /*----------------------------------------------------------------------*/ | |
166 | ||
d62b98f3 PK |
167 | #ifdef CONFIG_SPI_MASTER |
168 | ||
e58b9e27 DB |
169 | static int mcp23s08_read(struct mcp23s08 *mcp, unsigned reg) |
170 | { | |
171 | u8 tx[2], rx[1]; | |
172 | int status; | |
173 | ||
174 | tx[0] = mcp->addr | 0x01; | |
175 | tx[1] = reg; | |
33bc8411 | 176 | status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx)); |
e58b9e27 DB |
177 | return (status < 0) ? status : rx[0]; |
178 | } | |
179 | ||
0b7bb77f | 180 | static int mcp23s08_write(struct mcp23s08 *mcp, unsigned reg, unsigned val) |
e58b9e27 DB |
181 | { |
182 | u8 tx[3]; | |
183 | ||
184 | tx[0] = mcp->addr; | |
185 | tx[1] = reg; | |
186 | tx[2] = val; | |
33bc8411 | 187 | return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0); |
e58b9e27 DB |
188 | } |
189 | ||
190 | static int | |
0b7bb77f | 191 | mcp23s08_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n) |
e58b9e27 | 192 | { |
0b7bb77f PK |
193 | u8 tx[2], *tmp; |
194 | int status; | |
e58b9e27 | 195 | |
33bc8411 | 196 | if ((n + reg) > sizeof(mcp->cache)) |
e58b9e27 DB |
197 | return -EINVAL; |
198 | tx[0] = mcp->addr | 0x01; | |
199 | tx[1] = reg; | |
0b7bb77f PK |
200 | |
201 | tmp = (u8 *)vals; | |
33bc8411 | 202 | status = spi_write_then_read(mcp->data, tx, sizeof(tx), tmp, n); |
0b7bb77f PK |
203 | if (status >= 0) { |
204 | while (n--) | |
205 | vals[n] = tmp[n]; /* expand to 16bit */ | |
206 | } | |
207 | return status; | |
208 | } | |
209 | ||
210 | static int mcp23s17_read(struct mcp23s08 *mcp, unsigned reg) | |
211 | { | |
212 | u8 tx[2], rx[2]; | |
213 | int status; | |
214 | ||
215 | tx[0] = mcp->addr | 0x01; | |
216 | tx[1] = reg << 1; | |
33bc8411 | 217 | status = spi_write_then_read(mcp->data, tx, sizeof(tx), rx, sizeof(rx)); |
0b7bb77f PK |
218 | return (status < 0) ? status : (rx[0] | (rx[1] << 8)); |
219 | } | |
220 | ||
221 | static int mcp23s17_write(struct mcp23s08 *mcp, unsigned reg, unsigned val) | |
222 | { | |
223 | u8 tx[4]; | |
224 | ||
225 | tx[0] = mcp->addr; | |
226 | tx[1] = reg << 1; | |
227 | tx[2] = val; | |
228 | tx[3] = val >> 8; | |
33bc8411 | 229 | return spi_write_then_read(mcp->data, tx, sizeof(tx), NULL, 0); |
0b7bb77f PK |
230 | } |
231 | ||
232 | static int | |
233 | mcp23s17_read_regs(struct mcp23s08 *mcp, unsigned reg, u16 *vals, unsigned n) | |
234 | { | |
235 | u8 tx[2]; | |
236 | int status; | |
237 | ||
33bc8411 | 238 | if ((n + reg) > sizeof(mcp->cache)) |
0b7bb77f PK |
239 | return -EINVAL; |
240 | tx[0] = mcp->addr | 0x01; | |
241 | tx[1] = reg << 1; | |
242 | ||
33bc8411 | 243 | status = spi_write_then_read(mcp->data, tx, sizeof(tx), |
0b7bb77f PK |
244 | (u8 *)vals, n * 2); |
245 | if (status >= 0) { | |
246 | while (n--) | |
247 | vals[n] = __le16_to_cpu((__le16)vals[n]); | |
248 | } | |
249 | ||
250 | return status; | |
e58b9e27 DB |
251 | } |
252 | ||
0b7bb77f PK |
253 | static const struct mcp23s08_ops mcp23s08_ops = { |
254 | .read = mcp23s08_read, | |
255 | .write = mcp23s08_write, | |
256 | .read_regs = mcp23s08_read_regs, | |
257 | }; | |
258 | ||
259 | static const struct mcp23s08_ops mcp23s17_ops = { | |
260 | .read = mcp23s17_read, | |
261 | .write = mcp23s17_write, | |
262 | .read_regs = mcp23s17_read_regs, | |
263 | }; | |
264 | ||
d62b98f3 | 265 | #endif /* CONFIG_SPI_MASTER */ |
0b7bb77f | 266 | |
e58b9e27 DB |
267 | /*----------------------------------------------------------------------*/ |
268 | ||
269 | static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) | |
270 | { | |
271 | struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip); | |
272 | int status; | |
273 | ||
274 | mutex_lock(&mcp->lock); | |
275 | mcp->cache[MCP_IODIR] |= (1 << offset); | |
0b7bb77f | 276 | status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); |
e58b9e27 DB |
277 | mutex_unlock(&mcp->lock); |
278 | return status; | |
279 | } | |
280 | ||
281 | static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) | |
282 | { | |
283 | struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip); | |
284 | int status; | |
285 | ||
286 | mutex_lock(&mcp->lock); | |
287 | ||
288 | /* REVISIT reading this clears any IRQ ... */ | |
0b7bb77f | 289 | status = mcp->ops->read(mcp, MCP_GPIO); |
e58b9e27 DB |
290 | if (status < 0) |
291 | status = 0; | |
292 | else { | |
293 | mcp->cache[MCP_GPIO] = status; | |
294 | status = !!(status & (1 << offset)); | |
295 | } | |
296 | mutex_unlock(&mcp->lock); | |
297 | return status; | |
298 | } | |
299 | ||
300 | static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value) | |
301 | { | |
0b7bb77f | 302 | unsigned olat = mcp->cache[MCP_OLAT]; |
e58b9e27 DB |
303 | |
304 | if (value) | |
305 | olat |= mask; | |
306 | else | |
307 | olat &= ~mask; | |
308 | mcp->cache[MCP_OLAT] = olat; | |
0b7bb77f | 309 | return mcp->ops->write(mcp, MCP_OLAT, olat); |
e58b9e27 DB |
310 | } |
311 | ||
312 | static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) | |
313 | { | |
314 | struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip); | |
0b7bb77f | 315 | unsigned mask = 1 << offset; |
e58b9e27 DB |
316 | |
317 | mutex_lock(&mcp->lock); | |
318 | __mcp23s08_set(mcp, mask, value); | |
319 | mutex_unlock(&mcp->lock); | |
320 | } | |
321 | ||
322 | static int | |
323 | mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
324 | { | |
325 | struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip); | |
0b7bb77f | 326 | unsigned mask = 1 << offset; |
e58b9e27 DB |
327 | int status; |
328 | ||
329 | mutex_lock(&mcp->lock); | |
330 | status = __mcp23s08_set(mcp, mask, value); | |
331 | if (status == 0) { | |
332 | mcp->cache[MCP_IODIR] &= ~mask; | |
0b7bb77f | 333 | status = mcp->ops->write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); |
e58b9e27 DB |
334 | } |
335 | mutex_unlock(&mcp->lock); | |
336 | return status; | |
337 | } | |
338 | ||
4e47f91b LP |
339 | /*----------------------------------------------------------------------*/ |
340 | static irqreturn_t mcp23s08_irq(int irq, void *data) | |
341 | { | |
342 | struct mcp23s08 *mcp = data; | |
343 | int intcap, intf, i; | |
344 | unsigned int child_irq; | |
345 | ||
346 | mutex_lock(&mcp->lock); | |
347 | intf = mcp->ops->read(mcp, MCP_INTF); | |
348 | if (intf < 0) { | |
349 | mutex_unlock(&mcp->lock); | |
350 | return IRQ_HANDLED; | |
351 | } | |
352 | ||
353 | mcp->cache[MCP_INTF] = intf; | |
354 | ||
355 | intcap = mcp->ops->read(mcp, MCP_INTCAP); | |
356 | if (intcap < 0) { | |
357 | mutex_unlock(&mcp->lock); | |
358 | return IRQ_HANDLED; | |
359 | } | |
360 | ||
361 | mcp->cache[MCP_INTCAP] = intcap; | |
362 | mutex_unlock(&mcp->lock); | |
363 | ||
364 | ||
365 | for (i = 0; i < mcp->chip.ngpio; i++) { | |
366 | if ((BIT(i) & mcp->cache[MCP_INTF]) && | |
367 | ((BIT(i) & intcap & mcp->irq_rise) || | |
368 | (mcp->irq_fall & ~intcap & BIT(i)))) { | |
369 | child_irq = irq_find_mapping(mcp->irq_domain, i); | |
370 | handle_nested_irq(child_irq); | |
371 | } | |
372 | } | |
373 | ||
374 | return IRQ_HANDLED; | |
375 | } | |
376 | ||
377 | static int mcp23s08_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
378 | { | |
379 | struct mcp23s08 *mcp = container_of(chip, struct mcp23s08, chip); | |
380 | ||
381 | return irq_find_mapping(mcp->irq_domain, offset); | |
382 | } | |
383 | ||
384 | static void mcp23s08_irq_mask(struct irq_data *data) | |
385 | { | |
386 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
387 | unsigned int pos = data->hwirq; | |
388 | ||
389 | mcp->cache[MCP_GPINTEN] &= ~BIT(pos); | |
390 | } | |
391 | ||
392 | static void mcp23s08_irq_unmask(struct irq_data *data) | |
393 | { | |
394 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
395 | unsigned int pos = data->hwirq; | |
396 | ||
397 | mcp->cache[MCP_GPINTEN] |= BIT(pos); | |
398 | } | |
399 | ||
400 | static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) | |
401 | { | |
402 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
403 | unsigned int pos = data->hwirq; | |
404 | int status = 0; | |
405 | ||
406 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
407 | mcp->cache[MCP_INTCON] &= ~BIT(pos); | |
408 | mcp->irq_rise |= BIT(pos); | |
409 | mcp->irq_fall |= BIT(pos); | |
410 | } else if (type & IRQ_TYPE_EDGE_RISING) { | |
411 | mcp->cache[MCP_INTCON] &= ~BIT(pos); | |
412 | mcp->irq_rise |= BIT(pos); | |
413 | mcp->irq_fall &= ~BIT(pos); | |
414 | } else if (type & IRQ_TYPE_EDGE_FALLING) { | |
415 | mcp->cache[MCP_INTCON] &= ~BIT(pos); | |
416 | mcp->irq_rise &= ~BIT(pos); | |
417 | mcp->irq_fall |= BIT(pos); | |
418 | } else | |
419 | return -EINVAL; | |
420 | ||
421 | return status; | |
422 | } | |
423 | ||
424 | static void mcp23s08_irq_bus_lock(struct irq_data *data) | |
425 | { | |
426 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
427 | ||
428 | mutex_lock(&mcp->irq_lock); | |
429 | } | |
430 | ||
431 | static void mcp23s08_irq_bus_unlock(struct irq_data *data) | |
432 | { | |
433 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
434 | ||
435 | mutex_lock(&mcp->lock); | |
436 | mcp->ops->write(mcp, MCP_GPINTEN, mcp->cache[MCP_GPINTEN]); | |
437 | mcp->ops->write(mcp, MCP_DEFVAL, mcp->cache[MCP_DEFVAL]); | |
438 | mcp->ops->write(mcp, MCP_INTCON, mcp->cache[MCP_INTCON]); | |
439 | mutex_unlock(&mcp->lock); | |
440 | mutex_unlock(&mcp->irq_lock); | |
441 | } | |
442 | ||
57ef0428 | 443 | static int mcp23s08_irq_reqres(struct irq_data *data) |
4e47f91b LP |
444 | { |
445 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
446 | ||
57ef0428 | 447 | if (gpio_lock_as_irq(&mcp->chip, data->hwirq)) { |
4e47f91b LP |
448 | dev_err(mcp->chip.dev, |
449 | "unable to lock HW IRQ %lu for IRQ usage\n", | |
450 | data->hwirq); | |
57ef0428 LW |
451 | return -EINVAL; |
452 | } | |
4e47f91b | 453 | |
4e47f91b LP |
454 | return 0; |
455 | } | |
456 | ||
57ef0428 | 457 | static void mcp23s08_irq_relres(struct irq_data *data) |
4e47f91b LP |
458 | { |
459 | struct mcp23s08 *mcp = irq_data_get_irq_chip_data(data); | |
460 | ||
4e47f91b LP |
461 | gpio_unlock_as_irq(&mcp->chip, data->hwirq); |
462 | } | |
463 | ||
464 | static struct irq_chip mcp23s08_irq_chip = { | |
465 | .name = "gpio-mcp23xxx", | |
466 | .irq_mask = mcp23s08_irq_mask, | |
467 | .irq_unmask = mcp23s08_irq_unmask, | |
468 | .irq_set_type = mcp23s08_irq_set_type, | |
469 | .irq_bus_lock = mcp23s08_irq_bus_lock, | |
470 | .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock, | |
57ef0428 LW |
471 | .irq_request_resources = mcp23s08_irq_reqres, |
472 | .irq_release_resources = mcp23s08_irq_relres, | |
4e47f91b LP |
473 | }; |
474 | ||
475 | static int mcp23s08_irq_setup(struct mcp23s08 *mcp) | |
476 | { | |
477 | struct gpio_chip *chip = &mcp->chip; | |
478 | int err, irq, j; | |
479 | ||
480 | mutex_init(&mcp->irq_lock); | |
481 | ||
3af0dbd5 | 482 | mcp->irq_domain = irq_domain_add_linear(chip->dev->of_node, chip->ngpio, |
4e47f91b LP |
483 | &irq_domain_simple_ops, mcp); |
484 | if (!mcp->irq_domain) | |
485 | return -ENODEV; | |
486 | ||
487 | err = devm_request_threaded_irq(chip->dev, mcp->irq, NULL, mcp23s08_irq, | |
488 | IRQF_TRIGGER_LOW | IRQF_ONESHOT, | |
489 | dev_name(chip->dev), mcp); | |
490 | if (err != 0) { | |
491 | dev_err(chip->dev, "unable to request IRQ#%d: %d\n", | |
492 | mcp->irq, err); | |
493 | return err; | |
494 | } | |
495 | ||
496 | chip->to_irq = mcp23s08_gpio_to_irq; | |
497 | ||
498 | for (j = 0; j < mcp->chip.ngpio; j++) { | |
499 | irq = irq_create_mapping(mcp->irq_domain, j); | |
500 | irq_set_lockdep_class(irq, &gpio_lock_class); | |
501 | irq_set_chip_data(irq, mcp); | |
502 | irq_set_chip(irq, &mcp23s08_irq_chip); | |
503 | irq_set_nested_thread(irq, true); | |
504 | #ifdef CONFIG_ARM | |
505 | set_irq_flags(irq, IRQF_VALID); | |
506 | #else | |
507 | irq_set_noprobe(irq); | |
508 | #endif | |
509 | } | |
510 | return 0; | |
511 | } | |
512 | ||
513 | static void mcp23s08_irq_teardown(struct mcp23s08 *mcp) | |
514 | { | |
515 | unsigned int irq, i; | |
516 | ||
517 | free_irq(mcp->irq, mcp); | |
518 | ||
519 | for (i = 0; i < mcp->chip.ngpio; i++) { | |
520 | irq = irq_find_mapping(mcp->irq_domain, i); | |
521 | if (irq > 0) | |
522 | irq_dispose_mapping(irq); | |
523 | } | |
524 | ||
525 | irq_domain_remove(mcp->irq_domain); | |
526 | } | |
527 | ||
e58b9e27 DB |
528 | /*----------------------------------------------------------------------*/ |
529 | ||
530 | #ifdef CONFIG_DEBUG_FS | |
531 | ||
532 | #include <linux/seq_file.h> | |
533 | ||
534 | /* | |
535 | * This shows more info than the generic gpio dump code: | |
536 | * pullups, deglitching, open drain drive. | |
537 | */ | |
538 | static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
539 | { | |
540 | struct mcp23s08 *mcp; | |
541 | char bank; | |
1d1c1d9b | 542 | int t; |
e58b9e27 DB |
543 | unsigned mask; |
544 | ||
545 | mcp = container_of(chip, struct mcp23s08, chip); | |
546 | ||
547 | /* NOTE: we only handle one bank for now ... */ | |
0b7bb77f | 548 | bank = '0' + ((mcp->addr >> 1) & 0x7); |
e58b9e27 DB |
549 | |
550 | mutex_lock(&mcp->lock); | |
0b7bb77f | 551 | t = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache)); |
e58b9e27 DB |
552 | if (t < 0) { |
553 | seq_printf(s, " I/O ERROR %d\n", t); | |
554 | goto done; | |
555 | } | |
556 | ||
0b7bb77f | 557 | for (t = 0, mask = 1; t < chip->ngpio; t++, mask <<= 1) { |
e58b9e27 DB |
558 | const char *label; |
559 | ||
560 | label = gpiochip_is_requested(chip, t); | |
561 | if (!label) | |
562 | continue; | |
563 | ||
564 | seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s", | |
565 | chip->base + t, bank, t, label, | |
566 | (mcp->cache[MCP_IODIR] & mask) ? "in " : "out", | |
567 | (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo", | |
eb1567f7 | 568 | (mcp->cache[MCP_GPPU] & mask) ? "up" : " "); |
e58b9e27 | 569 | /* NOTE: ignoring the irq-related registers */ |
33bc8411 | 570 | seq_puts(s, "\n"); |
e58b9e27 DB |
571 | } |
572 | done: | |
573 | mutex_unlock(&mcp->lock); | |
574 | } | |
575 | ||
576 | #else | |
577 | #define mcp23s08_dbg_show NULL | |
578 | #endif | |
579 | ||
580 | /*----------------------------------------------------------------------*/ | |
581 | ||
d62b98f3 | 582 | static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, |
4e47f91b | 583 | void *data, unsigned addr, unsigned type, |
3af0dbd5 | 584 | struct mcp23s08_platform_data *pdata, int cs) |
e58b9e27 | 585 | { |
d62b98f3 | 586 | int status; |
4e47f91b | 587 | bool mirror = false; |
e58b9e27 | 588 | |
e58b9e27 DB |
589 | mutex_init(&mcp->lock); |
590 | ||
d62b98f3 PK |
591 | mcp->data = data; |
592 | mcp->addr = addr; | |
e58b9e27 | 593 | |
e58b9e27 DB |
594 | mcp->chip.direction_input = mcp23s08_direction_input; |
595 | mcp->chip.get = mcp23s08_get; | |
596 | mcp->chip.direction_output = mcp23s08_direction_output; | |
597 | mcp->chip.set = mcp23s08_set; | |
598 | mcp->chip.dbg_show = mcp23s08_dbg_show; | |
97ddb1c8 LP |
599 | #ifdef CONFIG_OF |
600 | mcp->chip.of_gpio_n_cells = 2; | |
601 | mcp->chip.of_node = dev->of_node; | |
602 | #endif | |
e58b9e27 | 603 | |
d62b98f3 PK |
604 | switch (type) { |
605 | #ifdef CONFIG_SPI_MASTER | |
606 | case MCP_TYPE_S08: | |
0b7bb77f PK |
607 | mcp->ops = &mcp23s08_ops; |
608 | mcp->chip.ngpio = 8; | |
609 | mcp->chip.label = "mcp23s08"; | |
d62b98f3 PK |
610 | break; |
611 | ||
612 | case MCP_TYPE_S17: | |
613 | mcp->ops = &mcp23s17_ops; | |
614 | mcp->chip.ngpio = 16; | |
615 | mcp->chip.label = "mcp23s17"; | |
616 | break; | |
617 | #endif /* CONFIG_SPI_MASTER */ | |
618 | ||
cbf24fad | 619 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 PK |
620 | case MCP_TYPE_008: |
621 | mcp->ops = &mcp23008_ops; | |
622 | mcp->chip.ngpio = 8; | |
623 | mcp->chip.label = "mcp23008"; | |
624 | break; | |
625 | ||
626 | case MCP_TYPE_017: | |
627 | mcp->ops = &mcp23017_ops; | |
628 | mcp->chip.ngpio = 16; | |
629 | mcp->chip.label = "mcp23017"; | |
630 | break; | |
631 | #endif /* CONFIG_I2C */ | |
632 | ||
d62b98f3 PK |
633 | default: |
634 | dev_err(dev, "invalid device type (%d)\n", type); | |
635 | return -EINVAL; | |
0b7bb77f | 636 | } |
d62b98f3 | 637 | |
3af0dbd5 | 638 | mcp->chip.base = pdata->base; |
9fb1f39e | 639 | mcp->chip.can_sleep = true; |
d62b98f3 | 640 | mcp->chip.dev = dev; |
d72cbed0 | 641 | mcp->chip.owner = THIS_MODULE; |
e58b9e27 | 642 | |
8f1cc3b1 DB |
643 | /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, |
644 | * and MCP_IOCON.HAEN = 1, so we work with all chips. | |
645 | */ | |
4e47f91b | 646 | |
0b7bb77f | 647 | status = mcp->ops->read(mcp, MCP_IOCON); |
e58b9e27 DB |
648 | if (status < 0) |
649 | goto fail; | |
4e47f91b | 650 | |
3af0dbd5 | 651 | mcp->irq_controller = pdata->irq_controller; |
4e47f91b | 652 | if (mcp->irq && mcp->irq_controller && (type == MCP_TYPE_017)) |
3af0dbd5 | 653 | mirror = pdata->mirror; |
4e47f91b LP |
654 | |
655 | if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror) { | |
0b7bb77f PK |
656 | /* mcp23s17 has IOCON twice, make sure they are in sync */ |
657 | status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); | |
658 | status |= IOCON_HAEN | (IOCON_HAEN << 8); | |
4e47f91b LP |
659 | status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8)); |
660 | if (mirror) | |
661 | status |= IOCON_MIRROR | (IOCON_MIRROR << 8); | |
662 | ||
0b7bb77f | 663 | status = mcp->ops->write(mcp, MCP_IOCON, status); |
e58b9e27 DB |
664 | if (status < 0) |
665 | goto fail; | |
666 | } | |
667 | ||
668 | /* configure ~100K pullups */ | |
3af0dbd5 | 669 | status = mcp->ops->write(mcp, MCP_GPPU, pdata->chip[cs].pullups); |
e58b9e27 DB |
670 | if (status < 0) |
671 | goto fail; | |
672 | ||
0b7bb77f | 673 | status = mcp->ops->read_regs(mcp, 0, mcp->cache, ARRAY_SIZE(mcp->cache)); |
e58b9e27 DB |
674 | if (status < 0) |
675 | goto fail; | |
676 | ||
677 | /* disable inverter on input */ | |
678 | if (mcp->cache[MCP_IPOL] != 0) { | |
679 | mcp->cache[MCP_IPOL] = 0; | |
0b7bb77f PK |
680 | status = mcp->ops->write(mcp, MCP_IPOL, 0); |
681 | if (status < 0) | |
682 | goto fail; | |
e58b9e27 DB |
683 | } |
684 | ||
685 | /* disable irqs */ | |
686 | if (mcp->cache[MCP_GPINTEN] != 0) { | |
687 | mcp->cache[MCP_GPINTEN] = 0; | |
0b7bb77f | 688 | status = mcp->ops->write(mcp, MCP_GPINTEN, 0); |
8f1cc3b1 DB |
689 | if (status < 0) |
690 | goto fail; | |
e58b9e27 DB |
691 | } |
692 | ||
693 | status = gpiochip_add(&mcp->chip); | |
4e47f91b LP |
694 | if (status < 0) |
695 | goto fail; | |
696 | ||
697 | if (mcp->irq && mcp->irq_controller) { | |
698 | status = mcp23s08_irq_setup(mcp); | |
699 | if (status) { | |
700 | mcp23s08_irq_teardown(mcp); | |
701 | goto fail; | |
702 | } | |
703 | } | |
8f1cc3b1 DB |
704 | fail: |
705 | if (status < 0) | |
d62b98f3 PK |
706 | dev_dbg(dev, "can't setup chip %d, --> %d\n", |
707 | addr, status); | |
8f1cc3b1 DB |
708 | return status; |
709 | } | |
710 | ||
752ad5e8 PK |
711 | /*----------------------------------------------------------------------*/ |
712 | ||
97ddb1c8 LP |
713 | #ifdef CONFIG_OF |
714 | #ifdef CONFIG_SPI_MASTER | |
ac791804 | 715 | static const struct of_device_id mcp23s08_spi_of_match[] = { |
97ddb1c8 | 716 | { |
45971686 LP |
717 | .compatible = "microchip,mcp23s08", |
718 | .data = (void *) MCP_TYPE_S08, | |
97ddb1c8 LP |
719 | }, |
720 | { | |
45971686 LP |
721 | .compatible = "microchip,mcp23s17", |
722 | .data = (void *) MCP_TYPE_S17, | |
723 | }, | |
724 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ | |
725 | { | |
726 | .compatible = "mcp,mcp23s08", | |
727 | .data = (void *) MCP_TYPE_S08, | |
728 | }, | |
729 | { | |
730 | .compatible = "mcp,mcp23s17", | |
731 | .data = (void *) MCP_TYPE_S17, | |
97ddb1c8 LP |
732 | }, |
733 | { }, | |
734 | }; | |
735 | MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); | |
736 | #endif | |
737 | ||
738 | #if IS_ENABLED(CONFIG_I2C) | |
ac791804 | 739 | static const struct of_device_id mcp23s08_i2c_of_match[] = { |
97ddb1c8 | 740 | { |
45971686 LP |
741 | .compatible = "microchip,mcp23008", |
742 | .data = (void *) MCP_TYPE_008, | |
97ddb1c8 LP |
743 | }, |
744 | { | |
45971686 LP |
745 | .compatible = "microchip,mcp23017", |
746 | .data = (void *) MCP_TYPE_017, | |
747 | }, | |
748 | /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ | |
749 | { | |
750 | .compatible = "mcp,mcp23008", | |
751 | .data = (void *) MCP_TYPE_008, | |
752 | }, | |
753 | { | |
754 | .compatible = "mcp,mcp23017", | |
755 | .data = (void *) MCP_TYPE_017, | |
97ddb1c8 LP |
756 | }, |
757 | { }, | |
758 | }; | |
759 | MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); | |
760 | #endif | |
761 | #endif /* CONFIG_OF */ | |
762 | ||
763 | ||
cbf24fad | 764 | #if IS_ENABLED(CONFIG_I2C) |
752ad5e8 | 765 | |
3836309d | 766 | static int mcp230xx_probe(struct i2c_client *client, |
752ad5e8 PK |
767 | const struct i2c_device_id *id) |
768 | { | |
3af0dbd5 | 769 | struct mcp23s08_platform_data *pdata, local_pdata; |
752ad5e8 | 770 | struct mcp23s08 *mcp; |
3af0dbd5 | 771 | int status; |
97ddb1c8 LP |
772 | const struct of_device_id *match; |
773 | ||
774 | match = of_match_device(of_match_ptr(mcp23s08_i2c_of_match), | |
775 | &client->dev); | |
3af0dbd5 SZ |
776 | if (match) { |
777 | pdata = &local_pdata; | |
778 | pdata->base = -1; | |
779 | pdata->chip[0].pullups = 0; | |
780 | pdata->irq_controller = of_property_read_bool( | |
781 | client->dev.of_node, | |
782 | "interrupt-controller"); | |
783 | pdata->mirror = of_property_read_bool(client->dev.of_node, | |
784 | "microchip,irq-mirror"); | |
4e47f91b | 785 | client->irq = irq_of_parse_and_map(client->dev.of_node, 0); |
97ddb1c8 | 786 | } else { |
3af0dbd5 SZ |
787 | pdata = dev_get_platdata(&client->dev); |
788 | if (!pdata || !gpio_is_valid(pdata->base)) { | |
8a564065 | 789 | dev_dbg(&client->dev, "invalid platform data\n"); |
97ddb1c8 LP |
790 | return -EINVAL; |
791 | } | |
752ad5e8 PK |
792 | } |
793 | ||
33bc8411 | 794 | mcp = kzalloc(sizeof(*mcp), GFP_KERNEL); |
752ad5e8 PK |
795 | if (!mcp) |
796 | return -ENOMEM; | |
797 | ||
4e47f91b | 798 | mcp->irq = client->irq; |
752ad5e8 | 799 | status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, |
3af0dbd5 | 800 | id->driver_data, pdata, 0); |
752ad5e8 PK |
801 | if (status) |
802 | goto fail; | |
803 | ||
804 | i2c_set_clientdata(client, mcp); | |
805 | ||
806 | return 0; | |
807 | ||
808 | fail: | |
809 | kfree(mcp); | |
810 | ||
811 | return status; | |
812 | } | |
813 | ||
206210ce | 814 | static int mcp230xx_remove(struct i2c_client *client) |
752ad5e8 PK |
815 | { |
816 | struct mcp23s08 *mcp = i2c_get_clientdata(client); | |
752ad5e8 | 817 | |
4e47f91b LP |
818 | if (client->irq && mcp->irq_controller) |
819 | mcp23s08_irq_teardown(mcp); | |
820 | ||
9f5132ae | 821 | gpiochip_remove(&mcp->chip); |
822 | kfree(mcp); | |
752ad5e8 | 823 | |
9f5132ae | 824 | return 0; |
752ad5e8 PK |
825 | } |
826 | ||
827 | static const struct i2c_device_id mcp230xx_id[] = { | |
828 | { "mcp23008", MCP_TYPE_008 }, | |
829 | { "mcp23017", MCP_TYPE_017 }, | |
830 | { }, | |
831 | }; | |
832 | MODULE_DEVICE_TABLE(i2c, mcp230xx_id); | |
833 | ||
834 | static struct i2c_driver mcp230xx_driver = { | |
835 | .driver = { | |
836 | .name = "mcp230xx", | |
837 | .owner = THIS_MODULE, | |
97ddb1c8 | 838 | .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), |
752ad5e8 PK |
839 | }, |
840 | .probe = mcp230xx_probe, | |
8283c4ff | 841 | .remove = mcp230xx_remove, |
752ad5e8 PK |
842 | .id_table = mcp230xx_id, |
843 | }; | |
844 | ||
845 | static int __init mcp23s08_i2c_init(void) | |
846 | { | |
847 | return i2c_add_driver(&mcp230xx_driver); | |
848 | } | |
849 | ||
850 | static void mcp23s08_i2c_exit(void) | |
851 | { | |
852 | i2c_del_driver(&mcp230xx_driver); | |
853 | } | |
854 | ||
855 | #else | |
856 | ||
857 | static int __init mcp23s08_i2c_init(void) { return 0; } | |
858 | static void mcp23s08_i2c_exit(void) { } | |
859 | ||
860 | #endif /* CONFIG_I2C */ | |
861 | ||
862 | /*----------------------------------------------------------------------*/ | |
863 | ||
d62b98f3 PK |
864 | #ifdef CONFIG_SPI_MASTER |
865 | ||
8f1cc3b1 DB |
866 | static int mcp23s08_probe(struct spi_device *spi) |
867 | { | |
3af0dbd5 | 868 | struct mcp23s08_platform_data *pdata, local_pdata; |
8f1cc3b1 | 869 | unsigned addr; |
596a1c5f | 870 | int chips = 0; |
8f1cc3b1 | 871 | struct mcp23s08_driver_data *data; |
0b7bb77f | 872 | int status, type; |
3af0dbd5 | 873 | unsigned ngpio = 0; |
97ddb1c8 LP |
874 | const struct of_device_id *match; |
875 | u32 spi_present_mask = 0; | |
876 | ||
877 | match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); | |
878 | if (match) { | |
de755c33 | 879 | type = (int)(uintptr_t)match->data; |
97ddb1c8 | 880 | status = of_property_read_u32(spi->dev.of_node, |
45971686 | 881 | "microchip,spi-present-mask", &spi_present_mask); |
97ddb1c8 | 882 | if (status) { |
45971686 LP |
883 | status = of_property_read_u32(spi->dev.of_node, |
884 | "mcp,spi-present-mask", &spi_present_mask); | |
885 | if (status) { | |
886 | dev_err(&spi->dev, | |
887 | "DT has no spi-present-mask\n"); | |
888 | return -ENODEV; | |
889 | } | |
97ddb1c8 LP |
890 | } |
891 | if ((spi_present_mask <= 0) || (spi_present_mask >= 256)) { | |
892 | dev_err(&spi->dev, "invalid spi-present-mask\n"); | |
893 | return -ENODEV; | |
894 | } | |
8f1cc3b1 | 895 | |
3af0dbd5 SZ |
896 | pdata = &local_pdata; |
897 | pdata->base = -1; | |
99e4b98d | 898 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { |
3af0dbd5 | 899 | pdata->chip[addr].pullups = 0; |
3e3bed91 MS |
900 | if (spi_present_mask & (1 << addr)) |
901 | chips++; | |
99e4b98d | 902 | } |
3af0dbd5 SZ |
903 | pdata->irq_controller = of_property_read_bool( |
904 | spi->dev.of_node, | |
905 | "interrupt-controller"); | |
906 | pdata->mirror = of_property_read_bool(spi->dev.of_node, | |
907 | "microchip,irq-mirror"); | |
97ddb1c8 LP |
908 | } else { |
909 | type = spi_get_device_id(spi)->driver_data; | |
e56aee18 | 910 | pdata = dev_get_platdata(&spi->dev); |
97ddb1c8 LP |
911 | if (!pdata || !gpio_is_valid(pdata->base)) { |
912 | dev_dbg(&spi->dev, | |
913 | "invalid or missing platform data\n"); | |
0b7bb77f PK |
914 | return -EINVAL; |
915 | } | |
97ddb1c8 LP |
916 | |
917 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { | |
918 | if (!pdata->chip[addr].is_present) | |
919 | continue; | |
920 | chips++; | |
921 | if ((type == MCP_TYPE_S08) && (addr > 3)) { | |
922 | dev_err(&spi->dev, | |
923 | "mcp23s08 only supports address 0..3\n"); | |
924 | return -EINVAL; | |
925 | } | |
926 | spi_present_mask |= 1 << addr; | |
97ddb1c8 | 927 | } |
8f1cc3b1 | 928 | } |
8f1cc3b1 | 929 | |
99e4b98d MW |
930 | if (!chips) |
931 | return -ENODEV; | |
932 | ||
33bc8411 | 933 | data = kzalloc(sizeof(*data) + chips * sizeof(struct mcp23s08), |
8f1cc3b1 DB |
934 | GFP_KERNEL); |
935 | if (!data) | |
936 | return -ENOMEM; | |
937 | spi_set_drvdata(spi, data); | |
938 | ||
0b7bb77f | 939 | for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { |
97ddb1c8 | 940 | if (!(spi_present_mask & (1 << addr))) |
8f1cc3b1 DB |
941 | continue; |
942 | chips--; | |
943 | data->mcp[addr] = &data->chip[chips]; | |
d62b98f3 | 944 | status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, |
3af0dbd5 SZ |
945 | 0x40 | (addr << 1), type, pdata, |
946 | addr); | |
8f1cc3b1 DB |
947 | if (status < 0) |
948 | goto fail; | |
0b7bb77f | 949 | |
3af0dbd5 SZ |
950 | if (pdata->base != -1) |
951 | pdata->base += (type == MCP_TYPE_S17) ? 16 : 8; | |
97ddb1c8 | 952 | ngpio += (type == MCP_TYPE_S17) ? 16 : 8; |
8f1cc3b1 | 953 | } |
97ddb1c8 | 954 | data->ngpio = ngpio; |
e58b9e27 DB |
955 | |
956 | /* NOTE: these chips have a relatively sane IRQ framework, with | |
957 | * per-signal masking and level/edge triggering. It's not yet | |
958 | * handled here... | |
959 | */ | |
960 | ||
e58b9e27 DB |
961 | return 0; |
962 | ||
963 | fail: | |
0b7bb77f | 964 | for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) { |
8f1cc3b1 DB |
965 | |
966 | if (!data->mcp[addr]) | |
967 | continue; | |
9f5132ae | 968 | gpiochip_remove(&data->mcp[addr]->chip); |
8f1cc3b1 DB |
969 | } |
970 | kfree(data); | |
e58b9e27 DB |
971 | return status; |
972 | } | |
973 | ||
974 | static int mcp23s08_remove(struct spi_device *spi) | |
975 | { | |
8f1cc3b1 | 976 | struct mcp23s08_driver_data *data = spi_get_drvdata(spi); |
8f1cc3b1 | 977 | unsigned addr; |
e58b9e27 | 978 | |
0b7bb77f | 979 | for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) { |
8f1cc3b1 DB |
980 | |
981 | if (!data->mcp[addr]) | |
982 | continue; | |
983 | ||
9f5132ae | 984 | gpiochip_remove(&data->mcp[addr]->chip); |
8f1cc3b1 | 985 | } |
9f5132ae | 986 | kfree(data); |
987 | return 0; | |
e58b9e27 DB |
988 | } |
989 | ||
0b7bb77f PK |
990 | static const struct spi_device_id mcp23s08_ids[] = { |
991 | { "mcp23s08", MCP_TYPE_S08 }, | |
992 | { "mcp23s17", MCP_TYPE_S17 }, | |
993 | { }, | |
994 | }; | |
995 | MODULE_DEVICE_TABLE(spi, mcp23s08_ids); | |
996 | ||
e58b9e27 DB |
997 | static struct spi_driver mcp23s08_driver = { |
998 | .probe = mcp23s08_probe, | |
999 | .remove = mcp23s08_remove, | |
0b7bb77f | 1000 | .id_table = mcp23s08_ids, |
e58b9e27 DB |
1001 | .driver = { |
1002 | .name = "mcp23s08", | |
1003 | .owner = THIS_MODULE, | |
97ddb1c8 | 1004 | .of_match_table = of_match_ptr(mcp23s08_spi_of_match), |
e58b9e27 DB |
1005 | }, |
1006 | }; | |
1007 | ||
d62b98f3 PK |
1008 | static int __init mcp23s08_spi_init(void) |
1009 | { | |
1010 | return spi_register_driver(&mcp23s08_driver); | |
1011 | } | |
1012 | ||
1013 | static void mcp23s08_spi_exit(void) | |
1014 | { | |
1015 | spi_unregister_driver(&mcp23s08_driver); | |
1016 | } | |
1017 | ||
1018 | #else | |
1019 | ||
1020 | static int __init mcp23s08_spi_init(void) { return 0; } | |
1021 | static void mcp23s08_spi_exit(void) { } | |
1022 | ||
1023 | #endif /* CONFIG_SPI_MASTER */ | |
1024 | ||
e58b9e27 DB |
1025 | /*----------------------------------------------------------------------*/ |
1026 | ||
1027 | static int __init mcp23s08_init(void) | |
1028 | { | |
752ad5e8 PK |
1029 | int ret; |
1030 | ||
1031 | ret = mcp23s08_spi_init(); | |
1032 | if (ret) | |
1033 | goto spi_fail; | |
1034 | ||
1035 | ret = mcp23s08_i2c_init(); | |
1036 | if (ret) | |
1037 | goto i2c_fail; | |
1038 | ||
1039 | return 0; | |
1040 | ||
1041 | i2c_fail: | |
1042 | mcp23s08_spi_exit(); | |
1043 | spi_fail: | |
1044 | return ret; | |
e58b9e27 | 1045 | } |
752ad5e8 | 1046 | /* register after spi/i2c postcore initcall and before |
673c0c00 DB |
1047 | * subsys initcalls that may rely on these GPIOs |
1048 | */ | |
1049 | subsys_initcall(mcp23s08_init); | |
e58b9e27 DB |
1050 | |
1051 | static void __exit mcp23s08_exit(void) | |
1052 | { | |
d62b98f3 | 1053 | mcp23s08_spi_exit(); |
752ad5e8 | 1054 | mcp23s08_i2c_exit(); |
e58b9e27 DB |
1055 | } |
1056 | module_exit(mcp23s08_exit); | |
1057 | ||
1058 | MODULE_LICENSE("GPL"); |