[mirror_ubuntu-hirsute-kernel.git] / drivers / gpio / gpio-ml-ioh.c

/*
 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 */
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#define IOH_EDGE_FALLING	0
#define IOH_EDGE_RISING		BIT(0)
#define IOH_LEVEL_L		BIT(1)
#define IOH_LEVEL_H		(BIT(0) | BIT(1))
#define IOH_EDGE_BOTH		BIT(2)
#define IOH_IM_MASK		(BIT(0) | BIT(1) | BIT(2))

#define IOH_IRQ_BASE		0

#define PCI_VENDOR_ID_ROHM             0x10DB

struct ioh_reg_comn {
	u32	ien;
	u32	istatus;
	u32	idisp;
	u32	iclr;
	u32	imask;
	u32	imaskclr;
	u32	po;
	u32	pi;
	u32	pm;
	u32	im_0;
	u32	im_1;
	u32	reserved;
};

struct ioh_regs {
	struct ioh_reg_comn regs[8];
	u32 reserve1[16];
	u32 ioh_sel_reg[4];
	u32 reserve2[11];
	u32 srst;
};

/**
 * struct ioh_gpio_reg_data - The register store data.
 * @ien_reg	To store contents of interrupt enable register.
 * @imask_reg:	To store contents of interrupt mask regist
 * @po_reg:	To store contents of PO register.
 * @pm_reg:	To store contents of PM register.
 * @im0_reg:	To store contents of interrupt mode regist0
 * @im1_reg:	To store contents of interrupt mode regist1
 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
 */
struct ioh_gpio_reg_data {
	u32 ien_reg;
	u32 imask_reg;
	u32 po_reg;
	u32 pm_reg;
	u32 im0_reg;
	u32 im1_reg;
	u32 use_sel_reg;
};

/**
 * struct ioh_gpio - GPIO private data structure.
 * @base:			PCI base address of Memory mapped I/O register.
 * @reg:			Memory mapped IOH GPIO register list.
 * @dev:			Pointer to device structure.
 * @gpio:			Data for GPIO infrastructure.
 * @ioh_gpio_reg:		Memory mapped Register data is saved here
 *				when suspend.
 * @gpio_use_sel:		Save GPIO_USE_SEL1~4 register for PM
 * @ch:				Indicate GPIO channel
 * @irq_base:		Save base of IRQ number for interrupt
 * @spinlock:		Used for register access protection in
 *				interrupt context ioh_irq_type and PM;
 */
struct ioh_gpio {
	void __iomem *base;
	struct ioh_regs __iomem *reg;
	struct device *dev;
	struct gpio_chip gpio;
	struct ioh_gpio_reg_data ioh_gpio_reg;
	u32 gpio_use_sel;
	struct mutex lock;
	int ch;
	int irq_base;
	spinlock_t spinlock;
};

static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};

static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
{
	u32 reg_val;
	struct ioh_gpio *chip =	container_of(gpio, struct ioh_gpio, gpio);

	mutex_lock(&chip->lock);
	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
	if (val)
		reg_val |= (1 << nr);
	else
		reg_val &= ~(1 << nr);

	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
	mutex_unlock(&chip->lock);
}

static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct ioh_gpio *chip =	container_of(gpio, struct ioh_gpio, gpio);

	return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
}

static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
				     int val)
{
	struct ioh_gpio *chip =	container_of(gpio, struct ioh_gpio, gpio);
	u32 pm;
	u32 reg_val;

	mutex_lock(&chip->lock);
	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
					((1 << num_ports[chip->ch]) - 1);
	pm |= (1 << nr);
	iowrite32(pm, &chip->reg->regs[chip->ch].pm);

	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
	if (val)
		reg_val |= (1 << nr);
	else
		reg_val &= ~(1 << nr);
	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);

	mutex_unlock(&chip->lock);

	return 0;
}

static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	struct ioh_gpio *chip =	container_of(gpio, struct ioh_gpio, gpio);
	u32 pm;

	mutex_lock(&chip->lock);
	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
				((1 << num_ports[chip->ch]) - 1);
	pm &= ~(1 << nr);
	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
	mutex_unlock(&chip->lock);

	return 0;
}

#ifdef CONFIG_PM
/*
 * Save register configuration and disable interrupts.
 */
static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
{
	int i;

	for (i = 0; i < 8; i ++, chip++) {
		chip->ioh_gpio_reg.po_reg =
					ioread32(&chip->reg->regs[chip->ch].po);
		chip->ioh_gpio_reg.pm_reg =
					ioread32(&chip->reg->regs[chip->ch].pm);
		chip->ioh_gpio_reg.ien_reg =
				       ioread32(&chip->reg->regs[chip->ch].ien);
		chip->ioh_gpio_reg.imask_reg =
				     ioread32(&chip->reg->regs[chip->ch].imask);
		chip->ioh_gpio_reg.im0_reg =
				      ioread32(&chip->reg->regs[chip->ch].im_0);
		chip->ioh_gpio_reg.im1_reg =
				      ioread32(&chip->reg->regs[chip->ch].im_1);
		if (i < 4)
			chip->ioh_gpio_reg.use_sel_reg =
					   ioread32(&chip->reg->ioh_sel_reg[i]);
	}
}

/*
 * This function restores the register configuration of the GPIO device.
 */
static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
{
	int i;

	for (i = 0; i < 8; i ++, chip++) {
		iowrite32(chip->ioh_gpio_reg.po_reg,
			  &chip->reg->regs[chip->ch].po);
		iowrite32(chip->ioh_gpio_reg.pm_reg,
			  &chip->reg->regs[chip->ch].pm);
		iowrite32(chip->ioh_gpio_reg.ien_reg,
			  &chip->reg->regs[chip->ch].ien);
		iowrite32(chip->ioh_gpio_reg.imask_reg,
			  &chip->reg->regs[chip->ch].imask);
		iowrite32(chip->ioh_gpio_reg.im0_reg,
			  &chip->reg->regs[chip->ch].im_0);
		iowrite32(chip->ioh_gpio_reg.im1_reg,
			  &chip->reg->regs[chip->ch].im_1);
		if (i < 4)
			iowrite32(chip->ioh_gpio_reg.use_sel_reg,
				  &chip->reg->ioh_sel_reg[i]);
	}
}
#endif

static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	return chip->irq_base + offset;
}

static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
{
	struct gpio_chip *gpio = &chip->gpio;

	gpio->label = dev_name(chip->dev);
	gpio->owner = THIS_MODULE;
	gpio->direction_input = ioh_gpio_direction_input;
	gpio->get = ioh_gpio_get;
	gpio->direction_output = ioh_gpio_direction_output;
	gpio->set = ioh_gpio_set;
	gpio->dbg_show = NULL;
	gpio->base = -1;
	gpio->ngpio = num_port;
	gpio->can_sleep = 0;
	gpio->to_irq = ioh_gpio_to_irq;
}

static int ioh_irq_type(struct irq_data *d, unsigned int type)
{
	u32 im;
	u32 *im_reg;
	u32 ien;
	u32 im_pos;
	int ch;
	unsigned long flags;
	u32 val;
	int irq = d->irq;
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;

	ch = irq - chip->irq_base;
	if (irq <= chip->irq_base + 7) {
		im_reg = &chip->reg->regs[chip->ch].im_0;
		im_pos = ch;
	} else {
		im_reg = &chip->reg->regs[chip->ch].im_1;
		im_pos = ch - 8;
	}
	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
		__func__, irq, type, ch, im_pos, type);

	spin_lock_irqsave(&chip->spinlock, flags);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		val = IOH_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		val = IOH_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		val = IOH_EDGE_BOTH;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		val = IOH_LEVEL_H;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		val = IOH_LEVEL_L;
		break;
	case IRQ_TYPE_PROBE:
		goto end;
	default:
		dev_warn(chip->dev, "%s: unknown type(%dd)",
			__func__, type);
		goto end;
	}

	/* Set interrupt mode */
	im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
	iowrite32(im | (val << (im_pos * 4)), im_reg);

	/* iclr */
	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);

	/* IMASKCLR */
	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);

	/* Enable interrupt */
	ien = ioread32(&chip->reg->regs[chip->ch].ien);
	iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
end:
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

static void ioh_irq_unmask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base),
		  &chip->reg->regs[chip->ch].imaskclr);
}

static void ioh_irq_mask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct ioh_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base),
		  &chip->reg->regs[chip->ch].imask);
}

static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
{
	struct ioh_gpio *chip = dev_id;
	u32 reg_val;
	int i, j;
	int ret = IRQ_NONE;

	for (i = 0; i < 8; i++) {
		reg_val = ioread32(&chip->reg->regs[i].istatus);
		for (j = 0; j < num_ports[i]; j++) {
			if (reg_val & BIT(j)) {
				dev_dbg(chip->dev,
					"%s:[%d]:irq=%d status=0x%x\n",
					__func__, j, irq, reg_val);
				iowrite32(BIT(j),
					  &chip->reg->regs[chip->ch].iclr);
				generic_handle_irq(chip->irq_base + j);
				ret = IRQ_HANDLED;
			}
		}
	}
	return ret;
}

static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
				unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
				    handle_simple_irq);
	gc->private = chip;
	ct = gc->chip_types;

	ct->chip.irq_mask = ioh_irq_mask;
	ct->chip.irq_unmask = ioh_irq_unmask;
	ct->chip.irq_set_type = ioh_irq_type;

	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
				    const struct pci_device_id *id)
{
	int ret;
	int i, j;
	struct ioh_gpio *chip;
	void __iomem *base;
	void __iomem *chip_save;
	int irq_base;

	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
		goto err_pci_enable;
	}

	ret = pci_request_regions(pdev, KBUILD_MODNAME);
	if (ret) {
		dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
		goto err_request_regions;
	}

	base = pci_iomap(pdev, 1, 0);
	if (base == 0) {
		dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
		ret = -ENOMEM;
		goto err_iomap;
	}

	chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
	if (chip_save == NULL) {
		dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
		ret = -ENOMEM;
		goto err_kzalloc;
	}

	chip = chip_save;
	for (i = 0; i < 8; i++, chip++) {
		chip->dev = &pdev->dev;
		chip->base = base;
		chip->reg = chip->base;
		chip->ch = i;
		mutex_init(&chip->lock);
		ioh_gpio_setup(chip, num_ports[i]);
		ret = gpiochip_add(&chip->gpio);
		if (ret) {
			dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
			goto err_gpiochip_add;
		}
	}

	chip = chip_save;
	for (j = 0; j < 8; j++, chip++) {
		irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
					   NUMA_NO_NODE);
		if (irq_base < 0) {
			dev_warn(&pdev->dev,
				"ml_ioh_gpio: Failed to get IRQ base num\n");
			chip->irq_base = -1;
			goto err_irq_alloc_descs;
		}
		chip->irq_base = irq_base;
		ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
	}

	chip = chip_save;
	ret = request_irq(pdev->irq, ioh_gpio_handler,
			     IRQF_SHARED, KBUILD_MODNAME, chip);
	if (ret != 0) {
		dev_err(&pdev->dev,
			"%s request_irq failed\n", __func__);
		goto err_request_irq;
	}

	pci_set_drvdata(pdev, chip);

	return 0;

err_request_irq:
	chip = chip_save;
err_irq_alloc_descs:
	while (--j >= 0) {
		chip--;
		irq_free_descs(chip->irq_base, num_ports[j]);
	}

	chip = chip_save;
err_gpiochip_add:
	while (--i >= 0) {
		chip--;
		ret = gpiochip_remove(&chip->gpio);
		if (ret)
			dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
	}
	kfree(chip_save);

err_kzalloc:
	pci_iounmap(pdev, base);

err_iomap:
	pci_release_regions(pdev);

err_request_regions:
	pci_disable_device(pdev);

err_pci_enable:

	dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
	return ret;
}

static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
{
	int err;
	int i;
	struct ioh_gpio *chip = pci_get_drvdata(pdev);
	void __iomem *chip_save;

	chip_save = chip;

	free_irq(pdev->irq, chip);

	for (i = 0; i < 8; i++, chip++) {
		irq_free_descs(chip->irq_base, num_ports[i]);
		err = gpiochip_remove(&chip->gpio);
		if (err)
			dev_err(&pdev->dev, "Failed gpiochip_remove\n");
	}

	chip = chip_save;
	pci_iounmap(pdev, chip->base);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	kfree(chip);
}

#ifdef CONFIG_PM
static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
{
	s32 ret;
	struct ioh_gpio *chip = pci_get_drvdata(pdev);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	ioh_gpio_save_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	ret = pci_save_state(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
		return ret;
	}
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D0);
	ret = pci_enable_wake(pdev, PCI_D0, 1);
	if (ret)
		dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);

	return 0;
}

static int ioh_gpio_resume(struct pci_dev *pdev)
{
	s32 ret;
	struct ioh_gpio *chip = pci_get_drvdata(pdev);
	unsigned long flags;

	ret = pci_enable_wake(pdev, PCI_D0, 0);

	pci_set_power_state(pdev, PCI_D0);
	ret = pci_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
		return ret;
	}
	pci_restore_state(pdev);

	spin_lock_irqsave(&chip->spinlock, flags);
	iowrite32(0x01, &chip->reg->srst);
	iowrite32(0x00, &chip->reg->srst);
	ioh_gpio_restore_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}
#else
#define ioh_gpio_suspend NULL
#define ioh_gpio_resume NULL
#endif

static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);

static struct pci_driver ioh_gpio_driver = {
	.name = "ml_ioh_gpio",
	.id_table = ioh_gpio_pcidev_id,
	.probe = ioh_gpio_probe,
	.remove = __devexit_p(ioh_gpio_remove),
	.suspend = ioh_gpio_suspend,
	.resume = ioh_gpio_resume
};

static int __init ioh_gpio_pci_init(void)
{
	return pci_register_driver(&ioh_gpio_driver);
}
module_init(ioh_gpio_pci_init);

static void __exit ioh_gpio_pci_exit(void)
{
	pci_unregister_driver(&ioh_gpio_driver);
}
module_exit(ioh_gpio_pci_exit);

MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
49a36793 TM	1	/*
	2	* Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; version 2 of the License.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, write to the Free Software
	15	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
	16	*/
	17	#include <linux/kernel.h>
545554e7	18	#include <linux/slab.h>
49a36793 TM	19	#include <linux/pci.h>
49a36793 TM	20	#include <linux/gpio.h>
54be5663 TM	21	#include <linux/interrupt.h>
	22	#include <linux/irq.h>
	23
	24	#define IOH_EDGE_FALLING 0
	25	#define IOH_EDGE_RISING BIT(0)
	26	#define IOH_LEVEL_L BIT(1)
	27	#define IOH_LEVEL_H (BIT(0) \| BIT(1))
	28	#define IOH_EDGE_BOTH BIT(2)
	29	#define IOH_IM_MASK (BIT(0) \| BIT(1) \| BIT(2))
	30
	31	#define IOH_IRQ_BASE 0
49a36793 TM	32
	33	#define PCI_VENDOR_ID_ROHM 0x10DB
	34
	35	struct ioh_reg_comn {
	36	u32 ien;
	37	u32 istatus;
	38	u32 idisp;
	39	u32 iclr;
	40	u32 imask;
	41	u32 imaskclr;
	42	u32 po;
	43	u32 pi;
	44	u32 pm;
	45	u32 im_0;
	46	u32 im_1;
	47	u32 reserved;
	48	};
	49
	50	struct ioh_regs {
	51	struct ioh_reg_comn regs[8];
	52	u32 reserve1[16];
	53	u32 ioh_sel_reg[4];
	54	u32 reserve2[11];
	55	u32 srst;
	56	};
	57
	58	/**
	59	* struct ioh_gpio_reg_data - The register store data.
54be5663 TM	60	* @ien_reg To store contents of interrupt enable register.
54be5663 TM	61	* @imask_reg: To store contents of interrupt mask regist
49a36793 TM	62	* @po_reg: To store contents of PO register.
49a36793 TM	63	* @pm_reg: To store contents of PM register.
54be5663 TM	64	* @im0_reg: To store contents of interrupt mode regist0
54be5663 TM	65	* @im1_reg: To store contents of interrupt mode regist1
b490fa0b	66	* @use_sel_reg: To store contents of GPIO_USE_SEL0~3
49a36793 TM	67	*/
49a36793 TM	68	struct ioh_gpio_reg_data {
54be5663 TM	69	u32 ien_reg;
54be5663 TM	70	u32 imask_reg;
49a36793 TM	71	u32 po_reg;
49a36793 TM	72	u32 pm_reg;
54be5663 TM	73	u32 im0_reg;
54be5663 TM	74	u32 im1_reg;
b490fa0b	75	u32 use_sel_reg;
49a36793 TM	76	};
	77
	78	/**
	79	* struct ioh_gpio - GPIO private data structure.
	80	* @base: PCI base address of Memory mapped I/O register.
	81	* @reg: Memory mapped IOH GPIO register list.
	82	* @dev: Pointer to device structure.
	83	* @gpio: Data for GPIO infrastructure.
	84	* @ioh_gpio_reg: Memory mapped Register data is saved here
	85	* when suspend.
b490fa0b	86	* @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
49a36793	87	* @ch: Indicate GPIO channel
54be5663 TM	88	* @irq_base: Save base of IRQ number for interrupt
	89	* @spinlock: Used for register access protection in
	90	* interrupt context ioh_irq_type and PM;
49a36793 TM	91	*/
	92	struct ioh_gpio {
	93	void __iomem *base;
	94	struct ioh_regs __iomem *reg;
	95	struct device *dev;
	96	struct gpio_chip gpio;
	97	struct ioh_gpio_reg_data ioh_gpio_reg;
b490fa0b	98	u32 gpio_use_sel;
49a36793 TM	99	struct mutex lock;
49a36793 TM	100	int ch;
54be5663 TM	101	int irq_base;
54be5663 TM	102	spinlock_t spinlock;
49a36793 TM	103	};
	104
	105	static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
	106
	107	static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
	108	{
	109	u32 reg_val;
	110	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	111
	112	mutex_lock(&chip->lock);
	113	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
	114	if (val)
	115	reg_val \|= (1 << nr);
	116	else
	117	reg_val &= ~(1 << nr);
	118
	119	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
	120	mutex_unlock(&chip->lock);
	121	}
	122
	123	static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
	124	{
	125	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	126
	127	return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
	128	}
	129
	130	static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	131	int val)
	132	{
	133	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	134	u32 pm;
	135	u32 reg_val;
	136
	137	mutex_lock(&chip->lock);
	138	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
	139	((1 << num_ports[chip->ch]) - 1);
	140	pm \|= (1 << nr);
	141	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
	142
	143	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
	144	if (val)
	145	reg_val \|= (1 << nr);
	146	else
	147	reg_val &= ~(1 << nr);
ba438612	148	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
49a36793 TM	149
	150	mutex_unlock(&chip->lock);
	151
	152	return 0;
	153	}
	154
	155	static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	156	{
	157	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	158	u32 pm;
	159
	160	mutex_lock(&chip->lock);
	161	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
	162	((1 << num_ports[chip->ch]) - 1);
	163	pm &= ~(1 << nr);
	164	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
	165	mutex_unlock(&chip->lock);
	166
	167	return 0;
	168	}
	169
545554e7	170	#ifdef CONFIG_PM
49a36793 TM	171	/*
	172	* Save register configuration and disable interrupts.
	173	*/
	174	static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
	175	{
b490fa0b TM	176	int i;
	177
	178	for (i = 0; i < 8; i ++, chip++) {
	179	chip->ioh_gpio_reg.po_reg =
	180	ioread32(&chip->reg->regs[chip->ch].po);
	181	chip->ioh_gpio_reg.pm_reg =
	182	ioread32(&chip->reg->regs[chip->ch].pm);
	183	chip->ioh_gpio_reg.ien_reg =
	184	ioread32(&chip->reg->regs[chip->ch].ien);
	185	chip->ioh_gpio_reg.imask_reg =
	186	ioread32(&chip->reg->regs[chip->ch].imask);
	187	chip->ioh_gpio_reg.im0_reg =
	188	ioread32(&chip->reg->regs[chip->ch].im_0);
	189	chip->ioh_gpio_reg.im1_reg =
	190	ioread32(&chip->reg->regs[chip->ch].im_1);
	191	if (i < 4)
	192	chip->ioh_gpio_reg.use_sel_reg =
	193	ioread32(&chip->reg->ioh_sel_reg[i]);
	194	}
49a36793 TM	195	}
	196
	197	/*
	198	* This function restores the register configuration of the GPIO device.
	199	*/
	200	static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
	201	{
b490fa0b TM	202	int i;
	203
	204	for (i = 0; i < 8; i ++, chip++) {
	205	iowrite32(chip->ioh_gpio_reg.po_reg,
	206	&chip->reg->regs[chip->ch].po);
	207	iowrite32(chip->ioh_gpio_reg.pm_reg,
	208	&chip->reg->regs[chip->ch].pm);
	209	iowrite32(chip->ioh_gpio_reg.ien_reg,
	210	&chip->reg->regs[chip->ch].ien);
	211	iowrite32(chip->ioh_gpio_reg.imask_reg,
	212	&chip->reg->regs[chip->ch].imask);
	213	iowrite32(chip->ioh_gpio_reg.im0_reg,
	214	&chip->reg->regs[chip->ch].im_0);
	215	iowrite32(chip->ioh_gpio_reg.im1_reg,
	216	&chip->reg->regs[chip->ch].im_1);
	217	if (i < 4)
	218	iowrite32(chip->ioh_gpio_reg.use_sel_reg,
	219	&chip->reg->ioh_sel_reg[i]);
	220	}
49a36793	221	}
545554e7	222	#endif
49a36793	223
54be5663 TM	224	static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
	225	{
	226	struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
	227	return chip->irq_base + offset;
	228	}
	229
49a36793 TM	230	static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
	231	{
	232	struct gpio_chip *gpio = &chip->gpio;
	233
	234	gpio->label = dev_name(chip->dev);
	235	gpio->owner = THIS_MODULE;
	236	gpio->direction_input = ioh_gpio_direction_input;
	237	gpio->get = ioh_gpio_get;
	238	gpio->direction_output = ioh_gpio_direction_output;
	239	gpio->set = ioh_gpio_set;
	240	gpio->dbg_show = NULL;
	241	gpio->base = -1;
	242	gpio->ngpio = num_port;
	243	gpio->can_sleep = 0;
54be5663 TM	244	gpio->to_irq = ioh_gpio_to_irq;
	245	}
	246
	247	static int ioh_irq_type(struct irq_data *d, unsigned int type)
	248	{
	249	u32 im;
	250	u32 *im_reg;
	251	u32 ien;
	252	u32 im_pos;
	253	int ch;
	254	unsigned long flags;
	255	u32 val;
	256	int irq = d->irq;
	257	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	258	struct ioh_gpio *chip = gc->private;
	259
	260	ch = irq - chip->irq_base;
	261	if (irq <= chip->irq_base + 7) {
	262	im_reg = &chip->reg->regs[chip->ch].im_0;
	263	im_pos = ch;
	264	} else {
	265	im_reg = &chip->reg->regs[chip->ch].im_1;
	266	im_pos = ch - 8;
	267	}
	268	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
	269	__func__, irq, type, ch, im_pos, type);
	270
	271	spin_lock_irqsave(&chip->spinlock, flags);
	272
	273	switch (type) {
	274	case IRQ_TYPE_EDGE_RISING:
	275	val = IOH_EDGE_RISING;
	276	break;
	277	case IRQ_TYPE_EDGE_FALLING:
	278	val = IOH_EDGE_FALLING;
	279	break;
	280	case IRQ_TYPE_EDGE_BOTH:
	281	val = IOH_EDGE_BOTH;
	282	break;
	283	case IRQ_TYPE_LEVEL_HIGH:
	284	val = IOH_LEVEL_H;
	285	break;
	286	case IRQ_TYPE_LEVEL_LOW:
	287	val = IOH_LEVEL_L;
	288	break;
	289	case IRQ_TYPE_PROBE:
	290	goto end;
	291	default:
	292	dev_warn(chip->dev, "%s: unknown type(%dd)",
	293	__func__, type);
	294	goto end;
	295	}
	296
	297	/* Set interrupt mode */
	298	im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
	299	iowrite32(im \| (val << (im_pos * 4)), im_reg);
	300
	301	/* iclr */
	302	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
	303
	304	/* IMASKCLR */
	305	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
	306
	307	/* Enable interrupt */
308	ien = ioread32(&chip->reg->regs[chip->ch].ien);
309	iowrite32(ien \| BIT(ch), &chip->reg->regs[chip->ch].ien);
310	end:
311	spin_unlock_irqrestore(&chip->spinlock, flags);
312
313	return 0;
314	}
315
316	static void ioh_irq_unmask(struct irq_data *d)
317	{
318	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
319	struct ioh_gpio *chip = gc->private;
320
321	iowrite32(1 << (d->irq - chip->irq_base),
322	&chip->reg->regs[chip->ch].imaskclr);
323	}
324
325	static void ioh_irq_mask(struct irq_data *d)
326	{
327	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
328	struct ioh_gpio *chip = gc->private;
329
330	iowrite32(1 << (d->irq - chip->irq_base),
331	&chip->reg->regs[chip->ch].imask);
332	}
333
334	static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
335	{
336	struct ioh_gpio *chip = dev_id;
337	u32 reg_val;
338	int i, j;
339	int ret = IRQ_NONE;
340
341	for (i = 0; i < 8; i++) {
342	reg_val = ioread32(&chip->reg->regs[i].istatus);
343	for (j = 0; j < num_ports[i]; j++) {
344	if (reg_val & BIT(j)) {
345	dev_dbg(chip->dev,
346	"%s:[%d]:irq=%d status=0x%x\n",
347	__func__, j, irq, reg_val);
348	iowrite32(BIT(j),
349	&chip->reg->regs[chip->ch].iclr);
350	generic_handle_irq(chip->irq_base + j);
351	ret = IRQ_HANDLED;
352	}
353	}
354	}
355	return ret;
356	}
357
358	static __devinit void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
359	unsigned int irq_start, unsigned int num)
360	{
361	struct irq_chip_generic *gc;
362	struct irq_chip_type *ct;
363
364	gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
365	handle_simple_irq);
366	gc->private = chip;
367	ct = gc->chip_types;
368
369	ct->chip.irq_mask = ioh_irq_mask;
370	ct->chip.irq_unmask = ioh_irq_unmask;
371	ct->chip.irq_set_type = ioh_irq_type;
372
373	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
374	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
49a36793 TM	375	}
	376
	377	static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
	378	const struct pci_device_id *id)
	379	{
	380	int ret;
54be5663	381	int i, j;
49a36793 TM	382	struct ioh_gpio *chip;
	383	void __iomem *base;
	384	void __iomem *chip_save;
54be5663	385	int irq_base;
49a36793 TM	386
	387	ret = pci_enable_device(pdev);
	388	if (ret) {
	389	dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
	390	goto err_pci_enable;
	391	}
	392
	393	ret = pci_request_regions(pdev, KBUILD_MODNAME);
	394	if (ret) {
	395	dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
	396	goto err_request_regions;
	397	}
	398
	399	base = pci_iomap(pdev, 1, 0);
	400	if (base == 0) {
	401	dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
	402	ret = -ENOMEM;
	403	goto err_iomap;
	404	}
	405
	406	chip_save = kzalloc(sizeof(chip) 8, GFP_KERNEL);
	407	if (chip_save == NULL) {
	408	dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
	409	ret = -ENOMEM;
	410	goto err_kzalloc;
	411	}
	412
	413	chip = chip_save;
	414	for (i = 0; i < 8; i++, chip++) {
	415	chip->dev = &pdev->dev;
	416	chip->base = base;
	417	chip->reg = chip->base;
	418	chip->ch = i;
	419	mutex_init(&chip->lock);
	420	ioh_gpio_setup(chip, num_ports[i]);
	421	ret = gpiochip_add(&chip->gpio);
	422	if (ret) {
	423	dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
	424	goto err_gpiochip_add;
	425	}
	426	}
	427
	428	chip = chip_save;
54be5663 TM	429	for (j = 0; j < 8; j++, chip++) {
54be5663 TM	430	irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
a7aaa4f8	431	NUMA_NO_NODE);
54be5663 TM	432	if (irq_base < 0) {
	433	dev_warn(&pdev->dev,
	434	"ml_ioh_gpio: Failed to get IRQ base num\n");
	435	chip->irq_base = -1;
	436	goto err_irq_alloc_descs;
	437	}
	438	chip->irq_base = irq_base;
	439	ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
	440	}
	441
	442	chip = chip_save;
	443	ret = request_irq(pdev->irq, ioh_gpio_handler,
	444	IRQF_SHARED, KBUILD_MODNAME, chip);
	445	if (ret != 0) {
	446	dev_err(&pdev->dev,
	447	"%s request_irq failed\n", __func__);
	448	goto err_request_irq;
	449	}
	450
49a36793 TM	451	pci_set_drvdata(pdev, chip);
	452
	453	return 0;
	454
54be5663 TM	455	err_request_irq:
	456	chip = chip_save;
	457	err_irq_alloc_descs:
	458	while (--j >= 0) {
	459	chip--;
	460	irq_free_descs(chip->irq_base, num_ports[j]);
	461	}
	462
	463	chip = chip_save;
49a36793	464	err_gpiochip_add:
33300571	465	while (--i >= 0) {
49a36793 TM	466	chip--;
	467	ret = gpiochip_remove(&chip->gpio);
	468	if (ret)
	469	dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
	470	}
	471	kfree(chip_save);
	472
	473	err_kzalloc:
	474	pci_iounmap(pdev, base);
	475
	476	err_iomap:
	477	pci_release_regions(pdev);
	478
	479	err_request_regions:
	480	pci_disable_device(pdev);
	481
	482	err_pci_enable:
	483
	484	dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
	485	return ret;
	486	}
	487
	488	static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
	489	{
	490	int err;
	491	int i;
	492	struct ioh_gpio *chip = pci_get_drvdata(pdev);
	493	void __iomem *chip_save;
	494
	495	chip_save = chip;
54be5663 TM	496
	497	free_irq(pdev->irq, chip);
	498
49a36793	499	for (i = 0; i < 8; i++, chip++) {
54be5663	500	irq_free_descs(chip->irq_base, num_ports[i]);
49a36793 TM	501	err = gpiochip_remove(&chip->gpio);
	502	if (err)
	503	dev_err(&pdev->dev, "Failed gpiochip_remove\n");
	504	}
	505
	506	chip = chip_save;
	507	pci_iounmap(pdev, chip->base);
	508	pci_release_regions(pdev);
	509	pci_disable_device(pdev);
	510	kfree(chip);
	511	}
	512
	513	#ifdef CONFIG_PM
	514	static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
	515	{
	516	s32 ret;
	517	struct ioh_gpio *chip = pci_get_drvdata(pdev);
b490fa0b	518	unsigned long flags;
49a36793	519
b490fa0b	520	spin_lock_irqsave(&chip->spinlock, flags);
49a36793	521	ioh_gpio_save_reg_conf(chip);
b490fa0b	522	spin_unlock_irqrestore(&chip->spinlock, flags);
49a36793 TM	523
	524	ret = pci_save_state(pdev);
	525	if (ret) {
	526	dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
	527	return ret;
	528	}
	529	pci_disable_device(pdev);
	530	pci_set_power_state(pdev, PCI_D0);
	531	ret = pci_enable_wake(pdev, PCI_D0, 1);
	532	if (ret)
	533	dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
	534
	535	return 0;
	536	}
	537
	538	static int ioh_gpio_resume(struct pci_dev *pdev)
	539	{
	540	s32 ret;
	541	struct ioh_gpio *chip = pci_get_drvdata(pdev);
b490fa0b	542	unsigned long flags;
49a36793 TM	543
	544	ret = pci_enable_wake(pdev, PCI_D0, 0);
	545
	546	pci_set_power_state(pdev, PCI_D0);
	547	ret = pci_enable_device(pdev);
	548	if (ret) {
	549	dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
	550	return ret;
	551	}
	552	pci_restore_state(pdev);
	553
b490fa0b	554	spin_lock_irqsave(&chip->spinlock, flags);
49a36793 TM	555	iowrite32(0x01, &chip->reg->srst);
	556	iowrite32(0x00, &chip->reg->srst);
	557	ioh_gpio_restore_reg_conf(chip);
b490fa0b	558	spin_unlock_irqrestore(&chip->spinlock, flags);
49a36793 TM	559
	560	return 0;
	561	}
	562	#else
	563	#define ioh_gpio_suspend NULL
	564	#define ioh_gpio_resume NULL
	565	#endif
	566
	567	static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
	568	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
	569	{ 0, }
	570	};
19234cdd	571	MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
49a36793 TM	572
	573	static struct pci_driver ioh_gpio_driver = {
	574	.name = "ml_ioh_gpio",
	575	.id_table = ioh_gpio_pcidev_id,
	576	.probe = ioh_gpio_probe,
	577	.remove = __devexit_p(ioh_gpio_remove),
	578	.suspend = ioh_gpio_suspend,
	579	.resume = ioh_gpio_resume
	580	};
	581
	582	static int __init ioh_gpio_pci_init(void)
	583	{
	584	return pci_register_driver(&ioh_gpio_driver);
	585	}
	586	module_init(ioh_gpio_pci_init);
	587
	588	static void __exit ioh_gpio_pci_exit(void)
	589	{
	590	pci_unregister_driver(&ioh_gpio_driver);
	591	}
	592	module_exit(ioh_gpio_pci_exit);
	593
	594	MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
	595	MODULE_LICENSE("GPL");