[mirror_ubuntu-hirsute-kernel.git] / drivers / gpio / gpio-mpc8xxx.c

/*
 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
 *
 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
 * Copyright (C) 2016 Freescale Semiconductor Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>

#define MPC8XXX_GPIO_PINS	32

#define GPIO_DIR		0x00
#define GPIO_ODR		0x04
#define GPIO_DAT		0x08
#define GPIO_IER		0x0c
#define GPIO_IMR		0x10
#define GPIO_ICR		0x14
#define GPIO_ICR2		0x18
#define GPIO_IBE		0x18

struct mpc8xxx_gpio_chip {
	struct gpio_chip	gc;
	void __iomem *regs;
	raw_spinlock_t lock;

	int (*direction_output)(struct gpio_chip *chip,
				unsigned offset, int value);

	struct irq_domain *irq;
	unsigned int irqn;
};

/*
 * This hardware has a big endian bit assignment such that GPIO line 0 is
 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
 * This inline helper give the right bitmask for a certain line.
 */
static inline u32 mpc_pin2mask(unsigned int offset)
{
	return BIT(31 - offset);
}

/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
 * defined as output cannot be determined by reading GPDAT register,
 * so we use shadow data register instead. The status of input pins
 * is determined by reading GPDAT register.
 */
static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	u32 val;
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	u32 out_mask, out_shadow;

	out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
	val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
	out_shadow = gc->bgpio_data & out_mask;

	return !!((val | out_shadow) & mpc_pin2mask(gpio));
}

static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
				unsigned int gpio, int val)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	/* GPIO 28..31 are input only on MPC5121 */
	if (gpio >= 28)
		return -EINVAL;

	return mpc8xxx_gc->direction_output(gc, gpio, val);
}

static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
				unsigned int gpio, int val)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	/* GPIO 0..3 are input only on MPC5125 */
	if (gpio <= 3)
		return -EINVAL;

	return mpc8xxx_gc->direction_output(gc, gpio, val);
}

static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);

	if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
		return irq_create_mapping(mpc8xxx_gc->irq, offset);
	else
		return -ENXIO;
}

static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long mask;
	int i;

	mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
		& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
	for_each_set_bit(i, &mask, 32)
		generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));

	return IRQ_HANDLED;
}

static void mpc8xxx_irq_unmask(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long flags;

	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
		gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
		| mpc_pin2mask(irqd_to_hwirq(d)));

	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static void mpc8xxx_irq_mask(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long flags;

	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
		gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
		& ~mpc_pin2mask(irqd_to_hwirq(d)));

	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static void mpc8xxx_irq_ack(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;

	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
		      mpc_pin2mask(irqd_to_hwirq(d)));
}

static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long flags;

	switch (flow_type) {
	case IRQ_TYPE_EDGE_FALLING:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
			gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
			| mpc_pin2mask(irqd_to_hwirq(d)));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_BOTH:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
			gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
			& ~mpc_pin2mask(irqd_to_hwirq(d)));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long gpio = irqd_to_hwirq(d);
	void __iomem *reg;
	unsigned int shift;
	unsigned long flags;

	if (gpio < 16) {
		reg = mpc8xxx_gc->regs + GPIO_ICR;
		shift = (15 - gpio) * 2;
	} else {
		reg = mpc8xxx_gc->regs + GPIO_ICR2;
		shift = (15 - (gpio % 16)) * 2;
	}

	switch (flow_type) {
	case IRQ_TYPE_EDGE_FALLING:
	case IRQ_TYPE_LEVEL_LOW:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
			| (2 << shift));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_RISING:
	case IRQ_TYPE_LEVEL_HIGH:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
			| (1 << shift));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_BOTH:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static struct irq_chip mpc8xxx_irq_chip = {
	.name		= "mpc8xxx-gpio",
	.irq_unmask	= mpc8xxx_irq_unmask,
	.irq_mask	= mpc8xxx_irq_mask,
	.irq_ack	= mpc8xxx_irq_ack,
	/* this might get overwritten in mpc8xxx_probe() */
	.irq_set_type	= mpc8xxx_irq_set_type,
};

static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
				irq_hw_number_t hwirq)
{
	irq_set_chip_data(irq, h->host_data);
	irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);

	return 0;
}

static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
	.map	= mpc8xxx_gpio_irq_map,
	.xlate	= irq_domain_xlate_twocell,
};

struct mpc8xxx_gpio_devtype {
	int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
	int (*gpio_get)(struct gpio_chip *, unsigned int);
	int (*irq_set_type)(struct irq_data *, unsigned int);
};

static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
	.gpio_dir_out = mpc5121_gpio_dir_out,
	.irq_set_type = mpc512x_irq_set_type,
};

static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
	.gpio_dir_out = mpc5125_gpio_dir_out,
	.irq_set_type = mpc512x_irq_set_type,
};

static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
	.gpio_get = mpc8572_gpio_get,
};

static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
	.irq_set_type = mpc8xxx_irq_set_type,
};

static const struct of_device_id mpc8xxx_gpio_ids[] = {
	{ .compatible = "fsl,mpc8349-gpio", },
	{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
	{ .compatible = "fsl,mpc8610-gpio", },
	{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
	{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
	{ .compatible = "fsl,pq3-gpio",     },
	{ .compatible = "fsl,ls1028a-gpio", },
	{ .compatible = "fsl,ls1088a-gpio", },
	{ .compatible = "fsl,qoriq-gpio",   },
	{}
};

static int mpc8xxx_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
	struct gpio_chip	*gc;
	const struct mpc8xxx_gpio_devtype *devtype =
		of_device_get_match_data(&pdev->dev);
	int ret;

	mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
	if (!mpc8xxx_gc)
		return -ENOMEM;

	platform_set_drvdata(pdev, mpc8xxx_gc);

	raw_spin_lock_init(&mpc8xxx_gc->lock);

	mpc8xxx_gc->regs = of_iomap(np, 0);
	if (!mpc8xxx_gc->regs)
		return -ENOMEM;

	gc = &mpc8xxx_gc->gc;
	gc->parent = &pdev->dev;

	if (of_property_read_bool(np, "little-endian")) {
		ret = bgpio_init(gc, &pdev->dev, 4,
				 mpc8xxx_gc->regs + GPIO_DAT,
				 NULL, NULL,
				 mpc8xxx_gc->regs + GPIO_DIR, NULL,
				 BGPIOF_BIG_ENDIAN);
		if (ret)
			goto err;
		dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
	} else {
		ret = bgpio_init(gc, &pdev->dev, 4,
				 mpc8xxx_gc->regs + GPIO_DAT,
				 NULL, NULL,
				 mpc8xxx_gc->regs + GPIO_DIR, NULL,
				 BGPIOF_BIG_ENDIAN
				 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
		if (ret)
			goto err;
		dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
	}

	mpc8xxx_gc->direction_output = gc->direction_output;

	if (!devtype)
		devtype = &mpc8xxx_gpio_devtype_default;

	/*
	 * It's assumed that only a single type of gpio controller is available
	 * on the current machine, so overwriting global data is fine.
	 */
	if (devtype->irq_set_type)
		mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;

	if (devtype->gpio_dir_out)
		gc->direction_output = devtype->gpio_dir_out;
	if (devtype->gpio_get)
		gc->get = devtype->gpio_get;

	gc->to_irq = mpc8xxx_gpio_to_irq;

	/*
	 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
	 * the input enable of each individual GPIO port.  When an individual
	 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
	 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
	 * the port value to the GPIO Data Register.
	 */
	if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
	    of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
	    of_device_is_compatible(np, "fsl,ls1088a-gpio"))
		gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);

	ret = gpiochip_add_data(gc, mpc8xxx_gc);
	if (ret) {
		pr_err("%pOF: GPIO chip registration failed with status %d\n",
		       np, ret);
		goto err;
	}

	mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
	if (!mpc8xxx_gc->irqn)
		return 0;

	mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
					&mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
	if (!mpc8xxx_gc->irq)
		return 0;

	/* ack and mask all irqs */
	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);

	ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
			       mpc8xxx_gpio_irq_cascade,
			       IRQF_SHARED, "gpio-cascade",
			       mpc8xxx_gc);
	if (ret) {
		dev_err(&pdev->dev, "%s: failed to devm_request_irq(%d), ret = %d\n",
			np->full_name, mpc8xxx_gc->irqn, ret);
		goto err;
	}

	return 0;
err:
	iounmap(mpc8xxx_gc->regs);
	return ret;
}

static int mpc8xxx_remove(struct platform_device *pdev)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);

	if (mpc8xxx_gc->irq) {
		irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
		irq_domain_remove(mpc8xxx_gc->irq);
	}

	gpiochip_remove(&mpc8xxx_gc->gc);
	iounmap(mpc8xxx_gc->regs);

	return 0;
}

static struct platform_driver mpc8xxx_plat_driver = {
	.probe		= mpc8xxx_probe,
	.remove		= mpc8xxx_remove,
	.driver		= {
		.name = "gpio-mpc8xxx",
		.of_match_table	= mpc8xxx_gpio_ids,
	},
};

static int __init mpc8xxx_init(void)
{
	return platform_driver_register(&mpc8xxx_plat_driver);
}

arch_initcall(mpc8xxx_init);
Commit	Line	Data
1e16dfc1	1	/*
42178e2a	2	* GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
1e16dfc1 PK	3	*
1e16dfc1 PK	4	* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
42178e2a	5	* Copyright (C) 2016 Freescale Semiconductor Inc.
1e16dfc1 PK	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
	14	#include <linux/spinlock.h>
	15	#include <linux/io.h>
	16	#include <linux/of.h>
	17	#include <linux/of_gpio.h>
42178e2a	18	#include <linux/of_address.h>
5af50730	19	#include <linux/of_irq.h>
98686d9a	20	#include <linux/of_platform.h>
5a0e3ad6	21	#include <linux/slab.h>
345e5c8a	22	#include <linux/irq.h>
42178e2a	23	#include <linux/gpio/driver.h>
b3222f71	24	#include <linux/bitops.h>
698b8eea	25	#include <linux/interrupt.h>
1e16dfc1 PK	26
	27	#define MPC8XXX_GPIO_PINS 32
	28
	29	#define GPIO_DIR 0x00
	30	#define GPIO_ODR 0x04
	31	#define GPIO_DAT 0x08
	32	#define GPIO_IER 0x0c
	33	#define GPIO_IMR 0x10
	34	#define GPIO_ICR 0x14
e39d5ef6	35	#define GPIO_ICR2 0x18
bd4bd337	36	#define GPIO_IBE 0x18
1e16dfc1 PK	37
1e16dfc1 PK	38	struct mpc8xxx_gpio_chip {
42178e2a LG	39	struct gpio_chip gc;
42178e2a LG	40	void __iomem *regs;
50593613	41	raw_spinlock_t lock;
1e16dfc1	42
42178e2a LG	43	int (direction_output)(struct gpio_chip chip,
	44	unsigned offset, int value);
	45
bae1d8f1	46	struct irq_domain *irq;
257e1075	47	unsigned int irqn;
1e16dfc1 PK	48	};
1e16dfc1 PK	49
b3222f71 LW	50	/*
	51	* This hardware has a big endian bit assignment such that GPIO line 0 is
	52	* connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
	53	* This inline helper give the right bitmask for a certain line.
	54	*/
	55	static inline u32 mpc_pin2mask(unsigned int offset)
	56	{
	57	return BIT(31 - offset);
	58	}
	59
c1a676df FR	60	/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
	61	* defined as output cannot be determined by reading GPDAT register,
	62	* so we use shadow data register instead. The status of input pins
	63	* is determined by reading GPDAT register.
	64	*/
	65	static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	66	{
	67	u32 val;
709d71a1	68	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
1aeef303	69	u32 out_mask, out_shadow;
c1a676df	70
cd0d3f58 AL	71	out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
cd0d3f58 AL	72	val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
42178e2a	73	out_shadow = gc->bgpio_data & out_mask;
1aeef303	74
b3222f71	75	return !!((val \| out_shadow) & mpc_pin2mask(gpio));
c1a676df FR	76	}
c1a676df FR	77
42178e2a LG	78	static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
42178e2a LG	79	unsigned int gpio, int val)
1e16dfc1	80	{
709d71a1	81	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
28538df0 WS	82	/* GPIO 28..31 are input only on MPC5121 */
	83	if (gpio >= 28)
	84	return -EINVAL;
	85
42178e2a	86	return mpc8xxx_gc->direction_output(gc, gpio, val);
28538df0 WS	87	}
28538df0 WS	88
42178e2a LG	89	static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
42178e2a LG	90	unsigned int gpio, int val)
0ba69e08	91	{
42178e2a	92	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
0ba69e08 UKK	93	/* GPIO 0..3 are input only on MPC5125 */
	94	if (gpio <= 3)
	95	return -EINVAL;
	96
42178e2a	97	return mpc8xxx_gc->direction_output(gc, gpio, val);
0ba69e08 UKK	98	}
0ba69e08 UKK	99
345e5c8a PK	100	static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
345e5c8a PK	101	{
709d71a1	102	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
345e5c8a PK	103
	104	if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
	105	return irq_create_mapping(mpc8xxx_gc->irq, offset);
	106	else
	107	return -ENXIO;
	108	}
	109
698b8eea	110	static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
345e5c8a	111	{
698b8eea	112	struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
cd0d3f58	113	struct gpio_chip *gc = &mpc8xxx_gc->gc;
698b8eea SH	114	unsigned long mask;
698b8eea SH	115	int i;
345e5c8a	116
cd0d3f58 AL	117	mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
cd0d3f58 AL	118	& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
698b8eea SH	119	for_each_set_bit(i, &mask, 32)
	120	generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));
	121
	122	return IRQ_HANDLED;
345e5c8a PK	123	}
345e5c8a PK	124
94347cb3	125	static void mpc8xxx_irq_unmask(struct irq_data *d)
345e5c8a	126	{
94347cb3	127	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a	128	struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a PK	129	unsigned long flags;
345e5c8a PK	130
50593613	131	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
345e5c8a	132
cd0d3f58 AL	133	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
cd0d3f58 AL	134	gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
b3222f71	135	\| mpc_pin2mask(irqd_to_hwirq(d)));
345e5c8a	136
50593613	137	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	138	}
345e5c8a PK	139
94347cb3	140	static void mpc8xxx_irq_mask(struct irq_data *d)
345e5c8a	141	{
94347cb3	142	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a	143	struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a PK	144	unsigned long flags;
345e5c8a PK	145
50593613	146	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
345e5c8a	147
cd0d3f58 AL	148	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
cd0d3f58 AL	149	gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
b3222f71	150	& ~mpc_pin2mask(irqd_to_hwirq(d)));
345e5c8a	151
50593613	152	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	153	}
345e5c8a PK	154
94347cb3	155	static void mpc8xxx_irq_ack(struct irq_data *d)
345e5c8a	156	{
94347cb3	157	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a	158	struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a	159
cd0d3f58	160	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
b3222f71	161	mpc_pin2mask(irqd_to_hwirq(d)));
345e5c8a PK	162	}
345e5c8a PK	163
94347cb3	164	static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
345e5c8a	165	{
94347cb3	166	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a	167	struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a PK	168	unsigned long flags;
	169
	170	switch (flow_type) {
	171	case IRQ_TYPE_EDGE_FALLING:
50593613	172	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58 AL	173	gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
cd0d3f58 AL	174	gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
b3222f71	175	\| mpc_pin2mask(irqd_to_hwirq(d)));
50593613	176	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	177	break;
	178
	179	case IRQ_TYPE_EDGE_BOTH:
50593613	180	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58 AL	181	gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
cd0d3f58 AL	182	gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
b3222f71	183	& ~mpc_pin2mask(irqd_to_hwirq(d)));
50593613	184	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	185	break;
	186
	187	default:
	188	return -EINVAL;
	189	}
	190
	191	return 0;
	192	}
	193
94347cb3	194	static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
e39d5ef6	195	{
94347cb3	196	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
cd0d3f58	197	struct gpio_chip *gc = &mpc8xxx_gc->gc;
476eb491	198	unsigned long gpio = irqd_to_hwirq(d);
e39d5ef6 AG	199	void __iomem *reg;
	200	unsigned int shift;
	201	unsigned long flags;
	202
	203	if (gpio < 16) {
42178e2a	204	reg = mpc8xxx_gc->regs + GPIO_ICR;
e39d5ef6 AG	205	shift = (15 - gpio) * 2;
e39d5ef6 AG	206	} else {
42178e2a	207	reg = mpc8xxx_gc->regs + GPIO_ICR2;
e39d5ef6 AG	208	shift = (15 - (gpio % 16)) * 2;
	209	}
	210
	211	switch (flow_type) {
	212	case IRQ_TYPE_EDGE_FALLING:
	213	case IRQ_TYPE_LEVEL_LOW:
50593613	214	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58	215	gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
42178e2a	216	\| (2 << shift));
50593613	217	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6 AG	218	break;
	219
	220	case IRQ_TYPE_EDGE_RISING:
	221	case IRQ_TYPE_LEVEL_HIGH:
50593613	222	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58	223	gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
42178e2a	224	\| (1 << shift));
50593613	225	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6 AG	226	break;
	227
	228	case IRQ_TYPE_EDGE_BOTH:
50593613	229	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58	230	gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
50593613	231	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6 AG	232	break;
	233
	234	default:
	235	return -EINVAL;
	236	}
	237
	238	return 0;
	239	}
	240
345e5c8a PK	241	static struct irq_chip mpc8xxx_irq_chip = {
345e5c8a PK	242	.name = "mpc8xxx-gpio",
94347cb3 LB	243	.irq_unmask = mpc8xxx_irq_unmask,
	244	.irq_mask = mpc8xxx_irq_mask,
	245	.irq_ack = mpc8xxx_irq_ack,
82e39b0d	246	/* this might get overwritten in mpc8xxx_probe() */
94347cb3	247	.irq_set_type = mpc8xxx_irq_set_type,
345e5c8a PK	248	};
345e5c8a PK	249
5ba17ae9 LW	250	static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
5ba17ae9 LW	251	irq_hw_number_t hwirq)
345e5c8a	252	{
5ba17ae9	253	irq_set_chip_data(irq, h->host_data);
d71cf15b	254	irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
345e5c8a PK	255
	256	return 0;
	257	}
	258
0b354dc4	259	static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
345e5c8a	260	.map = mpc8xxx_gpio_irq_map,
ff8c3ab8	261	.xlate = irq_domain_xlate_twocell,
345e5c8a PK	262	};
345e5c8a PK	263
82e39b0d UKK	264	struct mpc8xxx_gpio_devtype {
	265	int (gpio_dir_out)(struct gpio_chip , unsigned int, int);
	266	int (gpio_get)(struct gpio_chip , unsigned int);
	267	int (irq_set_type)(struct irq_data , unsigned int);
	268	};
	269
	270	static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
	271	.gpio_dir_out = mpc5121_gpio_dir_out,
	272	.irq_set_type = mpc512x_irq_set_type,
	273	};
	274
0ba69e08 UKK	275	static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
	276	.gpio_dir_out = mpc5125_gpio_dir_out,
	277	.irq_set_type = mpc512x_irq_set_type,
	278	};
	279
82e39b0d UKK	280	static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
	281	.gpio_get = mpc8572_gpio_get,
	282	};
	283
	284	static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
82e39b0d UKK	285	.irq_set_type = mpc8xxx_irq_set_type,
	286	};
	287
4183afef	288	static const struct of_device_id mpc8xxx_gpio_ids[] = {
e39d5ef6	289	{ .compatible = "fsl,mpc8349-gpio", },
82e39b0d	290	{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
e39d5ef6	291	{ .compatible = "fsl,mpc8610-gpio", },
82e39b0d	292	{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
0ba69e08	293	{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
15a5148c	294	{ .compatible = "fsl,pq3-gpio", },
3795d7cc MW	295	{ .compatible = "fsl,ls1028a-gpio", },
3795d7cc MW	296	{ .compatible = "fsl,ls1088a-gpio", },
d1dcfbbb	297	{ .compatible = "fsl,qoriq-gpio", },
e39d5ef6 AG	298	{}
	299	};
	300
98686d9a	301	static int mpc8xxx_probe(struct platform_device *pdev)
1e16dfc1	302	{
98686d9a	303	struct device_node *np = pdev->dev.of_node;
1e16dfc1	304	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
42178e2a	305	struct gpio_chip *gc;
82e39b0d UKK	306	const struct mpc8xxx_gpio_devtype *devtype =
82e39b0d UKK	307	of_device_get_match_data(&pdev->dev);
1e16dfc1 PK	308	int ret;
1e16dfc1 PK	309
98686d9a RR	310	mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
	311	if (!mpc8xxx_gc)
	312	return -ENOMEM;
1e16dfc1	313
257e1075 RR	314	platform_set_drvdata(pdev, mpc8xxx_gc);
257e1075 RR	315
50593613	316	raw_spin_lock_init(&mpc8xxx_gc->lock);
1e16dfc1	317
42178e2a LG	318	mpc8xxx_gc->regs = of_iomap(np, 0);
	319	if (!mpc8xxx_gc->regs)
	320	return -ENOMEM;
	321
	322	gc = &mpc8xxx_gc->gc;
322f6a31	323	gc->parent = &pdev->dev;
42178e2a LG	324
	325	if (of_property_read_bool(np, "little-endian")) {
	326	ret = bgpio_init(gc, &pdev->dev, 4,
	327	mpc8xxx_gc->regs + GPIO_DAT,
	328	NULL, NULL,
	329	mpc8xxx_gc->regs + GPIO_DIR, NULL,
	330	BGPIOF_BIG_ENDIAN);
	331	if (ret)
	332	goto err;
	333	dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
	334	} else {
	335	ret = bgpio_init(gc, &pdev->dev, 4,
	336	mpc8xxx_gc->regs + GPIO_DAT,
	337	NULL, NULL,
	338	mpc8xxx_gc->regs + GPIO_DIR, NULL,
	339	BGPIOF_BIG_ENDIAN
	340	\| BGPIOF_BIG_ENDIAN_BYTE_ORDER);
	341	if (ret)
	342	goto err;
	343	dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
	344	}
1e16dfc1	345
fa4007ca	346	mpc8xxx_gc->direction_output = gc->direction_output;
82e39b0d UKK	347
	348	if (!devtype)
	349	devtype = &mpc8xxx_gpio_devtype_default;
	350
	351	/*
	352	* It's assumed that only a single type of gpio controller is available
	353	* on the current machine, so overwriting global data is fine.
	354	*/
4e50573f VO	355	if (devtype->irq_set_type)
4e50573f VO	356	mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
82e39b0d	357
adf32eaa AL	358	if (devtype->gpio_dir_out)
	359	gc->direction_output = devtype->gpio_dir_out;
	360	if (devtype->gpio_get)
	361	gc->get = devtype->gpio_get;
	362
345e5c8a	363	gc->to_irq = mpc8xxx_gpio_to_irq;
1e16dfc1	364
3795d7cc MW	365	/*
	366	* The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
	367	* the input enable of each individual GPIO port. When an individual
	368	* GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
	369	* associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
	370	* the port value to the GPIO Data Register.
	371	*/
	372	if (of_device_is_compatible(np, "fsl,qoriq-gpio") \|\|
	373	of_device_is_compatible(np, "fsl,ls1028a-gpio") \|\|
	374	of_device_is_compatible(np, "fsl,ls1088a-gpio"))
787b64a4 RK	375	gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
787b64a4 RK	376
42178e2a LG	377	ret = gpiochip_add_data(gc, mpc8xxx_gc);
42178e2a LG	378	if (ret) {
7eb6ce2f RH	379	pr_err("%pOF: GPIO chip registration failed with status %d\n",
7eb6ce2f RH	380	np, ret);
42178e2a LG	381	goto err;
42178e2a LG	382	}
1e16dfc1	383
257e1075	384	mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
42178e2a	385	if (!mpc8xxx_gc->irqn)
98686d9a	386	return 0;
345e5c8a	387
a8db8cf0 GL	388	mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
a8db8cf0 GL	389	&mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
345e5c8a	390	if (!mpc8xxx_gc->irq)
98686d9a	391	return 0;
345e5c8a	392
345e5c8a	393	/* ack and mask all irqs */
cd0d3f58 AL	394	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
cd0d3f58 AL	395	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
345e5c8a	396
698b8eea SH	397	ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
698b8eea SH	398	mpc8xxx_gpio_irq_cascade,
3d5bfbd9	399	IRQF_SHARED, "gpio-cascade",
698b8eea SH	400	mpc8xxx_gc);
	401	if (ret) {
	402	dev_err(&pdev->dev, "%s: failed to devm_request_irq(%d), ret = %d\n",
	403	np->full_name, mpc8xxx_gc->irqn, ret);
	404	goto err;
	405	}
	406
257e1075	407	return 0;
42178e2a LG	408	err:
	409	iounmap(mpc8xxx_gc->regs);
	410	return ret;
257e1075 RR	411	}
	412
	413	static int mpc8xxx_remove(struct platform_device *pdev)
	414	{
	415	struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
	416
	417	if (mpc8xxx_gc->irq) {
05379818	418	irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
257e1075 RR	419	irq_domain_remove(mpc8xxx_gc->irq);
	420	}
	421
42178e2a LG	422	gpiochip_remove(&mpc8xxx_gc->gc);
42178e2a LG	423	iounmap(mpc8xxx_gc->regs);
345e5c8a	424
98686d9a	425	return 0;
1e16dfc1 PK	426	}
1e16dfc1 PK	427
98686d9a RR	428	static struct platform_driver mpc8xxx_plat_driver = {
98686d9a RR	429	.probe = mpc8xxx_probe,
257e1075	430	.remove = mpc8xxx_remove,
98686d9a RR	431	.driver = {
	432	.name = "gpio-mpc8xxx",
	433	.of_match_table = mpc8xxx_gpio_ids,
	434	},
	435	};
1e16dfc1	436
98686d9a RR	437	static int __init mpc8xxx_init(void)
	438	{
	439	return platform_driver_register(&mpc8xxx_plat_driver);
1e16dfc1	440	}
98686d9a RR	441
98686d9a RR	442	arch_initcall(mpc8xxx_init);