[mirror_ubuntu-jammy-kernel.git] / drivers / gpio / gpio-mpc8xxx.c

/*
 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
 *
 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
 * Copyright (C) 2016 Freescale Semiconductor Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/acpi.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/property.h>
#include <linux/mod_devicetable.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>

#define MPC8XXX_GPIO_PINS	32

#define GPIO_DIR		0x00
#define GPIO_ODR		0x04
#define GPIO_DAT		0x08
#define GPIO_IER		0x0c
#define GPIO_IMR		0x10
#define GPIO_ICR		0x14
#define GPIO_ICR2		0x18
#define GPIO_IBE		0x18

struct mpc8xxx_gpio_chip {
	struct gpio_chip	gc;
	void __iomem *regs;
	raw_spinlock_t lock;

	int (*direction_output)(struct gpio_chip *chip,
				unsigned offset, int value);

	struct irq_domain *irq;
	unsigned int irqn;
};

/*
 * This hardware has a big endian bit assignment such that GPIO line 0 is
 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
 * This inline helper give the right bitmask for a certain line.
 */
static inline u32 mpc_pin2mask(unsigned int offset)
{
	return BIT(31 - offset);
}

/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
 * defined as output cannot be determined by reading GPDAT register,
 * so we use shadow data register instead. The status of input pins
 * is determined by reading GPDAT register.
 */
static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	u32 val;
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	u32 out_mask, out_shadow;

	out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
	val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
	out_shadow = gc->bgpio_data & out_mask;

	return !!((val | out_shadow) & mpc_pin2mask(gpio));
}

static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
				unsigned int gpio, int val)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	/* GPIO 28..31 are input only on MPC5121 */
	if (gpio >= 28)
		return -EINVAL;

	return mpc8xxx_gc->direction_output(gc, gpio, val);
}

static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
				unsigned int gpio, int val)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
	/* GPIO 0..3 are input only on MPC5125 */
	if (gpio <= 3)
		return -EINVAL;

	return mpc8xxx_gc->direction_output(gc, gpio, val);
}

static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);

	if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
		return irq_create_mapping(mpc8xxx_gc->irq, offset);
	else
		return -ENXIO;
}

static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long mask;
	int i;

	mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
		& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
	for_each_set_bit(i, &mask, 32)
		generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));

	return IRQ_HANDLED;
}

static void mpc8xxx_irq_unmask(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long flags;

	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
		gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
		| mpc_pin2mask(irqd_to_hwirq(d)));

	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static void mpc8xxx_irq_mask(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long flags;

	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);

	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
		gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
		& ~mpc_pin2mask(irqd_to_hwirq(d)));

	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
}

static void mpc8xxx_irq_ack(struct irq_data *d)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;

	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
		      mpc_pin2mask(irqd_to_hwirq(d)));
}

static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long flags;

	switch (flow_type) {
	case IRQ_TYPE_EDGE_FALLING:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
			gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
			| mpc_pin2mask(irqd_to_hwirq(d)));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_BOTH:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
			gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
			& ~mpc_pin2mask(irqd_to_hwirq(d)));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
	struct gpio_chip *gc = &mpc8xxx_gc->gc;
	unsigned long gpio = irqd_to_hwirq(d);
	void __iomem *reg;
	unsigned int shift;
	unsigned long flags;

	if (gpio < 16) {
		reg = mpc8xxx_gc->regs + GPIO_ICR;
		shift = (15 - gpio) * 2;
	} else {
		reg = mpc8xxx_gc->regs + GPIO_ICR2;
		shift = (15 - (gpio % 16)) * 2;
	}

	switch (flow_type) {
	case IRQ_TYPE_EDGE_FALLING:
	case IRQ_TYPE_LEVEL_LOW:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
			| (2 << shift));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_RISING:
	case IRQ_TYPE_LEVEL_HIGH:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
			| (1 << shift));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	case IRQ_TYPE_EDGE_BOTH:
		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
		gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

static struct irq_chip mpc8xxx_irq_chip = {
	.name		= "mpc8xxx-gpio",
	.irq_unmask	= mpc8xxx_irq_unmask,
	.irq_mask	= mpc8xxx_irq_mask,
	.irq_ack	= mpc8xxx_irq_ack,
	/* this might get overwritten in mpc8xxx_probe() */
	.irq_set_type	= mpc8xxx_irq_set_type,
};

static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
				irq_hw_number_t hwirq)
{
	irq_set_chip_data(irq, h->host_data);
	irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);

	return 0;
}

static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
	.map	= mpc8xxx_gpio_irq_map,
	.xlate	= irq_domain_xlate_twocell,
};

struct mpc8xxx_gpio_devtype {
	int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
	int (*gpio_get)(struct gpio_chip *, unsigned int);
	int (*irq_set_type)(struct irq_data *, unsigned int);
};

static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
	.gpio_dir_out = mpc5121_gpio_dir_out,
	.irq_set_type = mpc512x_irq_set_type,
};

static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
	.gpio_dir_out = mpc5125_gpio_dir_out,
	.irq_set_type = mpc512x_irq_set_type,
};

static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
	.gpio_get = mpc8572_gpio_get,
};

static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
	.irq_set_type = mpc8xxx_irq_set_type,
};

static const struct of_device_id mpc8xxx_gpio_ids[] = {
	{ .compatible = "fsl,mpc8349-gpio", },
	{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
	{ .compatible = "fsl,mpc8610-gpio", },
	{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
	{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
	{ .compatible = "fsl,pq3-gpio",     },
	{ .compatible = "fsl,ls1028a-gpio", },
	{ .compatible = "fsl,ls1088a-gpio", },
	{ .compatible = "fsl,qoriq-gpio",   },
	{}
};

static int mpc8xxx_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
	struct gpio_chip	*gc;
	const struct mpc8xxx_gpio_devtype *devtype = NULL;
	struct fwnode_handle *fwnode;
	int ret;

	mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
	if (!mpc8xxx_gc)
		return -ENOMEM;

	platform_set_drvdata(pdev, mpc8xxx_gc);

	raw_spin_lock_init(&mpc8xxx_gc->lock);

	mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(mpc8xxx_gc->regs))
		return PTR_ERR(mpc8xxx_gc->regs);

	gc = &mpc8xxx_gc->gc;
	gc->parent = &pdev->dev;

	if (device_property_read_bool(&pdev->dev, "little-endian")) {
		ret = bgpio_init(gc, &pdev->dev, 4,
				 mpc8xxx_gc->regs + GPIO_DAT,
				 NULL, NULL,
				 mpc8xxx_gc->regs + GPIO_DIR, NULL,
				 BGPIOF_BIG_ENDIAN);
		if (ret)
			goto err;
		dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
	} else {
		ret = bgpio_init(gc, &pdev->dev, 4,
				 mpc8xxx_gc->regs + GPIO_DAT,
				 NULL, NULL,
				 mpc8xxx_gc->regs + GPIO_DIR, NULL,
				 BGPIOF_BIG_ENDIAN
				 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
		if (ret)
			goto err;
		dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
	}

	mpc8xxx_gc->direction_output = gc->direction_output;

	devtype = device_get_match_data(&pdev->dev);
	if (!devtype)
		devtype = &mpc8xxx_gpio_devtype_default;

	/*
	 * It's assumed that only a single type of gpio controller is available
	 * on the current machine, so overwriting global data is fine.
	 */
	if (devtype->irq_set_type)
		mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;

	if (devtype->gpio_dir_out)
		gc->direction_output = devtype->gpio_dir_out;
	if (devtype->gpio_get)
		gc->get = devtype->gpio_get;

	gc->to_irq = mpc8xxx_gpio_to_irq;

	/*
	 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
	 * the input enable of each individual GPIO port.  When an individual
	 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
	 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
	 * the port value to the GPIO Data Register.
	 */
	fwnode = dev_fwnode(&pdev->dev);
	if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
	    of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
	    of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
	    is_acpi_node(fwnode))
		gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);

	ret = gpiochip_add_data(gc, mpc8xxx_gc);
	if (ret) {
		dev_err(&pdev->dev,
			"GPIO chip registration failed with status %d\n", ret);
		goto err;
	}

	mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
	if (!mpc8xxx_gc->irqn)
		return 0;

	mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
						   MPC8XXX_GPIO_PINS,
						   &mpc8xxx_gpio_irq_ops,
						   mpc8xxx_gc);

	if (!mpc8xxx_gc->irq)
		return 0;

	/* ack and mask all irqs */
	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);

	ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
			       mpc8xxx_gpio_irq_cascade,
			       IRQF_SHARED, "gpio-cascade",
			       mpc8xxx_gc);
	if (ret) {
		dev_err(&pdev->dev,
			"failed to devm_request_irq(%d), ret = %d\n",
			mpc8xxx_gc->irqn, ret);
		goto err;
	}

	return 0;
err:
	if (mpc8xxx_gc->irq)
		irq_domain_remove(mpc8xxx_gc->irq);
	iounmap(mpc8xxx_gc->regs);
	return ret;
}

static int mpc8xxx_remove(struct platform_device *pdev)
{
	struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);

	if (mpc8xxx_gc->irq) {
		irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
		irq_domain_remove(mpc8xxx_gc->irq);
	}

	gpiochip_remove(&mpc8xxx_gc->gc);
	iounmap(mpc8xxx_gc->regs);

	return 0;
}

#ifdef CONFIG_ACPI
static const struct acpi_device_id gpio_acpi_ids[] = {
	{"NXP0031",},
	{ }
};
MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
#endif

static struct platform_driver mpc8xxx_plat_driver = {
	.probe		= mpc8xxx_probe,
	.remove		= mpc8xxx_remove,
	.driver		= {
		.name = "gpio-mpc8xxx",
		.of_match_table	= mpc8xxx_gpio_ids,
		.acpi_match_table = ACPI_PTR(gpio_acpi_ids),
	},
};

static int __init mpc8xxx_init(void)
{
	return platform_driver_register(&mpc8xxx_plat_driver);
}

arch_initcall(mpc8xxx_init);
Commit	Line	Data
1e16dfc1	1	/*
42178e2a	2	* GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
1e16dfc1 PK	3	*
1e16dfc1 PK	4	* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
42178e2a	5	* Copyright (C) 2016 Freescale Semiconductor Inc.
1e16dfc1 PK	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
76c47d14	12	#include <linux/acpi.h>
1e16dfc1 PK	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/spinlock.h>
	16	#include <linux/io.h>
	17	#include <linux/of.h>
	18	#include <linux/of_gpio.h>
42178e2a	19	#include <linux/of_address.h>
5af50730	20	#include <linux/of_irq.h>
98686d9a	21	#include <linux/of_platform.h>
76c47d14 RW	22	#include <linux/property.h>
76c47d14 RW	23	#include <linux/mod_devicetable.h>
5a0e3ad6	24	#include <linux/slab.h>
345e5c8a	25	#include <linux/irq.h>
42178e2a	26	#include <linux/gpio/driver.h>
b3222f71	27	#include <linux/bitops.h>
698b8eea	28	#include <linux/interrupt.h>
1e16dfc1 PK	29
	30	#define MPC8XXX_GPIO_PINS 32
	31
	32	#define GPIO_DIR 0x00
	33	#define GPIO_ODR 0x04
	34	#define GPIO_DAT 0x08
	35	#define GPIO_IER 0x0c
	36	#define GPIO_IMR 0x10
	37	#define GPIO_ICR 0x14
e39d5ef6	38	#define GPIO_ICR2 0x18
bd4bd337	39	#define GPIO_IBE 0x18
1e16dfc1 PK	40
1e16dfc1 PK	41	struct mpc8xxx_gpio_chip {
42178e2a LG	42	struct gpio_chip gc;
42178e2a LG	43	void __iomem *regs;
50593613	44	raw_spinlock_t lock;
1e16dfc1	45
42178e2a LG	46	int (direction_output)(struct gpio_chip chip,
	47	unsigned offset, int value);
	48
bae1d8f1	49	struct irq_domain *irq;
257e1075	50	unsigned int irqn;
1e16dfc1 PK	51	};
1e16dfc1 PK	52
b3222f71 LW	53	/*
	54	* This hardware has a big endian bit assignment such that GPIO line 0 is
	55	* connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
	56	* This inline helper give the right bitmask for a certain line.
	57	*/
	58	static inline u32 mpc_pin2mask(unsigned int offset)
	59	{
	60	return BIT(31 - offset);
	61	}
	62
c1a676df FR	63	/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
	64	* defined as output cannot be determined by reading GPDAT register,
	65	* so we use shadow data register instead. The status of input pins
	66	* is determined by reading GPDAT register.
	67	*/
	68	static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	69	{
	70	u32 val;
709d71a1	71	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
1aeef303	72	u32 out_mask, out_shadow;
c1a676df	73
cd0d3f58 AL	74	out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
cd0d3f58 AL	75	val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
42178e2a	76	out_shadow = gc->bgpio_data & out_mask;
1aeef303	77
b3222f71	78	return !!((val \| out_shadow) & mpc_pin2mask(gpio));
c1a676df FR	79	}
c1a676df FR	80
42178e2a LG	81	static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
42178e2a LG	82	unsigned int gpio, int val)
1e16dfc1	83	{
709d71a1	84	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
28538df0 WS	85	/* GPIO 28..31 are input only on MPC5121 */
	86	if (gpio >= 28)
	87	return -EINVAL;
	88
42178e2a	89	return mpc8xxx_gc->direction_output(gc, gpio, val);
28538df0 WS	90	}
28538df0 WS	91
42178e2a LG	92	static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
42178e2a LG	93	unsigned int gpio, int val)
0ba69e08	94	{
42178e2a	95	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
0ba69e08 UKK	96	/* GPIO 0..3 are input only on MPC5125 */
	97	if (gpio <= 3)
	98	return -EINVAL;
	99
42178e2a	100	return mpc8xxx_gc->direction_output(gc, gpio, val);
0ba69e08 UKK	101	}
0ba69e08 UKK	102
345e5c8a PK	103	static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
345e5c8a PK	104	{
709d71a1	105	struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
345e5c8a PK	106
	107	if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
	108	return irq_create_mapping(mpc8xxx_gc->irq, offset);
	109	else
	110	return -ENXIO;
	111	}
	112
698b8eea	113	static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
345e5c8a	114	{
698b8eea	115	struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
cd0d3f58	116	struct gpio_chip *gc = &mpc8xxx_gc->gc;
698b8eea SH	117	unsigned long mask;
698b8eea SH	118	int i;
345e5c8a	119
cd0d3f58 AL	120	mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
cd0d3f58 AL	121	& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
698b8eea SH	122	for_each_set_bit(i, &mask, 32)
	123	generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i));
	124
	125	return IRQ_HANDLED;
345e5c8a PK	126	}
345e5c8a PK	127
94347cb3	128	static void mpc8xxx_irq_unmask(struct irq_data *d)
345e5c8a	129	{
94347cb3	130	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a	131	struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a PK	132	unsigned long flags;
345e5c8a PK	133
50593613	134	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
345e5c8a	135
cd0d3f58 AL	136	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
cd0d3f58 AL	137	gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
b3222f71	138	\| mpc_pin2mask(irqd_to_hwirq(d)));
345e5c8a	139
50593613	140	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	141	}
345e5c8a PK	142
94347cb3	143	static void mpc8xxx_irq_mask(struct irq_data *d)
345e5c8a	144	{
94347cb3	145	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a	146	struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a PK	147	unsigned long flags;
345e5c8a PK	148
50593613	149	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
345e5c8a	150
cd0d3f58 AL	151	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
cd0d3f58 AL	152	gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
b3222f71	153	& ~mpc_pin2mask(irqd_to_hwirq(d)));
345e5c8a	154
50593613	155	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	156	}
345e5c8a PK	157
94347cb3	158	static void mpc8xxx_irq_ack(struct irq_data *d)
345e5c8a	159	{
94347cb3	160	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a	161	struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a	162
cd0d3f58	163	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
b3222f71	164	mpc_pin2mask(irqd_to_hwirq(d)));
345e5c8a PK	165	}
345e5c8a PK	166
94347cb3	167	static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
345e5c8a	168	{
94347cb3	169	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a	170	struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a PK	171	unsigned long flags;
	172
	173	switch (flow_type) {
	174	case IRQ_TYPE_EDGE_FALLING:
50593613	175	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58 AL	176	gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
cd0d3f58 AL	177	gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
b3222f71	178	\| mpc_pin2mask(irqd_to_hwirq(d)));
50593613	179	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	180	break;
	181
	182	case IRQ_TYPE_EDGE_BOTH:
50593613	183	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58 AL	184	gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
cd0d3f58 AL	185	gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
b3222f71	186	& ~mpc_pin2mask(irqd_to_hwirq(d)));
50593613	187	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a PK	188	break;
	189
	190	default:
	191	return -EINVAL;
	192	}
	193
	194	return 0;
	195	}
	196
94347cb3	197	static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
e39d5ef6	198	{
94347cb3	199	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
cd0d3f58	200	struct gpio_chip *gc = &mpc8xxx_gc->gc;
476eb491	201	unsigned long gpio = irqd_to_hwirq(d);
e39d5ef6 AG	202	void __iomem *reg;
	203	unsigned int shift;
	204	unsigned long flags;
	205
	206	if (gpio < 16) {
42178e2a	207	reg = mpc8xxx_gc->regs + GPIO_ICR;
e39d5ef6 AG	208	shift = (15 - gpio) * 2;
e39d5ef6 AG	209	} else {
42178e2a	210	reg = mpc8xxx_gc->regs + GPIO_ICR2;
e39d5ef6 AG	211	shift = (15 - (gpio % 16)) * 2;
	212	}
	213
	214	switch (flow_type) {
	215	case IRQ_TYPE_EDGE_FALLING:
	216	case IRQ_TYPE_LEVEL_LOW:
50593613	217	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58	218	gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
42178e2a	219	\| (2 << shift));
50593613	220	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6 AG	221	break;
	222
	223	case IRQ_TYPE_EDGE_RISING:
	224	case IRQ_TYPE_LEVEL_HIGH:
50593613	225	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58	226	gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
42178e2a	227	\| (1 << shift));
50593613	228	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6 AG	229	break;
	230
	231	case IRQ_TYPE_EDGE_BOTH:
50593613	232	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58	233	gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
50593613	234	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6 AG	235	break;
	236
	237	default:
	238	return -EINVAL;
	239	}
	240
	241	return 0;
	242	}
	243
345e5c8a PK	244	static struct irq_chip mpc8xxx_irq_chip = {
345e5c8a PK	245	.name = "mpc8xxx-gpio",
94347cb3 LB	246	.irq_unmask = mpc8xxx_irq_unmask,
	247	.irq_mask = mpc8xxx_irq_mask,
	248	.irq_ack = mpc8xxx_irq_ack,
82e39b0d	249	/* this might get overwritten in mpc8xxx_probe() */
94347cb3	250	.irq_set_type = mpc8xxx_irq_set_type,
345e5c8a PK	251	};
345e5c8a PK	252
5ba17ae9 LW	253	static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
5ba17ae9 LW	254	irq_hw_number_t hwirq)
345e5c8a	255	{
5ba17ae9	256	irq_set_chip_data(irq, h->host_data);
d71cf15b	257	irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
345e5c8a PK	258
	259	return 0;
	260	}
	261
0b354dc4	262	static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
345e5c8a	263	.map = mpc8xxx_gpio_irq_map,
ff8c3ab8	264	.xlate = irq_domain_xlate_twocell,
345e5c8a PK	265	};
345e5c8a PK	266
82e39b0d UKK	267	struct mpc8xxx_gpio_devtype {
	268	int (gpio_dir_out)(struct gpio_chip , unsigned int, int);
	269	int (gpio_get)(struct gpio_chip , unsigned int);
	270	int (irq_set_type)(struct irq_data , unsigned int);
	271	};
	272
	273	static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
	274	.gpio_dir_out = mpc5121_gpio_dir_out,
	275	.irq_set_type = mpc512x_irq_set_type,
	276	};
	277
0ba69e08 UKK	278	static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
	279	.gpio_dir_out = mpc5125_gpio_dir_out,
	280	.irq_set_type = mpc512x_irq_set_type,
	281	};
	282
82e39b0d UKK	283	static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
	284	.gpio_get = mpc8572_gpio_get,
	285	};
	286
	287	static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
82e39b0d UKK	288	.irq_set_type = mpc8xxx_irq_set_type,
	289	};
	290
4183afef	291	static const struct of_device_id mpc8xxx_gpio_ids[] = {
e39d5ef6	292	{ .compatible = "fsl,mpc8349-gpio", },
82e39b0d	293	{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
e39d5ef6	294	{ .compatible = "fsl,mpc8610-gpio", },
82e39b0d	295	{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
0ba69e08	296	{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
15a5148c	297	{ .compatible = "fsl,pq3-gpio", },
3795d7cc MW	298	{ .compatible = "fsl,ls1028a-gpio", },
3795d7cc MW	299	{ .compatible = "fsl,ls1088a-gpio", },
d1dcfbbb	300	{ .compatible = "fsl,qoriq-gpio", },
e39d5ef6 AG	301	{}
	302	};
	303
98686d9a	304	static int mpc8xxx_probe(struct platform_device *pdev)
1e16dfc1	305	{
98686d9a	306	struct device_node *np = pdev->dev.of_node;
1e16dfc1	307	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
42178e2a	308	struct gpio_chip *gc;
76c47d14 RW	309	const struct mpc8xxx_gpio_devtype *devtype = NULL;
76c47d14 RW	310	struct fwnode_handle *fwnode;
1e16dfc1 PK	311	int ret;
1e16dfc1 PK	312
98686d9a RR	313	mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
	314	if (!mpc8xxx_gc)
	315	return -ENOMEM;
1e16dfc1	316
257e1075 RR	317	platform_set_drvdata(pdev, mpc8xxx_gc);
257e1075 RR	318
50593613	319	raw_spin_lock_init(&mpc8xxx_gc->lock);
1e16dfc1	320
76c47d14 RW	321	mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
	322	if (IS_ERR(mpc8xxx_gc->regs))
	323	return PTR_ERR(mpc8xxx_gc->regs);
42178e2a LG	324
42178e2a LG	325	gc = &mpc8xxx_gc->gc;
322f6a31	326	gc->parent = &pdev->dev;
42178e2a	327
76c47d14	328	if (device_property_read_bool(&pdev->dev, "little-endian")) {
42178e2a LG	329	ret = bgpio_init(gc, &pdev->dev, 4,
	330	mpc8xxx_gc->regs + GPIO_DAT,
	331	NULL, NULL,
	332	mpc8xxx_gc->regs + GPIO_DIR, NULL,
	333	BGPIOF_BIG_ENDIAN);
	334	if (ret)
	335	goto err;
	336	dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
	337	} else {
	338	ret = bgpio_init(gc, &pdev->dev, 4,
	339	mpc8xxx_gc->regs + GPIO_DAT,
	340	NULL, NULL,
	341	mpc8xxx_gc->regs + GPIO_DIR, NULL,
	342	BGPIOF_BIG_ENDIAN
	343	\| BGPIOF_BIG_ENDIAN_BYTE_ORDER);
	344	if (ret)
	345	goto err;
	346	dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
	347	}
1e16dfc1	348
fa4007ca	349	mpc8xxx_gc->direction_output = gc->direction_output;
82e39b0d	350
76c47d14	351	devtype = device_get_match_data(&pdev->dev);
82e39b0d UKK	352	if (!devtype)
	353	devtype = &mpc8xxx_gpio_devtype_default;
	354
	355	/*
	356	* It's assumed that only a single type of gpio controller is available
	357	* on the current machine, so overwriting global data is fine.
	358	*/
4e50573f VO	359	if (devtype->irq_set_type)
4e50573f VO	360	mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
82e39b0d	361
adf32eaa AL	362	if (devtype->gpio_dir_out)
	363	gc->direction_output = devtype->gpio_dir_out;
	364	if (devtype->gpio_get)
	365	gc->get = devtype->gpio_get;
	366
345e5c8a	367	gc->to_irq = mpc8xxx_gpio_to_irq;
1e16dfc1	368
3795d7cc MW	369	/*
	370	* The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
	371	* the input enable of each individual GPIO port. When an individual
	372	* GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
	373	* associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
	374	* the port value to the GPIO Data Register.
	375	*/
76c47d14	376	fwnode = dev_fwnode(&pdev->dev);
3795d7cc MW	377	if (of_device_is_compatible(np, "fsl,qoriq-gpio") \|\|
3795d7cc MW	378	of_device_is_compatible(np, "fsl,ls1028a-gpio") \|\|
76c47d14 RW	379	of_device_is_compatible(np, "fsl,ls1088a-gpio") \|\|
76c47d14 RW	380	is_acpi_node(fwnode))
787b64a4 RK	381	gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
787b64a4 RK	382
42178e2a LG	383	ret = gpiochip_add_data(gc, mpc8xxx_gc);
42178e2a LG	384	if (ret) {
76c47d14 RW	385	dev_err(&pdev->dev,
76c47d14 RW	386	"GPIO chip registration failed with status %d\n", ret);
42178e2a LG	387	goto err;
42178e2a LG	388	}
1e16dfc1	389
76c47d14	390	mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
42178e2a	391	if (!mpc8xxx_gc->irqn)
98686d9a	392	return 0;
345e5c8a	393
76c47d14 RW	394	mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
	395	MPC8XXX_GPIO_PINS,
	396	&mpc8xxx_gpio_irq_ops,
	397	mpc8xxx_gc);
	398
345e5c8a	399	if (!mpc8xxx_gc->irq)
98686d9a	400	return 0;
345e5c8a	401
345e5c8a	402	/* ack and mask all irqs */
cd0d3f58 AL	403	gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
cd0d3f58 AL	404	gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
345e5c8a	405
698b8eea SH	406	ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
698b8eea SH	407	mpc8xxx_gpio_irq_cascade,
3d5bfbd9	408	IRQF_SHARED, "gpio-cascade",
698b8eea SH	409	mpc8xxx_gc);
698b8eea SH	410	if (ret) {
76c47d14 RW	411	dev_err(&pdev->dev,
	412	"failed to devm_request_irq(%d), ret = %d\n",
	413	mpc8xxx_gc->irqn, ret);
698b8eea SH	414	goto err;
	415	}
	416
257e1075	417	return 0;
42178e2a	418	err:
555bda42 CJ	419	if (mpc8xxx_gc->irq)
555bda42 CJ	420	irq_domain_remove(mpc8xxx_gc->irq);
42178e2a LG	421	iounmap(mpc8xxx_gc->regs);
42178e2a LG	422	return ret;
257e1075 RR	423	}
	424
	425	static int mpc8xxx_remove(struct platform_device *pdev)
	426	{
	427	struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
	428
	429	if (mpc8xxx_gc->irq) {
05379818	430	irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
257e1075 RR	431	irq_domain_remove(mpc8xxx_gc->irq);
	432	}
	433
42178e2a LG	434	gpiochip_remove(&mpc8xxx_gc->gc);
42178e2a LG	435	iounmap(mpc8xxx_gc->regs);
345e5c8a	436
98686d9a	437	return 0;
1e16dfc1 PK	438	}
1e16dfc1 PK	439
76c47d14 RW	440	#ifdef CONFIG_ACPI
	441	static const struct acpi_device_id gpio_acpi_ids[] = {
	442	{"NXP0031",},
	443	{ }
	444	};
	445	MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
	446	#endif
	447
98686d9a RR	448	static struct platform_driver mpc8xxx_plat_driver = {
98686d9a RR	449	.probe = mpc8xxx_probe,
257e1075	450	.remove = mpc8xxx_remove,
98686d9a RR	451	.driver = {
	452	.name = "gpio-mpc8xxx",
	453	.of_match_table = mpc8xxx_gpio_ids,
76c47d14	454	.acpi_match_table = ACPI_PTR(gpio_acpi_ids),
98686d9a RR	455	},
98686d9a RR	456	};
1e16dfc1	457
98686d9a RR	458	static int __init mpc8xxx_init(void)
	459	{
	460	return platform_driver_register(&mpc8xxx_plat_driver);
1e16dfc1	461	}
98686d9a RR	462
98686d9a RR	463	arch_initcall(mpc8xxx_init);