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1e16dfc1 1/*
42178e2a 2 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
1e16dfc1
PK
3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
42178e2a 5 * Copyright (C) 2016 Freescale Semiconductor Inc.
1e16dfc1
PK
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/spinlock.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/of_gpio.h>
42178e2a 18#include <linux/of_address.h>
5af50730 19#include <linux/of_irq.h>
98686d9a 20#include <linux/of_platform.h>
5a0e3ad6 21#include <linux/slab.h>
345e5c8a 22#include <linux/irq.h>
42178e2a 23#include <linux/gpio/driver.h>
1e16dfc1
PK
24
25#define MPC8XXX_GPIO_PINS 32
26
27#define GPIO_DIR 0x00
28#define GPIO_ODR 0x04
29#define GPIO_DAT 0x08
30#define GPIO_IER 0x0c
31#define GPIO_IMR 0x10
32#define GPIO_ICR 0x14
e39d5ef6 33#define GPIO_ICR2 0x18
1e16dfc1
PK
34
35struct mpc8xxx_gpio_chip {
42178e2a
LG
36 struct gpio_chip gc;
37 void __iomem *regs;
50593613 38 raw_spinlock_t lock;
1e16dfc1 39
42178e2a
LG
40 int (*direction_output)(struct gpio_chip *chip,
41 unsigned offset, int value);
42
bae1d8f1 43 struct irq_domain *irq;
257e1075 44 unsigned int irqn;
1e16dfc1
PK
45};
46
c1a676df
FR
47/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
48 * defined as output cannot be determined by reading GPDAT register,
49 * so we use shadow data register instead. The status of input pins
50 * is determined by reading GPDAT register.
51 */
52static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
53{
54 u32 val;
709d71a1 55 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
1aeef303 56 u32 out_mask, out_shadow;
c1a676df 57
cd0d3f58
AL
58 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
59 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
42178e2a 60 out_shadow = gc->bgpio_data & out_mask;
1aeef303 61
42178e2a 62 return !!((val | out_shadow) & gc->pin2mask(gc, gpio));
c1a676df
FR
63}
64
42178e2a
LG
65static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
66 unsigned int gpio, int val)
1e16dfc1 67{
709d71a1 68 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
28538df0
WS
69 /* GPIO 28..31 are input only on MPC5121 */
70 if (gpio >= 28)
71 return -EINVAL;
72
42178e2a 73 return mpc8xxx_gc->direction_output(gc, gpio, val);
28538df0
WS
74}
75
42178e2a
LG
76static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
77 unsigned int gpio, int val)
0ba69e08 78{
42178e2a 79 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
0ba69e08
UKK
80 /* GPIO 0..3 are input only on MPC5125 */
81 if (gpio <= 3)
82 return -EINVAL;
83
42178e2a 84 return mpc8xxx_gc->direction_output(gc, gpio, val);
0ba69e08
UKK
85}
86
345e5c8a
PK
87static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
88{
709d71a1 89 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
345e5c8a
PK
90
91 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
92 return irq_create_mapping(mpc8xxx_gc->irq, offset);
93 else
94 return -ENXIO;
95}
96
bd0b9ac4 97static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
345e5c8a 98{
ec775d0e 99 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
cfadd838 100 struct irq_chip *chip = irq_desc_get_chip(desc);
cd0d3f58 101 struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a
PK
102 unsigned int mask;
103
cd0d3f58
AL
104 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
105 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
345e5c8a
PK
106 if (mask)
107 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
108 32 - ffs(mask)));
d6de85e8
TG
109 if (chip->irq_eoi)
110 chip->irq_eoi(&desc->irq_data);
345e5c8a
PK
111}
112
94347cb3 113static void mpc8xxx_irq_unmask(struct irq_data *d)
345e5c8a 114{
94347cb3 115 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a 116 struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a
PK
117 unsigned long flags;
118
50593613 119 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
345e5c8a 120
cd0d3f58
AL
121 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
122 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
42178e2a 123 | gc->pin2mask(gc, irqd_to_hwirq(d)));
345e5c8a 124
50593613 125 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a
PK
126}
127
94347cb3 128static void mpc8xxx_irq_mask(struct irq_data *d)
345e5c8a 129{
94347cb3 130 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a 131 struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a
PK
132 unsigned long flags;
133
50593613 134 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
345e5c8a 135
cd0d3f58
AL
136 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
137 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
42178e2a 138 & ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
345e5c8a 139
50593613 140 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a
PK
141}
142
94347cb3 143static void mpc8xxx_irq_ack(struct irq_data *d)
345e5c8a 144{
94347cb3 145 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a 146 struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a 147
cd0d3f58
AL
148 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
149 gc->pin2mask(gc, irqd_to_hwirq(d)));
345e5c8a
PK
150}
151
94347cb3 152static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
345e5c8a 153{
94347cb3 154 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
42178e2a 155 struct gpio_chip *gc = &mpc8xxx_gc->gc;
345e5c8a
PK
156 unsigned long flags;
157
158 switch (flow_type) {
159 case IRQ_TYPE_EDGE_FALLING:
50593613 160 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58
AL
161 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
162 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
42178e2a 163 | gc->pin2mask(gc, irqd_to_hwirq(d)));
50593613 164 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a
PK
165 break;
166
167 case IRQ_TYPE_EDGE_BOTH:
50593613 168 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58
AL
169 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
170 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
42178e2a 171 & ~(gc->pin2mask(gc, irqd_to_hwirq(d))));
50593613 172 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
345e5c8a
PK
173 break;
174
175 default:
176 return -EINVAL;
177 }
178
179 return 0;
180}
181
94347cb3 182static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
e39d5ef6 183{
94347cb3 184 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
cd0d3f58 185 struct gpio_chip *gc = &mpc8xxx_gc->gc;
476eb491 186 unsigned long gpio = irqd_to_hwirq(d);
e39d5ef6
AG
187 void __iomem *reg;
188 unsigned int shift;
189 unsigned long flags;
190
191 if (gpio < 16) {
42178e2a 192 reg = mpc8xxx_gc->regs + GPIO_ICR;
e39d5ef6
AG
193 shift = (15 - gpio) * 2;
194 } else {
42178e2a 195 reg = mpc8xxx_gc->regs + GPIO_ICR2;
e39d5ef6
AG
196 shift = (15 - (gpio % 16)) * 2;
197 }
198
199 switch (flow_type) {
200 case IRQ_TYPE_EDGE_FALLING:
201 case IRQ_TYPE_LEVEL_LOW:
50593613 202 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58 203 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
42178e2a 204 | (2 << shift));
50593613 205 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6
AG
206 break;
207
208 case IRQ_TYPE_EDGE_RISING:
209 case IRQ_TYPE_LEVEL_HIGH:
50593613 210 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58 211 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
42178e2a 212 | (1 << shift));
50593613 213 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6
AG
214 break;
215
216 case IRQ_TYPE_EDGE_BOTH:
50593613 217 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
cd0d3f58 218 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
50593613 219 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
e39d5ef6
AG
220 break;
221
222 default:
223 return -EINVAL;
224 }
225
226 return 0;
227}
228
345e5c8a
PK
229static struct irq_chip mpc8xxx_irq_chip = {
230 .name = "mpc8xxx-gpio",
94347cb3
LB
231 .irq_unmask = mpc8xxx_irq_unmask,
232 .irq_mask = mpc8xxx_irq_mask,
233 .irq_ack = mpc8xxx_irq_ack,
82e39b0d 234 /* this might get overwritten in mpc8xxx_probe() */
94347cb3 235 .irq_set_type = mpc8xxx_irq_set_type,
345e5c8a
PK
236};
237
5ba17ae9
LW
238static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
239 irq_hw_number_t hwirq)
345e5c8a 240{
5ba17ae9 241 irq_set_chip_data(irq, h->host_data);
d71cf15b 242 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
345e5c8a
PK
243
244 return 0;
245}
246
0b354dc4 247static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
345e5c8a 248 .map = mpc8xxx_gpio_irq_map,
ff8c3ab8 249 .xlate = irq_domain_xlate_twocell,
345e5c8a
PK
250};
251
82e39b0d
UKK
252struct mpc8xxx_gpio_devtype {
253 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
254 int (*gpio_get)(struct gpio_chip *, unsigned int);
255 int (*irq_set_type)(struct irq_data *, unsigned int);
256};
257
258static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
259 .gpio_dir_out = mpc5121_gpio_dir_out,
260 .irq_set_type = mpc512x_irq_set_type,
261};
262
0ba69e08
UKK
263static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
264 .gpio_dir_out = mpc5125_gpio_dir_out,
265 .irq_set_type = mpc512x_irq_set_type,
266};
267
82e39b0d
UKK
268static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
269 .gpio_get = mpc8572_gpio_get,
270};
271
272static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
82e39b0d
UKK
273 .irq_set_type = mpc8xxx_irq_set_type,
274};
275
4183afef 276static const struct of_device_id mpc8xxx_gpio_ids[] = {
e39d5ef6 277 { .compatible = "fsl,mpc8349-gpio", },
82e39b0d 278 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
e39d5ef6 279 { .compatible = "fsl,mpc8610-gpio", },
82e39b0d 280 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
0ba69e08 281 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
15a5148c 282 { .compatible = "fsl,pq3-gpio", },
d1dcfbbb 283 { .compatible = "fsl,qoriq-gpio", },
e39d5ef6
AG
284 {}
285};
286
98686d9a 287static int mpc8xxx_probe(struct platform_device *pdev)
1e16dfc1 288{
98686d9a 289 struct device_node *np = pdev->dev.of_node;
1e16dfc1 290 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
42178e2a 291 struct gpio_chip *gc;
82e39b0d
UKK
292 const struct mpc8xxx_gpio_devtype *devtype =
293 of_device_get_match_data(&pdev->dev);
1e16dfc1
PK
294 int ret;
295
98686d9a
RRD
296 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
297 if (!mpc8xxx_gc)
298 return -ENOMEM;
1e16dfc1 299
257e1075
RRD
300 platform_set_drvdata(pdev, mpc8xxx_gc);
301
50593613 302 raw_spin_lock_init(&mpc8xxx_gc->lock);
1e16dfc1 303
42178e2a
LG
304 mpc8xxx_gc->regs = of_iomap(np, 0);
305 if (!mpc8xxx_gc->regs)
306 return -ENOMEM;
307
308 gc = &mpc8xxx_gc->gc;
309
310 if (of_property_read_bool(np, "little-endian")) {
311 ret = bgpio_init(gc, &pdev->dev, 4,
312 mpc8xxx_gc->regs + GPIO_DAT,
313 NULL, NULL,
314 mpc8xxx_gc->regs + GPIO_DIR, NULL,
315 BGPIOF_BIG_ENDIAN);
316 if (ret)
317 goto err;
318 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
319 } else {
320 ret = bgpio_init(gc, &pdev->dev, 4,
321 mpc8xxx_gc->regs + GPIO_DAT,
322 NULL, NULL,
323 mpc8xxx_gc->regs + GPIO_DIR, NULL,
324 BGPIOF_BIG_ENDIAN
325 | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
326 if (ret)
327 goto err;
328 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
329 }
1e16dfc1 330
fa4007ca 331 mpc8xxx_gc->direction_output = gc->direction_output;
82e39b0d
UKK
332
333 if (!devtype)
334 devtype = &mpc8xxx_gpio_devtype_default;
335
336 /*
337 * It's assumed that only a single type of gpio controller is available
338 * on the current machine, so overwriting global data is fine.
339 */
340 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
341
adf32eaa
AL
342 if (devtype->gpio_dir_out)
343 gc->direction_output = devtype->gpio_dir_out;
344 if (devtype->gpio_get)
345 gc->get = devtype->gpio_get;
346
345e5c8a 347 gc->to_irq = mpc8xxx_gpio_to_irq;
1e16dfc1 348
42178e2a
LG
349 ret = gpiochip_add_data(gc, mpc8xxx_gc);
350 if (ret) {
351 pr_err("%s: GPIO chip registration failed with status %d\n",
352 np->full_name, ret);
353 goto err;
354 }
1e16dfc1 355
257e1075 356 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
42178e2a 357 if (!mpc8xxx_gc->irqn)
98686d9a 358 return 0;
345e5c8a 359
a8db8cf0
GL
360 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
361 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
345e5c8a 362 if (!mpc8xxx_gc->irq)
98686d9a 363 return 0;
345e5c8a 364
345e5c8a 365 /* ack and mask all irqs */
cd0d3f58
AL
366 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
367 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
345e5c8a 368
05379818
TG
369 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
370 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
257e1075 371 return 0;
42178e2a
LG
372err:
373 iounmap(mpc8xxx_gc->regs);
374 return ret;
257e1075
RRD
375}
376
377static int mpc8xxx_remove(struct platform_device *pdev)
378{
379 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
380
381 if (mpc8xxx_gc->irq) {
05379818 382 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
257e1075
RRD
383 irq_domain_remove(mpc8xxx_gc->irq);
384 }
385
42178e2a
LG
386 gpiochip_remove(&mpc8xxx_gc->gc);
387 iounmap(mpc8xxx_gc->regs);
345e5c8a 388
98686d9a 389 return 0;
1e16dfc1
PK
390}
391
98686d9a
RRD
392static struct platform_driver mpc8xxx_plat_driver = {
393 .probe = mpc8xxx_probe,
257e1075 394 .remove = mpc8xxx_remove,
98686d9a
RRD
395 .driver = {
396 .name = "gpio-mpc8xxx",
397 .of_match_table = mpc8xxx_gpio_ids,
398 },
399};
1e16dfc1 400
98686d9a
RRD
401static int __init mpc8xxx_init(void)
402{
403 return platform_driver_register(&mpc8xxx_plat_driver);
1e16dfc1 404}
98686d9a
RRD
405
406arch_initcall(mpc8xxx_init);