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fefe7b09 TP |
1 | /* |
2 | * GPIO driver for Marvell SoCs | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
7 | * Andrew Lunn <andrew@lunn.ch> | |
8 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | * | |
14 | * This driver is a fairly straightforward GPIO driver for the | |
15 | * complete family of Marvell EBU SoC platforms (Orion, Dove, | |
16 | * Kirkwood, Discovery, Armada 370/XP). The only complexity of this | |
17 | * driver is the different register layout that exists between the | |
18 | * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP | |
19 | * platforms (MV78200 from the Discovery family and the Armada | |
20 | * XP). Therefore, this driver handles three variants of the GPIO | |
21 | * block: | |
22 | * - the basic variant, called "orion-gpio", with the simplest | |
23 | * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and | |
24 | * non-SMP Discovery systems | |
25 | * - the mv78200 variant for MV78200 Discovery systems. This variant | |
26 | * turns the edge mask and level mask registers into CPU0 edge | |
27 | * mask/level mask registers, and adds CPU1 edge mask/level mask | |
28 | * registers. | |
29 | * - the armadaxp variant for Armada XP systems. This variant keeps | |
30 | * the normal cause/edge mask/level mask registers when the global | |
31 | * interrupts are used, but adds per-CPU cause/edge mask/level mask | |
32 | * registers n a separate memory area for the per-CPU GPIO | |
33 | * interrupts. | |
34 | */ | |
35 | ||
641d0342 | 36 | #include <linux/err.h> |
ed329f3a | 37 | #include <linux/init.h> |
fefe7b09 TP |
38 | #include <linux/gpio.h> |
39 | #include <linux/irq.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/irqdomain.h> | |
42 | #include <linux/io.h> | |
43 | #include <linux/of_irq.h> | |
44 | #include <linux/of_device.h> | |
de88747f | 45 | #include <linux/clk.h> |
fefe7b09 | 46 | #include <linux/pinctrl/consumer.h> |
01ca59f1 | 47 | #include <linux/irqchip/chained_irq.h> |
d2cabc4a | 48 | #include <linux/bitops.h> |
fefe7b09 TP |
49 | |
50 | /* | |
51 | * GPIO unit register offsets. | |
52 | */ | |
53 | #define GPIO_OUT_OFF 0x0000 | |
54 | #define GPIO_IO_CONF_OFF 0x0004 | |
55 | #define GPIO_BLINK_EN_OFF 0x0008 | |
56 | #define GPIO_IN_POL_OFF 0x000c | |
57 | #define GPIO_DATA_IN_OFF 0x0010 | |
58 | #define GPIO_EDGE_CAUSE_OFF 0x0014 | |
59 | #define GPIO_EDGE_MASK_OFF 0x0018 | |
60 | #define GPIO_LEVEL_MASK_OFF 0x001c | |
61 | ||
62 | /* The MV78200 has per-CPU registers for edge mask and level mask */ | |
a4319a61 | 63 | #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) |
fefe7b09 TP |
64 | #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) |
65 | ||
7077f4cc RS |
66 | /* |
67 | * The Armada XP has per-CPU registers for interrupt cause, interrupt | |
fefe7b09 | 68 | * mask and interrupt level mask. Those are relative to the |
7077f4cc RS |
69 | * percpu_membase. |
70 | */ | |
fefe7b09 TP |
71 | #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) |
72 | #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) | |
73 | #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) | |
74 | ||
a4319a61 AL |
75 | #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 |
76 | #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 | |
fefe7b09 TP |
77 | #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 |
78 | ||
a4319a61 | 79 | #define MVEBU_MAX_GPIO_PER_BANK 32 |
fefe7b09 TP |
80 | |
81 | struct mvebu_gpio_chip { | |
82 | struct gpio_chip chip; | |
83 | spinlock_t lock; | |
84 | void __iomem *membase; | |
85 | void __iomem *percpu_membase; | |
d5359226 | 86 | int irqbase; |
fefe7b09 | 87 | struct irq_domain *domain; |
a4319a61 | 88 | int soc_variant; |
b5b7b487 | 89 | |
a4319a61 | 90 | /* Used to preserve GPIO registers across suspend/resume */ |
f4c240ca RS |
91 | u32 out_reg; |
92 | u32 io_conf_reg; | |
93 | u32 blink_en_reg; | |
94 | u32 in_pol_reg; | |
95 | u32 edge_mask_regs[4]; | |
96 | u32 level_mask_regs[4]; | |
fefe7b09 TP |
97 | }; |
98 | ||
99 | /* | |
100 | * Functions returning addresses of individual registers for a given | |
101 | * GPIO controller. | |
102 | */ | |
f07708c4 | 103 | static void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip) |
fefe7b09 TP |
104 | { |
105 | return mvchip->membase + GPIO_OUT_OFF; | |
106 | } | |
107 | ||
f07708c4 | 108 | static void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip) |
e9133760 JL |
109 | { |
110 | return mvchip->membase + GPIO_BLINK_EN_OFF; | |
111 | } | |
112 | ||
f07708c4 | 113 | static void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) |
fefe7b09 TP |
114 | { |
115 | return mvchip->membase + GPIO_IO_CONF_OFF; | |
116 | } | |
117 | ||
f07708c4 | 118 | static void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip) |
fefe7b09 TP |
119 | { |
120 | return mvchip->membase + GPIO_IN_POL_OFF; | |
121 | } | |
122 | ||
f07708c4 | 123 | static void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) |
fefe7b09 TP |
124 | { |
125 | return mvchip->membase + GPIO_DATA_IN_OFF; | |
126 | } | |
127 | ||
f07708c4 | 128 | static void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) |
fefe7b09 TP |
129 | { |
130 | int cpu; | |
131 | ||
f4dcd2d9 | 132 | switch (mvchip->soc_variant) { |
fefe7b09 TP |
133 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
134 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
135 | return mvchip->membase + GPIO_EDGE_CAUSE_OFF; | |
136 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
137 | cpu = smp_processor_id(); | |
a4319a61 AL |
138 | return mvchip->percpu_membase + |
139 | GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); | |
fefe7b09 TP |
140 | default: |
141 | BUG(); | |
142 | } | |
143 | } | |
144 | ||
f07708c4 | 145 | static void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) |
fefe7b09 TP |
146 | { |
147 | int cpu; | |
148 | ||
f4dcd2d9 | 149 | switch (mvchip->soc_variant) { |
fefe7b09 TP |
150 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
151 | return mvchip->membase + GPIO_EDGE_MASK_OFF; | |
152 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
153 | cpu = smp_processor_id(); | |
154 | return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); | |
155 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
156 | cpu = smp_processor_id(); | |
a4319a61 AL |
157 | return mvchip->percpu_membase + |
158 | GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); | |
fefe7b09 TP |
159 | default: |
160 | BUG(); | |
161 | } | |
162 | } | |
163 | ||
164 | static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip) | |
165 | { | |
166 | int cpu; | |
167 | ||
f4dcd2d9 | 168 | switch (mvchip->soc_variant) { |
fefe7b09 TP |
169 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
170 | return mvchip->membase + GPIO_LEVEL_MASK_OFF; | |
171 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
172 | cpu = smp_processor_id(); | |
173 | return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); | |
174 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
175 | cpu = smp_processor_id(); | |
a4319a61 AL |
176 | return mvchip->percpu_membase + |
177 | GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); | |
fefe7b09 TP |
178 | default: |
179 | BUG(); | |
180 | } | |
181 | } | |
182 | ||
183 | /* | |
184 | * Functions implementing the gpio_chip methods | |
185 | */ | |
d276de70 | 186 | static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) |
fefe7b09 | 187 | { |
bbe76004 | 188 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
fefe7b09 TP |
189 | unsigned long flags; |
190 | u32 u; | |
191 | ||
192 | spin_lock_irqsave(&mvchip->lock, flags); | |
193 | u = readl_relaxed(mvebu_gpioreg_out(mvchip)); | |
194 | if (value) | |
d2cabc4a | 195 | u |= BIT(pin); |
fefe7b09 | 196 | else |
d2cabc4a | 197 | u &= ~BIT(pin); |
fefe7b09 TP |
198 | writel_relaxed(u, mvebu_gpioreg_out(mvchip)); |
199 | spin_unlock_irqrestore(&mvchip->lock, flags); | |
200 | } | |
201 | ||
d276de70 | 202 | static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) |
fefe7b09 | 203 | { |
bbe76004 | 204 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
fefe7b09 TP |
205 | u32 u; |
206 | ||
d2cabc4a | 207 | if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & BIT(pin)) { |
fefe7b09 TP |
208 | u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^ |
209 | readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
210 | } else { | |
211 | u = readl_relaxed(mvebu_gpioreg_out(mvchip)); | |
212 | } | |
213 | ||
214 | return (u >> pin) & 1; | |
215 | } | |
216 | ||
d276de70 RS |
217 | static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, |
218 | int value) | |
e9133760 | 219 | { |
bbe76004 | 220 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
e9133760 JL |
221 | unsigned long flags; |
222 | u32 u; | |
223 | ||
224 | spin_lock_irqsave(&mvchip->lock, flags); | |
225 | u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); | |
226 | if (value) | |
d2cabc4a | 227 | u |= BIT(pin); |
e9133760 | 228 | else |
d2cabc4a | 229 | u &= ~BIT(pin); |
e9133760 JL |
230 | writel_relaxed(u, mvebu_gpioreg_blink(mvchip)); |
231 | spin_unlock_irqrestore(&mvchip->lock, flags); | |
232 | } | |
233 | ||
d276de70 | 234 | static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) |
fefe7b09 | 235 | { |
bbe76004 | 236 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
fefe7b09 TP |
237 | unsigned long flags; |
238 | int ret; | |
239 | u32 u; | |
240 | ||
7077f4cc RS |
241 | /* |
242 | * Check with the pinctrl driver whether this pin is usable as | |
243 | * an input GPIO | |
244 | */ | |
fefe7b09 TP |
245 | ret = pinctrl_gpio_direction_input(chip->base + pin); |
246 | if (ret) | |
247 | return ret; | |
248 | ||
249 | spin_lock_irqsave(&mvchip->lock, flags); | |
250 | u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); | |
d2cabc4a | 251 | u |= BIT(pin); |
fefe7b09 TP |
252 | writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); |
253 | spin_unlock_irqrestore(&mvchip->lock, flags); | |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
d276de70 | 258 | static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, |
fefe7b09 TP |
259 | int value) |
260 | { | |
bbe76004 | 261 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
fefe7b09 TP |
262 | unsigned long flags; |
263 | int ret; | |
264 | u32 u; | |
265 | ||
7077f4cc RS |
266 | /* |
267 | * Check with the pinctrl driver whether this pin is usable as | |
268 | * an output GPIO | |
269 | */ | |
fefe7b09 TP |
270 | ret = pinctrl_gpio_direction_output(chip->base + pin); |
271 | if (ret) | |
272 | return ret; | |
273 | ||
e9133760 | 274 | mvebu_gpio_blink(chip, pin, 0); |
c57d75c0 TP |
275 | mvebu_gpio_set(chip, pin, value); |
276 | ||
fefe7b09 TP |
277 | spin_lock_irqsave(&mvchip->lock, flags); |
278 | u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); | |
d2cabc4a | 279 | u &= ~BIT(pin); |
fefe7b09 TP |
280 | writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); |
281 | spin_unlock_irqrestore(&mvchip->lock, flags); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
d276de70 | 286 | static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) |
fefe7b09 | 287 | { |
bbe76004 | 288 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
163ad364 | 289 | |
fefe7b09 TP |
290 | return irq_create_mapping(mvchip->domain, pin); |
291 | } | |
292 | ||
293 | /* | |
294 | * Functions implementing the irq_chip methods | |
295 | */ | |
296 | static void mvebu_gpio_irq_ack(struct irq_data *d) | |
297 | { | |
298 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
299 | struct mvebu_gpio_chip *mvchip = gc->private; | |
812d4788 | 300 | u32 mask = d->mask; |
fefe7b09 TP |
301 | |
302 | irq_gc_lock(gc); | |
812d4788 | 303 | writel_relaxed(~mask, mvebu_gpioreg_edge_cause(mvchip)); |
fefe7b09 TP |
304 | irq_gc_unlock(gc); |
305 | } | |
306 | ||
307 | static void mvebu_gpio_edge_irq_mask(struct irq_data *d) | |
308 | { | |
309 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
310 | struct mvebu_gpio_chip *mvchip = gc->private; | |
61819549 | 311 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
812d4788 | 312 | u32 mask = d->mask; |
fefe7b09 TP |
313 | |
314 | irq_gc_lock(gc); | |
61819549 GC |
315 | ct->mask_cache_priv &= ~mask; |
316 | ||
317 | writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); | |
fefe7b09 TP |
318 | irq_gc_unlock(gc); |
319 | } | |
320 | ||
321 | static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) | |
322 | { | |
323 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
324 | struct mvebu_gpio_chip *mvchip = gc->private; | |
61819549 | 325 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
812d4788 | 326 | u32 mask = d->mask; |
fefe7b09 TP |
327 | |
328 | irq_gc_lock(gc); | |
61819549 GC |
329 | ct->mask_cache_priv |= mask; |
330 | writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); | |
fefe7b09 TP |
331 | irq_gc_unlock(gc); |
332 | } | |
333 | ||
334 | static void mvebu_gpio_level_irq_mask(struct irq_data *d) | |
335 | { | |
336 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
337 | struct mvebu_gpio_chip *mvchip = gc->private; | |
61819549 | 338 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
812d4788 | 339 | u32 mask = d->mask; |
fefe7b09 TP |
340 | |
341 | irq_gc_lock(gc); | |
61819549 GC |
342 | ct->mask_cache_priv &= ~mask; |
343 | writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); | |
fefe7b09 TP |
344 | irq_gc_unlock(gc); |
345 | } | |
346 | ||
347 | static void mvebu_gpio_level_irq_unmask(struct irq_data *d) | |
348 | { | |
349 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
350 | struct mvebu_gpio_chip *mvchip = gc->private; | |
61819549 | 351 | struct irq_chip_type *ct = irq_data_get_chip_type(d); |
812d4788 | 352 | u32 mask = d->mask; |
fefe7b09 TP |
353 | |
354 | irq_gc_lock(gc); | |
61819549 GC |
355 | ct->mask_cache_priv |= mask; |
356 | writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); | |
fefe7b09 TP |
357 | irq_gc_unlock(gc); |
358 | } | |
359 | ||
360 | /***************************************************************************** | |
361 | * MVEBU GPIO IRQ | |
362 | * | |
363 | * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same | |
364 | * value of the line or the opposite value. | |
365 | * | |
366 | * Level IRQ handlers: DATA_IN is used directly as cause register. | |
a4319a61 | 367 | * Interrupt are masked by LEVEL_MASK registers. |
fefe7b09 | 368 | * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. |
a4319a61 | 369 | * Interrupt are masked by EDGE_MASK registers. |
fefe7b09 | 370 | * Both-edge handlers: Similar to regular Edge handlers, but also swaps |
a4319a61 AL |
371 | * the polarity to catch the next line transaction. |
372 | * This is a race condition that might not perfectly | |
373 | * work on some use cases. | |
fefe7b09 TP |
374 | * |
375 | * Every eight GPIO lines are grouped (OR'ed) before going up to main | |
376 | * cause register. | |
377 | * | |
a4319a61 AL |
378 | * EDGE cause mask |
379 | * data-in /--------| |-----| |----\ | |
380 | * -----| |----- ---- to main cause reg | |
381 | * X \----------------| |----/ | |
382 | * polarity LEVEL mask | |
fefe7b09 TP |
383 | * |
384 | ****************************************************************************/ | |
385 | ||
386 | static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
387 | { | |
388 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
389 | struct irq_chip_type *ct = irq_data_get_chip_type(d); | |
390 | struct mvebu_gpio_chip *mvchip = gc->private; | |
391 | int pin; | |
392 | u32 u; | |
393 | ||
394 | pin = d->hwirq; | |
395 | ||
d2cabc4a | 396 | u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & BIT(pin); |
a4319a61 | 397 | if (!u) |
fefe7b09 | 398 | return -EINVAL; |
fefe7b09 TP |
399 | |
400 | type &= IRQ_TYPE_SENSE_MASK; | |
401 | if (type == IRQ_TYPE_NONE) | |
402 | return -EINVAL; | |
403 | ||
404 | /* Check if we need to change chip and handler */ | |
405 | if (!(ct->type & type)) | |
406 | if (irq_setup_alt_chip(d, type)) | |
407 | return -EINVAL; | |
408 | ||
409 | /* | |
410 | * Configure interrupt polarity. | |
411 | */ | |
f4dcd2d9 | 412 | switch (type) { |
fefe7b09 TP |
413 | case IRQ_TYPE_EDGE_RISING: |
414 | case IRQ_TYPE_LEVEL_HIGH: | |
415 | u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
d2cabc4a | 416 | u &= ~BIT(pin); |
fefe7b09 | 417 | writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); |
7cf8c9f7 | 418 | break; |
fefe7b09 TP |
419 | case IRQ_TYPE_EDGE_FALLING: |
420 | case IRQ_TYPE_LEVEL_LOW: | |
421 | u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
d2cabc4a | 422 | u |= BIT(pin); |
fefe7b09 | 423 | writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); |
7cf8c9f7 | 424 | break; |
fefe7b09 TP |
425 | case IRQ_TYPE_EDGE_BOTH: { |
426 | u32 v; | |
427 | ||
428 | v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^ | |
429 | readl_relaxed(mvebu_gpioreg_data_in(mvchip)); | |
430 | ||
431 | /* | |
432 | * set initial polarity based on current input level | |
433 | */ | |
434 | u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
d2cabc4a RS |
435 | if (v & BIT(pin)) |
436 | u |= BIT(pin); /* falling */ | |
fefe7b09 | 437 | else |
d2cabc4a | 438 | u &= ~BIT(pin); /* rising */ |
fefe7b09 | 439 | writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); |
7cf8c9f7 | 440 | break; |
fefe7b09 TP |
441 | } |
442 | } | |
443 | return 0; | |
444 | } | |
445 | ||
bd0b9ac4 | 446 | static void mvebu_gpio_irq_handler(struct irq_desc *desc) |
fefe7b09 | 447 | { |
476f8b4c | 448 | struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); |
01ca59f1 | 449 | struct irq_chip *chip = irq_desc_get_chip(desc); |
fefe7b09 TP |
450 | u32 cause, type; |
451 | int i; | |
452 | ||
453 | if (mvchip == NULL) | |
454 | return; | |
455 | ||
01ca59f1 TP |
456 | chained_irq_enter(chip, desc); |
457 | ||
fefe7b09 TP |
458 | cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) & |
459 | readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); | |
460 | cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) & | |
461 | readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); | |
462 | ||
463 | for (i = 0; i < mvchip->chip.ngpio; i++) { | |
464 | int irq; | |
465 | ||
812d4788 | 466 | irq = irq_find_mapping(mvchip->domain, i); |
fefe7b09 | 467 | |
d2cabc4a | 468 | if (!(cause & BIT(i))) |
fefe7b09 TP |
469 | continue; |
470 | ||
fb90c22a | 471 | type = irq_get_trigger_type(irq); |
fefe7b09 TP |
472 | if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
473 | /* Swap polarity (race with GPIO line) */ | |
474 | u32 polarity; | |
475 | ||
476 | polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
d2cabc4a | 477 | polarity ^= BIT(i); |
fefe7b09 TP |
478 | writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip)); |
479 | } | |
01ca59f1 | 480 | |
fefe7b09 TP |
481 | generic_handle_irq(irq); |
482 | } | |
01ca59f1 TP |
483 | |
484 | chained_irq_exit(chip, desc); | |
fefe7b09 TP |
485 | } |
486 | ||
a4ba5e1b SG |
487 | #ifdef CONFIG_DEBUG_FS |
488 | #include <linux/seq_file.h> | |
489 | ||
490 | static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
491 | { | |
bbe76004 | 492 | struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); |
a4ba5e1b SG |
493 | u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; |
494 | int i; | |
495 | ||
496 | out = readl_relaxed(mvebu_gpioreg_out(mvchip)); | |
497 | io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); | |
498 | blink = readl_relaxed(mvebu_gpioreg_blink(mvchip)); | |
499 | in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); | |
500 | data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip)); | |
501 | cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)); | |
502 | edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); | |
503 | lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); | |
504 | ||
505 | for (i = 0; i < chip->ngpio; i++) { | |
506 | const char *label; | |
507 | u32 msk; | |
508 | bool is_out; | |
509 | ||
510 | label = gpiochip_is_requested(chip, i); | |
511 | if (!label) | |
512 | continue; | |
513 | ||
d2cabc4a | 514 | msk = BIT(i); |
a4ba5e1b SG |
515 | is_out = !(io_conf & msk); |
516 | ||
517 | seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); | |
518 | ||
519 | if (is_out) { | |
520 | seq_printf(s, " out %s %s\n", | |
521 | out & msk ? "hi" : "lo", | |
522 | blink & msk ? "(blink )" : ""); | |
523 | continue; | |
524 | } | |
525 | ||
526 | seq_printf(s, " in %s (act %s) - IRQ", | |
527 | (data_in ^ in_pol) & msk ? "hi" : "lo", | |
528 | in_pol & msk ? "lo" : "hi"); | |
529 | if (!((edg_msk | lvl_msk) & msk)) { | |
a4319a61 | 530 | seq_puts(s, " disabled\n"); |
a4ba5e1b SG |
531 | continue; |
532 | } | |
533 | if (edg_msk & msk) | |
a4319a61 | 534 | seq_puts(s, " edge "); |
a4ba5e1b | 535 | if (lvl_msk & msk) |
a4319a61 | 536 | seq_puts(s, " level"); |
a4ba5e1b SG |
537 | seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); |
538 | } | |
539 | } | |
540 | #else | |
541 | #define mvebu_gpio_dbg_show NULL | |
542 | #endif | |
543 | ||
271b17b6 | 544 | static const struct of_device_id mvebu_gpio_of_match[] = { |
fefe7b09 TP |
545 | { |
546 | .compatible = "marvell,orion-gpio", | |
a4319a61 | 547 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, |
fefe7b09 TP |
548 | }, |
549 | { | |
550 | .compatible = "marvell,mv78200-gpio", | |
a4319a61 | 551 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, |
fefe7b09 TP |
552 | }, |
553 | { | |
554 | .compatible = "marvell,armadaxp-gpio", | |
a4319a61 | 555 | .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, |
fefe7b09 TP |
556 | }, |
557 | { | |
558 | /* sentinel */ | |
559 | }, | |
560 | }; | |
fefe7b09 | 561 | |
b5b7b487 TP |
562 | static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) |
563 | { | |
564 | struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); | |
565 | int i; | |
566 | ||
567 | mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip)); | |
568 | mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip)); | |
569 | mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip)); | |
570 | mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip)); | |
571 | ||
572 | switch (mvchip->soc_variant) { | |
573 | case MVEBU_GPIO_SOC_VARIANT_ORION: | |
574 | mvchip->edge_mask_regs[0] = | |
575 | readl(mvchip->membase + GPIO_EDGE_MASK_OFF); | |
576 | mvchip->level_mask_regs[0] = | |
577 | readl(mvchip->membase + GPIO_LEVEL_MASK_OFF); | |
578 | break; | |
579 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
580 | for (i = 0; i < 2; i++) { | |
581 | mvchip->edge_mask_regs[i] = | |
582 | readl(mvchip->membase + | |
583 | GPIO_EDGE_MASK_MV78200_OFF(i)); | |
584 | mvchip->level_mask_regs[i] = | |
585 | readl(mvchip->membase + | |
586 | GPIO_LEVEL_MASK_MV78200_OFF(i)); | |
587 | } | |
588 | break; | |
589 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
590 | for (i = 0; i < 4; i++) { | |
591 | mvchip->edge_mask_regs[i] = | |
592 | readl(mvchip->membase + | |
593 | GPIO_EDGE_MASK_ARMADAXP_OFF(i)); | |
594 | mvchip->level_mask_regs[i] = | |
595 | readl(mvchip->membase + | |
596 | GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); | |
597 | } | |
598 | break; | |
599 | default: | |
600 | BUG(); | |
601 | } | |
602 | ||
603 | return 0; | |
604 | } | |
605 | ||
606 | static int mvebu_gpio_resume(struct platform_device *pdev) | |
607 | { | |
608 | struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); | |
609 | int i; | |
610 | ||
611 | writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip)); | |
612 | writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip)); | |
613 | writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip)); | |
614 | writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip)); | |
615 | ||
616 | switch (mvchip->soc_variant) { | |
617 | case MVEBU_GPIO_SOC_VARIANT_ORION: | |
618 | writel(mvchip->edge_mask_regs[0], | |
619 | mvchip->membase + GPIO_EDGE_MASK_OFF); | |
620 | writel(mvchip->level_mask_regs[0], | |
621 | mvchip->membase + GPIO_LEVEL_MASK_OFF); | |
622 | break; | |
623 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
624 | for (i = 0; i < 2; i++) { | |
625 | writel(mvchip->edge_mask_regs[i], | |
626 | mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i)); | |
627 | writel(mvchip->level_mask_regs[i], | |
628 | mvchip->membase + | |
629 | GPIO_LEVEL_MASK_MV78200_OFF(i)); | |
630 | } | |
631 | break; | |
632 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
633 | for (i = 0; i < 4; i++) { | |
634 | writel(mvchip->edge_mask_regs[i], | |
635 | mvchip->membase + | |
636 | GPIO_EDGE_MASK_ARMADAXP_OFF(i)); | |
637 | writel(mvchip->level_mask_regs[i], | |
638 | mvchip->membase + | |
639 | GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); | |
640 | } | |
641 | break; | |
642 | default: | |
643 | BUG(); | |
644 | } | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
3836309d | 649 | static int mvebu_gpio_probe(struct platform_device *pdev) |
fefe7b09 TP |
650 | { |
651 | struct mvebu_gpio_chip *mvchip; | |
652 | const struct of_device_id *match; | |
653 | struct device_node *np = pdev->dev.of_node; | |
654 | struct resource *res; | |
655 | struct irq_chip_generic *gc; | |
656 | struct irq_chip_type *ct; | |
de88747f | 657 | struct clk *clk; |
fefe7b09 | 658 | unsigned int ngpios; |
812d4788 | 659 | bool have_irqs; |
fefe7b09 TP |
660 | int soc_variant; |
661 | int i, cpu, id; | |
f1d2d081 | 662 | int err; |
fefe7b09 TP |
663 | |
664 | match = of_match_device(mvebu_gpio_of_match, &pdev->dev); | |
665 | if (match) | |
f0d50460 | 666 | soc_variant = (unsigned long) match->data; |
fefe7b09 TP |
667 | else |
668 | soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; | |
669 | ||
812d4788 JG |
670 | /* Some gpio controllers do not provide irq support */ |
671 | have_irqs = of_irq_count(np) != 0; | |
672 | ||
a4319a61 AL |
673 | mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), |
674 | GFP_KERNEL); | |
6c8365f6 | 675 | if (!mvchip) |
fefe7b09 | 676 | return -ENOMEM; |
fefe7b09 | 677 | |
b5b7b487 TP |
678 | platform_set_drvdata(pdev, mvchip); |
679 | ||
fefe7b09 TP |
680 | if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { |
681 | dev_err(&pdev->dev, "Missing ngpios OF property\n"); | |
682 | return -ENODEV; | |
683 | } | |
684 | ||
685 | id = of_alias_get_id(pdev->dev.of_node, "gpio"); | |
686 | if (id < 0) { | |
687 | dev_err(&pdev->dev, "Couldn't get OF id\n"); | |
688 | return id; | |
689 | } | |
690 | ||
de88747f AL |
691 | clk = devm_clk_get(&pdev->dev, NULL); |
692 | /* Not all SoCs require a clock.*/ | |
693 | if (!IS_ERR(clk)) | |
694 | clk_prepare_enable(clk); | |
695 | ||
fefe7b09 TP |
696 | mvchip->soc_variant = soc_variant; |
697 | mvchip->chip.label = dev_name(&pdev->dev); | |
58383c78 | 698 | mvchip->chip.parent = &pdev->dev; |
203f0daa JG |
699 | mvchip->chip.request = gpiochip_generic_request; |
700 | mvchip->chip.free = gpiochip_generic_free; | |
fefe7b09 TP |
701 | mvchip->chip.direction_input = mvebu_gpio_direction_input; |
702 | mvchip->chip.get = mvebu_gpio_get; | |
703 | mvchip->chip.direction_output = mvebu_gpio_direction_output; | |
704 | mvchip->chip.set = mvebu_gpio_set; | |
812d4788 JG |
705 | if (have_irqs) |
706 | mvchip->chip.to_irq = mvebu_gpio_to_irq; | |
fefe7b09 TP |
707 | mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; |
708 | mvchip->chip.ngpio = ngpios; | |
9fb1f39e | 709 | mvchip->chip.can_sleep = false; |
fefe7b09 | 710 | mvchip->chip.of_node = np; |
a4ba5e1b | 711 | mvchip->chip.dbg_show = mvebu_gpio_dbg_show; |
fefe7b09 TP |
712 | |
713 | spin_lock_init(&mvchip->lock); | |
08a67a58 | 714 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
641d0342 | 715 | mvchip->membase = devm_ioremap_resource(&pdev->dev, res); |
422d26b6 | 716 | if (IS_ERR(mvchip->membase)) |
641d0342 | 717 | return PTR_ERR(mvchip->membase); |
fefe7b09 | 718 | |
7077f4cc RS |
719 | /* |
720 | * The Armada XP has a second range of registers for the | |
721 | * per-CPU registers | |
722 | */ | |
fefe7b09 TP |
723 | if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { |
724 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
641d0342 TR |
725 | mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev, |
726 | res); | |
f4dcd2d9 | 727 | if (IS_ERR(mvchip->percpu_membase)) |
641d0342 | 728 | return PTR_ERR(mvchip->percpu_membase); |
fefe7b09 TP |
729 | } |
730 | ||
731 | /* | |
732 | * Mask and clear GPIO interrupts. | |
733 | */ | |
f4dcd2d9 | 734 | switch (soc_variant) { |
fefe7b09 TP |
735 | case MVEBU_GPIO_SOC_VARIANT_ORION: |
736 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); | |
737 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); | |
738 | writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); | |
739 | break; | |
740 | case MVEBU_GPIO_SOC_VARIANT_MV78200: | |
741 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); | |
742 | for (cpu = 0; cpu < 2; cpu++) { | |
743 | writel_relaxed(0, mvchip->membase + | |
744 | GPIO_EDGE_MASK_MV78200_OFF(cpu)); | |
745 | writel_relaxed(0, mvchip->membase + | |
746 | GPIO_LEVEL_MASK_MV78200_OFF(cpu)); | |
747 | } | |
748 | break; | |
749 | case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: | |
750 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); | |
751 | writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); | |
752 | writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); | |
753 | for (cpu = 0; cpu < 4; cpu++) { | |
754 | writel_relaxed(0, mvchip->percpu_membase + | |
755 | GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu)); | |
756 | writel_relaxed(0, mvchip->percpu_membase + | |
757 | GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)); | |
758 | writel_relaxed(0, mvchip->percpu_membase + | |
759 | GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu)); | |
760 | } | |
761 | break; | |
762 | default: | |
763 | BUG(); | |
764 | } | |
765 | ||
00b9ab4a | 766 | devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); |
fefe7b09 TP |
767 | |
768 | /* Some gpio controllers do not provide irq support */ | |
812d4788 | 769 | if (!have_irqs) |
fefe7b09 TP |
770 | return 0; |
771 | ||
812d4788 JG |
772 | mvchip->domain = |
773 | irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL); | |
774 | if (!mvchip->domain) { | |
775 | dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", | |
776 | mvchip->chip.label); | |
777 | return -ENODEV; | |
fefe7b09 TP |
778 | } |
779 | ||
812d4788 JG |
780 | err = irq_alloc_domain_generic_chips( |
781 | mvchip->domain, ngpios, 2, np->name, handle_level_irq, | |
782 | IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); | |
783 | if (err) { | |
784 | dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", | |
785 | mvchip->chip.label); | |
786 | goto err_domain; | |
fefe7b09 TP |
787 | } |
788 | ||
899c37ed RS |
789 | /* |
790 | * NOTE: The common accessors cannot be used because of the percpu | |
812d4788 JG |
791 | * access to the mask registers |
792 | */ | |
793 | gc = irq_get_domain_generic_chip(mvchip->domain, 0); | |
fefe7b09 TP |
794 | gc->private = mvchip; |
795 | ct = &gc->chip_types[0]; | |
796 | ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; | |
797 | ct->chip.irq_mask = mvebu_gpio_level_irq_mask; | |
798 | ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; | |
799 | ct->chip.irq_set_type = mvebu_gpio_irq_set_type; | |
800 | ct->chip.name = mvchip->chip.label; | |
801 | ||
802 | ct = &gc->chip_types[1]; | |
803 | ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
804 | ct->chip.irq_ack = mvebu_gpio_irq_ack; | |
805 | ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; | |
806 | ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; | |
807 | ct->chip.irq_set_type = mvebu_gpio_irq_set_type; | |
808 | ct->handler = handle_edge_irq; | |
809 | ct->chip.name = mvchip->chip.label; | |
810 | ||
899c37ed RS |
811 | /* |
812 | * Setup the interrupt handlers. Each chip can have up to 4 | |
812d4788 JG |
813 | * interrupt handlers, with each handler dealing with 8 GPIO |
814 | * pins. | |
815 | */ | |
816 | for (i = 0; i < 4; i++) { | |
817 | int irq = platform_get_irq(pdev, i); | |
fefe7b09 | 818 | |
812d4788 JG |
819 | if (irq < 0) |
820 | continue; | |
821 | irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, | |
822 | mvchip); | |
fefe7b09 TP |
823 | } |
824 | ||
825 | return 0; | |
f1d2d081 | 826 | |
812d4788 JG |
827 | err_domain: |
828 | irq_domain_remove(mvchip->domain); | |
f1d2d081 | 829 | |
f1d2d081 | 830 | return err; |
fefe7b09 TP |
831 | } |
832 | ||
833 | static struct platform_driver mvebu_gpio_driver = { | |
834 | .driver = { | |
a4319a61 | 835 | .name = "mvebu-gpio", |
fefe7b09 TP |
836 | .of_match_table = mvebu_gpio_of_match, |
837 | }, | |
838 | .probe = mvebu_gpio_probe, | |
b5b7b487 TP |
839 | .suspend = mvebu_gpio_suspend, |
840 | .resume = mvebu_gpio_resume, | |
fefe7b09 | 841 | }; |
ed329f3a | 842 | builtin_platform_driver(mvebu_gpio_driver); |