[mirror_ubuntu-bionic-kernel.git] / drivers / gpio / gpio-mxs.c

/*
 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * Based on code from Freescale,
 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA  02110-1301, USA.
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
/* FIXME: for gpio_get_value(), replace this by direct register read */
#include <linux/gpio.h>
#include <linux/module.h>

#define MXS_SET		0x4
#define MXS_CLR		0x8

#define PINCTRL_DOUT(p)		((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
#define PINCTRL_DIN(p)		((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
#define PINCTRL_DOE(p)		((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
#define PINCTRL_PIN2IRQ(p)	((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
#define PINCTRL_IRQEN(p)	((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
#define PINCTRL_IRQLEV(p)	((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
#define PINCTRL_IRQPOL(p)	((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
#define PINCTRL_IRQSTAT(p)	((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)

#define GPIO_INT_FALL_EDGE	0x0
#define GPIO_INT_LOW_LEV	0x1
#define GPIO_INT_RISE_EDGE	0x2
#define GPIO_INT_HIGH_LEV	0x3
#define GPIO_INT_LEV_MASK	(1 << 0)
#define GPIO_INT_POL_MASK	(1 << 1)

enum mxs_gpio_id {
	IMX23_GPIO,
	IMX28_GPIO,
};

struct mxs_gpio_port {
	void __iomem *base;
	int id;
	int irq;
	struct irq_domain *domain;
	struct gpio_chip gc;
	struct device *dev;
	enum mxs_gpio_id devid;
	u32 both_edges;
};

static inline int is_imx23_gpio(struct mxs_gpio_port *port)
{
	return port->devid == IMX23_GPIO;
}

static inline int is_imx28_gpio(struct mxs_gpio_port *port)
{
	return port->devid == IMX28_GPIO;
}

/* Note: This driver assumes 32 GPIOs are handled in one register */

static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
	u32 val;
	u32 pin_mask = 1 << d->hwirq;
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct irq_chip_type *ct = irq_data_get_chip_type(d);
	struct mxs_gpio_port *port = gc->private;
	void __iomem *pin_addr;
	int edge;

	if (!(ct->type & type))
		if (irq_setup_alt_chip(d, type))
			return -EINVAL;

	port->both_edges &= ~pin_mask;
	switch (type) {
	case IRQ_TYPE_EDGE_BOTH:
		val = gpio_get_value(port->gc.base + d->hwirq);
		if (val)
			edge = GPIO_INT_FALL_EDGE;
		else
			edge = GPIO_INT_RISE_EDGE;
		port->both_edges |= pin_mask;
		break;
	case IRQ_TYPE_EDGE_RISING:
		edge = GPIO_INT_RISE_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		edge = GPIO_INT_FALL_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		edge = GPIO_INT_LOW_LEV;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		edge = GPIO_INT_HIGH_LEV;
		break;
	default:
		return -EINVAL;
	}

	/* set level or edge */
	pin_addr = port->base + PINCTRL_IRQLEV(port);
	if (edge & GPIO_INT_LEV_MASK) {
		writel(pin_mask, pin_addr + MXS_SET);
		writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
	} else {
		writel(pin_mask, pin_addr + MXS_CLR);
		writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
	}

	/* set polarity */
	pin_addr = port->base + PINCTRL_IRQPOL(port);
	if (edge & GPIO_INT_POL_MASK)
		writel(pin_mask, pin_addr + MXS_SET);
	else
		writel(pin_mask, pin_addr + MXS_CLR);

	writel(pin_mask,
	       port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);

	return 0;
}

static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
{
	u32 bit, val, edge;
	void __iomem *pin_addr;

	bit = 1 << gpio;

	pin_addr = port->base + PINCTRL_IRQPOL(port);
	val = readl(pin_addr);
	edge = val & bit;

	if (edge)
		writel(bit, pin_addr + MXS_CLR);
	else
		writel(bit, pin_addr + MXS_SET);
}

/* MXS has one interrupt *per* gpio port */
static void mxs_gpio_irq_handler(struct irq_desc *desc)
{
	u32 irq_stat;
	struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);

	desc->irq_data.chip->irq_ack(&desc->irq_data);

	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
			readl(port->base + PINCTRL_IRQEN(port));

	while (irq_stat != 0) {
		int irqoffset = fls(irq_stat) - 1;
		if (port->both_edges & (1 << irqoffset))
			mxs_flip_edge(port, irqoffset);

		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
		irq_stat &= ~(1 << irqoffset);
	}
}

/*
 * Set interrupt number "irq" in the GPIO as a wake-up source.
 * While system is running, all registered GPIO interrupts need to have
 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 * need to have wake-up enabled.
 * @param  irq          interrupt source number
 * @param  enable       enable as wake-up if equal to non-zero
 * @return       This function returns 0 on success.
 */
static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxs_gpio_port *port = gc->private;

	if (enable)
		enable_irq_wake(port->irq);
	else
		disable_irq_wake(port->irq);

	return 0;
}

static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int rv;

	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
					 port->base, handle_level_irq);
	if (!gc)
		return -ENOMEM;

	gc->private = port;

	ct = &gc->chip_types[0];
	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
	ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
	ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;

	ct = &gc->chip_types[1];
	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
	ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
	ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
	ct->handler = handle_level_irq;

	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
					 IRQ_GC_INIT_NESTED_LOCK,
					 IRQ_NOREQUEST, 0);

	return rv;
}

static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct mxs_gpio_port *port = gpiochip_get_data(gc);

	return irq_find_mapping(port->domain, offset);
}

static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
{
	struct mxs_gpio_port *port = gpiochip_get_data(gc);
	u32 mask = 1 << offset;
	u32 dir;

	dir = readl(port->base + PINCTRL_DOE(port));
	return !(dir & mask);
}

static const struct platform_device_id mxs_gpio_ids[] = {
	{
		.name = "imx23-gpio",
		.driver_data = IMX23_GPIO,
	}, {
		.name = "imx28-gpio",
		.driver_data = IMX28_GPIO,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);

static const struct of_device_id mxs_gpio_dt_ids[] = {
	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);

static int mxs_gpio_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxs_gpio_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct device_node *parent;
	static void __iomem *base;
	struct mxs_gpio_port *port;
	int irq_base;
	int err;

	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->id = of_alias_get_id(np, "gpio");
	if (port->id < 0)
		return port->id;
	port->devid = (enum mxs_gpio_id) of_id->data;
	port->dev = &pdev->dev;
	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	/*
	 * map memory region only once, as all the gpio ports
	 * share the same one
	 */
	if (!base) {
		parent = of_get_parent(np);
		base = of_iomap(parent, 0);
		of_node_put(parent);
		if (!base)
			return -EADDRNOTAVAIL;
	}
	port->base = base;

	/* initially disable the interrupts */
	writel(0, port->base + PINCTRL_PIN2IRQ(port));
	writel(0, port->base + PINCTRL_IRQEN(port));

	/* clear address has to be used to clear IRQSTAT bits */
	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);

	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
	if (irq_base < 0) {
		err = irq_base;
		goto out_iounmap;
	}

	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
					     &irq_domain_simple_ops, NULL);
	if (!port->domain) {
		err = -ENODEV;
		goto out_iounmap;
	}

	/* gpio-mxs can be a generic irq chip */
	err = mxs_gpio_init_gc(port, irq_base);
	if (err < 0)
		goto out_irqdomain_remove;

	/* setup one handler for each entry */
	irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
					 port);

	err = bgpio_init(&port->gc, &pdev->dev, 4,
			 port->base + PINCTRL_DIN(port),
			 port->base + PINCTRL_DOUT(port) + MXS_SET,
			 port->base + PINCTRL_DOUT(port) + MXS_CLR,
			 port->base + PINCTRL_DOE(port), NULL, 0);
	if (err)
		goto out_irqdomain_remove;

	port->gc.to_irq = mxs_gpio_to_irq;
	port->gc.get_direction = mxs_gpio_get_direction;
	port->gc.base = port->id * 32;

	err = gpiochip_add_data(&port->gc, port);
	if (err)
		goto out_irqdomain_remove;

	return 0;

out_irqdomain_remove:
	irq_domain_remove(port->domain);
out_iounmap:
	iounmap(port->base);
	return err;
}

static struct platform_driver mxs_gpio_driver = {
	.driver		= {
		.name	= "gpio-mxs",
		.of_match_table = mxs_gpio_dt_ids,
		.suppress_bind_attrs = true,
	},
	.probe		= mxs_gpio_probe,
	.id_table	= mxs_gpio_ids,
};

static int __init mxs_gpio_init(void)
{
	return platform_driver_register(&mxs_gpio_driver);
}
postcore_initcall(mxs_gpio_init);

MODULE_AUTHOR("Freescale Semiconductor, "
	      "Daniel Mack <danielncaiaq.de>, "
	      "Juergen Beisert <kernel@pengutronix.de>");
MODULE_DESCRIPTION("Freescale MXS GPIO");
MODULE_LICENSE("GPL");
Commit	Line	Data
fba311fc SG	1	/*
	2	* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	*
	5	* Based on code from Freescale,
	6	* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version 2
	11	* of the License, or (at your option) any later version.
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	20	* MA 02110-1301, USA.
	21	*/
	22
641d0342	23	#include <linux/err.h>
fba311fc SG	24	#include <linux/init.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/io.h>
	27	#include <linux/irq.h>
0b76c541	28	#include <linux/irqdomain.h>
4052d45e SG	29	#include <linux/of.h>
	30	#include <linux/of_address.h>
	31	#include <linux/of_device.h>
8d7cf837 SG	32	#include <linux/platform_device.h>
8d7cf837 SG	33	#include <linux/slab.h>
0f4630f3 LW	34	#include <linux/gpio/driver.h>
	35	/* FIXME: for gpio_get_value(), replace this by direct register read */
	36	#include <linux/gpio.h>
bb207ef1	37	#include <linux/module.h>
fba311fc	38
8d7cf837 SG	39	#define MXS_SET 0x4
8d7cf837 SG	40	#define MXS_CLR 0x8
fba311fc	41
164387d2 SG	42	#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
	43	#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
	44	#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
	45	#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
	46	#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
	47	#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
	48	#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
	49	#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
fba311fc SG	50
	51	#define GPIO_INT_FALL_EDGE 0x0
	52	#define GPIO_INT_LOW_LEV 0x1
	53	#define GPIO_INT_RISE_EDGE 0x2
	54	#define GPIO_INT_HIGH_LEV 0x3
	55	#define GPIO_INT_LEV_MASK (1 << 0)
	56	#define GPIO_INT_POL_MASK (1 << 1)
	57
164387d2 SG	58	enum mxs_gpio_id {
	59	IMX23_GPIO,
	60	IMX28_GPIO,
	61	};
	62
7b2fa570 GL	63	struct mxs_gpio_port {
	64	void __iomem *base;
	65	int id;
	66	int irq;
0b76c541	67	struct irq_domain *domain;
0f4630f3	68	struct gpio_chip gc;
5751d3dc	69	struct device *dev;
164387d2	70	enum mxs_gpio_id devid;
66d7990e	71	u32 both_edges;
7b2fa570 GL	72	};
7b2fa570 GL	73
164387d2 SG	74	static inline int is_imx23_gpio(struct mxs_gpio_port *port)
	75	{
	76	return port->devid == IMX23_GPIO;
	77	}
	78
	79	static inline int is_imx28_gpio(struct mxs_gpio_port *port)
	80	{
	81	return port->devid == IMX28_GPIO;
	82	}
	83
fba311fc SG	84	/* Note: This driver assumes 32 GPIOs are handled in one register */
fba311fc SG	85
bf0c1118	86	static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
fba311fc	87	{
66d7990e	88	u32 val;
0b76c541	89	u32 pin_mask = 1 << d->hwirq;
498c17cf	90	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
f08ea3cc	91	struct irq_chip_type *ct = irq_data_get_chip_type(d);
498c17cf	92	struct mxs_gpio_port *port = gc->private;
fba311fc SG	93	void __iomem *pin_addr;
	94	int edge;
	95
f08ea3cc SH	96	if (!(ct->type & type))
	97	if (irq_setup_alt_chip(d, type))
	98	return -EINVAL;
	99
66d7990e	100	port->both_edges &= ~pin_mask;
fba311fc	101	switch (type) {
66d7990e	102	case IRQ_TYPE_EDGE_BOTH:
0f4630f3	103	val = gpio_get_value(port->gc.base + d->hwirq);
66d7990e GGM	104	if (val)
	105	edge = GPIO_INT_FALL_EDGE;
	106	else
	107	edge = GPIO_INT_RISE_EDGE;
	108	port->both_edges \|= pin_mask;
	109	break;
fba311fc SG	110	case IRQ_TYPE_EDGE_RISING:
	111	edge = GPIO_INT_RISE_EDGE;
	112	break;
	113	case IRQ_TYPE_EDGE_FALLING:
	114	edge = GPIO_INT_FALL_EDGE;
	115	break;
	116	case IRQ_TYPE_LEVEL_LOW:
	117	edge = GPIO_INT_LOW_LEV;
	118	break;
	119	case IRQ_TYPE_LEVEL_HIGH:
	120	edge = GPIO_INT_HIGH_LEV;
	121	break;
	122	default:
	123	return -EINVAL;
	124	}
	125
	126	/* set level or edge */
164387d2	127	pin_addr = port->base + PINCTRL_IRQLEV(port);
f08ea3cc	128	if (edge & GPIO_INT_LEV_MASK) {
8d7cf837	129	writel(pin_mask, pin_addr + MXS_SET);
f08ea3cc SH	130	writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
f08ea3cc SH	131	} else {
8d7cf837	132	writel(pin_mask, pin_addr + MXS_CLR);
f08ea3cc SH	133	writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
f08ea3cc SH	134	}
fba311fc SG	135
fba311fc SG	136	/* set polarity */
164387d2	137	pin_addr = port->base + PINCTRL_IRQPOL(port);
fba311fc	138	if (edge & GPIO_INT_POL_MASK)
8d7cf837	139	writel(pin_mask, pin_addr + MXS_SET);
fba311fc	140	else
8d7cf837	141	writel(pin_mask, pin_addr + MXS_CLR);
fba311fc	142
0b76c541	143	writel(pin_mask,
164387d2	144	port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
fba311fc SG	145
	146	return 0;
	147	}
	148
66d7990e GGM	149	static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
	150	{
	151	u32 bit, val, edge;
	152	void __iomem *pin_addr;
	153
	154	bit = 1 << gpio;
	155
	156	pin_addr = port->base + PINCTRL_IRQPOL(port);
	157	val = readl(pin_addr);
	158	edge = val & bit;
	159
	160	if (edge)
	161	writel(bit, pin_addr + MXS_CLR);
	162	else
	163	writel(bit, pin_addr + MXS_SET);
	164	}
	165
fba311fc	166	/* MXS has one interrupt per gpio port */
bd0b9ac4	167	static void mxs_gpio_irq_handler(struct irq_desc *desc)
fba311fc SG	168	{
fba311fc SG	169	u32 irq_stat;
476f8b4c	170	struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
fba311fc	171
1f6b5dd4 UKK	172	desc->irq_data.chip->irq_ack(&desc->irq_data);
1f6b5dd4 UKK	173
164387d2 SG	174	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
164387d2 SG	175	readl(port->base + PINCTRL_IRQEN(port));
fba311fc SG	176
	177	while (irq_stat != 0) {
	178	int irqoffset = fls(irq_stat) - 1;
66d7990e GGM	179	if (port->both_edges & (1 << irqoffset))
	180	mxs_flip_edge(port, irqoffset);
	181
0b76c541	182	generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
fba311fc SG	183	irq_stat &= ~(1 << irqoffset);
	184	}
	185	}
	186
	187	/*
	188	* Set interrupt number "irq" in the GPIO as a wake-up source.
	189	* While system is running, all registered GPIO interrupts need to have
	190	* wake-up enabled. When system is suspended, only selected GPIO interrupts
	191	* need to have wake-up enabled.
	192	* @param irq interrupt source number
	193	* @param enable enable as wake-up if equal to non-zero
	194	* @return This function returns 0 on success.
	195	*/
bf0c1118	196	static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
fba311fc	197	{
498c17cf SG	198	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
498c17cf SG	199	struct mxs_gpio_port *port = gc->private;
fba311fc	200
6161715e SG	201	if (enable)
	202	enable_irq_wake(port->irq);
	203	else
	204	disable_irq_wake(port->irq);
fba311fc SG	205
	206	return 0;
	207	}
	208
abc8d583	209	static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
498c17cf SG	210	{
	211	struct irq_chip_generic *gc;
	212	struct irq_chip_type *ct;
5751d3dc	213	int rv;
498c17cf	214
5751d3dc BG	215	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
5751d3dc BG	216	port->base, handle_level_irq);
1bbc557d PF	217	if (!gc)
	218	return -ENOMEM;
	219
498c17cf SG	220	gc->private = port;
498c17cf SG	221
f08ea3cc SH	222	ct = &gc->chip_types[0];
	223	ct->type = IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW;
	224	ct->chip.irq_ack = irq_gc_ack_set_bit;
	225	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	226	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
	227	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
	228	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
	229	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
	230	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
	231	ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
	232	ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
	233
	234	ct = &gc->chip_types[1];
	235	ct->type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
591567a5	236	ct->chip.irq_ack = irq_gc_ack_set_bit;
66a37c3b SH	237	ct->chip.irq_mask = irq_gc_mask_disable_reg;
66a37c3b SH	238	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
498c17cf	239	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
591567a5	240	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
f08ea3cc	241	ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
164387d2	242	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
66a37c3b SH	243	ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
66a37c3b SH	244	ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
f08ea3cc	245	ct->handler = handle_level_irq;
498c17cf	246
5751d3dc BG	247	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
	248	IRQ_GC_INIT_NESTED_LOCK,
	249	IRQ_NOREQUEST, 0);
1bbc557d	250
5751d3dc	251	return rv;
498c17cf	252	}
fba311fc	253
06f88a8a	254	static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
fba311fc	255	{
0f4630f3	256	struct mxs_gpio_port *port = gpiochip_get_data(gc);
fba311fc	257
0b76c541	258	return irq_find_mapping(port->domain, offset);
fba311fc SG	259	}
fba311fc SG	260
c8aaa1bf JU	261	static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
c8aaa1bf JU	262	{
0f4630f3	263	struct mxs_gpio_port *port = gpiochip_get_data(gc);
c8aaa1bf JU	264	u32 mask = 1 << offset;
	265	u32 dir;
	266
	267	dir = readl(port->base + PINCTRL_DOE(port));
	268	return !(dir & mask);
	269	}
	270
f4f79d40	271	static const struct platform_device_id mxs_gpio_ids[] = {
164387d2 SG	272	{
	273	.name = "imx23-gpio",
	274	.driver_data = IMX23_GPIO,
	275	}, {
	276	.name = "imx28-gpio",
	277	.driver_data = IMX28_GPIO,
	278	}, {
	279	/* sentinel */
	280	}
	281	};
	282	MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
	283
4052d45e SG	284	static const struct of_device_id mxs_gpio_dt_ids[] = {
	285	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
	286	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
	287	{ /* sentinel */ }
	288	};
	289	MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
	290
3836309d	291	static int mxs_gpio_probe(struct platform_device *pdev)
fba311fc	292	{
4052d45e SG	293	const struct of_device_id *of_id =
	294	of_match_device(mxs_gpio_dt_ids, &pdev->dev);
	295	struct device_node *np = pdev->dev.of_node;
	296	struct device_node *parent;
8d7cf837 SG	297	static void __iomem *base;
8d7cf837 SG	298	struct mxs_gpio_port *port;
0b76c541	299	int irq_base;
498c17cf	300	int err;
8d7cf837	301
940a4f7b	302	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
8d7cf837 SG	303	if (!port)
	304	return -ENOMEM;
	305
99357127 FE	306	port->id = of_alias_get_id(np, "gpio");
	307	if (port->id < 0)
	308	return port->id;
	309	port->devid = (enum mxs_gpio_id) of_id->data;
5751d3dc	310	port->dev = &pdev->dev;
940a4f7b SG	311	port->irq = platform_get_irq(pdev, 0);
	312	if (port->irq < 0)
	313	return port->irq;
	314
8d7cf837 SG	315	/*
	316	* map memory region only once, as all the gpio ports
	317	* share the same one
	318	*/
	319	if (!base) {
99357127 FE	320	parent = of_get_parent(np);
	321	base = of_iomap(parent, 0);
	322	of_node_put(parent);
	323	if (!base)
	324	return -EADDRNOTAVAIL;
8d7cf837 SG	325	}
8d7cf837 SG	326	port->base = base;
fba311fc	327
f08ea3cc SH	328	/* initially disable the interrupts */
f08ea3cc SH	329	writel(0, port->base + PINCTRL_PIN2IRQ(port));
164387d2	330	writel(0, port->base + PINCTRL_IRQEN(port));
fba311fc	331
8d7cf837	332	/* clear address has to be used to clear IRQSTAT bits */
164387d2	333	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
fba311fc	334
8514b543	335	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
44df0819 AY	336	if (irq_base < 0) {
	337	err = irq_base;
	338	goto out_iounmap;
	339	}
0b76c541 SG	340
	341	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
	342	&irq_domain_simple_ops, NULL);
	343	if (!port->domain) {
	344	err = -ENODEV;
8514b543	345	goto out_iounmap;
0b76c541 SG	346	}
0b76c541 SG	347
498c17cf	348	/* gpio-mxs can be a generic irq chip */
1bbc557d PF	349	err = mxs_gpio_init_gc(port, irq_base);
	350	if (err < 0)
	351	goto out_irqdomain_remove;
fba311fc	352
8d7cf837	353	/* setup one handler for each entry */
a44735f4 RK	354	irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
a44735f4 RK	355	port);
fba311fc	356
0f4630f3	357	err = bgpio_init(&port->gc, &pdev->dev, 4,
164387d2	358	port->base + PINCTRL_DIN(port),
90dae4eb MR	359	port->base + PINCTRL_DOUT(port) + MXS_SET,
90dae4eb MR	360	port->base + PINCTRL_DOUT(port) + MXS_CLR,
84a442b9	361	port->base + PINCTRL_DOE(port), NULL, 0);
8d7cf837	362	if (err)
0f4630f3	363	goto out_irqdomain_remove;
fba311fc	364
0f4630f3 LW	365	port->gc.to_irq = mxs_gpio_to_irq;
	366	port->gc.get_direction = mxs_gpio_get_direction;
	367	port->gc.base = port->id * 32;
06f88a8a	368
0f4630f3	369	err = gpiochip_add_data(&port->gc, port);
0b76c541	370	if (err)
0f4630f3	371	goto out_irqdomain_remove;
06f88a8a	372
8d7cf837	373	return 0;
0b76c541	374
1bbc557d PF	375	out_irqdomain_remove:
1bbc557d PF	376	irq_domain_remove(port->domain);
44df0819 AY	377	out_iounmap:
44df0819 AY	378	iounmap(port->base);
0b76c541	379	return err;
ef19660b	380	}
8d7cf837 SG	381
	382	static struct platform_driver mxs_gpio_driver = {
	383	.driver = {
	384	.name = "gpio-mxs",
4052d45e	385	.of_match_table = mxs_gpio_dt_ids,
60909ec9	386	.suppress_bind_attrs = true,
8d7cf837 SG	387	},
8d7cf837 SG	388	.probe = mxs_gpio_probe,
164387d2	389	.id_table = mxs_gpio_ids,
fba311fc	390	};
ef19660b	391
8d7cf837	392	static int __init mxs_gpio_init(void)
ef19660b	393	{
8d7cf837	394	return platform_driver_register(&mxs_gpio_driver);
ef19660b	395	}
8d7cf837 SG	396	postcore_initcall(mxs_gpio_init);
	397
	398	MODULE_AUTHOR("Freescale Semiconductor, "
	399	"Daniel Mack <danielncaiaq.de>, "
	400	"Juergen Beisert <kernel@pengutronix.de>");
	401	MODULE_DESCRIPTION("Freescale MXS GPIO");
	402	MODULE_LICENSE("GPL");