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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/device.h> | |
3e3c62ca | 16 | #include <linux/platform_device.h> |
2ec1d359 | 17 | #include <linux/io.h> |
af7dc228 RV |
18 | #include <linux/clk.h> |
19 | #include <linux/err.h> | |
2ec1d359 AR |
20 | #include <linux/gpio.h> |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/irq.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
2ec1d359 | 25 | |
adfed159 WD |
26 | #include <asm/mach/irq.h> |
27 | ||
378be066 | 28 | #include <plat/pincfg.h> |
2ec1d359 AR |
29 | #include <mach/hardware.h> |
30 | #include <mach/gpio.h> | |
31 | ||
32 | /* | |
33 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
34 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 35 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
36 | * |
37 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
38 | */ | |
39 | ||
01727e61 RV |
40 | #define NMK_GPIO_PER_CHIP 32 |
41 | ||
2ec1d359 AR |
42 | struct nmk_gpio_chip { |
43 | struct gpio_chip chip; | |
44 | void __iomem *addr; | |
af7dc228 | 45 | struct clk *clk; |
33b744b3 | 46 | unsigned int bank; |
2ec1d359 | 47 | unsigned int parent_irq; |
2c8bb0eb | 48 | int secondary_parent_irq; |
33b744b3 | 49 | u32 (*get_secondary_status)(unsigned int bank); |
01727e61 | 50 | void (*set_ioforce)(bool enable); |
c0fcb8db | 51 | spinlock_t lock; |
2ec1d359 AR |
52 | /* Keep track of configured edges */ |
53 | u32 edge_rising; | |
54 | u32 edge_falling; | |
b9df468d RV |
55 | u32 real_wake; |
56 | u32 rwimsc; | |
57 | u32 fwimsc; | |
58 | u32 slpm; | |
d1118f68 | 59 | u32 enabled; |
bc6f5cf6 | 60 | u32 pull_up; |
2ec1d359 AR |
61 | }; |
62 | ||
01727e61 RV |
63 | static struct nmk_gpio_chip * |
64 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
65 | ||
66 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
67 | ||
68 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
69 | ||
6f9a974c RV |
70 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
71 | unsigned offset, int gpio_mode) | |
72 | { | |
73 | u32 bit = 1 << offset; | |
74 | u32 afunc, bfunc; | |
75 | ||
76 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
77 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
78 | if (gpio_mode & NMK_GPIO_ALT_A) | |
79 | afunc |= bit; | |
80 | if (gpio_mode & NMK_GPIO_ALT_B) | |
81 | bfunc |= bit; | |
82 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
83 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
84 | } | |
85 | ||
81a3c298 RV |
86 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
87 | unsigned offset, enum nmk_gpio_slpm mode) | |
88 | { | |
89 | u32 bit = 1 << offset; | |
90 | u32 slpm; | |
91 | ||
92 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
93 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
94 | slpm |= bit; | |
95 | else | |
96 | slpm &= ~bit; | |
97 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
98 | } | |
99 | ||
5b327edf RV |
100 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
101 | unsigned offset, enum nmk_gpio_pull pull) | |
102 | { | |
103 | u32 bit = 1 << offset; | |
104 | u32 pdis; | |
105 | ||
106 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 107 | if (pull == NMK_GPIO_PULL_NONE) { |
5b327edf | 108 | pdis |= bit; |
bc6f5cf6 RA |
109 | nmk_chip->pull_up &= ~bit; |
110 | } else { | |
5b327edf | 111 | pdis &= ~bit; |
bc6f5cf6 RA |
112 | } |
113 | ||
5b327edf RV |
114 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
115 | ||
bc6f5cf6 RA |
116 | if (pull == NMK_GPIO_PULL_UP) { |
117 | nmk_chip->pull_up |= bit; | |
5b327edf | 118 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
bc6f5cf6 RA |
119 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
120 | nmk_chip->pull_up &= ~bit; | |
5b327edf | 121 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
bc6f5cf6 | 122 | } |
5b327edf RV |
123 | } |
124 | ||
378be066 RV |
125 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
126 | unsigned offset) | |
127 | { | |
128 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
129 | } | |
130 | ||
6720db7c RV |
131 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
132 | unsigned offset, int val) | |
133 | { | |
134 | if (val) | |
135 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
136 | else | |
137 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
138 | } | |
139 | ||
140 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
141 | unsigned offset, int val) | |
142 | { | |
143 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
144 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
145 | } | |
146 | ||
01727e61 RV |
147 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
148 | unsigned offset, int gpio_mode, | |
149 | bool glitch) | |
150 | { | |
3c4bee04 LW |
151 | u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC); |
152 | u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC); | |
01727e61 RV |
153 | |
154 | if (glitch && nmk_chip->set_ioforce) { | |
155 | u32 bit = BIT(offset); | |
156 | ||
01727e61 RV |
157 | /* Prevent spurious wakeups */ |
158 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
159 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
160 | ||
161 | nmk_chip->set_ioforce(true); | |
162 | } | |
163 | ||
164 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
165 | ||
166 | if (glitch && nmk_chip->set_ioforce) { | |
167 | nmk_chip->set_ioforce(false); | |
168 | ||
169 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
170 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
171 | } | |
172 | } | |
173 | ||
378be066 | 174 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
01727e61 | 175 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) |
378be066 RV |
176 | { |
177 | static const char *afnames[] = { | |
178 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
179 | [NMK_GPIO_ALT_A] = "A", | |
180 | [NMK_GPIO_ALT_B] = "B", | |
181 | [NMK_GPIO_ALT_C] = "C" | |
182 | }; | |
183 | static const char *pullnames[] = { | |
184 | [NMK_GPIO_PULL_NONE] = "none", | |
185 | [NMK_GPIO_PULL_UP] = "up", | |
186 | [NMK_GPIO_PULL_DOWN] = "down", | |
187 | [3] /* illegal */ = "??" | |
188 | }; | |
189 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
190 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
191 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
192 | }; |
193 | ||
194 | int pin = PIN_NUM(cfg); | |
195 | int pull = PIN_PULL(cfg); | |
196 | int af = PIN_ALT(cfg); | |
197 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
198 | int output = PIN_DIR(cfg); |
199 | int val = PIN_VAL(cfg); | |
01727e61 | 200 | bool glitch = af == NMK_GPIO_ALT_C; |
378be066 | 201 | |
dacdc96c RV |
202 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
203 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
204 | output ? "output " : "input", |
205 | output ? (val ? "high" : "low") : ""); | |
206 | ||
dacdc96c RV |
207 | if (sleep) { |
208 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
209 | int slpm_output = PIN_SLPM_DIR(cfg); | |
210 | int slpm_val = PIN_SLPM_VAL(cfg); | |
211 | ||
3546d15c RV |
212 | af = NMK_GPIO_ALT_GPIO; |
213 | ||
dacdc96c RV |
214 | /* |
215 | * The SLPM_* values are normal values + 1 to allow zero to | |
216 | * mean "same as normal". | |
217 | */ | |
218 | if (slpm_pull) | |
219 | pull = slpm_pull - 1; | |
220 | if (slpm_output) | |
221 | output = slpm_output - 1; | |
222 | if (slpm_val) | |
223 | val = slpm_val - 1; | |
224 | ||
225 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
226 | pin, | |
227 | slpm_pull ? pullnames[pull] : "same", | |
228 | slpm_output ? (output ? "output" : "input") : "same", | |
229 | slpm_val ? (val ? "high" : "low") : "same"); | |
230 | } | |
231 | ||
6720db7c RV |
232 | if (output) |
233 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
234 | else { | |
235 | __nmk_gpio_make_input(nmk_chip, offset); | |
236 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
237 | } | |
378be066 | 238 | |
01727e61 RV |
239 | /* |
240 | * If we've backed up the SLPM registers (glitch workaround), modify | |
241 | * the backups since they will be restored. | |
242 | */ | |
243 | if (slpmregs) { | |
244 | if (slpm == NMK_GPIO_SLPM_NOCHANGE) | |
245 | slpmregs[nmk_chip->bank] |= BIT(offset); | |
246 | else | |
247 | slpmregs[nmk_chip->bank] &= ~BIT(offset); | |
248 | } else | |
249 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); | |
250 | ||
251 | __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); | |
252 | } | |
253 | ||
254 | /* | |
255 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
256 | * - Save SLPM registers | |
257 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
258 | * - Configure the GPIO registers for the IOs that are being switched | |
259 | * - Set IOFORCE=1 | |
260 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
261 | * - Set IOFORCE=0 | |
262 | * - Restore SLPM registers | |
263 | * - Any spurious wake up event during switch sequence to be ignored and | |
264 | * cleared | |
265 | */ | |
266 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
267 | { | |
268 | int i; | |
269 | ||
270 | for (i = 0; i < NUM_BANKS; i++) { | |
271 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
272 | unsigned int temp = slpm[i]; | |
273 | ||
274 | if (!chip) | |
275 | break; | |
276 | ||
277 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); | |
278 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
279 | } | |
280 | } | |
281 | ||
282 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
283 | { | |
284 | int i; | |
285 | ||
286 | for (i = 0; i < NUM_BANKS; i++) { | |
287 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
288 | ||
289 | if (!chip) | |
290 | break; | |
291 | ||
292 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
293 | } | |
294 | } | |
295 | ||
296 | static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |
297 | { | |
298 | static unsigned int slpm[NUM_BANKS]; | |
299 | unsigned long flags; | |
300 | bool glitch = false; | |
301 | int ret = 0; | |
302 | int i; | |
303 | ||
304 | for (i = 0; i < num; i++) { | |
305 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { | |
306 | glitch = true; | |
307 | break; | |
308 | } | |
309 | } | |
310 | ||
311 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
312 | ||
313 | if (glitch) { | |
314 | memset(slpm, 0xff, sizeof(slpm)); | |
315 | ||
316 | for (i = 0; i < num; i++) { | |
317 | int pin = PIN_NUM(cfgs[i]); | |
318 | int offset = pin % NMK_GPIO_PER_CHIP; | |
319 | ||
320 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) | |
321 | slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); | |
322 | } | |
323 | ||
324 | nmk_gpio_glitch_slpm_init(slpm); | |
325 | } | |
326 | ||
327 | for (i = 0; i < num; i++) { | |
328 | struct nmk_gpio_chip *nmk_chip; | |
329 | int pin = PIN_NUM(cfgs[i]); | |
330 | ||
6845664a | 331 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); |
01727e61 RV |
332 | if (!nmk_chip) { |
333 | ret = -EINVAL; | |
334 | break; | |
335 | } | |
336 | ||
337 | spin_lock(&nmk_chip->lock); | |
338 | __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base, | |
339 | cfgs[i], sleep, glitch ? slpm : NULL); | |
340 | spin_unlock(&nmk_chip->lock); | |
341 | } | |
342 | ||
343 | if (glitch) | |
344 | nmk_gpio_glitch_slpm_restore(slpm); | |
345 | ||
346 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
347 | ||
348 | return ret; | |
378be066 RV |
349 | } |
350 | ||
351 | /** | |
352 | * nmk_config_pin - configure a pin's mux attributes | |
353 | * @cfg: pin confguration | |
354 | * | |
355 | * Configures a pin's mode (alternate function or GPIO), its pull up status, | |
356 | * and its sleep mode based on the specified configuration. The @cfg is | |
357 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
358 | * are constructed using, and can be further enhanced with, the macros in | |
359 | * plat/pincfg.h. | |
360 | * | |
361 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
362 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
363 | * calls. | |
364 | */ | |
dacdc96c | 365 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 | 366 | { |
01727e61 | 367 | return __nmk_config_pins(&cfg, 1, sleep); |
378be066 RV |
368 | } |
369 | EXPORT_SYMBOL(nmk_config_pin); | |
370 | ||
371 | /** | |
372 | * nmk_config_pins - configure several pins at once | |
373 | * @cfgs: array of pin configurations | |
374 | * @num: number of elments in the array | |
375 | * | |
376 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
377 | * further information. | |
378 | */ | |
379 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
380 | { | |
01727e61 | 381 | return __nmk_config_pins(cfgs, num, false); |
378be066 RV |
382 | } |
383 | EXPORT_SYMBOL(nmk_config_pins); | |
384 | ||
dacdc96c RV |
385 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
386 | { | |
01727e61 | 387 | return __nmk_config_pins(cfgs, num, true); |
dacdc96c RV |
388 | } |
389 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
390 | ||
81a3c298 RV |
391 | /** |
392 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
393 | * @gpio: pin number | |
394 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
395 | * | |
396 | * Sets the sleep mode of a pin. If @mode is NMK_GPIO_SLPM_INPUT, the pin is | |
397 | * changed to an input (with pullup/down enabled) in sleep and deep sleep. If | |
398 | * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was | |
399 | * configured even when in sleep and deep sleep. | |
7e3f7e59 RV |
400 | * |
401 | * On DB8500v2 onwards, this setting loses the previous meaning and instead | |
402 | * indicates if wakeup detection is enabled on the pin. Note that | |
403 | * enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
404 | */ |
405 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
406 | { | |
407 | struct nmk_gpio_chip *nmk_chip; | |
408 | unsigned long flags; | |
409 | ||
6845664a | 410 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
81a3c298 RV |
411 | if (!nmk_chip) |
412 | return -EINVAL; | |
413 | ||
01727e61 RV |
414 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
415 | spin_lock(&nmk_chip->lock); | |
416 | ||
81a3c298 | 417 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); |
01727e61 RV |
418 | |
419 | spin_unlock(&nmk_chip->lock); | |
420 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
81a3c298 RV |
421 | |
422 | return 0; | |
423 | } | |
424 | ||
5b327edf RV |
425 | /** |
426 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
427 | * @gpio: pin number | |
428 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
429 | * | |
430 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
431 | * the pin is configured as an input (either explicitly or by the alternate | |
432 | * function). | |
433 | * | |
434 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
435 | * configured as an input. Otherwise, due to the way the controller registers | |
436 | * work, this function will change the value output on the pin. | |
437 | */ | |
438 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
439 | { | |
440 | struct nmk_gpio_chip *nmk_chip; | |
441 | unsigned long flags; | |
442 | ||
6845664a | 443 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
5b327edf RV |
444 | if (!nmk_chip) |
445 | return -EINVAL; | |
446 | ||
447 | spin_lock_irqsave(&nmk_chip->lock, flags); | |
448 | __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); | |
449 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
2ec1d359 | 454 | /* Mode functions */ |
9c66ee6f JA |
455 | /** |
456 | * nmk_gpio_set_mode() - set the mux mode of a gpio pin | |
457 | * @gpio: pin number | |
458 | * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, | |
459 | * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C | |
460 | * | |
461 | * Sets the mode of the specified pin to one of the alternate functions or | |
462 | * plain GPIO. | |
463 | */ | |
2ec1d359 AR |
464 | int nmk_gpio_set_mode(int gpio, int gpio_mode) |
465 | { | |
466 | struct nmk_gpio_chip *nmk_chip; | |
467 | unsigned long flags; | |
2ec1d359 | 468 | |
6845664a | 469 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
2ec1d359 AR |
470 | if (!nmk_chip) |
471 | return -EINVAL; | |
472 | ||
2ec1d359 | 473 | spin_lock_irqsave(&nmk_chip->lock, flags); |
6f9a974c | 474 | __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); |
2ec1d359 AR |
475 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
476 | ||
477 | return 0; | |
478 | } | |
479 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
480 | ||
481 | int nmk_gpio_get_mode(int gpio) | |
482 | { | |
483 | struct nmk_gpio_chip *nmk_chip; | |
484 | u32 afunc, bfunc, bit; | |
485 | ||
6845664a | 486 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
2ec1d359 AR |
487 | if (!nmk_chip) |
488 | return -EINVAL; | |
489 | ||
490 | bit = 1 << (gpio - nmk_chip->chip.base); | |
491 | ||
492 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; | |
493 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
494 | ||
495 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); | |
496 | } | |
497 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
498 | ||
499 | ||
500 | /* IRQ functions */ | |
501 | static inline int nmk_gpio_get_bitmask(int gpio) | |
502 | { | |
503 | return 1 << (gpio % 32); | |
504 | } | |
505 | ||
f272c00e | 506 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 AR |
507 | { |
508 | int gpio; | |
509 | struct nmk_gpio_chip *nmk_chip; | |
510 | ||
f272c00e LB |
511 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
512 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
513 | if (!nmk_chip) |
514 | return; | |
515 | writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); | |
516 | } | |
517 | ||
4d4e20f7 RV |
518 | enum nmk_gpio_irq_type { |
519 | NORMAL, | |
520 | WAKE, | |
521 | }; | |
522 | ||
040e5ecd | 523 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
524 | int gpio, enum nmk_gpio_irq_type which, |
525 | bool enable) | |
2ec1d359 | 526 | { |
4d4e20f7 RV |
527 | u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC; |
528 | u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC; | |
040e5ecd RV |
529 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
530 | u32 reg; | |
2ec1d359 | 531 | |
040e5ecd | 532 | /* we must individually set/clear the two edges */ |
2ec1d359 | 533 | if (nmk_chip->edge_rising & bitmask) { |
4d4e20f7 | 534 | reg = readl(nmk_chip->addr + rimsc); |
040e5ecd RV |
535 | if (enable) |
536 | reg |= bitmask; | |
537 | else | |
538 | reg &= ~bitmask; | |
4d4e20f7 | 539 | writel(reg, nmk_chip->addr + rimsc); |
2ec1d359 AR |
540 | } |
541 | if (nmk_chip->edge_falling & bitmask) { | |
4d4e20f7 | 542 | reg = readl(nmk_chip->addr + fimsc); |
040e5ecd RV |
543 | if (enable) |
544 | reg |= bitmask; | |
545 | else | |
546 | reg &= ~bitmask; | |
4d4e20f7 | 547 | writel(reg, nmk_chip->addr + fimsc); |
2ec1d359 | 548 | } |
040e5ecd | 549 | } |
2ec1d359 | 550 | |
b9df468d RV |
551 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
552 | int gpio, bool on) | |
553 | { | |
b9df468d RV |
554 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
555 | } | |
556 | ||
557 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 AR |
558 | { |
559 | int gpio; | |
560 | struct nmk_gpio_chip *nmk_chip; | |
561 | unsigned long flags; | |
040e5ecd | 562 | u32 bitmask; |
2ec1d359 | 563 | |
f272c00e LB |
564 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
565 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
566 | bitmask = nmk_gpio_get_bitmask(gpio); |
567 | if (!nmk_chip) | |
4d4e20f7 | 568 | return -EINVAL; |
2ec1d359 | 569 | |
d1118f68 TG |
570 | if (enable) |
571 | nmk_chip->enabled |= bitmask; | |
572 | else | |
573 | nmk_chip->enabled &= ~bitmask; | |
574 | ||
b9df468d RV |
575 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
576 | spin_lock(&nmk_chip->lock); | |
577 | ||
578 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable); | |
579 | ||
580 | if (!(nmk_chip->real_wake & bitmask)) | |
581 | __nmk_gpio_set_wake(nmk_chip, gpio, enable); | |
582 | ||
583 | spin_unlock(&nmk_chip->lock); | |
584 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
4d4e20f7 RV |
585 | |
586 | return 0; | |
2ec1d359 AR |
587 | } |
588 | ||
f272c00e | 589 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 590 | { |
b9df468d | 591 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 592 | } |
040e5ecd | 593 | |
f272c00e | 594 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 595 | { |
b9df468d | 596 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
597 | } |
598 | ||
f272c00e | 599 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 600 | { |
7e3f7e59 RV |
601 | struct nmk_gpio_chip *nmk_chip; |
602 | unsigned long flags; | |
b9df468d | 603 | u32 bitmask; |
7e3f7e59 RV |
604 | int gpio; |
605 | ||
f272c00e LB |
606 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
607 | nmk_chip = irq_data_get_irq_chip_data(d); | |
7e3f7e59 RV |
608 | if (!nmk_chip) |
609 | return -EINVAL; | |
b9df468d | 610 | bitmask = nmk_gpio_get_bitmask(gpio); |
7e3f7e59 | 611 | |
01727e61 RV |
612 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
613 | spin_lock(&nmk_chip->lock); | |
614 | ||
d1118f68 | 615 | if (!(nmk_chip->enabled & bitmask)) |
b9df468d RV |
616 | __nmk_gpio_set_wake(nmk_chip, gpio, on); |
617 | ||
618 | if (on) | |
619 | nmk_chip->real_wake |= bitmask; | |
620 | else | |
621 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
622 | |
623 | spin_unlock(&nmk_chip->lock); | |
624 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
7e3f7e59 RV |
625 | |
626 | return 0; | |
040e5ecd RV |
627 | } |
628 | ||
f272c00e | 629 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 630 | { |
d1118f68 | 631 | bool enabled, wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
632 | int gpio; |
633 | struct nmk_gpio_chip *nmk_chip; | |
634 | unsigned long flags; | |
635 | u32 bitmask; | |
636 | ||
f272c00e LB |
637 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
638 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
639 | bitmask = nmk_gpio_get_bitmask(gpio); |
640 | if (!nmk_chip) | |
641 | return -EINVAL; | |
642 | ||
643 | if (type & IRQ_TYPE_LEVEL_HIGH) | |
644 | return -EINVAL; | |
645 | if (type & IRQ_TYPE_LEVEL_LOW) | |
646 | return -EINVAL; | |
647 | ||
d1118f68 TG |
648 | enabled = nmk_chip->enabled & bitmask; |
649 | ||
2ec1d359 AR |
650 | spin_lock_irqsave(&nmk_chip->lock, flags); |
651 | ||
7a852d80 | 652 | if (enabled) |
4d4e20f7 RV |
653 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); |
654 | ||
b9df468d | 655 | if (enabled || wake) |
4d4e20f7 | 656 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); |
7a852d80 | 657 | |
2ec1d359 AR |
658 | nmk_chip->edge_rising &= ~bitmask; |
659 | if (type & IRQ_TYPE_EDGE_RISING) | |
660 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
661 | |
662 | nmk_chip->edge_falling &= ~bitmask; | |
663 | if (type & IRQ_TYPE_EDGE_FALLING) | |
664 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 665 | |
7a852d80 | 666 | if (enabled) |
4d4e20f7 RV |
667 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); |
668 | ||
b9df468d | 669 | if (enabled || wake) |
4d4e20f7 | 670 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); |
2ec1d359 | 671 | |
7a852d80 | 672 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
2ec1d359 AR |
673 | |
674 | return 0; | |
675 | } | |
676 | ||
677 | static struct irq_chip nmk_gpio_irq_chip = { | |
678 | .name = "Nomadik-GPIO", | |
f272c00e LB |
679 | .irq_ack = nmk_gpio_irq_ack, |
680 | .irq_mask = nmk_gpio_irq_mask, | |
681 | .irq_unmask = nmk_gpio_irq_unmask, | |
682 | .irq_set_type = nmk_gpio_irq_set_type, | |
683 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
2ec1d359 AR |
684 | }; |
685 | ||
33b744b3 RV |
686 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
687 | u32 status) | |
2ec1d359 AR |
688 | { |
689 | struct nmk_gpio_chip *nmk_chip; | |
6845664a | 690 | struct irq_chip *host_chip = irq_get_chip(irq); |
2ec1d359 AR |
691 | unsigned int first_irq; |
692 | ||
adfed159 | 693 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 694 | |
6845664a | 695 | nmk_chip = irq_get_handler_data(irq); |
2ec1d359 | 696 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); |
33b744b3 RV |
697 | while (status) { |
698 | int bit = __ffs(status); | |
699 | ||
700 | generic_handle_irq(first_irq + bit); | |
701 | status &= ~BIT(bit); | |
2ec1d359 | 702 | } |
aaedaa2b | 703 | |
adfed159 | 704 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
705 | } |
706 | ||
33b744b3 RV |
707 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
708 | { | |
6845664a | 709 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
710 | u32 status = readl(nmk_chip->addr + NMK_GPIO_IS); |
711 | ||
712 | __nmk_gpio_irq_handler(irq, desc, status); | |
713 | } | |
714 | ||
715 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
716 | struct irq_desc *desc) | |
717 | { | |
6845664a | 718 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
719 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
720 | ||
721 | __nmk_gpio_irq_handler(irq, desc, status); | |
722 | } | |
723 | ||
2ec1d359 AR |
724 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
725 | { | |
726 | unsigned int first_irq; | |
727 | int i; | |
728 | ||
729 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | |
e493e06f | 730 | for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { |
f38c02f3 TG |
731 | irq_set_chip_and_handler(i, &nmk_gpio_irq_chip, |
732 | handle_edge_irq); | |
2ec1d359 | 733 | set_irq_flags(i, IRQF_VALID); |
6845664a TG |
734 | irq_set_chip_data(i, nmk_chip); |
735 | irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); | |
2ec1d359 | 736 | } |
33b744b3 | 737 | |
6845664a TG |
738 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
739 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
740 | |
741 | if (nmk_chip->secondary_parent_irq >= 0) { | |
6845664a | 742 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
33b744b3 | 743 | nmk_gpio_secondary_irq_handler); |
6845664a | 744 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
33b744b3 RV |
745 | } |
746 | ||
2ec1d359 AR |
747 | return 0; |
748 | } | |
749 | ||
750 | /* I/O Functions */ | |
751 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) | |
752 | { | |
753 | struct nmk_gpio_chip *nmk_chip = | |
754 | container_of(chip, struct nmk_gpio_chip, chip); | |
755 | ||
756 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
757 | return 0; | |
758 | } | |
759 | ||
2ec1d359 AR |
760 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
761 | { | |
762 | struct nmk_gpio_chip *nmk_chip = | |
763 | container_of(chip, struct nmk_gpio_chip, chip); | |
764 | u32 bit = 1 << offset; | |
765 | ||
766 | return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; | |
767 | } | |
768 | ||
769 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
770 | int val) | |
771 | { | |
772 | struct nmk_gpio_chip *nmk_chip = | |
773 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 774 | |
6720db7c | 775 | __nmk_gpio_set_output(nmk_chip, offset, val); |
2ec1d359 AR |
776 | } |
777 | ||
6647c6c0 RV |
778 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
779 | int val) | |
780 | { | |
781 | struct nmk_gpio_chip *nmk_chip = | |
782 | container_of(chip, struct nmk_gpio_chip, chip); | |
783 | ||
6720db7c | 784 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 RV |
785 | |
786 | return 0; | |
787 | } | |
788 | ||
0d2aec9c RV |
789 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
790 | { | |
791 | struct nmk_gpio_chip *nmk_chip = | |
792 | container_of(chip, struct nmk_gpio_chip, chip); | |
793 | ||
794 | return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; | |
795 | } | |
796 | ||
d0b543c7 RV |
797 | #ifdef CONFIG_DEBUG_FS |
798 | ||
799 | #include <linux/seq_file.h> | |
800 | ||
801 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
802 | { | |
803 | int mode; | |
804 | unsigned i; | |
805 | unsigned gpio = chip->base; | |
806 | int is_out; | |
807 | struct nmk_gpio_chip *nmk_chip = | |
808 | container_of(chip, struct nmk_gpio_chip, chip); | |
809 | const char *modes[] = { | |
810 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
811 | [NMK_GPIO_ALT_A] = "altA", | |
812 | [NMK_GPIO_ALT_B] = "altB", | |
813 | [NMK_GPIO_ALT_C] = "altC", | |
814 | }; | |
815 | ||
816 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
817 | const char *label = gpiochip_is_requested(chip, i); | |
818 | bool pull; | |
819 | u32 bit = 1 << i; | |
820 | ||
d0b543c7 RV |
821 | is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; |
822 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
823 | mode = nmk_gpio_get_mode(gpio); | |
824 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
8ea72a30 | 825 | gpio, label ?: "(none)", |
d0b543c7 RV |
826 | is_out ? "out" : "in ", |
827 | chip->get | |
828 | ? (chip->get(chip, i) ? "hi" : "lo") | |
829 | : "? ", | |
830 | (mode < 0) ? "unknown" : modes[mode], | |
831 | pull ? "pull" : "none"); | |
8ea72a30 RV |
832 | |
833 | if (label && !is_out) { | |
834 | int irq = gpio_to_irq(gpio); | |
835 | struct irq_desc *desc = irq_to_desc(irq); | |
836 | ||
837 | /* This races with request_irq(), set_irq_type(), | |
838 | * and set_irq_wake() ... but those are "rare". | |
839 | */ | |
840 | if (irq >= 0 && desc->action) { | |
841 | char *trigger; | |
842 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | |
843 | ||
844 | if (nmk_chip->edge_rising & bitmask) | |
845 | trigger = "edge-rising"; | |
846 | else if (nmk_chip->edge_falling & bitmask) | |
847 | trigger = "edge-falling"; | |
848 | else | |
849 | trigger = "edge-undefined"; | |
850 | ||
851 | seq_printf(s, " irq-%d %s%s", | |
852 | irq, trigger, | |
853 | irqd_is_wakeup_set(&desc->irq_data) | |
854 | ? " wakeup" : ""); | |
855 | } | |
856 | } | |
857 | ||
d0b543c7 RV |
858 | seq_printf(s, "\n"); |
859 | } | |
860 | } | |
861 | ||
862 | #else | |
863 | #define nmk_gpio_dbg_show NULL | |
864 | #endif | |
865 | ||
2ec1d359 AR |
866 | /* This structure is replicated for each GPIO block allocated at probe time */ |
867 | static struct gpio_chip nmk_gpio_template = { | |
868 | .direction_input = nmk_gpio_make_input, | |
869 | .get = nmk_gpio_get_input, | |
870 | .direction_output = nmk_gpio_make_output, | |
871 | .set = nmk_gpio_set_output, | |
0d2aec9c | 872 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 873 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
874 | .can_sleep = 0, |
875 | }; | |
876 | ||
b9df468d RV |
877 | /* |
878 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
879 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
880 | * and not the rest of the interrupts which we needed to have as wakeups for | |
881 | * cpuidle. | |
882 | * | |
883 | * PM ops are not used since this needs to be done at the end, after all the | |
884 | * other drivers are done with their suspend callbacks. | |
885 | */ | |
886 | void nmk_gpio_wakeups_suspend(void) | |
887 | { | |
888 | int i; | |
889 | ||
890 | for (i = 0; i < NUM_BANKS; i++) { | |
891 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
892 | ||
893 | if (!chip) | |
894 | break; | |
895 | ||
896 | chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC); | |
897 | chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC); | |
898 | ||
899 | writel(chip->rwimsc & chip->real_wake, | |
900 | chip->addr + NMK_GPIO_RWIMSC); | |
901 | writel(chip->fwimsc & chip->real_wake, | |
902 | chip->addr + NMK_GPIO_FWIMSC); | |
903 | ||
904 | if (cpu_is_u8500v2()) { | |
905 | chip->slpm = readl(chip->addr + NMK_GPIO_SLPC); | |
906 | ||
907 | /* 0 -> wakeup enable */ | |
908 | writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC); | |
909 | } | |
910 | } | |
911 | } | |
912 | ||
913 | void nmk_gpio_wakeups_resume(void) | |
914 | { | |
915 | int i; | |
916 | ||
917 | for (i = 0; i < NUM_BANKS; i++) { | |
918 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
919 | ||
920 | if (!chip) | |
921 | break; | |
922 | ||
923 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); | |
924 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
925 | ||
926 | if (cpu_is_u8500v2()) | |
927 | writel(chip->slpm, chip->addr + NMK_GPIO_SLPC); | |
928 | } | |
929 | } | |
930 | ||
bc6f5cf6 RA |
931 | /* |
932 | * Read the pull up/pull down status. | |
933 | * A bit set in 'pull_up' means that pull up | |
934 | * is selected if pull is enabled in PDIS register. | |
935 | * Note: only pull up/down set via this driver can | |
936 | * be detected due to HW limitations. | |
937 | */ | |
938 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
939 | { | |
940 | if (gpio_bank < NUM_BANKS) { | |
941 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
942 | ||
943 | if (!chip) | |
944 | return; | |
945 | ||
946 | *pull_up = chip->pull_up; | |
947 | } | |
948 | } | |
949 | ||
fd0d67d6 | 950 | static int __devinit nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 951 | { |
3e3c62ca | 952 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
2ec1d359 AR |
953 | struct nmk_gpio_chip *nmk_chip; |
954 | struct gpio_chip *chip; | |
3e3c62ca | 955 | struct resource *res; |
af7dc228 | 956 | struct clk *clk; |
33b744b3 | 957 | int secondary_irq; |
3e3c62ca | 958 | int irq; |
2ec1d359 AR |
959 | int ret; |
960 | ||
3e3c62ca RV |
961 | if (!pdata) |
962 | return -ENODEV; | |
963 | ||
964 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
965 | if (!res) { | |
966 | ret = -ENOENT; | |
967 | goto out; | |
968 | } | |
969 | ||
970 | irq = platform_get_irq(dev, 0); | |
971 | if (irq < 0) { | |
972 | ret = irq; | |
973 | goto out; | |
974 | } | |
975 | ||
33b744b3 RV |
976 | secondary_irq = platform_get_irq(dev, 1); |
977 | if (secondary_irq >= 0 && !pdata->get_secondary_status) { | |
978 | ret = -EINVAL; | |
979 | goto out; | |
980 | } | |
981 | ||
3e3c62ca RV |
982 | if (request_mem_region(res->start, resource_size(res), |
983 | dev_name(&dev->dev)) == NULL) { | |
984 | ret = -EBUSY; | |
985 | goto out; | |
986 | } | |
2ec1d359 | 987 | |
af7dc228 RV |
988 | clk = clk_get(&dev->dev, NULL); |
989 | if (IS_ERR(clk)) { | |
990 | ret = PTR_ERR(clk); | |
991 | goto out_release; | |
992 | } | |
993 | ||
994 | clk_enable(clk); | |
995 | ||
2ec1d359 AR |
996 | nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); |
997 | if (!nmk_chip) { | |
998 | ret = -ENOMEM; | |
af7dc228 | 999 | goto out_clk; |
2ec1d359 AR |
1000 | } |
1001 | /* | |
1002 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1003 | * so we can simply convert the resource address, without remapping | |
1004 | */ | |
33b744b3 | 1005 | nmk_chip->bank = dev->id; |
af7dc228 | 1006 | nmk_chip->clk = clk; |
3e3c62ca | 1007 | nmk_chip->addr = io_p2v(res->start); |
2ec1d359 | 1008 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 1009 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
1010 | nmk_chip->secondary_parent_irq = secondary_irq; |
1011 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
01727e61 | 1012 | nmk_chip->set_ioforce = pdata->set_ioforce; |
c0fcb8db | 1013 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1014 | |
1015 | chip = &nmk_chip->chip; | |
1016 | chip->base = pdata->first_gpio; | |
e493e06f | 1017 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 1018 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
1019 | chip->dev = &dev->dev; |
1020 | chip->owner = THIS_MODULE; | |
1021 | ||
1022 | ret = gpiochip_add(&nmk_chip->chip); | |
1023 | if (ret) | |
1024 | goto out_free; | |
1025 | ||
01727e61 RV |
1026 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1027 | ||
1028 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
3e3c62ca | 1029 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 AR |
1030 | |
1031 | nmk_gpio_init_irq(nmk_chip); | |
1032 | ||
1033 | dev_info(&dev->dev, "Bits %i-%i at address %p\n", | |
1034 | nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr); | |
1035 | return 0; | |
1036 | ||
3e3c62ca | 1037 | out_free: |
2ec1d359 | 1038 | kfree(nmk_chip); |
af7dc228 RV |
1039 | out_clk: |
1040 | clk_disable(clk); | |
1041 | clk_put(clk); | |
3e3c62ca RV |
1042 | out_release: |
1043 | release_mem_region(res->start, resource_size(res)); | |
1044 | out: | |
2ec1d359 AR |
1045 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
1046 | pdata->first_gpio, pdata->first_gpio+31); | |
1047 | return ret; | |
1048 | } | |
1049 | ||
3e3c62ca RV |
1050 | static struct platform_driver nmk_gpio_driver = { |
1051 | .driver = { | |
2ec1d359 AR |
1052 | .owner = THIS_MODULE, |
1053 | .name = "gpio", | |
5317e4d1 | 1054 | }, |
2ec1d359 | 1055 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
1056 | }; |
1057 | ||
1058 | static int __init nmk_gpio_init(void) | |
1059 | { | |
3e3c62ca | 1060 | return platform_driver_register(&nmk_gpio_driver); |
2ec1d359 AR |
1061 | } |
1062 | ||
33f45ea9 | 1063 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
1064 | |
1065 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
1066 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
1067 | MODULE_LICENSE("GPL"); | |
1068 | ||
1069 |