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Commit | Line | Data |
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5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/irqdomain.h> | |
de88cbb7 | 28 | #include <linux/irqchip/chained_irq.h> |
4b25408f TL |
29 | #include <linux/gpio.h> |
30 | #include <linux/platform_data/gpio-omap.h> | |
5e1c5ff4 | 31 | |
2dc983c5 TKD |
32 | #define OFF_MODE 1 |
33 | ||
03e128ca C |
34 | static LIST_HEAD(omap_gpio_list); |
35 | ||
6d62e216 C |
36 | struct gpio_regs { |
37 | u32 irqenable1; | |
38 | u32 irqenable2; | |
39 | u32 wake_en; | |
40 | u32 ctrl; | |
41 | u32 oe; | |
42 | u32 leveldetect0; | |
43 | u32 leveldetect1; | |
44 | u32 risingdetect; | |
45 | u32 fallingdetect; | |
46 | u32 dataout; | |
ae547354 NM |
47 | u32 debounce; |
48 | u32 debounce_en; | |
6d62e216 C |
49 | }; |
50 | ||
5e1c5ff4 | 51 | struct gpio_bank { |
03e128ca | 52 | struct list_head node; |
92105bb7 | 53 | void __iomem *base; |
5e1c5ff4 | 54 | u16 irq; |
384ebe1c | 55 | struct irq_domain *domain; |
3ac4fa99 JY |
56 | u32 non_wakeup_gpios; |
57 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 58 | struct gpio_regs context; |
3ac4fa99 | 59 | u32 saved_datain; |
b144ff6f | 60 | u32 level_mask; |
4318f36b | 61 | u32 toggle_mask; |
5e1c5ff4 | 62 | spinlock_t lock; |
52e31344 | 63 | struct gpio_chip chip; |
89db9482 | 64 | struct clk *dbck; |
058af1ea | 65 | u32 mod_usage; |
8865b9b6 | 66 | u32 dbck_enable_mask; |
72f83af9 | 67 | bool dbck_enabled; |
77640aab | 68 | struct device *dev; |
d0d665a8 | 69 | bool is_mpuio; |
77640aab | 70 | bool dbck_flag; |
0cde8d03 | 71 | bool loses_context; |
352a2d5b | 72 | bool context_valid; |
5de62b86 | 73 | int stride; |
d5f46247 | 74 | u32 width; |
60a3437d | 75 | int context_loss_count; |
2dc983c5 TKD |
76 | int power_mode; |
77 | bool workaround_enabled; | |
fa87931a KH |
78 | |
79 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60a3437d | 80 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
81 | |
82 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
83 | }; |
84 | ||
129fd223 KH |
85 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
86 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
c8eef65a | 87 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 88 | |
25db711d BC |
89 | static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq) |
90 | { | |
ede4d7a5 JH |
91 | return bank->chip.base + gpio_irq; |
92 | } | |
93 | ||
94 | static int omap_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
95 | { | |
96 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); | |
97 | ||
98 | return irq_find_mapping(bank->domain, offset); | |
25db711d BC |
99 | } |
100 | ||
5e1c5ff4 TL |
101 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) |
102 | { | |
92105bb7 | 103 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
104 | u32 l; |
105 | ||
fa87931a | 106 | reg += bank->regs->direction; |
5e1c5ff4 TL |
107 | l = __raw_readl(reg); |
108 | if (is_input) | |
109 | l |= 1 << gpio; | |
110 | else | |
111 | l &= ~(1 << gpio); | |
112 | __raw_writel(l, reg); | |
41d87cbd | 113 | bank->context.oe = l; |
5e1c5ff4 TL |
114 | } |
115 | ||
fa87931a KH |
116 | |
117 | /* set data out value using dedicate set/clear register */ | |
118 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 119 | { |
92105bb7 | 120 | void __iomem *reg = bank->base; |
fa87931a | 121 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 122 | |
2c836f7e | 123 | if (enable) { |
fa87931a | 124 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
125 | bank->context.dataout |= l; |
126 | } else { | |
fa87931a | 127 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
128 | bank->context.dataout &= ~l; |
129 | } | |
5e1c5ff4 | 130 | |
5e1c5ff4 TL |
131 | __raw_writel(l, reg); |
132 | } | |
133 | ||
fa87931a KH |
134 | /* set data out value using mask register */ |
135 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 136 | { |
fa87931a KH |
137 | void __iomem *reg = bank->base + bank->regs->dataout; |
138 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
139 | u32 l; | |
5e1c5ff4 | 140 | |
fa87931a KH |
141 | l = __raw_readl(reg); |
142 | if (enable) | |
143 | l |= gpio_bit; | |
144 | else | |
145 | l &= ~gpio_bit; | |
5e1c5ff4 | 146 | __raw_writel(l, reg); |
41d87cbd | 147 | bank->context.dataout = l; |
5e1c5ff4 TL |
148 | } |
149 | ||
7fcca715 | 150 | static int _get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 151 | { |
fa87931a | 152 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 153 | |
7fcca715 | 154 | return (__raw_readl(reg) & (1 << offset)) != 0; |
5e1c5ff4 | 155 | } |
b37c45b8 | 156 | |
7fcca715 | 157 | static int _get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 158 | { |
fa87931a | 159 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 160 | |
7fcca715 | 161 | return (__raw_readl(reg) & (1 << offset)) != 0; |
b37c45b8 RQ |
162 | } |
163 | ||
ece9528e KH |
164 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
165 | { | |
166 | int l = __raw_readl(base + reg); | |
167 | ||
862ff640 | 168 | if (set) |
ece9528e KH |
169 | l |= mask; |
170 | else | |
171 | l &= ~mask; | |
172 | ||
173 | __raw_writel(l, base + reg); | |
174 | } | |
92105bb7 | 175 | |
72f83af9 TKD |
176 | static inline void _gpio_dbck_enable(struct gpio_bank *bank) |
177 | { | |
178 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
179 | clk_enable(bank->dbck); | |
180 | bank->dbck_enabled = true; | |
9e303f22 GI |
181 | |
182 | __raw_writel(bank->dbck_enable_mask, | |
183 | bank->base + bank->regs->debounce_en); | |
72f83af9 TKD |
184 | } |
185 | } | |
186 | ||
187 | static inline void _gpio_dbck_disable(struct gpio_bank *bank) | |
188 | { | |
189 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
190 | /* |
191 | * Disable debounce before cutting it's clock. If debounce is | |
192 | * enabled but the clock is not, GPIO module seems to be unable | |
193 | * to detect events and generate interrupts at least on OMAP3. | |
194 | */ | |
195 | __raw_writel(0, bank->base + bank->regs->debounce_en); | |
196 | ||
72f83af9 TKD |
197 | clk_disable(bank->dbck); |
198 | bank->dbck_enabled = false; | |
199 | } | |
200 | } | |
201 | ||
168ef3d9 FB |
202 | /** |
203 | * _set_gpio_debounce - low level gpio debounce time | |
204 | * @bank: the gpio bank we're acting upon | |
205 | * @gpio: the gpio number on this @gpio | |
206 | * @debounce: debounce time to use | |
207 | * | |
208 | * OMAP's debounce time is in 31us steps so we need | |
209 | * to convert and round up to the closest unit. | |
210 | */ | |
211 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
212 | unsigned debounce) | |
213 | { | |
9942da0e | 214 | void __iomem *reg; |
168ef3d9 FB |
215 | u32 val; |
216 | u32 l; | |
217 | ||
77640aab VC |
218 | if (!bank->dbck_flag) |
219 | return; | |
220 | ||
168ef3d9 FB |
221 | if (debounce < 32) |
222 | debounce = 0x01; | |
223 | else if (debounce > 7936) | |
224 | debounce = 0xff; | |
225 | else | |
226 | debounce = (debounce / 0x1f) - 1; | |
227 | ||
129fd223 | 228 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 229 | |
6fd9c421 | 230 | clk_enable(bank->dbck); |
9942da0e | 231 | reg = bank->base + bank->regs->debounce; |
168ef3d9 FB |
232 | __raw_writel(debounce, reg); |
233 | ||
9942da0e | 234 | reg = bank->base + bank->regs->debounce_en; |
168ef3d9 FB |
235 | val = __raw_readl(reg); |
236 | ||
6fd9c421 | 237 | if (debounce) |
168ef3d9 | 238 | val |= l; |
6fd9c421 | 239 | else |
168ef3d9 | 240 | val &= ~l; |
f7ec0b0b | 241 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
242 | |
243 | __raw_writel(val, reg); | |
6fd9c421 TKD |
244 | clk_disable(bank->dbck); |
245 | /* | |
246 | * Enable debounce clock per module. | |
247 | * This call is mandatory because in omap_gpio_request() when | |
248 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
249 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
250 | * used within _gpio_dbck_enable() is still not initialized at | |
251 | * that point. Therefore we have to enable dbck here. | |
252 | */ | |
253 | _gpio_dbck_enable(bank); | |
ae547354 NM |
254 | if (bank->dbck_enable_mask) { |
255 | bank->context.debounce = debounce; | |
256 | bank->context.debounce_en = val; | |
257 | } | |
168ef3d9 FB |
258 | } |
259 | ||
c9c55d92 JH |
260 | /** |
261 | * _clear_gpio_debounce - clear debounce settings for a gpio | |
262 | * @bank: the gpio bank we're acting upon | |
263 | * @gpio: the gpio number on this @gpio | |
264 | * | |
265 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
266 | * this is the only gpio in this bank using debounce, then clear the debounce | |
267 | * time too. The debounce clock will also be disabled when calling this function | |
268 | * if this is the only gpio in the bank using debounce. | |
269 | */ | |
270 | static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio) | |
271 | { | |
272 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
273 | ||
274 | if (!bank->dbck_flag) | |
275 | return; | |
276 | ||
277 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
278 | return; | |
279 | ||
280 | bank->dbck_enable_mask &= ~gpio_bit; | |
281 | bank->context.debounce_en &= ~gpio_bit; | |
282 | __raw_writel(bank->context.debounce_en, | |
283 | bank->base + bank->regs->debounce_en); | |
284 | ||
285 | if (!bank->dbck_enable_mask) { | |
286 | bank->context.debounce = 0; | |
287 | __raw_writel(bank->context.debounce, bank->base + | |
288 | bank->regs->debounce); | |
289 | clk_disable(bank->dbck); | |
290 | bank->dbck_enabled = false; | |
291 | } | |
292 | } | |
293 | ||
5e571f38 | 294 | static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 295 | unsigned trigger) |
5e1c5ff4 | 296 | { |
3ac4fa99 | 297 | void __iomem *base = bank->base; |
92105bb7 TL |
298 | u32 gpio_bit = 1 << gpio; |
299 | ||
5e571f38 TKD |
300 | _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
301 | trigger & IRQ_TYPE_LEVEL_LOW); | |
302 | _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
303 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
304 | _gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
305 | trigger & IRQ_TYPE_EDGE_RISING); | |
306 | _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
307 | trigger & IRQ_TYPE_EDGE_FALLING); | |
308 | ||
41d87cbd TKD |
309 | bank->context.leveldetect0 = |
310 | __raw_readl(bank->base + bank->regs->leveldetect0); | |
311 | bank->context.leveldetect1 = | |
312 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
313 | bank->context.risingdetect = | |
314 | __raw_readl(bank->base + bank->regs->risingdetect); | |
315 | bank->context.fallingdetect = | |
316 | __raw_readl(bank->base + bank->regs->fallingdetect); | |
317 | ||
318 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
5e571f38 | 319 | _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd TKD |
320 | bank->context.wake_en = |
321 | __raw_readl(bank->base + bank->regs->wkup_en); | |
322 | } | |
5e571f38 | 323 | |
55b220ca | 324 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
325 | if (!bank->regs->irqctrl) { |
326 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
327 | if (bank->non_wakeup_gpios) { | |
328 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
329 | goto exit; | |
330 | } | |
331 | ||
699117a6 CW |
332 | /* |
333 | * Log the edge gpio and manually trigger the IRQ | |
334 | * after resume if the input level changes | |
335 | * to avoid irq lost during PER RET/OFF mode | |
336 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
337 | */ | |
338 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
339 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
340 | else | |
341 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
342 | } | |
5eb3bb9c | 343 | |
5e571f38 | 344 | exit: |
9ea14d8c TKD |
345 | bank->level_mask = |
346 | __raw_readl(bank->base + bank->regs->leveldetect0) | | |
347 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
348 | } |
349 | ||
9198bcd3 | 350 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
351 | /* |
352 | * This only applies to chips that can't do both rising and falling edge | |
353 | * detection at once. For all other chips, this function is a noop. | |
354 | */ | |
355 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
356 | { | |
357 | void __iomem *reg = bank->base; | |
358 | u32 l = 0; | |
359 | ||
5e571f38 | 360 | if (!bank->regs->irqctrl) |
4318f36b | 361 | return; |
5e571f38 TKD |
362 | |
363 | reg += bank->regs->irqctrl; | |
4318f36b CM |
364 | |
365 | l = __raw_readl(reg); | |
366 | if ((l >> gpio) & 1) | |
367 | l &= ~(1 << gpio); | |
368 | else | |
369 | l |= 1 << gpio; | |
370 | ||
371 | __raw_writel(l, reg); | |
372 | } | |
5e571f38 TKD |
373 | #else |
374 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} | |
9198bcd3 | 375 | #endif |
4318f36b | 376 | |
00ece7e4 TKD |
377 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, |
378 | unsigned trigger) | |
92105bb7 TL |
379 | { |
380 | void __iomem *reg = bank->base; | |
5e571f38 | 381 | void __iomem *base = bank->base; |
92105bb7 | 382 | u32 l = 0; |
5e1c5ff4 | 383 | |
5e571f38 TKD |
384 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
385 | set_gpio_trigger(bank, gpio, trigger); | |
386 | } else if (bank->regs->irqctrl) { | |
387 | reg += bank->regs->irqctrl; | |
388 | ||
5e1c5ff4 | 389 | l = __raw_readl(reg); |
29501577 | 390 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 391 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 392 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 393 | l |= 1 << gpio; |
6cab4860 | 394 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 395 | l &= ~(1 << gpio); |
92105bb7 | 396 | else |
5e571f38 TKD |
397 | return -EINVAL; |
398 | ||
399 | __raw_writel(l, reg); | |
400 | } else if (bank->regs->edgectrl1) { | |
5e1c5ff4 | 401 | if (gpio & 0x08) |
5e571f38 | 402 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 403 | else |
5e571f38 TKD |
404 | reg += bank->regs->edgectrl1; |
405 | ||
5e1c5ff4 TL |
406 | gpio &= 0x07; |
407 | l = __raw_readl(reg); | |
408 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 409 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 410 | l |= 2 << (gpio << 1); |
6cab4860 | 411 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 412 | l |= 1 << (gpio << 1); |
5e571f38 TKD |
413 | |
414 | /* Enable wake-up during idle for dynamic tick */ | |
415 | _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger); | |
41d87cbd TKD |
416 | bank->context.wake_en = |
417 | __raw_readl(bank->base + bank->regs->wkup_en); | |
5e571f38 | 418 | __raw_writel(l, reg); |
5e1c5ff4 | 419 | } |
92105bb7 | 420 | return 0; |
5e1c5ff4 TL |
421 | } |
422 | ||
e9191028 | 423 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 424 | { |
25db711d | 425 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
4b25408f | 426 | unsigned gpio = 0; |
92105bb7 | 427 | int retval; |
a6472533 | 428 | unsigned long flags; |
92105bb7 | 429 | |
8d4c277e JH |
430 | if (WARN_ON(!bank->mod_usage)) |
431 | return -EINVAL; | |
432 | ||
4b25408f TL |
433 | #ifdef CONFIG_ARCH_OMAP1 |
434 | if (d->irq > IH_MPUIO_BASE) | |
e9191028 | 435 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
4b25408f TL |
436 | #endif |
437 | ||
438 | if (!gpio) | |
ede4d7a5 | 439 | gpio = irq_to_gpio(bank, d->hwirq); |
5e1c5ff4 | 440 | |
e5c56ed3 | 441 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 442 | return -EINVAL; |
e5c56ed3 | 443 | |
9ea14d8c TKD |
444 | if (!bank->regs->leveldetect0 && |
445 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
446 | return -EINVAL; |
447 | ||
a6472533 | 448 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 449 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
a6472533 | 450 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
451 | |
452 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 453 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 454 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 455 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 456 | |
92105bb7 | 457 | return retval; |
5e1c5ff4 TL |
458 | } |
459 | ||
460 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
461 | { | |
92105bb7 | 462 | void __iomem *reg = bank->base; |
5e1c5ff4 | 463 | |
eef4bec7 | 464 | reg += bank->regs->irqstatus; |
5e1c5ff4 | 465 | __raw_writel(gpio_mask, reg); |
bee7930f HD |
466 | |
467 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
468 | if (bank->regs->irqstatus2) { |
469 | reg = bank->base + bank->regs->irqstatus2; | |
bedfd154 | 470 | __raw_writel(gpio_mask, reg); |
eef4bec7 | 471 | } |
bedfd154 RQ |
472 | |
473 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
474 | __raw_readl(reg); | |
5e1c5ff4 TL |
475 | } |
476 | ||
477 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
478 | { | |
129fd223 | 479 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
480 | } |
481 | ||
ea6dedd7 ID |
482 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
483 | { | |
484 | void __iomem *reg = bank->base; | |
99c47707 | 485 | u32 l; |
c390aad0 | 486 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 487 | |
28f3b5a0 | 488 | reg += bank->regs->irqenable; |
99c47707 | 489 | l = __raw_readl(reg); |
28f3b5a0 | 490 | if (bank->regs->irqenable_inv) |
99c47707 ID |
491 | l = ~l; |
492 | l &= mask; | |
493 | return l; | |
ea6dedd7 ID |
494 | } |
495 | ||
28f3b5a0 | 496 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 497 | { |
92105bb7 | 498 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
499 | u32 l; |
500 | ||
28f3b5a0 KH |
501 | if (bank->regs->set_irqenable) { |
502 | reg += bank->regs->set_irqenable; | |
503 | l = gpio_mask; | |
2a900eb7 | 504 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
505 | } else { |
506 | reg += bank->regs->irqenable; | |
5e1c5ff4 | 507 | l = __raw_readl(reg); |
28f3b5a0 KH |
508 | if (bank->regs->irqenable_inv) |
509 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
510 | else |
511 | l |= gpio_mask; | |
2a900eb7 | 512 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
513 | } |
514 | ||
515 | __raw_writel(l, reg); | |
516 | } | |
517 | ||
518 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
519 | { | |
520 | void __iomem *reg = bank->base; | |
521 | u32 l; | |
522 | ||
523 | if (bank->regs->clr_irqenable) { | |
524 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 525 | l = gpio_mask; |
2a900eb7 | 526 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
527 | } else { |
528 | reg += bank->regs->irqenable; | |
56739a69 | 529 | l = __raw_readl(reg); |
28f3b5a0 | 530 | if (bank->regs->irqenable_inv) |
56739a69 | 531 | l |= gpio_mask; |
92105bb7 | 532 | else |
28f3b5a0 | 533 | l &= ~gpio_mask; |
2a900eb7 | 534 | bank->context.irqenable1 = l; |
5e1c5ff4 | 535 | } |
28f3b5a0 | 536 | |
5e1c5ff4 TL |
537 | __raw_writel(l, reg); |
538 | } | |
539 | ||
540 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
541 | { | |
8276536c TKD |
542 | if (enable) |
543 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | |
544 | else | |
545 | _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | |
5e1c5ff4 TL |
546 | } |
547 | ||
92105bb7 TL |
548 | /* |
549 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
550 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
551 | * to the target, system will wake up always on GPIO events. While | |
552 | * system is running all registered GPIO interrupts need to have wake-up | |
553 | * enabled. When system is suspended, only selected GPIO interrupts need | |
554 | * to have wake-up enabled. | |
555 | */ | |
556 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
557 | { | |
f64ad1a0 KH |
558 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
559 | unsigned long flags; | |
a6472533 | 560 | |
f64ad1a0 | 561 | if (bank->non_wakeup_gpios & gpio_bit) { |
862ff640 | 562 | dev_err(bank->dev, |
f64ad1a0 | 563 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); |
92105bb7 TL |
564 | return -EINVAL; |
565 | } | |
f64ad1a0 KH |
566 | |
567 | spin_lock_irqsave(&bank->lock, flags); | |
568 | if (enable) | |
0aa27273 | 569 | bank->context.wake_en |= gpio_bit; |
f64ad1a0 | 570 | else |
0aa27273 | 571 | bank->context.wake_en &= ~gpio_bit; |
f64ad1a0 | 572 | |
0aa27273 | 573 | __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en); |
f64ad1a0 KH |
574 | spin_unlock_irqrestore(&bank->lock, flags); |
575 | ||
576 | return 0; | |
92105bb7 TL |
577 | } |
578 | ||
4196dd6b TL |
579 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
580 | { | |
129fd223 | 581 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
582 | _set_gpio_irqenable(bank, gpio, 0); |
583 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 584 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
c9c55d92 | 585 | _clear_gpio_debounce(bank, gpio); |
4196dd6b TL |
586 | } |
587 | ||
92105bb7 | 588 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 589 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 590 | { |
25db711d | 591 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 592 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
92105bb7 | 593 | |
25db711d | 594 | return _set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
595 | } |
596 | ||
3ff164e1 | 597 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 598 | { |
3ff164e1 | 599 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 600 | unsigned long flags; |
52e31344 | 601 | |
55b93c32 TKD |
602 | /* |
603 | * If this is the first gpio_request for the bank, | |
604 | * enable the bank module. | |
605 | */ | |
606 | if (!bank->mod_usage) | |
607 | pm_runtime_get_sync(bank->dev); | |
92105bb7 | 608 | |
55b93c32 | 609 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b TL |
610 | /* Set trigger to none. You need to enable the desired trigger with |
611 | * request_irq() or set_irq_type(). | |
612 | */ | |
3ff164e1 | 613 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 614 | |
fad96ea8 C |
615 | if (bank->regs->pinctrl) { |
616 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
5e1c5ff4 | 617 | |
92105bb7 | 618 | /* Claim the pin for MPU */ |
3ff164e1 | 619 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 | 620 | } |
fad96ea8 | 621 | |
c8eef65a C |
622 | if (bank->regs->ctrl && !bank->mod_usage) { |
623 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
624 | u32 ctrl; | |
625 | ||
626 | ctrl = __raw_readl(reg); | |
627 | /* Module is enabled, clocks are not gated */ | |
628 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
629 | __raw_writel(ctrl, reg); | |
41d87cbd | 630 | bank->context.ctrl = ctrl; |
058af1ea | 631 | } |
c8eef65a C |
632 | |
633 | bank->mod_usage |= 1 << offset; | |
634 | ||
a6472533 | 635 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
636 | |
637 | return 0; | |
638 | } | |
639 | ||
3ff164e1 | 640 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 641 | { |
3ff164e1 | 642 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
6ed87c5b | 643 | void __iomem *base = bank->base; |
a6472533 | 644 | unsigned long flags; |
5e1c5ff4 | 645 | |
a6472533 | 646 | spin_lock_irqsave(&bank->lock, flags); |
6ed87c5b | 647 | |
41d87cbd | 648 | if (bank->regs->wkup_en) { |
9f096868 | 649 | /* Disable wake-up during idle for dynamic tick */ |
6ed87c5b | 650 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); |
41d87cbd TKD |
651 | bank->context.wake_en = |
652 | __raw_readl(bank->base + bank->regs->wkup_en); | |
653 | } | |
6ed87c5b | 654 | |
c8eef65a C |
655 | bank->mod_usage &= ~(1 << offset); |
656 | ||
657 | if (bank->regs->ctrl && !bank->mod_usage) { | |
658 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
659 | u32 ctrl; | |
660 | ||
661 | ctrl = __raw_readl(reg); | |
662 | /* Module is disabled, clocks are gated */ | |
663 | ctrl |= GPIO_MOD_CTRL_BIT; | |
664 | __raw_writel(ctrl, reg); | |
41d87cbd | 665 | bank->context.ctrl = ctrl; |
058af1ea | 666 | } |
c8eef65a | 667 | |
3ff164e1 | 668 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 669 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
670 | |
671 | /* | |
672 | * If this is the last gpio to be freed in the bank, | |
673 | * disable the bank module. | |
674 | */ | |
675 | if (!bank->mod_usage) | |
676 | pm_runtime_put(bank->dev); | |
5e1c5ff4 TL |
677 | } |
678 | ||
679 | /* | |
680 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
681 | * avoid missing GPIO interrupts for other lines in the bank. | |
682 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
683 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
684 | * If we wait to unmask individual GPIO lines in the bank after the | |
685 | * line's interrupt handler has been run, we may miss some nested | |
686 | * interrupts. | |
687 | */ | |
10dd5ce2 | 688 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 689 | { |
92105bb7 | 690 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 691 | u32 isr; |
3513cdec | 692 | unsigned int bit; |
5e1c5ff4 | 693 | struct gpio_bank *bank; |
ea6dedd7 | 694 | int unmasked = 0; |
ee144182 | 695 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 696 | |
ee144182 | 697 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 698 | |
6845664a | 699 | bank = irq_get_handler_data(irq); |
eef4bec7 | 700 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 701 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
702 | |
703 | if (WARN_ON(!isr_reg)) | |
704 | goto exit; | |
705 | ||
e83507b7 | 706 | while (1) { |
6e60e79a | 707 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 708 | u32 enabled; |
6e60e79a | 709 | |
ea6dedd7 ID |
710 | enabled = _get_gpio_irqbank_mask(bank); |
711 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a | 712 | |
9ea14d8c | 713 | if (bank->level_mask) |
b144ff6f | 714 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
715 | |
716 | /* clear edge sensitive interrupts before handler(s) are | |
717 | called so that we don't miss any interrupt occurred while | |
718 | executing them */ | |
28f3b5a0 | 719 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 720 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 721 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
722 | |
723 | /* if there is only edge sensitive GPIO pin interrupts | |
724 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
725 | if (!level_mask && !unmasked) { |
726 | unmasked = 1; | |
ee144182 | 727 | chained_irq_exit(chip, desc); |
ea6dedd7 | 728 | } |
92105bb7 TL |
729 | |
730 | if (!isr) | |
731 | break; | |
732 | ||
3513cdec JH |
733 | while (isr) { |
734 | bit = __ffs(isr); | |
735 | isr &= ~(1 << bit); | |
25db711d | 736 | |
4318f36b CM |
737 | /* |
738 | * Some chips can't respond to both rising and falling | |
739 | * at the same time. If this irq was requested with | |
740 | * both flags, we need to flip the ICR data for the IRQ | |
741 | * to respond to the IRQ for the opposite direction. | |
742 | * This will be indicated in the bank toggle_mask. | |
743 | */ | |
3513cdec JH |
744 | if (bank->toggle_mask & (1 << bit)) |
745 | _toggle_gpio_edge_triggering(bank, bit); | |
4318f36b | 746 | |
3513cdec | 747 | generic_handle_irq(irq_find_mapping(bank->domain, bit)); |
92105bb7 | 748 | } |
1a8bfa1e | 749 | } |
ea6dedd7 ID |
750 | /* if bank has any level sensitive GPIO pin interrupt |
751 | configured, we must unmask the bank interrupt only after | |
752 | handler(s) are executed in order to avoid spurious bank | |
753 | interrupt */ | |
b1cc4c55 | 754 | exit: |
ea6dedd7 | 755 | if (!unmasked) |
ee144182 | 756 | chained_irq_exit(chip, desc); |
55b93c32 | 757 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
758 | } |
759 | ||
e9191028 | 760 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 761 | { |
e9191028 | 762 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 763 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
85ec7b97 | 764 | unsigned long flags; |
4196dd6b | 765 | |
85ec7b97 | 766 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 767 | _reset_gpio(bank, gpio); |
85ec7b97 | 768 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
769 | } |
770 | ||
e9191028 | 771 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 772 | { |
e9191028 | 773 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 774 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
5e1c5ff4 TL |
775 | |
776 | _clear_gpio_irqstatus(bank, gpio); | |
777 | } | |
778 | ||
e9191028 | 779 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 780 | { |
e9191028 | 781 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 782 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
85ec7b97 | 783 | unsigned long flags; |
5e1c5ff4 | 784 | |
85ec7b97 | 785 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 786 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 787 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 788 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
789 | } |
790 | ||
e9191028 | 791 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 792 | { |
e9191028 | 793 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
ede4d7a5 | 794 | unsigned int gpio = irq_to_gpio(bank, d->hwirq); |
129fd223 | 795 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 796 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 797 | unsigned long flags; |
55b6019a | 798 | |
85ec7b97 | 799 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 800 | if (trigger) |
129fd223 | 801 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
802 | |
803 | /* For level-triggered GPIOs, the clearing must be done after | |
804 | * the HW source is cleared, thus after the handler has run */ | |
805 | if (bank->level_mask & irq_mask) { | |
806 | _set_gpio_irqenable(bank, gpio, 0); | |
807 | _clear_gpio_irqstatus(bank, gpio); | |
808 | } | |
5e1c5ff4 | 809 | |
4de8c75b | 810 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 811 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
812 | } |
813 | ||
e5c56ed3 DB |
814 | static struct irq_chip gpio_irq_chip = { |
815 | .name = "GPIO", | |
e9191028 LB |
816 | .irq_shutdown = gpio_irq_shutdown, |
817 | .irq_ack = gpio_ack_irq, | |
818 | .irq_mask = gpio_mask_irq, | |
819 | .irq_unmask = gpio_unmask_irq, | |
820 | .irq_set_type = gpio_irq_type, | |
821 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
822 | }; |
823 | ||
824 | /*---------------------------------------------------------------------*/ | |
825 | ||
79ee031f | 826 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 827 | { |
79ee031f | 828 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 829 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
830 | void __iomem *mask_reg = bank->base + |
831 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 832 | unsigned long flags; |
11a78b79 | 833 | |
a6472533 | 834 | spin_lock_irqsave(&bank->lock, flags); |
0aa27273 | 835 | __raw_writel(0xffff & ~bank->context.wake_en, mask_reg); |
a6472533 | 836 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
837 | |
838 | return 0; | |
839 | } | |
840 | ||
79ee031f | 841 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 842 | { |
79ee031f | 843 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 844 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
845 | void __iomem *mask_reg = bank->base + |
846 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 847 | unsigned long flags; |
11a78b79 | 848 | |
a6472533 | 849 | spin_lock_irqsave(&bank->lock, flags); |
499fa287 | 850 | __raw_writel(bank->context.wake_en, mask_reg); |
a6472533 | 851 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
852 | |
853 | return 0; | |
854 | } | |
855 | ||
47145210 | 856 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
857 | .suspend_noirq = omap_mpuio_suspend_noirq, |
858 | .resume_noirq = omap_mpuio_resume_noirq, | |
859 | }; | |
860 | ||
3c437ffd | 861 | /* use platform_driver for this. */ |
11a78b79 | 862 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
863 | .driver = { |
864 | .name = "mpuio", | |
79ee031f | 865 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
866 | }, |
867 | }; | |
868 | ||
869 | static struct platform_device omap_mpuio_device = { | |
870 | .name = "mpuio", | |
871 | .id = -1, | |
872 | .dev = { | |
873 | .driver = &omap_mpuio_driver.driver, | |
874 | } | |
875 | /* could list the /proc/iomem resources */ | |
876 | }; | |
877 | ||
03e128ca | 878 | static inline void mpuio_init(struct gpio_bank *bank) |
11a78b79 | 879 | { |
77640aab | 880 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 881 | |
11a78b79 DB |
882 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
883 | (void) platform_device_register(&omap_mpuio_device); | |
884 | } | |
885 | ||
e5c56ed3 | 886 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 887 | |
52e31344 DB |
888 | static int gpio_input(struct gpio_chip *chip, unsigned offset) |
889 | { | |
890 | struct gpio_bank *bank; | |
891 | unsigned long flags; | |
892 | ||
893 | bank = container_of(chip, struct gpio_bank, chip); | |
894 | spin_lock_irqsave(&bank->lock, flags); | |
895 | _set_gpio_direction(bank, offset, 1); | |
896 | spin_unlock_irqrestore(&bank->lock, flags); | |
897 | return 0; | |
898 | } | |
899 | ||
b37c45b8 RQ |
900 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
901 | { | |
fa87931a | 902 | void __iomem *reg = bank->base + bank->regs->direction; |
b37c45b8 | 903 | |
b37c45b8 RQ |
904 | return __raw_readl(reg) & mask; |
905 | } | |
906 | ||
52e31344 DB |
907 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
908 | { | |
b37c45b8 | 909 | struct gpio_bank *bank; |
b37c45b8 RQ |
910 | u32 mask; |
911 | ||
a8be8daf | 912 | bank = container_of(chip, struct gpio_bank, chip); |
7fcca715 | 913 | mask = (1 << offset); |
b37c45b8 RQ |
914 | |
915 | if (gpio_is_input(bank, mask)) | |
7fcca715 | 916 | return _get_gpio_datain(bank, offset); |
b37c45b8 | 917 | else |
7fcca715 | 918 | return _get_gpio_dataout(bank, offset); |
52e31344 DB |
919 | } |
920 | ||
921 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
922 | { | |
923 | struct gpio_bank *bank; | |
924 | unsigned long flags; | |
925 | ||
926 | bank = container_of(chip, struct gpio_bank, chip); | |
927 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 928 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
929 | _set_gpio_direction(bank, offset, 0); |
930 | spin_unlock_irqrestore(&bank->lock, flags); | |
931 | return 0; | |
932 | } | |
933 | ||
168ef3d9 FB |
934 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
935 | unsigned debounce) | |
936 | { | |
937 | struct gpio_bank *bank; | |
938 | unsigned long flags; | |
939 | ||
940 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab | 941 | |
168ef3d9 FB |
942 | spin_lock_irqsave(&bank->lock, flags); |
943 | _set_gpio_debounce(bank, offset, debounce); | |
944 | spin_unlock_irqrestore(&bank->lock, flags); | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
52e31344 DB |
949 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
950 | { | |
951 | struct gpio_bank *bank; | |
952 | unsigned long flags; | |
953 | ||
954 | bank = container_of(chip, struct gpio_bank, chip); | |
955 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 956 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
957 | spin_unlock_irqrestore(&bank->lock, flags); |
958 | } | |
959 | ||
960 | /*---------------------------------------------------------------------*/ | |
961 | ||
9a748053 | 962 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 963 | { |
e5ff4440 | 964 | static bool called; |
9f7065da TL |
965 | u32 rev; |
966 | ||
e5ff4440 | 967 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
968 | return; |
969 | ||
e5ff4440 KH |
970 | rev = __raw_readw(bank->base + bank->regs->revision); |
971 | pr_info("OMAP GPIO hardware version %d.%d\n", | |
9f7065da | 972 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
973 | |
974 | called = true; | |
9f7065da TL |
975 | } |
976 | ||
8ba55c5c DB |
977 | /* This lock class tells lockdep that GPIO irqs are in a different |
978 | * category than their parents, so it won't report false recursion. | |
979 | */ | |
980 | static struct lock_class_key gpio_lock_class; | |
981 | ||
03e128ca | 982 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 983 | { |
ab985f0f TKD |
984 | void __iomem *base = bank->base; |
985 | u32 l = 0xffffffff; | |
2fae7fbe | 986 | |
ab985f0f TKD |
987 | if (bank->width == 16) |
988 | l = 0xffff; | |
989 | ||
d0d665a8 | 990 | if (bank->is_mpuio) { |
ab985f0f TKD |
991 | __raw_writel(l, bank->base + bank->regs->irqenable); |
992 | return; | |
2fae7fbe | 993 | } |
ab985f0f TKD |
994 | |
995 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv); | |
6edd94db | 996 | _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv); |
ab985f0f | 997 | if (bank->regs->debounce_en) |
6edd94db | 998 | __raw_writel(0, base + bank->regs->debounce_en); |
ab985f0f | 999 | |
2dc983c5 TKD |
1000 | /* Save OE default value (0xffffffff) in the context */ |
1001 | bank->context.oe = __raw_readl(bank->base + bank->regs->direction); | |
ab985f0f TKD |
1002 | /* Initialize interface clk ungated, module enabled */ |
1003 | if (bank->regs->ctrl) | |
6edd94db | 1004 | __raw_writel(0, base + bank->regs->ctrl); |
34672013 TKD |
1005 | |
1006 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1007 | if (IS_ERR(bank->dbck)) | |
1008 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
2fae7fbe VC |
1009 | } |
1010 | ||
3836309d | 1011 | static void |
f8b46b58 KH |
1012 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, |
1013 | unsigned int num) | |
1014 | { | |
1015 | struct irq_chip_generic *gc; | |
1016 | struct irq_chip_type *ct; | |
1017 | ||
1018 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
1019 | handle_simple_irq); | |
83233749 TP |
1020 | if (!gc) { |
1021 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
1022 | return; | |
1023 | } | |
1024 | ||
f8b46b58 KH |
1025 | ct = gc->chip_types; |
1026 | ||
1027 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
1028 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
1029 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
1030 | ct->chip.irq_set_type = gpio_irq_type; | |
6ed87c5b TKD |
1031 | |
1032 | if (bank->regs->wkup_en) | |
388f4308 | 1033 | ct->chip.irq_set_wake = gpio_wake_enable; |
f8b46b58 KH |
1034 | |
1035 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
1036 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
1037 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
1038 | } | |
1039 | ||
3836309d | 1040 | static void omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 1041 | { |
77640aab | 1042 | int j; |
2fae7fbe VC |
1043 | static int gpio; |
1044 | ||
2fae7fbe VC |
1045 | /* |
1046 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1047 | * over to the generic ones | |
1048 | */ | |
1049 | bank->chip.request = omap_gpio_request; | |
1050 | bank->chip.free = omap_gpio_free; | |
1051 | bank->chip.direction_input = gpio_input; | |
1052 | bank->chip.get = gpio_get; | |
1053 | bank->chip.direction_output = gpio_output; | |
1054 | bank->chip.set_debounce = gpio_debounce; | |
1055 | bank->chip.set = gpio_set; | |
ede4d7a5 | 1056 | bank->chip.to_irq = omap_gpio_to_irq; |
d0d665a8 | 1057 | if (bank->is_mpuio) { |
2fae7fbe | 1058 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
1059 | if (bank->regs->wkup_en) |
1060 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
1061 | bank->chip.base = OMAP_MPUIO(0); |
1062 | } else { | |
1063 | bank->chip.label = "gpio"; | |
1064 | bank->chip.base = gpio; | |
d5f46247 | 1065 | gpio += bank->width; |
2fae7fbe | 1066 | } |
d5f46247 | 1067 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
1068 | |
1069 | gpiochip_add(&bank->chip); | |
1070 | ||
ede4d7a5 JH |
1071 | for (j = 0; j < bank->width; j++) { |
1072 | int irq = irq_create_mapping(bank->domain, j); | |
1073 | irq_set_lockdep_class(irq, &gpio_lock_class); | |
1074 | irq_set_chip_data(irq, bank); | |
d0d665a8 | 1075 | if (bank->is_mpuio) { |
ede4d7a5 | 1076 | omap_mpuio_alloc_gc(bank, irq, bank->width); |
f8b46b58 | 1077 | } else { |
ede4d7a5 JH |
1078 | irq_set_chip_and_handler(irq, &gpio_irq_chip, |
1079 | handle_simple_irq); | |
1080 | set_irq_flags(irq, IRQF_VALID); | |
f8b46b58 | 1081 | } |
2fae7fbe | 1082 | } |
6845664a TG |
1083 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1084 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
1085 | } |
1086 | ||
384ebe1c BC |
1087 | static const struct of_device_id omap_gpio_match[]; |
1088 | ||
3836309d | 1089 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1090 | { |
862ff640 | 1091 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1092 | struct device_node *node = dev->of_node; |
1093 | const struct of_device_id *match; | |
f6817a2c | 1094 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1095 | struct resource *res; |
5e1c5ff4 | 1096 | struct gpio_bank *bank; |
397eada9 JMC |
1097 | #ifdef CONFIG_ARCH_OMAP1 |
1098 | int irq_base; | |
1099 | #endif | |
5e1c5ff4 | 1100 | |
384ebe1c BC |
1101 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1102 | ||
e56aee18 | 1103 | pdata = match ? match->data : dev_get_platdata(dev); |
384ebe1c | 1104 | if (!pdata) |
96751fcb | 1105 | return -EINVAL; |
5492fb1a | 1106 | |
086d585f | 1107 | bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL); |
03e128ca | 1108 | if (!bank) { |
862ff640 | 1109 | dev_err(dev, "Memory alloc failed\n"); |
96751fcb | 1110 | return -ENOMEM; |
03e128ca | 1111 | } |
92105bb7 | 1112 | |
77640aab VC |
1113 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1114 | if (unlikely(!res)) { | |
862ff640 | 1115 | dev_err(dev, "Invalid IRQ resource\n"); |
96751fcb | 1116 | return -ENODEV; |
44169075 | 1117 | } |
5e1c5ff4 | 1118 | |
77640aab | 1119 | bank->irq = res->start; |
862ff640 | 1120 | bank->dev = dev; |
77640aab | 1121 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1122 | bank->stride = pdata->bank_stride; |
d5f46247 | 1123 | bank->width = pdata->bank_width; |
d0d665a8 | 1124 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1125 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1126 | bank->regs = pdata->regs; |
384ebe1c BC |
1127 | #ifdef CONFIG_OF_GPIO |
1128 | bank->chip.of_node = of_node_get(node); | |
1129 | #endif | |
a2797bea JH |
1130 | if (node) { |
1131 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1132 | bank->loses_context = true; | |
1133 | } else { | |
1134 | bank->loses_context = pdata->loses_context; | |
352a2d5b JH |
1135 | |
1136 | if (bank->loses_context) | |
1137 | bank->get_context_loss_count = | |
1138 | pdata->get_context_loss_count; | |
384ebe1c BC |
1139 | } |
1140 | ||
397eada9 JMC |
1141 | #ifdef CONFIG_ARCH_OMAP1 |
1142 | /* | |
1143 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1144 | * irq_alloc_descs() and irq_domain_add_legacy() and just use a | |
1145 | * linear IRQ domain mapping for all OMAP platforms. | |
1146 | */ | |
1147 | irq_base = irq_alloc_descs(-1, 0, bank->width, 0); | |
1148 | if (irq_base < 0) { | |
1149 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
1150 | return -ENODEV; | |
1151 | } | |
384ebe1c | 1152 | |
397eada9 JMC |
1153 | bank->domain = irq_domain_add_legacy(node, bank->width, irq_base, |
1154 | 0, &irq_domain_simple_ops, NULL); | |
1155 | #else | |
ede4d7a5 JH |
1156 | bank->domain = irq_domain_add_linear(node, bank->width, |
1157 | &irq_domain_simple_ops, NULL); | |
397eada9 JMC |
1158 | #endif |
1159 | if (!bank->domain) { | |
1160 | dev_err(dev, "Couldn't register an IRQ domain\n"); | |
384ebe1c | 1161 | return -ENODEV; |
397eada9 | 1162 | } |
fa87931a KH |
1163 | |
1164 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1165 | bank->set_dataout = _set_gpio_dataout_reg; | |
1166 | else | |
1167 | bank->set_dataout = _set_gpio_dataout_mask; | |
9f7065da | 1168 | |
77640aab | 1169 | spin_lock_init(&bank->lock); |
9f7065da | 1170 | |
77640aab VC |
1171 | /* Static mapping, never released */ |
1172 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1173 | if (unlikely(!res)) { | |
862ff640 | 1174 | dev_err(dev, "Invalid mem resource\n"); |
879fe324 | 1175 | irq_domain_remove(bank->domain); |
96751fcb BC |
1176 | return -ENODEV; |
1177 | } | |
1178 | ||
1179 | if (!devm_request_mem_region(dev, res->start, resource_size(res), | |
1180 | pdev->name)) { | |
1181 | dev_err(dev, "Region already claimed\n"); | |
879fe324 | 1182 | irq_domain_remove(bank->domain); |
96751fcb | 1183 | return -EBUSY; |
77640aab | 1184 | } |
89db9482 | 1185 | |
96751fcb | 1186 | bank->base = devm_ioremap(dev, res->start, resource_size(res)); |
77640aab | 1187 | if (!bank->base) { |
862ff640 | 1188 | dev_err(dev, "Could not ioremap\n"); |
879fe324 | 1189 | irq_domain_remove(bank->domain); |
96751fcb | 1190 | return -ENOMEM; |
5e1c5ff4 TL |
1191 | } |
1192 | ||
065cd795 TKD |
1193 | platform_set_drvdata(pdev, bank); |
1194 | ||
77640aab | 1195 | pm_runtime_enable(bank->dev); |
55b93c32 | 1196 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1197 | pm_runtime_get_sync(bank->dev); |
1198 | ||
d0d665a8 | 1199 | if (bank->is_mpuio) |
ab985f0f TKD |
1200 | mpuio_init(bank); |
1201 | ||
03e128ca | 1202 | omap_gpio_mod_init(bank); |
77640aab | 1203 | omap_gpio_chip_init(bank); |
9a748053 | 1204 | omap_gpio_show_rev(bank); |
9f7065da | 1205 | |
55b93c32 TKD |
1206 | pm_runtime_put(bank->dev); |
1207 | ||
03e128ca | 1208 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1209 | |
879fe324 | 1210 | return 0; |
5e1c5ff4 TL |
1211 | } |
1212 | ||
55b93c32 TKD |
1213 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1214 | ||
2dc983c5 | 1215 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1216 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1217 | |
2dc983c5 | 1218 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1219 | { |
2dc983c5 TKD |
1220 | struct platform_device *pdev = to_platform_device(dev); |
1221 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1222 | u32 l1 = 0, l2 = 0; | |
1223 | unsigned long flags; | |
68942edb | 1224 | u32 wake_low, wake_hi; |
8865b9b6 | 1225 | |
2dc983c5 | 1226 | spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1227 | |
1228 | /* | |
1229 | * Only edges can generate a wakeup event to the PRCM. | |
1230 | * | |
1231 | * Therefore, ensure any wake-up capable GPIOs have | |
1232 | * edge-detection enabled before going idle to ensure a wakeup | |
1233 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1234 | * NDA TRM 25.5.3.1) | |
1235 | * | |
1236 | * The normal values will be restored upon ->runtime_resume() | |
1237 | * by writing back the values saved in bank->context. | |
1238 | */ | |
1239 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1240 | if (wake_low) | |
1241 | __raw_writel(wake_low | bank->context.fallingdetect, | |
1242 | bank->base + bank->regs->fallingdetect); | |
1243 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1244 | if (wake_hi) | |
1245 | __raw_writel(wake_hi | bank->context.risingdetect, | |
1246 | bank->base + bank->regs->risingdetect); | |
1247 | ||
b3c64bc3 KH |
1248 | if (!bank->enabled_non_wakeup_gpios) |
1249 | goto update_gpio_context_count; | |
1250 | ||
2dc983c5 TKD |
1251 | if (bank->power_mode != OFF_MODE) { |
1252 | bank->power_mode = 0; | |
41d87cbd | 1253 | goto update_gpio_context_count; |
2dc983c5 TKD |
1254 | } |
1255 | /* | |
1256 | * If going to OFF, remove triggering for all | |
1257 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1258 | * generated. See OMAP2420 Errata item 1.101. | |
1259 | */ | |
2dc983c5 TKD |
1260 | bank->saved_datain = __raw_readl(bank->base + |
1261 | bank->regs->datain); | |
c6f31c9e TKD |
1262 | l1 = bank->context.fallingdetect; |
1263 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1264 | |
2dc983c5 TKD |
1265 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1266 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1267 | |
2dc983c5 TKD |
1268 | __raw_writel(l1, bank->base + bank->regs->fallingdetect); |
1269 | __raw_writel(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1270 | |
2dc983c5 | 1271 | bank->workaround_enabled = true; |
3f1686a9 | 1272 | |
41d87cbd | 1273 | update_gpio_context_count: |
2dc983c5 TKD |
1274 | if (bank->get_context_loss_count) |
1275 | bank->context_loss_count = | |
60a3437d TKD |
1276 | bank->get_context_loss_count(bank->dev); |
1277 | ||
72f83af9 | 1278 | _gpio_dbck_disable(bank); |
2dc983c5 | 1279 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1280 | |
2dc983c5 | 1281 | return 0; |
3ac4fa99 JY |
1282 | } |
1283 | ||
352a2d5b JH |
1284 | static void omap_gpio_init_context(struct gpio_bank *p); |
1285 | ||
2dc983c5 | 1286 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1287 | { |
2dc983c5 TKD |
1288 | struct platform_device *pdev = to_platform_device(dev); |
1289 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
2dc983c5 TKD |
1290 | u32 l = 0, gen, gen0, gen1; |
1291 | unsigned long flags; | |
a2797bea | 1292 | int c; |
8865b9b6 | 1293 | |
2dc983c5 | 1294 | spin_lock_irqsave(&bank->lock, flags); |
352a2d5b JH |
1295 | |
1296 | /* | |
1297 | * On the first resume during the probe, the context has not | |
1298 | * been initialised and so initialise it now. Also initialise | |
1299 | * the context loss count. | |
1300 | */ | |
1301 | if (bank->loses_context && !bank->context_valid) { | |
1302 | omap_gpio_init_context(bank); | |
1303 | ||
1304 | if (bank->get_context_loss_count) | |
1305 | bank->context_loss_count = | |
1306 | bank->get_context_loss_count(bank->dev); | |
1307 | } | |
1308 | ||
72f83af9 | 1309 | _gpio_dbck_enable(bank); |
68942edb KH |
1310 | |
1311 | /* | |
1312 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1313 | * GPIOs were set to edge trigger also in order to be able to | |
1314 | * generate a PRCM wakeup. Here we restore the | |
1315 | * pre-runtime_suspend() values for edge triggering. | |
1316 | */ | |
1317 | __raw_writel(bank->context.fallingdetect, | |
1318 | bank->base + bank->regs->fallingdetect); | |
1319 | __raw_writel(bank->context.risingdetect, | |
1320 | bank->base + bank->regs->risingdetect); | |
1321 | ||
a2797bea JH |
1322 | if (bank->loses_context) { |
1323 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1324 | omap_gpio_restore_context(bank); |
1325 | } else { | |
a2797bea JH |
1326 | c = bank->get_context_loss_count(bank->dev); |
1327 | if (c != bank->context_loss_count) { | |
1328 | omap_gpio_restore_context(bank); | |
1329 | } else { | |
1330 | spin_unlock_irqrestore(&bank->lock, flags); | |
1331 | return 0; | |
1332 | } | |
60a3437d | 1333 | } |
2dc983c5 | 1334 | } |
43ffcd9a | 1335 | |
1b128703 TKD |
1336 | if (!bank->workaround_enabled) { |
1337 | spin_unlock_irqrestore(&bank->lock, flags); | |
1338 | return 0; | |
1339 | } | |
1340 | ||
2dc983c5 | 1341 | l = __raw_readl(bank->base + bank->regs->datain); |
3f1686a9 | 1342 | |
2dc983c5 TKD |
1343 | /* |
1344 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1345 | * state. If so, generate an IRQ by software. This is | |
1346 | * horribly racy, but it's the best we can do to work around | |
1347 | * this silicon bug. | |
1348 | */ | |
1349 | l ^= bank->saved_datain; | |
1350 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1351 | |
2dc983c5 TKD |
1352 | /* |
1353 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1354 | * configured with falling edge only; and vice versa. | |
1355 | */ | |
c6f31c9e | 1356 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1357 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1358 | |
c6f31c9e | 1359 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1360 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1361 | |
2dc983c5 | 1362 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1363 | gen = l & (~(bank->context.fallingdetect) & |
1364 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1365 | /* Consider all GPIO IRQs needed to be updated */ |
1366 | gen |= gen0 | gen1; | |
82dbb9d3 | 1367 | |
2dc983c5 TKD |
1368 | if (gen) { |
1369 | u32 old0, old1; | |
82dbb9d3 | 1370 | |
2dc983c5 TKD |
1371 | old0 = __raw_readl(bank->base + bank->regs->leveldetect0); |
1372 | old1 = __raw_readl(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1373 | |
4e962e89 | 1374 | if (!bank->regs->irqstatus_raw0) { |
2dc983c5 | 1375 | __raw_writel(old0 | gen, bank->base + |
9ea14d8c | 1376 | bank->regs->leveldetect0); |
2dc983c5 | 1377 | __raw_writel(old1 | gen, bank->base + |
9ea14d8c | 1378 | bank->regs->leveldetect1); |
2dc983c5 | 1379 | } |
9ea14d8c | 1380 | |
4e962e89 | 1381 | if (bank->regs->irqstatus_raw0) { |
2dc983c5 | 1382 | __raw_writel(old0 | l, bank->base + |
9ea14d8c | 1383 | bank->regs->leveldetect0); |
2dc983c5 | 1384 | __raw_writel(old1 | l, bank->base + |
9ea14d8c | 1385 | bank->regs->leveldetect1); |
3ac4fa99 | 1386 | } |
2dc983c5 TKD |
1387 | __raw_writel(old0, bank->base + bank->regs->leveldetect0); |
1388 | __raw_writel(old1, bank->base + bank->regs->leveldetect1); | |
1389 | } | |
1390 | ||
1391 | bank->workaround_enabled = false; | |
1392 | spin_unlock_irqrestore(&bank->lock, flags); | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | #endif /* CONFIG_PM_RUNTIME */ | |
1397 | ||
1398 | void omap2_gpio_prepare_for_idle(int pwr_mode) | |
1399 | { | |
1400 | struct gpio_bank *bank; | |
1401 | ||
1402 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
2dc983c5 TKD |
1403 | if (!bank->mod_usage || !bank->loses_context) |
1404 | continue; | |
1405 | ||
1406 | bank->power_mode = pwr_mode; | |
1407 | ||
2dc983c5 TKD |
1408 | pm_runtime_put_sync_suspend(bank->dev); |
1409 | } | |
1410 | } | |
1411 | ||
1412 | void omap2_gpio_resume_after_idle(void) | |
1413 | { | |
1414 | struct gpio_bank *bank; | |
1415 | ||
1416 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
2dc983c5 TKD |
1417 | if (!bank->mod_usage || !bank->loses_context) |
1418 | continue; | |
1419 | ||
2dc983c5 | 1420 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1421 | } |
3ac4fa99 JY |
1422 | } |
1423 | ||
2dc983c5 | 1424 | #if defined(CONFIG_PM_RUNTIME) |
352a2d5b JH |
1425 | static void omap_gpio_init_context(struct gpio_bank *p) |
1426 | { | |
1427 | struct omap_gpio_reg_offs *regs = p->regs; | |
1428 | void __iomem *base = p->base; | |
1429 | ||
1430 | p->context.ctrl = __raw_readl(base + regs->ctrl); | |
1431 | p->context.oe = __raw_readl(base + regs->direction); | |
1432 | p->context.wake_en = __raw_readl(base + regs->wkup_en); | |
1433 | p->context.leveldetect0 = __raw_readl(base + regs->leveldetect0); | |
1434 | p->context.leveldetect1 = __raw_readl(base + regs->leveldetect1); | |
1435 | p->context.risingdetect = __raw_readl(base + regs->risingdetect); | |
1436 | p->context.fallingdetect = __raw_readl(base + regs->fallingdetect); | |
1437 | p->context.irqenable1 = __raw_readl(base + regs->irqenable); | |
1438 | p->context.irqenable2 = __raw_readl(base + regs->irqenable2); | |
1439 | ||
1440 | if (regs->set_dataout && p->regs->clr_dataout) | |
1441 | p->context.dataout = __raw_readl(base + regs->set_dataout); | |
1442 | else | |
1443 | p->context.dataout = __raw_readl(base + regs->dataout); | |
1444 | ||
1445 | p->context_valid = true; | |
1446 | } | |
1447 | ||
60a3437d | 1448 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1449 | { |
60a3437d | 1450 | __raw_writel(bank->context.wake_en, |
ae10f233 TKD |
1451 | bank->base + bank->regs->wkup_en); |
1452 | __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
60a3437d | 1453 | __raw_writel(bank->context.leveldetect0, |
ae10f233 | 1454 | bank->base + bank->regs->leveldetect0); |
60a3437d | 1455 | __raw_writel(bank->context.leveldetect1, |
ae10f233 | 1456 | bank->base + bank->regs->leveldetect1); |
60a3437d | 1457 | __raw_writel(bank->context.risingdetect, |
ae10f233 | 1458 | bank->base + bank->regs->risingdetect); |
60a3437d | 1459 | __raw_writel(bank->context.fallingdetect, |
ae10f233 | 1460 | bank->base + bank->regs->fallingdetect); |
f86bcc30 NM |
1461 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
1462 | __raw_writel(bank->context.dataout, | |
1463 | bank->base + bank->regs->set_dataout); | |
1464 | else | |
1465 | __raw_writel(bank->context.dataout, | |
1466 | bank->base + bank->regs->dataout); | |
6d13eaaf NM |
1467 | __raw_writel(bank->context.oe, bank->base + bank->regs->direction); |
1468 | ||
ae547354 NM |
1469 | if (bank->dbck_enable_mask) { |
1470 | __raw_writel(bank->context.debounce, bank->base + | |
1471 | bank->regs->debounce); | |
1472 | __raw_writel(bank->context.debounce_en, | |
1473 | bank->base + bank->regs->debounce_en); | |
1474 | } | |
ba805be5 NM |
1475 | |
1476 | __raw_writel(bank->context.irqenable1, | |
1477 | bank->base + bank->regs->irqenable); | |
1478 | __raw_writel(bank->context.irqenable2, | |
1479 | bank->base + bank->regs->irqenable2); | |
40c670f0 | 1480 | } |
2dc983c5 | 1481 | #endif /* CONFIG_PM_RUNTIME */ |
55b93c32 | 1482 | #else |
2dc983c5 TKD |
1483 | #define omap_gpio_runtime_suspend NULL |
1484 | #define omap_gpio_runtime_resume NULL | |
ea4a21a2 | 1485 | static inline void omap_gpio_init_context(struct gpio_bank *p) {} |
40c670f0 RN |
1486 | #endif |
1487 | ||
55b93c32 | 1488 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1489 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1490 | NULL) | |
55b93c32 TKD |
1491 | }; |
1492 | ||
384ebe1c BC |
1493 | #if defined(CONFIG_OF) |
1494 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1495 | .revision = OMAP24XX_GPIO_REVISION, | |
1496 | .direction = OMAP24XX_GPIO_OE, | |
1497 | .datain = OMAP24XX_GPIO_DATAIN, | |
1498 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1499 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1500 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1501 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1502 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1503 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1504 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1505 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1506 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1507 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1508 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1509 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1510 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1511 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1512 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1513 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1514 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1515 | }; | |
1516 | ||
1517 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1518 | .revision = OMAP4_GPIO_REVISION, | |
1519 | .direction = OMAP4_GPIO_OE, | |
1520 | .datain = OMAP4_GPIO_DATAIN, | |
1521 | .dataout = OMAP4_GPIO_DATAOUT, | |
1522 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1523 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1524 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1525 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1526 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1527 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1528 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1529 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1530 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1531 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1532 | .ctrl = OMAP4_GPIO_CTRL, | |
1533 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1534 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1535 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1536 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1537 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1538 | }; | |
1539 | ||
e9a65bb6 | 1540 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1541 | .regs = &omap2_gpio_regs, |
1542 | .bank_width = 32, | |
1543 | .dbck_flag = false, | |
1544 | }; | |
1545 | ||
e9a65bb6 | 1546 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1547 | .regs = &omap2_gpio_regs, |
1548 | .bank_width = 32, | |
1549 | .dbck_flag = true, | |
1550 | }; | |
1551 | ||
e9a65bb6 | 1552 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1553 | .regs = &omap4_gpio_regs, |
1554 | .bank_width = 32, | |
1555 | .dbck_flag = true, | |
1556 | }; | |
1557 | ||
1558 | static const struct of_device_id omap_gpio_match[] = { | |
1559 | { | |
1560 | .compatible = "ti,omap4-gpio", | |
1561 | .data = &omap4_pdata, | |
1562 | }, | |
1563 | { | |
1564 | .compatible = "ti,omap3-gpio", | |
1565 | .data = &omap3_pdata, | |
1566 | }, | |
1567 | { | |
1568 | .compatible = "ti,omap2-gpio", | |
1569 | .data = &omap2_pdata, | |
1570 | }, | |
1571 | { }, | |
1572 | }; | |
1573 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1574 | #endif | |
1575 | ||
77640aab VC |
1576 | static struct platform_driver omap_gpio_driver = { |
1577 | .probe = omap_gpio_probe, | |
1578 | .driver = { | |
1579 | .name = "omap_gpio", | |
55b93c32 | 1580 | .pm = &gpio_pm_ops, |
384ebe1c | 1581 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1582 | }, |
1583 | }; | |
1584 | ||
5e1c5ff4 | 1585 | /* |
77640aab VC |
1586 | * gpio driver register needs to be done before |
1587 | * machine_init functions access gpio APIs. | |
1588 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1589 | */ |
77640aab | 1590 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1591 | { |
77640aab | 1592 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1593 | } |
77640aab | 1594 | postcore_initcall(omap_gpio_drv_reg); |