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Merge branch 'imx/devel' into next/dt
[mirror_ubuntu-zesty-kernel.git] / drivers / gpio / gpio-omap.c
CommitLineData
5e1c5ff4 1/*
5e1c5ff4
TL		 2 * Support functions for OMAP GPIO
3 *
92105bb7 4 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 6 *
44169075
SS		 7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
5e1c5ff4
TL		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
5e1c5ff4
TL		 15#include <linux/init.h>
16#include <linux/module.h>
5e1c5ff4 17#include <linux/interrupt.h>
3c437ffd 18#include <linux/syscore_ops.h>
92105bb7 19#include <linux/err.h>
f8ce2547 20#include <linux/clk.h>
fced80c7 21#include <linux/io.h>
77640aab
VC		 22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb
RK		 27#include <mach/irqs.h>
28#include <mach/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
5e1c5ff4 31struct gpio_bank {
9f7065da 32 unsigned long pbase;
92105bb7 33 void __iomem *base;
5e1c5ff4
TL		 34 u16 irq;
35 u16 virtual_irq_start;
92105bb7 36 int method;
92105bb7 37 u32 suspend_wakeup;
78a43158 38#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7 39 u32 saved_wakeup;
3ac4fa99 40#endif
3ac4fa99
JY		 41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
b144ff6f 47 u32 level_mask;
4318f36b 48 u32 toggle_mask;
5e1c5ff4 49 spinlock_t lock;
52e31344 50 struct gpio_chip chip;
89db9482 51 struct clk *dbck;
058af1ea 52 u32 mod_usage;
8865b9b6 53 u32 dbck_enable_mask;
77640aab
VC		 54 struct device *dev;
55 bool dbck_flag;
5de62b86 56 int stride;
d5f46247 57 u32 width;
fa87931a
KH		 58
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60
61 struct omap_gpio_reg_offs *regs;
5e1c5ff4
TL		 62};
63
a8eb7ca0 64#ifdef CONFIG_ARCH_OMAP3
40c670f0 65struct omap3_gpio_regs {
40c670f0
RN		 66 u32 irqenable1;
67 u32 irqenable2;
68 u32 wake_en;
69 u32 ctrl;
70 u32 oe;
71 u32 leveldetect0;
72 u32 leveldetect1;
73 u32 risingdetect;
74 u32 fallingdetect;
75 u32 dataout;
5492fb1a
SMK		 76};
77
40c670f0 78static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 79#endif
80
77640aab
VC		 81/*
82 * TODO: Cleanup gpio_bank usage as it is having information
83 * related to all instances of the device
84 */
85static struct gpio_bank *gpio_bank;
44169075 86
c95d10bc
VC		 87/* TODO: Analyze removing gpio_bank_count usage from driver code */
88int gpio_bank_count;
5e1c5ff4 89
129fd223
KH		 90#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
5e1c5ff4
TL		 92
93static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
94{
92105bb7 95 void __iomem *reg = bank->base;
5e1c5ff4
TL		 96 u32 l;
97
fa87931a 98 reg += bank->regs->direction;
5e1c5ff4
TL		 99 l = __raw_readl(reg);
100 if (is_input)
101 l |= 1 << gpio;
102 else
103 l &= ~(1 << gpio);
104 __raw_writel(l, reg);
105}
106
fa87931a
KH		 107
108/* set data out value using dedicate set/clear register */
109static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
5e1c5ff4 110{
92105bb7 111 void __iomem *reg = bank->base;
fa87931a 112 u32 l = GPIO_BIT(bank, gpio);
5e1c5ff4 113
fa87931a
KH		 114 if (enable)
115 reg += bank->regs->set_dataout;
116 else
117 reg += bank->regs->clr_dataout;
5e1c5ff4 118
5e1c5ff4
TL		 119 __raw_writel(l, reg);
120}
121
fa87931a
KH		 122/* set data out value using mask register */
123static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
5e1c5ff4 124{
fa87931a
KH		 125 void __iomem *reg = bank->base + bank->regs->dataout;
126 u32 gpio_bit = GPIO_BIT(bank, gpio);
127 u32 l;
5e1c5ff4 128
fa87931a
KH		 129 l = __raw_readl(reg);
130 if (enable)
131 l |= gpio_bit;
132 else
133 l &= ~gpio_bit;
5e1c5ff4 134 __raw_writel(l, reg);
5e1c5ff4
TL		 135}
136
b37c45b8 137static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
b37c45b8 138{
fa87931a 139 void __iomem *reg = bank->base + bank->regs->datain;
b37c45b8 140
fa87931a 141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
5e1c5ff4 142}
b37c45b8 143
b37c45b8
RQ		 144static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
145{
fa87931a 146 void __iomem *reg = bank->base + bank->regs->dataout;
b37c45b8 147
129fd223 148 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
b37c45b8
RQ		 149}
150
92105bb7
TL		 151#define MOD_REG_BIT(reg, bit_mask, set) \
152do { \
153 int l = __raw_readl(base + reg); \
154 if (set) l |= bit_mask; \
155 else l &= ~bit_mask; \
156 __raw_writel(l, base + reg); \
157} while(0)
158
168ef3d9
FB		 159/**
160 * _set_gpio_debounce - low level gpio debounce time
161 * @bank: the gpio bank we're acting upon
162 * @gpio: the gpio number on this @gpio
163 * @debounce: debounce time to use
164 *
165 * OMAP's debounce time is in 31us steps so we need
166 * to convert and round up to the closest unit.
167 */
168static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
169 unsigned debounce)
170{
9942da0e 171 void __iomem *reg;
168ef3d9
FB		 172 u32 val;
173 u32 l;
174
77640aab
VC		 175 if (!bank->dbck_flag)
176 return;
177
168ef3d9
FB		 178 if (debounce < 32)
179 debounce = 0x01;
180 else if (debounce > 7936)
181 debounce = 0xff;
182 else
183 debounce = (debounce / 0x1f) - 1;
184
129fd223 185 l = GPIO_BIT(bank, gpio);
168ef3d9 186
9942da0e 187 reg = bank->base + bank->regs->debounce;
168ef3d9
FB		 188 __raw_writel(debounce, reg);
189
9942da0e 190 reg = bank->base + bank->regs->debounce_en;
168ef3d9
FB		 191 val = __raw_readl(reg);
192
193 if (debounce) {
194 val |= l;
77640aab 195 clk_enable(bank->dbck);
168ef3d9
FB		 196 } else {
197 val &= ~l;
77640aab 198 clk_disable(bank->dbck);
168ef3d9 199 }
f7ec0b0b 200 bank->dbck_enable_mask = val;
168ef3d9
FB		 201
202 __raw_writel(val, reg);
203}
204
140455fa 205#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 206static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
207 int trigger)
5e1c5ff4 208{
3ac4fa99 209 void __iomem *base = bank->base;
92105bb7
TL		 210 u32 gpio_bit = 1 << gpio;
211
78a1a6d3
SR		 212 if (cpu_is_omap44xx()) {
213 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
214 trigger & IRQ_TYPE_LEVEL_LOW);
215 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
216 trigger & IRQ_TYPE_LEVEL_HIGH);
217 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
218 trigger & IRQ_TYPE_EDGE_RISING);
219 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
220 trigger & IRQ_TYPE_EDGE_FALLING);
221 } else {
222 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
223 trigger & IRQ_TYPE_LEVEL_LOW);
224 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
225 trigger & IRQ_TYPE_LEVEL_HIGH);
226 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
227 trigger & IRQ_TYPE_EDGE_RISING);
228 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
229 trigger & IRQ_TYPE_EDGE_FALLING);
230 }
3ac4fa99 231 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3 232 if (cpu_is_omap44xx()) {
0622b25b
CC		 233 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
234 trigger != 0);
78a1a6d3 235 } else {
699117a6
CW		 236 /*
237 * GPIO wakeup request can only be generated on edge
238 * transitions
239 */
240 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 241 __raw_writel(1 << gpio, bank->base
5eb3bb9c 242 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 243 else
244 __raw_writel(1 << gpio, bank->base
5eb3bb9c 245 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 246 }
a118b5f3 247 }
55b220ca
A		 248 /* This part needs to be executed always for OMAP{34xx, 44xx} */
249 if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
250 (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 251 /*
252 * Log the edge gpio and manually trigger the IRQ
253 * after resume if the input level changes
254 * to avoid irq lost during PER RET/OFF mode
255 * Applies for omap2 non-wakeup gpio and all omap3 gpios
256 */
257 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 258 bank->enabled_non_wakeup_gpios |= gpio_bit;
259 else
260 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
261 }
5eb3bb9c 262
78a1a6d3
SR		 263 if (cpu_is_omap44xx()) {
264 bank->level_mask =
265 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
266 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
267 } else {
268 bank->level_mask =
269 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
270 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
271 }
92105bb7 272}
3ac4fa99 273#endif
92105bb7 274
9198bcd3 275#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 276/*
277 * This only applies to chips that can't do both rising and falling edge
278 * detection at once. For all other chips, this function is a noop.
279 */
280static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
281{
282 void __iomem *reg = bank->base;
283 u32 l = 0;
284
285 switch (bank->method) {
4318f36b 286 case METHOD_MPUIO:
5de62b86 287 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
4318f36b 288 break;
4318f36b
CM		 289#ifdef CONFIG_ARCH_OMAP15XX
290 case METHOD_GPIO_1510:
291 reg += OMAP1510_GPIO_INT_CONTROL;
292 break;
293#endif
294#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
295 case METHOD_GPIO_7XX:
296 reg += OMAP7XX_GPIO_INT_CONTROL;
297 break;
298#endif
299 default:
300 return;
301 }
302
303 l = __raw_readl(reg);
304 if ((l >> gpio) & 1)
305 l &= ~(1 << gpio);
306 else
307 l |= 1 << gpio;
308
309 __raw_writel(l, reg);
310}
9198bcd3 311#endif
4318f36b 312
92105bb7
TL		 313static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
314{
315 void __iomem *reg = bank->base;
316 u32 l = 0;
5e1c5ff4
TL		 317
318 switch (bank->method) {
e5c56ed3 319#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 320 case METHOD_MPUIO:
5de62b86 321 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
5e1c5ff4 322 l = __raw_readl(reg);
29501577 323 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 324 bank->toggle_mask |= 1 << gpio;
6cab4860 325 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 326 l |= 1 << gpio;
6cab4860 327 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 328 l &= ~(1 << gpio);
92105bb7
TL		 329 else
330 goto bad;
5e1c5ff4 331 break;
e5c56ed3
DB		 332#endif
333#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 334 case METHOD_GPIO_1510:
335 reg += OMAP1510_GPIO_INT_CONTROL;
336 l = __raw_readl(reg);
29501577 337 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 338 bank->toggle_mask |= 1 << gpio;
6cab4860 339 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 340 l |= 1 << gpio;
6cab4860 341 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 342 l &= ~(1 << gpio);
92105bb7
TL		 343 else
344 goto bad;
5e1c5ff4 345 break;
e5c56ed3 346#endif
3ac4fa99 347#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 348 case METHOD_GPIO_1610:
5e1c5ff4
TL		 349 if (gpio & 0x08)
350 reg += OMAP1610_GPIO_EDGE_CTRL2;
351 else
352 reg += OMAP1610_GPIO_EDGE_CTRL1;
353 gpio &= 0x07;
354 l = __raw_readl(reg);
355 l &= ~(3 << (gpio << 1));
6cab4860 356 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 357 l |= 2 << (gpio << 1);
6cab4860 358 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 359 l |= 1 << (gpio << 1);
3ac4fa99
JY		 360 if (trigger)
361 /* Enable wake-up during idle for dynamic tick */
362 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
363 else
364 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 365 break;
3ac4fa99 366#endif
b718aa81 367#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 368 case METHOD_GPIO_7XX:
369 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 370 l = __raw_readl(reg);
29501577 371 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 372 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 373 if (trigger & IRQ_TYPE_EDGE_RISING)
374 l |= 1 << gpio;
375 else if (trigger & IRQ_TYPE_EDGE_FALLING)
376 l &= ~(1 << gpio);
377 else
378 goto bad;
379 break;
380#endif
140455fa 381#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 382 case METHOD_GPIO_24XX:
3f1686a9 383 case METHOD_GPIO_44XX:
3ac4fa99 384 set_24xx_gpio_triggering(bank, gpio, trigger);
f7c5cc45 385 return 0;
3ac4fa99 386#endif
5e1c5ff4 387 default:
92105bb7 388 goto bad;
5e1c5ff4 389 }
92105bb7
TL		 390 __raw_writel(l, reg);
391 return 0;
392bad:
393 return -EINVAL;
5e1c5ff4
TL		 394}
395
e9191028 396static int gpio_irq_type(struct irq_data *d, unsigned type)
5e1c5ff4
TL		 397{
398 struct gpio_bank *bank;
92105bb7
TL		 399 unsigned gpio;
400 int retval;
a6472533 401 unsigned long flags;
92105bb7 402
e9191028
LB		 403 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
404 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
92105bb7 405 else
e9191028 406 gpio = d->irq - IH_GPIO_BASE;
5e1c5ff4 407
e5c56ed3 408 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 409 return -EINVAL;
e5c56ed3
DB		 410
411 /* OMAP1 allows only only edge triggering */
5492fb1a 412 if (!cpu_class_is_omap2()
e5c56ed3 413 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 414 return -EINVAL;
415
e9191028 416 bank = irq_data_get_irq_chip_data(d);
a6472533 417 spin_lock_irqsave(&bank->lock, flags);
129fd223 418 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
a6472533 419 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 420
421 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
6845664a 422 __irq_set_handler_locked(d->irq, handle_level_irq);
672e302e 423 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
6845664a 424 __irq_set_handler_locked(d->irq, handle_edge_irq);
672e302e 425
92105bb7 426 return retval;
5e1c5ff4
TL		 427}
428
429static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
430{
92105bb7 431 void __iomem *reg = bank->base;
5e1c5ff4 432
eef4bec7 433 reg += bank->regs->irqstatus;
5e1c5ff4 434 __raw_writel(gpio_mask, reg);
bee7930f
HD		 435
436 /* Workaround for clearing DSP GPIO interrupts to allow retention */
eef4bec7
KH		 437 if (bank->regs->irqstatus2) {
438 reg = bank->base + bank->regs->irqstatus2;
bedfd154 439 __raw_writel(gpio_mask, reg);
eef4bec7 440 }
bedfd154
RQ		 441
442 /* Flush posted write for the irq status to avoid spurious interrupts */
443 __raw_readl(reg);
5e1c5ff4
TL		 444}
445
446static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
447{
129fd223 448 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 449}
450
ea6dedd7
ID		 451static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
452{
453 void __iomem *reg = bank->base;
99c47707 454 u32 l;
c390aad0 455 u32 mask = (1 << bank->width) - 1;
ea6dedd7 456
28f3b5a0 457 reg += bank->regs->irqenable;
99c47707 458 l = __raw_readl(reg);
28f3b5a0 459 if (bank->regs->irqenable_inv)
99c47707
ID		 460 l = ~l;
461 l &= mask;
462 return l;
ea6dedd7
ID		 463}
464
28f3b5a0 465static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
5e1c5ff4 466{
92105bb7 467 void __iomem *reg = bank->base;
5e1c5ff4
TL		 468 u32 l;
469
28f3b5a0
KH		 470 if (bank->regs->set_irqenable) {
471 reg += bank->regs->set_irqenable;
472 l = gpio_mask;
473 } else {
474 reg += bank->regs->irqenable;
5e1c5ff4 475 l = __raw_readl(reg);
28f3b5a0
KH		 476 if (bank->regs->irqenable_inv)
477 l &= ~gpio_mask;
5e1c5ff4
TL		 478 else
479 l |= gpio_mask;
28f3b5a0
KH		 480 }
481
482 __raw_writel(l, reg);
483}
484
485static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
486{
487 void __iomem *reg = bank->base;
488 u32 l;
489
490 if (bank->regs->clr_irqenable) {
491 reg += bank->regs->clr_irqenable;
5e1c5ff4 492 l = gpio_mask;
28f3b5a0
KH		 493 } else {
494 reg += bank->regs->irqenable;
56739a69 495 l = __raw_readl(reg);
28f3b5a0 496 if (bank->regs->irqenable_inv)
56739a69 497 l |= gpio_mask;
92105bb7 498 else
28f3b5a0 499 l &= ~gpio_mask;
5e1c5ff4 500 }
28f3b5a0 501
5e1c5ff4
TL		 502 __raw_writel(l, reg);
503}
504
505static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
506{
28f3b5a0 507 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 508}
509
92105bb7
TL		 510/*
511 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
512 * 1510 does not seem to have a wake-up register. If JTAG is connected
513 * to the target, system will wake up always on GPIO events. While
514 * system is running all registered GPIO interrupts need to have wake-up
515 * enabled. When system is suspended, only selected GPIO interrupts need
516 * to have wake-up enabled.
517 */
518static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
519{
f64ad1a0
KH		 520 u32 gpio_bit = GPIO_BIT(bank, gpio);
521 unsigned long flags;
a6472533 522
f64ad1a0
KH		 523 if (bank->non_wakeup_gpios & gpio_bit) {
524 dev_err(bank->dev,
525 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
92105bb7
TL		 526 return -EINVAL;
527 }
f64ad1a0
KH		 528
529 spin_lock_irqsave(&bank->lock, flags);
530 if (enable)
531 bank->suspend_wakeup |= gpio_bit;
532 else
533 bank->suspend_wakeup &= ~gpio_bit;
534
535 spin_unlock_irqrestore(&bank->lock, flags);
536
537 return 0;
92105bb7
TL		 538}
539
4196dd6b
TL		 540static void _reset_gpio(struct gpio_bank *bank, int gpio)
541{
129fd223 542 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
4196dd6b
TL		 543 _set_gpio_irqenable(bank, gpio, 0);
544 _clear_gpio_irqstatus(bank, gpio);
129fd223 545 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 546}
547
92105bb7 548/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
e9191028 549static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
92105bb7 550{
e9191028 551 unsigned int gpio = d->irq - IH_GPIO_BASE;
92105bb7
TL		 552 struct gpio_bank *bank;
553 int retval;
554
e9191028 555 bank = irq_data_get_irq_chip_data(d);
f64ad1a0 556 retval = _set_gpio_wakeup(bank, gpio, enable);
92105bb7
TL		 557
558 return retval;
559}
560
3ff164e1 561static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 562{
3ff164e1 563 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 564 unsigned long flags;
52e31344 565
a6472533 566 spin_lock_irqsave(&bank->lock, flags);
92105bb7 567
4196dd6b
TL		 568 /* Set trigger to none. You need to enable the desired trigger with
569 * request_irq() or set_irq_type().
570 */
3ff164e1 571 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 572
1a8bfa1e 573#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 574 if (bank->method == METHOD_GPIO_1510) {
92105bb7 575 void __iomem *reg;
5e1c5ff4 576
92105bb7 577 /* Claim the pin for MPU */
5e1c5ff4 578 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 579 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 580 }
581#endif
058af1ea
C		 582 if (!cpu_class_is_omap1()) {
583 if (!bank->mod_usage) {
9f096868 584 void __iomem *reg = bank->base;
058af1ea 585 u32 ctrl;
9f096868
C		 586
587 if (cpu_is_omap24xx() || cpu_is_omap34xx())
588 reg += OMAP24XX_GPIO_CTRL;
589 else if (cpu_is_omap44xx())
590 reg += OMAP4_GPIO_CTRL;
591 ctrl = __raw_readl(reg);
058af1ea 592 /* Module is enabled, clocks are not gated */
9f096868
C		 593 ctrl &= 0xFFFFFFFE;
594 __raw_writel(ctrl, reg);
058af1ea
C		 595 }
596 bank->mod_usage |= 1 << offset;
597 }
a6472533 598 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 599
600 return 0;
601}
602
3ff164e1 603static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 604{
3ff164e1 605 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 606 unsigned long flags;
5e1c5ff4 607
a6472533 608 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 609#ifdef CONFIG_ARCH_OMAP16XX
610 if (bank->method == METHOD_GPIO_1610) {
611 /* Disable wake-up during idle for dynamic tick */
612 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 613 __raw_writel(1 << offset, reg);
92105bb7
TL		 614 }
615#endif
9f096868
C		 616#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
617 if (bank->method == METHOD_GPIO_24XX) {
92105bb7
TL		 618 /* Disable wake-up during idle for dynamic tick */
619 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 620 __raw_writel(1 << offset, reg);
92105bb7 621 }
9f096868
C		 622#endif
623#ifdef CONFIG_ARCH_OMAP4
624 if (bank->method == METHOD_GPIO_44XX) {
625 /* Disable wake-up during idle for dynamic tick */
626 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
627 __raw_writel(1 << offset, reg);
628 }
92105bb7 629#endif
058af1ea
C		 630 if (!cpu_class_is_omap1()) {
631 bank->mod_usage &= ~(1 << offset);
632 if (!bank->mod_usage) {
9f096868 633 void __iomem *reg = bank->base;
058af1ea 634 u32 ctrl;
9f096868
C		 635
636 if (cpu_is_omap24xx() || cpu_is_omap34xx())
637 reg += OMAP24XX_GPIO_CTRL;
638 else if (cpu_is_omap44xx())
639 reg += OMAP4_GPIO_CTRL;
640 ctrl = __raw_readl(reg);
058af1ea
C		 641 /* Module is disabled, clocks are gated */
642 ctrl |= 1;
9f096868 643 __raw_writel(ctrl, reg);
058af1ea
C		 644 }
645 }
3ff164e1 646 _reset_gpio(bank, bank->chip.base + offset);
a6472533 647 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 648}
649
650/*
651 * We need to unmask the GPIO bank interrupt as soon as possible to
652 * avoid missing GPIO interrupts for other lines in the bank.
653 * Then we need to mask-read-clear-unmask the triggered GPIO lines
654 * in the bank to avoid missing nested interrupts for a GPIO line.
655 * If we wait to unmask individual GPIO lines in the bank after the
656 * line's interrupt handler has been run, we may miss some nested
657 * interrupts.
658 */
10dd5ce2 659static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 660{
92105bb7 661 void __iomem *isr_reg = NULL;
5e1c5ff4 662 u32 isr;
4318f36b 663 unsigned int gpio_irq, gpio_index;
5e1c5ff4 664 struct gpio_bank *bank;
ea6dedd7
ID		 665 u32 retrigger = 0;
666 int unmasked = 0;
ee144182 667 struct irq_chip *chip = irq_desc_get_chip(desc);
5e1c5ff4 668
ee144182 669 chained_irq_enter(chip, desc);
5e1c5ff4 670
6845664a 671 bank = irq_get_handler_data(irq);
eef4bec7 672 isr_reg = bank->base + bank->regs->irqstatus;
b1cc4c55
EK		 673
674 if (WARN_ON(!isr_reg))
675 goto exit;
676
92105bb7 677 while(1) {
6e60e79a 678 u32 isr_saved, level_mask = 0;
ea6dedd7 679 u32 enabled;
6e60e79a 680
ea6dedd7
ID		 681 enabled = _get_gpio_irqbank_mask(bank);
682 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 683
684 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
685 isr &= 0x0000ffff;
686
5492fb1a 687 if (cpu_class_is_omap2()) {
b144ff6f 688 level_mask = bank->level_mask & enabled;
ea6dedd7 689 }
6e60e79a
TL		 690
691 /* clear edge sensitive interrupts before handler(s) are
692 called so that we don't miss any interrupt occurred while
693 executing them */
28f3b5a0 694 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
6e60e79a 695 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
28f3b5a0 696 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
6e60e79a
TL		 697
698 /* if there is only edge sensitive GPIO pin interrupts
699 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 700 if (!level_mask && !unmasked) {
701 unmasked = 1;
ee144182 702 chained_irq_exit(chip, desc);
ea6dedd7 703 }
92105bb7 704
ea6dedd7
ID		 705 isr |= retrigger;
706 retrigger = 0;
92105bb7
TL		 707 if (!isr)
708 break;
709
710 gpio_irq = bank->virtual_irq_start;
711 for (; isr != 0; isr >>= 1, gpio_irq++) {
129fd223 712 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
4318f36b 713
92105bb7
TL		 714 if (!(isr & 1))
715 continue;
29454dde 716
4318f36b
CM		 717#ifdef CONFIG_ARCH_OMAP1
718 /*
719 * Some chips can't respond to both rising and falling
720 * at the same time. If this irq was requested with
721 * both flags, we need to flip the ICR data for the IRQ
722 * to respond to the IRQ for the opposite direction.
723 * This will be indicated in the bank toggle_mask.
724 */
725 if (bank->toggle_mask & (1 << gpio_index))
726 _toggle_gpio_edge_triggering(bank, gpio_index);
727#endif
728
d8aa0251 729 generic_handle_irq(gpio_irq);
92105bb7 730 }
1a8bfa1e 731 }
ea6dedd7
ID		 732 /* if bank has any level sensitive GPIO pin interrupt
733 configured, we must unmask the bank interrupt only after
734 handler(s) are executed in order to avoid spurious bank
735 interrupt */
b1cc4c55 736exit:
ea6dedd7 737 if (!unmasked)
ee144182 738 chained_irq_exit(chip, desc);
5e1c5ff4
TL		 739}
740
e9191028 741static void gpio_irq_shutdown(struct irq_data *d)
4196dd6b 742{
e9191028
LB		 743 unsigned int gpio = d->irq - IH_GPIO_BASE;
744 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 745 unsigned long flags;
4196dd6b 746
85ec7b97 747 spin_lock_irqsave(&bank->lock, flags);
4196dd6b 748 _reset_gpio(bank, gpio);
85ec7b97 749 spin_unlock_irqrestore(&bank->lock, flags);
4196dd6b
TL		 750}
751
e9191028 752static void gpio_ack_irq(struct irq_data *d)
5e1c5ff4 753{
e9191028
LB		 754 unsigned int gpio = d->irq - IH_GPIO_BASE;
755 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 756
757 _clear_gpio_irqstatus(bank, gpio);
758}
759
e9191028 760static void gpio_mask_irq(struct irq_data *d)
5e1c5ff4 761{
e9191028
LB		 762 unsigned int gpio = d->irq - IH_GPIO_BASE;
763 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 764 unsigned long flags;
5e1c5ff4 765
85ec7b97 766 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 767 _set_gpio_irqenable(bank, gpio, 0);
129fd223 768 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
85ec7b97 769 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 770}
771
e9191028 772static void gpio_unmask_irq(struct irq_data *d)
5e1c5ff4 773{
e9191028
LB		 774 unsigned int gpio = d->irq - IH_GPIO_BASE;
775 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
129fd223 776 unsigned int irq_mask = GPIO_BIT(bank, gpio);
8c04a176 777 u32 trigger = irqd_get_trigger_type(d);
85ec7b97 778 unsigned long flags;
55b6019a 779
85ec7b97 780 spin_lock_irqsave(&bank->lock, flags);
55b6019a 781 if (trigger)
129fd223 782 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
b144ff6f
KH		 783
784 /* For level-triggered GPIOs, the clearing must be done after
785 * the HW source is cleared, thus after the handler has run */
786 if (bank->level_mask & irq_mask) {
787 _set_gpio_irqenable(bank, gpio, 0);
788 _clear_gpio_irqstatus(bank, gpio);
789 }
5e1c5ff4 790
4de8c75b 791 _set_gpio_irqenable(bank, gpio, 1);
85ec7b97 792 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 793}
794
e5c56ed3
DB		 795static struct irq_chip gpio_irq_chip = {
796 .name = "GPIO",
e9191028
LB		 797 .irq_shutdown = gpio_irq_shutdown,
798 .irq_ack = gpio_ack_irq,
799 .irq_mask = gpio_mask_irq,
800 .irq_unmask = gpio_unmask_irq,
801 .irq_set_type = gpio_irq_type,
802 .irq_set_wake = gpio_wake_enable,
e5c56ed3
DB		 803};
804
805/*---------------------------------------------------------------------*/
806
807#ifdef CONFIG_ARCH_OMAP1
808
e5c56ed3
DB		 809#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
810
11a78b79
DB		 811#ifdef CONFIG_ARCH_OMAP16XX
812
813#include <linux/platform_device.h>
814
79ee031f 815static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 816{
79ee031f 817 struct platform_device *pdev = to_platform_device(dev);
11a78b79 818 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 819 void __iomem *mask_reg = bank->base +
820 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 821 unsigned long flags;
11a78b79 822
a6472533 823 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 824 bank->saved_wakeup = __raw_readl(mask_reg);
825 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 826 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 827
828 return 0;
829}
830
79ee031f 831static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 832{
79ee031f 833 struct platform_device *pdev = to_platform_device(dev);
11a78b79 834 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 835 void __iomem *mask_reg = bank->base +
836 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 837 unsigned long flags;
11a78b79 838
a6472533 839 spin_lock_irqsave(&bank->lock, flags);
11a78b79 840 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 841 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 842
843 return 0;
844}
845
47145210 846static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 847 .suspend_noirq = omap_mpuio_suspend_noirq,
848 .resume_noirq = omap_mpuio_resume_noirq,
849};
850
3c437ffd 851/* use platform_driver for this. */
11a78b79 852static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 853 .driver = {
854 .name = "mpuio",
79ee031f 855 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 856 },
857};
858
859static struct platform_device omap_mpuio_device = {
860 .name = "mpuio",
861 .id = -1,
862 .dev = {
863 .driver = &omap_mpuio_driver.driver,
864 }
865 /* could list the /proc/iomem resources */
866};
867
868static inline void mpuio_init(void)
869{
a8be8daf 870 struct gpio_bank *bank = &gpio_bank[0];
77640aab 871 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 872
11a78b79
DB		 873 if (platform_driver_register(&omap_mpuio_driver) == 0)
874 (void) platform_device_register(&omap_mpuio_device);
875}
876
877#else
878static inline void mpuio_init(void) {}
879#endif /* 16xx */
880
e5c56ed3
DB		 881#else
882
e5c56ed3 883#define bank_is_mpuio(bank) 0
11a78b79 884static inline void mpuio_init(void) {}
e5c56ed3
DB		 885
886#endif
887
888/*---------------------------------------------------------------------*/
5e1c5ff4 889
52e31344
DB		 890/* REVISIT these are stupid implementations! replace by ones that
891 * don't switch on METHOD_* and which mostly avoid spinlocks
892 */
893
894static int gpio_input(struct gpio_chip *chip, unsigned offset)
895{
896 struct gpio_bank *bank;
897 unsigned long flags;
898
899 bank = container_of(chip, struct gpio_bank, chip);
900 spin_lock_irqsave(&bank->lock, flags);
901 _set_gpio_direction(bank, offset, 1);
902 spin_unlock_irqrestore(&bank->lock, flags);
903 return 0;
904}
905
b37c45b8
RQ		 906static int gpio_is_input(struct gpio_bank *bank, int mask)
907{
fa87931a 908 void __iomem *reg = bank->base + bank->regs->direction;
b37c45b8 909
b37c45b8
RQ		 910 return __raw_readl(reg) & mask;
911}
912
52e31344
DB		 913static int gpio_get(struct gpio_chip *chip, unsigned offset)
914{
b37c45b8
RQ		 915 struct gpio_bank *bank;
916 void __iomem *reg;
917 int gpio;
918 u32 mask;
919
920 gpio = chip->base + offset;
a8be8daf 921 bank = container_of(chip, struct gpio_bank, chip);
b37c45b8 922 reg = bank->base;
129fd223 923 mask = GPIO_BIT(bank, gpio);
b37c45b8
RQ		 924
925 if (gpio_is_input(bank, mask))
926 return _get_gpio_datain(bank, gpio);
927 else
928 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 929}
930
931static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
932{
933 struct gpio_bank *bank;
934 unsigned long flags;
935
936 bank = container_of(chip, struct gpio_bank, chip);
937 spin_lock_irqsave(&bank->lock, flags);
fa87931a 938 bank->set_dataout(bank, offset, value);
52e31344
DB		 939 _set_gpio_direction(bank, offset, 0);
940 spin_unlock_irqrestore(&bank->lock, flags);
941 return 0;
942}
943
168ef3d9
FB		 944static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
945 unsigned debounce)
946{
947 struct gpio_bank *bank;
948 unsigned long flags;
949
950 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 951
952 if (!bank->dbck) {
953 bank->dbck = clk_get(bank->dev, "dbclk");
954 if (IS_ERR(bank->dbck))
955 dev_err(bank->dev, "Could not get gpio dbck\n");
956 }
957
168ef3d9
FB		 958 spin_lock_irqsave(&bank->lock, flags);
959 _set_gpio_debounce(bank, offset, debounce);
960 spin_unlock_irqrestore(&bank->lock, flags);
961
962 return 0;
963}
964
52e31344
DB		 965static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
966{
967 struct gpio_bank *bank;
968 unsigned long flags;
969
970 bank = container_of(chip, struct gpio_bank, chip);
971 spin_lock_irqsave(&bank->lock, flags);
fa87931a 972 bank->set_dataout(bank, offset, value);
52e31344
DB		 973 spin_unlock_irqrestore(&bank->lock, flags);
974}
975
a007b709
DB		 976static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
977{
978 struct gpio_bank *bank;
979
980 bank = container_of(chip, struct gpio_bank, chip);
981 return bank->virtual_irq_start + offset;
982}
983
52e31344
DB		 984/*---------------------------------------------------------------------*/
985
9a748053 986static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da 987{
e5ff4440 988 static bool called;
9f7065da
TL		 989 u32 rev;
990
e5ff4440 991 if (called || bank->regs->revision == USHRT_MAX)
9f7065da
TL		 992 return;
993
e5ff4440
KH		 994 rev = __raw_readw(bank->base + bank->regs->revision);
995 pr_info("OMAP GPIO hardware version %d.%d\n",
9f7065da 996 (rev >> 4) & 0x0f, rev & 0x0f);
e5ff4440
KH		 997
998 called = true;
9f7065da
TL		 999}
1000
8ba55c5c
DB		 1001/* This lock class tells lockdep that GPIO irqs are in a different
1002 * category than their parents, so it won't report false recursion.
1003 */
1004static struct lock_class_key gpio_lock_class;
1005
77640aab
VC		 1006static inline int init_gpio_info(struct platform_device *pdev)
1007{
1008 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1009 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1010 GFP_KERNEL);
1011 if (!gpio_bank) {
1012 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1013 return -ENOMEM;
1014 }
1015 return 0;
1016}
1017
1018/* TODO: Cleanup cpu_is_* checks */
2fae7fbe
VC		 1019static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1020{
1021 if (cpu_class_is_omap2()) {
1022 if (cpu_is_omap44xx()) {
1023 __raw_writel(0xffffffff, bank->base +
1024 OMAP4_GPIO_IRQSTATUSCLR0);
1025 __raw_writel(0x00000000, bank->base +
1026 OMAP4_GPIO_DEBOUNCENABLE);
1027 /* Initialize interface clk ungated, module enabled */
1028 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1029 } else if (cpu_is_omap34xx()) {
1030 __raw_writel(0x00000000, bank->base +
1031 OMAP24XX_GPIO_IRQENABLE1);
1032 __raw_writel(0xffffffff, bank->base +
1033 OMAP24XX_GPIO_IRQSTATUS1);
1034 __raw_writel(0x00000000, bank->base +
1035 OMAP24XX_GPIO_DEBOUNCE_EN);
1036
1037 /* Initialize interface clk ungated, module enabled */
1038 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1039 } else if (cpu_is_omap24xx()) {
1040 static const u32 non_wakeup_gpios[] = {
1041 0xe203ffc0, 0x08700040
1042 };
1043 if (id < ARRAY_SIZE(non_wakeup_gpios))
1044 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1045 }
1046 } else if (cpu_class_is_omap1()) {
1047 if (bank_is_mpuio(bank))
5de62b86
TL		 1048 __raw_writew(0xffff, bank->base +
1049 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
2fae7fbe
VC		 1050 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1051 __raw_writew(0xffff, bank->base
1052 + OMAP1510_GPIO_INT_MASK);
1053 __raw_writew(0x0000, bank->base
1054 + OMAP1510_GPIO_INT_STATUS);
1055 }
1056 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1057 __raw_writew(0x0000, bank->base
1058 + OMAP1610_GPIO_IRQENABLE1);
1059 __raw_writew(0xffff, bank->base
1060 + OMAP1610_GPIO_IRQSTATUS1);
1061 __raw_writew(0x0014, bank->base
1062 + OMAP1610_GPIO_SYSCONFIG);
1063
1064 /*
1065 * Enable system clock for GPIO module.
1066 * The CAM_CLK_CTRL *is* really the right place.
1067 */
1068 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1069 ULPD_CAM_CLK_CTRL);
1070 }
1071 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1072 __raw_writel(0xffffffff, bank->base
1073 + OMAP7XX_GPIO_INT_MASK);
1074 __raw_writel(0x00000000, bank->base
1075 + OMAP7XX_GPIO_INT_STATUS);
1076 }
1077 }
1078}
1079
f8b46b58
KH		 1080static __init void
1081omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1082 unsigned int num)
1083{
1084 struct irq_chip_generic *gc;
1085 struct irq_chip_type *ct;
1086
1087 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1088 handle_simple_irq);
1089 ct = gc->chip_types;
1090
1091 /* NOTE: No ack required, reading IRQ status clears it. */
1092 ct->chip.irq_mask = irq_gc_mask_set_bit;
1093 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1094 ct->chip.irq_set_type = gpio_irq_type;
1095 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1096 if (cpu_is_omap16xx())
1097 ct->chip.irq_set_wake = gpio_wake_enable,
1098
1099 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1100 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1101 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1102}
1103
d52b31de 1104static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
2fae7fbe 1105{
77640aab 1106 int j;
2fae7fbe
VC		 1107 static int gpio;
1108
2fae7fbe
VC		 1109 bank->mod_usage = 0;
1110 /*
1111 * REVISIT eventually switch from OMAP-specific gpio structs
1112 * over to the generic ones
1113 */
1114 bank->chip.request = omap_gpio_request;
1115 bank->chip.free = omap_gpio_free;
1116 bank->chip.direction_input = gpio_input;
1117 bank->chip.get = gpio_get;
1118 bank->chip.direction_output = gpio_output;
1119 bank->chip.set_debounce = gpio_debounce;
1120 bank->chip.set = gpio_set;
1121 bank->chip.to_irq = gpio_2irq;
1122 if (bank_is_mpuio(bank)) {
1123 bank->chip.label = "mpuio";
1124#ifdef CONFIG_ARCH_OMAP16XX
1125 bank->chip.dev = &omap_mpuio_device.dev;
1126#endif
1127 bank->chip.base = OMAP_MPUIO(0);
1128 } else {
1129 bank->chip.label = "gpio";
1130 bank->chip.base = gpio;
d5f46247 1131 gpio += bank->width;
2fae7fbe 1132 }
d5f46247 1133 bank->chip.ngpio = bank->width;
2fae7fbe
VC		 1134
1135 gpiochip_add(&bank->chip);
1136
1137 for (j = bank->virtual_irq_start;
d5f46247 1138 j < bank->virtual_irq_start + bank->width; j++) {
1475b85d 1139 irq_set_lockdep_class(j, &gpio_lock_class);
6845664a 1140 irq_set_chip_data(j, bank);
f8b46b58
KH		 1141 if (bank_is_mpuio(bank)) {
1142 omap_mpuio_alloc_gc(bank, j, bank->width);
1143 } else {
6845664a 1144 irq_set_chip(j, &gpio_irq_chip);
f8b46b58
KH		 1145 irq_set_handler(j, handle_simple_irq);
1146 set_irq_flags(j, IRQF_VALID);
1147 }
2fae7fbe 1148 }
6845664a
TG		 1149 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1150 irq_set_handler_data(bank->irq, bank);
2fae7fbe
VC		 1151}
1152
77640aab 1153static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1154{
77640aab
VC		 1155 static int gpio_init_done;
1156 struct omap_gpio_platform_data *pdata;
1157 struct resource *res;
1158 int id;
5e1c5ff4
TL		 1159 struct gpio_bank *bank;
1160
77640aab
VC		 1161 if (!pdev->dev.platform_data)
1162 return -EINVAL;
5e1c5ff4 1163
77640aab 1164 pdata = pdev->dev.platform_data;
56a25641 1165
77640aab
VC		 1166 if (!gpio_init_done) {
1167 int ret;
5492fb1a 1168
77640aab
VC		 1169 ret = init_gpio_info(pdev);
1170 if (ret)
1171 return ret;
5492fb1a 1172 }
5492fb1a 1173
77640aab
VC		 1174 id = pdev->id;
1175 bank = &gpio_bank[id];
92105bb7 1176
77640aab
VC		 1177 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1178 if (unlikely(!res)) {
1179 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1180 return -ENODEV;
44169075 1181 }
5e1c5ff4 1182
77640aab
VC		 1183 bank->irq = res->start;
1184 bank->virtual_irq_start = pdata->virtual_irq_start;
1185 bank->method = pdata->bank_type;
1186 bank->dev = &pdev->dev;
1187 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1188 bank->stride = pdata->bank_stride;
d5f46247 1189 bank->width = pdata->bank_width;
9f7065da 1190
fa87931a
KH		 1191 bank->regs = pdata->regs;
1192
1193 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1194 bank->set_dataout = _set_gpio_dataout_reg;
1195 else
1196 bank->set_dataout = _set_gpio_dataout_mask;
9f7065da 1197
77640aab 1198 spin_lock_init(&bank->lock);
9f7065da 1199
77640aab
VC		 1200 /* Static mapping, never released */
1201 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1202 if (unlikely(!res)) {
1203 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1204 return -ENODEV;
1205 }
89db9482 1206
77640aab
VC		 1207 bank->base = ioremap(res->start, resource_size(res));
1208 if (!bank->base) {
1209 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1210 return -ENOMEM;
5e1c5ff4
TL		 1211 }
1212
77640aab
VC		 1213 pm_runtime_enable(bank->dev);
1214 pm_runtime_get_sync(bank->dev);
1215
1216 omap_gpio_mod_init(bank, id);
1217 omap_gpio_chip_init(bank);
9a748053 1218 omap_gpio_show_rev(bank);
9f7065da 1219
77640aab
VC		 1220 if (!gpio_init_done)
1221 gpio_init_done = 1;
1222
5e1c5ff4
TL		 1223 return 0;
1224}
1225
140455fa 1226#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd 1227static int omap_gpio_suspend(void)
92105bb7
TL		 1228{
1229 int i;
1230
5492fb1a 1231 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1232 return 0;
1233
1234 for (i = 0; i < gpio_bank_count; i++) {
1235 struct gpio_bank *bank = &gpio_bank[i];
1236 void __iomem *wake_status;
1237 void __iomem *wake_clear;
1238 void __iomem *wake_set;
a6472533 1239 unsigned long flags;
92105bb7
TL		 1240
1241 switch (bank->method) {
e5c56ed3 1242#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1243 case METHOD_GPIO_1610:
1244 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1245 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1246 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1247 break;
e5c56ed3 1248#endif
a8eb7ca0 1249#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1250 case METHOD_GPIO_24XX:
723fdb78 1251 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1252 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1253 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1254 break;
78a1a6d3
SR		 1255#endif
1256#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1257 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1258 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1259 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1260 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1261 break;
e5c56ed3 1262#endif
92105bb7
TL		 1263 default:
1264 continue;
1265 }
1266
a6472533 1267 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1268 bank->saved_wakeup = __raw_readl(wake_status);
1269 __raw_writel(0xffffffff, wake_clear);
1270 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1271 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1272 }
1273
1274 return 0;
1275}
1276
3c437ffd 1277static void omap_gpio_resume(void)
92105bb7
TL		 1278{
1279 int i;
1280
723fdb78 1281 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
3c437ffd 1282 return;
92105bb7
TL		 1283
1284 for (i = 0; i < gpio_bank_count; i++) {
1285 struct gpio_bank *bank = &gpio_bank[i];
1286 void __iomem *wake_clear;
1287 void __iomem *wake_set;
a6472533 1288 unsigned long flags;
92105bb7
TL		 1289
1290 switch (bank->method) {
e5c56ed3 1291#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1292 case METHOD_GPIO_1610:
1293 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1294 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1295 break;
e5c56ed3 1296#endif
a8eb7ca0 1297#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1298 case METHOD_GPIO_24XX:
0d9356cb
TL		 1299 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1300 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1301 break;
78a1a6d3
SR		 1302#endif
1303#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1304 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1305 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1306 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1307 break;
e5c56ed3 1308#endif
92105bb7
TL		 1309 default:
1310 continue;
1311 }
1312
a6472533 1313 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1314 __raw_writel(0xffffffff, wake_clear);
1315 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1316 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1317 }
92105bb7
TL		 1318}
1319
3c437ffd 1320static struct syscore_ops omap_gpio_syscore_ops = {
92105bb7
TL		 1321 .suspend = omap_gpio_suspend,
1322 .resume = omap_gpio_resume,
1323};
1324
3ac4fa99
JY		 1325#endif
1326
140455fa 1327#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 1328
1329static int workaround_enabled;
1330
72e06d08 1331void omap2_gpio_prepare_for_idle(int off_mode)
3ac4fa99
JY		 1332{
1333 int i, c = 0;
a118b5f3 1334 int min = 0;
3ac4fa99 1335
a118b5f3
TK		 1336 if (cpu_is_omap34xx())
1337 min = 1;
43ffcd9a 1338
a118b5f3 1339 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1340 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1341 u32 l1 = 0, l2 = 0;
0aed0435 1342 int j;
3ac4fa99 1343
0aed0435 1344 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1345 clk_disable(bank->dbck);
1346
72e06d08 1347 if (!off_mode)
43ffcd9a
KH		 1348 continue;
1349
1350 /* If going to OFF, remove triggering for all
1351 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1352 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99
JY		 1353 if (!(bank->enabled_non_wakeup_gpios))
1354 continue;
3f1686a9
TL		 1355
1356 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1357 bank->saved_datain = __raw_readl(bank->base +
1358 OMAP24XX_GPIO_DATAIN);
1359 l1 = __raw_readl(bank->base +
1360 OMAP24XX_GPIO_FALLINGDETECT);
1361 l2 = __raw_readl(bank->base +
1362 OMAP24XX_GPIO_RISINGDETECT);
1363 }
1364
1365 if (cpu_is_omap44xx()) {
1366 bank->saved_datain = __raw_readl(bank->base +
1367 OMAP4_GPIO_DATAIN);
1368 l1 = __raw_readl(bank->base +
1369 OMAP4_GPIO_FALLINGDETECT);
1370 l2 = __raw_readl(bank->base +
1371 OMAP4_GPIO_RISINGDETECT);
1372 }
1373
3ac4fa99
JY		 1374 bank->saved_fallingdetect = l1;
1375 bank->saved_risingdetect = l2;
1376 l1 &= ~bank->enabled_non_wakeup_gpios;
1377 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 1378
1379 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1380 __raw_writel(l1, bank->base +
1381 OMAP24XX_GPIO_FALLINGDETECT);
1382 __raw_writel(l2, bank->base +
1383 OMAP24XX_GPIO_RISINGDETECT);
1384 }
1385
1386 if (cpu_is_omap44xx()) {
1387 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1388 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1389 }
1390
3ac4fa99
JY		 1391 c++;
1392 }
1393 if (!c) {
1394 workaround_enabled = 0;
1395 return;
1396 }
1397 workaround_enabled = 1;
1398}
1399
43ffcd9a 1400void omap2_gpio_resume_after_idle(void)
3ac4fa99
JY		 1401{
1402 int i;
a118b5f3 1403 int min = 0;
3ac4fa99 1404
a118b5f3
TK		 1405 if (cpu_is_omap34xx())
1406 min = 1;
1407 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1408 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1409 u32 l = 0, gen, gen0, gen1;
0aed0435 1410 int j;
3ac4fa99 1411
0aed0435 1412 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1413 clk_enable(bank->dbck);
1414
43ffcd9a
KH		 1415 if (!workaround_enabled)
1416 continue;
1417
3ac4fa99
JY		 1418 if (!(bank->enabled_non_wakeup_gpios))
1419 continue;
3f1686a9
TL		 1420
1421 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1422 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 1423 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 1424 __raw_writel(bank->saved_risingdetect,
3ac4fa99 1425 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 1426 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1427 }
1428
1429 if (cpu_is_omap44xx()) {
1430 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 1431 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 1432 __raw_writel(bank->saved_risingdetect,
78a1a6d3 1433 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 1434 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1435 }
1436
3ac4fa99
JY		 1437 /* Check if any of the non-wakeup interrupt GPIOs have changed
1438 * state. If so, generate an IRQ by software. This is
1439 * horribly racy, but it's the best we can do to work around
1440 * this silicon bug. */
3ac4fa99 1441 l ^= bank->saved_datain;
a118b5f3 1442 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 1443
1444 /*
1445 * No need to generate IRQs for the rising edge for gpio IRQs
1446 * configured with falling edge only; and vice versa.
1447 */
1448 gen0 = l & bank->saved_fallingdetect;
1449 gen0 &= bank->saved_datain;
1450
1451 gen1 = l & bank->saved_risingdetect;
1452 gen1 &= ~(bank->saved_datain);
1453
1454 /* FIXME: Consider GPIO IRQs with level detections properly! */
1455 gen = l & (~(bank->saved_fallingdetect) &
1456 ~(bank->saved_risingdetect));
1457 /* Consider all GPIO IRQs needed to be updated */
1458 gen |= gen0 | gen1;
1459
1460 if (gen) {
3ac4fa99 1461 u32 old0, old1;
3f1686a9 1462
f00d6497 1463 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 1464 old0 = __raw_readl(bank->base +
1465 OMAP24XX_GPIO_LEVELDETECT0);
1466 old1 = __raw_readl(bank->base +
1467 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1468 __raw_writel(old0 | gen, bank->base +
82dbb9d3 1469 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1470 __raw_writel(old1 | gen, bank->base +
82dbb9d3 1471 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1472 __raw_writel(old0, bank->base +
3f1686a9 1473 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1474 __raw_writel(old1, bank->base +
3f1686a9
TL		 1475 OMAP24XX_GPIO_LEVELDETECT1);
1476 }
1477
1478 if (cpu_is_omap44xx()) {
1479 old0 = __raw_readl(bank->base +
78a1a6d3 1480 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1481 old1 = __raw_readl(bank->base +
78a1a6d3 1482 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1483 __raw_writel(old0 | l, bank->base +
78a1a6d3 1484 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1485 __raw_writel(old1 | l, bank->base +
78a1a6d3 1486 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1487 __raw_writel(old0, bank->base +
78a1a6d3 1488 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1489 __raw_writel(old1, bank->base +
78a1a6d3 1490 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1491 }
3ac4fa99
JY		 1492 }
1493 }
1494
1495}
1496
92105bb7
TL		 1497#endif
1498
a8eb7ca0 1499#ifdef CONFIG_ARCH_OMAP3
40c670f0
RN		 1500/* save the registers of bank 2-6 */
1501void omap_gpio_save_context(void)
1502{
1503 int i;
1504
1505 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1506 for (i = 1; i < gpio_bank_count; i++) {
1507 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1508 gpio_context[i].irqenable1 =
1509 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1510 gpio_context[i].irqenable2 =
1511 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1512 gpio_context[i].wake_en =
1513 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1514 gpio_context[i].ctrl =
1515 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1516 gpio_context[i].oe =
1517 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1518 gpio_context[i].leveldetect0 =
1519 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1520 gpio_context[i].leveldetect1 =
1521 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1522 gpio_context[i].risingdetect =
1523 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1524 gpio_context[i].fallingdetect =
1525 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1526 gpio_context[i].dataout =
1527 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1528 }
1529}
1530
1531/* restore the required registers of bank 2-6 */
1532void omap_gpio_restore_context(void)
1533{
1534 int i;
1535
1536 for (i = 1; i < gpio_bank_count; i++) {
1537 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1538 __raw_writel(gpio_context[i].irqenable1,
1539 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1540 __raw_writel(gpio_context[i].irqenable2,
1541 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1542 __raw_writel(gpio_context[i].wake_en,
1543 bank->base + OMAP24XX_GPIO_WAKE_EN);
1544 __raw_writel(gpio_context[i].ctrl,
1545 bank->base + OMAP24XX_GPIO_CTRL);
1546 __raw_writel(gpio_context[i].oe,
1547 bank->base + OMAP24XX_GPIO_OE);
1548 __raw_writel(gpio_context[i].leveldetect0,
1549 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1550 __raw_writel(gpio_context[i].leveldetect1,
1551 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1552 __raw_writel(gpio_context[i].risingdetect,
1553 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1554 __raw_writel(gpio_context[i].fallingdetect,
1555 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1556 __raw_writel(gpio_context[i].dataout,
1557 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1558 }
1559}
1560#endif
1561
77640aab
VC		 1562static struct platform_driver omap_gpio_driver = {
1563 .probe = omap_gpio_probe,
1564 .driver = {
1565 .name = "omap_gpio",
1566 },
1567};
1568
5e1c5ff4 1569/*
77640aab
VC		 1570 * gpio driver register needs to be done before
1571 * machine_init functions access gpio APIs.
1572 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 1573 */
77640aab 1574static int __init omap_gpio_drv_reg(void)
5e1c5ff4 1575{
77640aab 1576 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 1577}
77640aab 1578postcore_initcall(omap_gpio_drv_reg);
5e1c5ff4 1579
92105bb7
TL		 1580static int __init omap_gpio_sysinit(void)
1581{
11a78b79
DB		 1582 mpuio_init();
1583
140455fa 1584#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd
RW		 1585 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1586 register_syscore_ops(&omap_gpio_syscore_ops);
92105bb7
TL		 1587#endif
1588
3c437ffd 1589 return 0;
92105bb7
TL		 1590}
1591
92105bb7 1592arch_initcall(omap_gpio_sysinit);
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