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Commit | Line | Data |
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5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
4b25408f | 27 | #include <linux/gpio.h> |
9370084e | 28 | #include <linux/bitops.h> |
4b25408f | 29 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 30 | |
2dc983c5 TKD |
31 | #define OFF_MODE 1 |
32 | ||
03e128ca C |
33 | static LIST_HEAD(omap_gpio_list); |
34 | ||
6d62e216 C |
35 | struct gpio_regs { |
36 | u32 irqenable1; | |
37 | u32 irqenable2; | |
38 | u32 wake_en; | |
39 | u32 ctrl; | |
40 | u32 oe; | |
41 | u32 leveldetect0; | |
42 | u32 leveldetect1; | |
43 | u32 risingdetect; | |
44 | u32 fallingdetect; | |
45 | u32 dataout; | |
ae547354 NM |
46 | u32 debounce; |
47 | u32 debounce_en; | |
6d62e216 C |
48 | }; |
49 | ||
5e1c5ff4 | 50 | struct gpio_bank { |
03e128ca | 51 | struct list_head node; |
92105bb7 | 52 | void __iomem *base; |
5e1c5ff4 | 53 | u16 irq; |
3ac4fa99 JY |
54 | u32 non_wakeup_gpios; |
55 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 56 | struct gpio_regs context; |
3ac4fa99 | 57 | u32 saved_datain; |
b144ff6f | 58 | u32 level_mask; |
4318f36b | 59 | u32 toggle_mask; |
5e1c5ff4 | 60 | spinlock_t lock; |
52e31344 | 61 | struct gpio_chip chip; |
89db9482 | 62 | struct clk *dbck; |
058af1ea | 63 | u32 mod_usage; |
fa365e4d | 64 | u32 irq_usage; |
8865b9b6 | 65 | u32 dbck_enable_mask; |
72f83af9 | 66 | bool dbck_enabled; |
77640aab | 67 | struct device *dev; |
d0d665a8 | 68 | bool is_mpuio; |
77640aab | 69 | bool dbck_flag; |
0cde8d03 | 70 | bool loses_context; |
352a2d5b | 71 | bool context_valid; |
5de62b86 | 72 | int stride; |
d5f46247 | 73 | u32 width; |
60a3437d | 74 | int context_loss_count; |
2dc983c5 TKD |
75 | int power_mode; |
76 | bool workaround_enabled; | |
fa87931a KH |
77 | |
78 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60a3437d | 79 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
80 | |
81 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
82 | }; |
83 | ||
129fd223 | 84 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
b1e9fec2 | 85 | #define GPIO_BIT(bank, gpio) (BIT(GPIO_INDEX(bank, gpio))) |
c8eef65a | 86 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 87 | |
fa365e4d | 88 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 89 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 90 | |
a0e827c6 | 91 | static int omap_irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq) |
25db711d | 92 | { |
ede4d7a5 JH |
93 | return bank->chip.base + gpio_irq; |
94 | } | |
95 | ||
a0e827c6 | 96 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 97 | { |
fb655f57 JMC |
98 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
99 | return container_of(chip, struct gpio_bank, chip); | |
25db711d BC |
100 | } |
101 | ||
a0e827c6 JMC |
102 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
103 | int is_input) | |
5e1c5ff4 | 104 | { |
92105bb7 | 105 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
106 | u32 l; |
107 | ||
fa87931a | 108 | reg += bank->regs->direction; |
661553b9 | 109 | l = readl_relaxed(reg); |
5e1c5ff4 | 110 | if (is_input) |
b1e9fec2 | 111 | l |= BIT(gpio); |
5e1c5ff4 | 112 | else |
b1e9fec2 | 113 | l &= ~(BIT(gpio)); |
661553b9 | 114 | writel_relaxed(l, reg); |
41d87cbd | 115 | bank->context.oe = l; |
5e1c5ff4 TL |
116 | } |
117 | ||
fa87931a KH |
118 | |
119 | /* set data out value using dedicate set/clear register */ | |
a0e827c6 JMC |
120 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, |
121 | int enable) | |
5e1c5ff4 | 122 | { |
92105bb7 | 123 | void __iomem *reg = bank->base; |
fa87931a | 124 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 125 | |
2c836f7e | 126 | if (enable) { |
fa87931a | 127 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
128 | bank->context.dataout |= l; |
129 | } else { | |
fa87931a | 130 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
131 | bank->context.dataout &= ~l; |
132 | } | |
5e1c5ff4 | 133 | |
661553b9 | 134 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
135 | } |
136 | ||
fa87931a | 137 | /* set data out value using mask register */ |
a0e827c6 JMC |
138 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, |
139 | int enable) | |
5e1c5ff4 | 140 | { |
fa87931a KH |
141 | void __iomem *reg = bank->base + bank->regs->dataout; |
142 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
143 | u32 l; | |
5e1c5ff4 | 144 | |
661553b9 | 145 | l = readl_relaxed(reg); |
fa87931a KH |
146 | if (enable) |
147 | l |= gpio_bit; | |
148 | else | |
149 | l &= ~gpio_bit; | |
661553b9 | 150 | writel_relaxed(l, reg); |
41d87cbd | 151 | bank->context.dataout = l; |
5e1c5ff4 TL |
152 | } |
153 | ||
a0e827c6 | 154 | static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 155 | { |
fa87931a | 156 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 157 | |
b1e9fec2 | 158 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
5e1c5ff4 | 159 | } |
b37c45b8 | 160 | |
a0e827c6 | 161 | static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 162 | { |
fa87931a | 163 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 164 | |
b1e9fec2 | 165 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
b37c45b8 RQ |
166 | } |
167 | ||
a0e827c6 | 168 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
ece9528e | 169 | { |
661553b9 | 170 | int l = readl_relaxed(base + reg); |
ece9528e | 171 | |
862ff640 | 172 | if (set) |
ece9528e KH |
173 | l |= mask; |
174 | else | |
175 | l &= ~mask; | |
176 | ||
661553b9 | 177 | writel_relaxed(l, base + reg); |
ece9528e | 178 | } |
92105bb7 | 179 | |
a0e827c6 | 180 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
181 | { |
182 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
345477ff | 183 | clk_prepare_enable(bank->dbck); |
72f83af9 | 184 | bank->dbck_enabled = true; |
9e303f22 | 185 | |
661553b9 | 186 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 187 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
188 | } |
189 | } | |
190 | ||
a0e827c6 | 191 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
192 | { |
193 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
194 | /* |
195 | * Disable debounce before cutting it's clock. If debounce is | |
196 | * enabled but the clock is not, GPIO module seems to be unable | |
197 | * to detect events and generate interrupts at least on OMAP3. | |
198 | */ | |
661553b9 | 199 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 200 | |
345477ff | 201 | clk_disable_unprepare(bank->dbck); |
72f83af9 TKD |
202 | bank->dbck_enabled = false; |
203 | } | |
204 | } | |
205 | ||
168ef3d9 | 206 | /** |
a0e827c6 | 207 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 FB |
208 | * @bank: the gpio bank we're acting upon |
209 | * @gpio: the gpio number on this @gpio | |
210 | * @debounce: debounce time to use | |
211 | * | |
212 | * OMAP's debounce time is in 31us steps so we need | |
213 | * to convert and round up to the closest unit. | |
214 | */ | |
a0e827c6 JMC |
215 | static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, |
216 | unsigned debounce) | |
168ef3d9 | 217 | { |
9942da0e | 218 | void __iomem *reg; |
168ef3d9 FB |
219 | u32 val; |
220 | u32 l; | |
221 | ||
77640aab VC |
222 | if (!bank->dbck_flag) |
223 | return; | |
224 | ||
168ef3d9 FB |
225 | if (debounce < 32) |
226 | debounce = 0x01; | |
227 | else if (debounce > 7936) | |
228 | debounce = 0xff; | |
229 | else | |
230 | debounce = (debounce / 0x1f) - 1; | |
231 | ||
129fd223 | 232 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 233 | |
345477ff | 234 | clk_prepare_enable(bank->dbck); |
9942da0e | 235 | reg = bank->base + bank->regs->debounce; |
661553b9 | 236 | writel_relaxed(debounce, reg); |
168ef3d9 | 237 | |
9942da0e | 238 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 239 | val = readl_relaxed(reg); |
168ef3d9 | 240 | |
6fd9c421 | 241 | if (debounce) |
168ef3d9 | 242 | val |= l; |
6fd9c421 | 243 | else |
168ef3d9 | 244 | val &= ~l; |
f7ec0b0b | 245 | bank->dbck_enable_mask = val; |
168ef3d9 | 246 | |
661553b9 | 247 | writel_relaxed(val, reg); |
345477ff | 248 | clk_disable_unprepare(bank->dbck); |
6fd9c421 TKD |
249 | /* |
250 | * Enable debounce clock per module. | |
251 | * This call is mandatory because in omap_gpio_request() when | |
252 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
253 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
254 | * used within _gpio_dbck_enable() is still not initialized at | |
255 | * that point. Therefore we have to enable dbck here. | |
256 | */ | |
a0e827c6 | 257 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
258 | if (bank->dbck_enable_mask) { |
259 | bank->context.debounce = debounce; | |
260 | bank->context.debounce_en = val; | |
261 | } | |
168ef3d9 FB |
262 | } |
263 | ||
c9c55d92 | 264 | /** |
a0e827c6 | 265 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 JH |
266 | * @bank: the gpio bank we're acting upon |
267 | * @gpio: the gpio number on this @gpio | |
268 | * | |
269 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
270 | * this is the only gpio in this bank using debounce, then clear the debounce | |
271 | * time too. The debounce clock will also be disabled when calling this function | |
272 | * if this is the only gpio in the bank using debounce. | |
273 | */ | |
a0e827c6 | 274 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio) |
c9c55d92 JH |
275 | { |
276 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
277 | ||
278 | if (!bank->dbck_flag) | |
279 | return; | |
280 | ||
281 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
282 | return; | |
283 | ||
284 | bank->dbck_enable_mask &= ~gpio_bit; | |
285 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 286 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
287 | bank->base + bank->regs->debounce_en); |
288 | ||
289 | if (!bank->dbck_enable_mask) { | |
290 | bank->context.debounce = 0; | |
661553b9 | 291 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 292 | bank->regs->debounce); |
345477ff | 293 | clk_disable_unprepare(bank->dbck); |
c9c55d92 JH |
294 | bank->dbck_enabled = false; |
295 | } | |
296 | } | |
297 | ||
a0e827c6 | 298 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 299 | unsigned trigger) |
5e1c5ff4 | 300 | { |
3ac4fa99 | 301 | void __iomem *base = bank->base; |
b1e9fec2 | 302 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 303 | |
a0e827c6 JMC |
304 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
305 | trigger & IRQ_TYPE_LEVEL_LOW); | |
306 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
307 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
308 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
309 | trigger & IRQ_TYPE_EDGE_RISING); | |
310 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
311 | trigger & IRQ_TYPE_EDGE_FALLING); | |
5e571f38 | 312 | |
41d87cbd | 313 | bank->context.leveldetect0 = |
661553b9 | 314 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 315 | bank->context.leveldetect1 = |
661553b9 | 316 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 317 | bank->context.risingdetect = |
661553b9 | 318 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 319 | bank->context.fallingdetect = |
661553b9 | 320 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
321 | |
322 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
a0e827c6 | 323 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd | 324 | bank->context.wake_en = |
661553b9 | 325 | readl_relaxed(bank->base + bank->regs->wkup_en); |
41d87cbd | 326 | } |
5e571f38 | 327 | |
55b220ca | 328 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
329 | if (!bank->regs->irqctrl) { |
330 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
331 | if (bank->non_wakeup_gpios) { | |
332 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
333 | goto exit; | |
334 | } | |
335 | ||
699117a6 CW |
336 | /* |
337 | * Log the edge gpio and manually trigger the IRQ | |
338 | * after resume if the input level changes | |
339 | * to avoid irq lost during PER RET/OFF mode | |
340 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
341 | */ | |
342 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
343 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
344 | else | |
345 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
346 | } | |
5eb3bb9c | 347 | |
5e571f38 | 348 | exit: |
9ea14d8c | 349 | bank->level_mask = |
661553b9 VK |
350 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
351 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
352 | } |
353 | ||
9198bcd3 | 354 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
355 | /* |
356 | * This only applies to chips that can't do both rising and falling edge | |
357 | * detection at once. For all other chips, this function is a noop. | |
358 | */ | |
a0e827c6 | 359 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b CM |
360 | { |
361 | void __iomem *reg = bank->base; | |
362 | u32 l = 0; | |
363 | ||
5e571f38 | 364 | if (!bank->regs->irqctrl) |
4318f36b | 365 | return; |
5e571f38 TKD |
366 | |
367 | reg += bank->regs->irqctrl; | |
4318f36b | 368 | |
661553b9 | 369 | l = readl_relaxed(reg); |
4318f36b | 370 | if ((l >> gpio) & 1) |
b1e9fec2 | 371 | l &= ~(BIT(gpio)); |
4318f36b | 372 | else |
b1e9fec2 | 373 | l |= BIT(gpio); |
4318f36b | 374 | |
661553b9 | 375 | writel_relaxed(l, reg); |
4318f36b | 376 | } |
5e571f38 | 377 | #else |
a0e827c6 | 378 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
9198bcd3 | 379 | #endif |
4318f36b | 380 | |
a0e827c6 JMC |
381 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
382 | unsigned trigger) | |
92105bb7 TL |
383 | { |
384 | void __iomem *reg = bank->base; | |
5e571f38 | 385 | void __iomem *base = bank->base; |
92105bb7 | 386 | u32 l = 0; |
5e1c5ff4 | 387 | |
5e571f38 | 388 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 389 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
390 | } else if (bank->regs->irqctrl) { |
391 | reg += bank->regs->irqctrl; | |
392 | ||
661553b9 | 393 | l = readl_relaxed(reg); |
29501577 | 394 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 395 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 396 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 397 | l |= BIT(gpio); |
6cab4860 | 398 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 399 | l &= ~(BIT(gpio)); |
92105bb7 | 400 | else |
5e571f38 TKD |
401 | return -EINVAL; |
402 | ||
661553b9 | 403 | writel_relaxed(l, reg); |
5e571f38 | 404 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 405 | if (gpio & 0x08) |
5e571f38 | 406 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 407 | else |
5e571f38 TKD |
408 | reg += bank->regs->edgectrl1; |
409 | ||
5e1c5ff4 | 410 | gpio &= 0x07; |
661553b9 | 411 | l = readl_relaxed(reg); |
5e1c5ff4 | 412 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 413 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 414 | l |= 2 << (gpio << 1); |
6cab4860 | 415 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 416 | l |= BIT(gpio << 1); |
5e571f38 TKD |
417 | |
418 | /* Enable wake-up during idle for dynamic tick */ | |
a0e827c6 | 419 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 420 | bank->context.wake_en = |
661553b9 VK |
421 | readl_relaxed(bank->base + bank->regs->wkup_en); |
422 | writel_relaxed(l, reg); | |
5e1c5ff4 | 423 | } |
92105bb7 | 424 | return 0; |
5e1c5ff4 TL |
425 | } |
426 | ||
a0e827c6 | 427 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
428 | { |
429 | if (bank->regs->pinctrl) { | |
430 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
431 | ||
432 | /* Claim the pin for MPU */ | |
b1e9fec2 | 433 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
434 | } |
435 | ||
436 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
437 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
438 | u32 ctrl; | |
439 | ||
661553b9 | 440 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
441 | /* Module is enabled, clocks are not gated */ |
442 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 443 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
444 | bank->context.ctrl = ctrl; |
445 | } | |
446 | } | |
447 | ||
a0e827c6 | 448 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
449 | { |
450 | void __iomem *base = bank->base; | |
451 | ||
452 | if (bank->regs->wkup_en && | |
453 | !LINE_USED(bank->mod_usage, offset) && | |
454 | !LINE_USED(bank->irq_usage, offset)) { | |
455 | /* Disable wake-up during idle for dynamic tick */ | |
a0e827c6 | 456 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 457 | bank->context.wake_en = |
661553b9 | 458 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
459 | } |
460 | ||
461 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
462 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
463 | u32 ctrl; | |
464 | ||
661553b9 | 465 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
466 | /* Module is disabled, clocks are gated */ |
467 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 468 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
469 | bank->context.ctrl = ctrl; |
470 | } | |
471 | } | |
472 | ||
a0e827c6 | 473 | static int omap_gpio_is_input(struct gpio_bank *bank, int mask) |
fa365e4d JMC |
474 | { |
475 | void __iomem *reg = bank->base + bank->regs->direction; | |
476 | ||
661553b9 | 477 | return readl_relaxed(reg) & mask; |
fa365e4d JMC |
478 | } |
479 | ||
a0e827c6 | 480 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 481 | { |
a0e827c6 | 482 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
4b25408f | 483 | unsigned gpio = 0; |
92105bb7 | 484 | int retval; |
a6472533 | 485 | unsigned long flags; |
fac7fa16 | 486 | unsigned offset; |
92105bb7 | 487 | |
fac7fa16 JMC |
488 | if (!BANK_USED(bank)) |
489 | pm_runtime_get_sync(bank->dev); | |
8d4c277e | 490 | |
4b25408f TL |
491 | #ifdef CONFIG_ARCH_OMAP1 |
492 | if (d->irq > IH_MPUIO_BASE) | |
e9191028 | 493 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
4b25408f TL |
494 | #endif |
495 | ||
496 | if (!gpio) | |
a0e827c6 | 497 | gpio = omap_irq_to_gpio(bank, d->hwirq); |
5e1c5ff4 | 498 | |
e5c56ed3 | 499 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 500 | return -EINVAL; |
e5c56ed3 | 501 | |
9ea14d8c TKD |
502 | if (!bank->regs->leveldetect0 && |
503 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
504 | return -EINVAL; |
505 | ||
a6472533 | 506 | spin_lock_irqsave(&bank->lock, flags); |
fac7fa16 | 507 | offset = GPIO_INDEX(bank, gpio); |
a0e827c6 | 508 | retval = omap_set_gpio_triggering(bank, offset, type); |
fac7fa16 | 509 | if (!LINE_USED(bank->mod_usage, offset)) { |
a0e827c6 JMC |
510 | omap_enable_gpio_module(bank, offset); |
511 | omap_set_gpio_direction(bank, offset, 1); | |
512 | } else if (!omap_gpio_is_input(bank, BIT(offset))) { | |
fac7fa16 JMC |
513 | spin_unlock_irqrestore(&bank->lock, flags); |
514 | return -EINVAL; | |
515 | } | |
516 | ||
b1e9fec2 | 517 | bank->irq_usage |= BIT(GPIO_INDEX(bank, gpio)); |
a6472533 | 518 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
519 | |
520 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 521 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 522 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 523 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 524 | |
92105bb7 | 525 | return retval; |
5e1c5ff4 TL |
526 | } |
527 | ||
a0e827c6 | 528 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 529 | { |
92105bb7 | 530 | void __iomem *reg = bank->base; |
5e1c5ff4 | 531 | |
eef4bec7 | 532 | reg += bank->regs->irqstatus; |
661553b9 | 533 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
534 | |
535 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
536 | if (bank->regs->irqstatus2) { |
537 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 538 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 539 | } |
bedfd154 RQ |
540 | |
541 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 542 | readl_relaxed(reg); |
5e1c5ff4 TL |
543 | } |
544 | ||
a0e827c6 | 545 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) |
5e1c5ff4 | 546 | { |
a0e827c6 | 547 | omap_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
548 | } |
549 | ||
a0e827c6 | 550 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
551 | { |
552 | void __iomem *reg = bank->base; | |
99c47707 | 553 | u32 l; |
b1e9fec2 | 554 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 555 | |
28f3b5a0 | 556 | reg += bank->regs->irqenable; |
661553b9 | 557 | l = readl_relaxed(reg); |
28f3b5a0 | 558 | if (bank->regs->irqenable_inv) |
99c47707 ID |
559 | l = ~l; |
560 | l &= mask; | |
561 | return l; | |
ea6dedd7 ID |
562 | } |
563 | ||
a0e827c6 | 564 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 565 | { |
92105bb7 | 566 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
567 | u32 l; |
568 | ||
28f3b5a0 KH |
569 | if (bank->regs->set_irqenable) { |
570 | reg += bank->regs->set_irqenable; | |
571 | l = gpio_mask; | |
2a900eb7 | 572 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
573 | } else { |
574 | reg += bank->regs->irqenable; | |
661553b9 | 575 | l = readl_relaxed(reg); |
28f3b5a0 KH |
576 | if (bank->regs->irqenable_inv) |
577 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
578 | else |
579 | l |= gpio_mask; | |
2a900eb7 | 580 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
581 | } |
582 | ||
661553b9 | 583 | writel_relaxed(l, reg); |
28f3b5a0 KH |
584 | } |
585 | ||
a0e827c6 | 586 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
28f3b5a0 KH |
587 | { |
588 | void __iomem *reg = bank->base; | |
589 | u32 l; | |
590 | ||
591 | if (bank->regs->clr_irqenable) { | |
592 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 593 | l = gpio_mask; |
2a900eb7 | 594 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
595 | } else { |
596 | reg += bank->regs->irqenable; | |
661553b9 | 597 | l = readl_relaxed(reg); |
28f3b5a0 | 598 | if (bank->regs->irqenable_inv) |
56739a69 | 599 | l |= gpio_mask; |
92105bb7 | 600 | else |
28f3b5a0 | 601 | l &= ~gpio_mask; |
2a900eb7 | 602 | bank->context.irqenable1 = l; |
5e1c5ff4 | 603 | } |
28f3b5a0 | 604 | |
661553b9 | 605 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
606 | } |
607 | ||
a0e827c6 JMC |
608 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, int gpio, |
609 | int enable) | |
5e1c5ff4 | 610 | { |
8276536c | 611 | if (enable) |
a0e827c6 | 612 | omap_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
8276536c | 613 | else |
a0e827c6 | 614 | omap_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
615 | } |
616 | ||
92105bb7 TL |
617 | /* |
618 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
619 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
620 | * to the target, system will wake up always on GPIO events. While | |
621 | * system is running all registered GPIO interrupts need to have wake-up | |
622 | * enabled. When system is suspended, only selected GPIO interrupts need | |
623 | * to have wake-up enabled. | |
624 | */ | |
a0e827c6 | 625 | static int omap_set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) |
92105bb7 | 626 | { |
f64ad1a0 KH |
627 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
628 | unsigned long flags; | |
a6472533 | 629 | |
f64ad1a0 | 630 | if (bank->non_wakeup_gpios & gpio_bit) { |
862ff640 | 631 | dev_err(bank->dev, |
f64ad1a0 | 632 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); |
92105bb7 TL |
633 | return -EINVAL; |
634 | } | |
f64ad1a0 KH |
635 | |
636 | spin_lock_irqsave(&bank->lock, flags); | |
637 | if (enable) | |
0aa27273 | 638 | bank->context.wake_en |= gpio_bit; |
f64ad1a0 | 639 | else |
0aa27273 | 640 | bank->context.wake_en &= ~gpio_bit; |
f64ad1a0 | 641 | |
661553b9 | 642 | writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en); |
f64ad1a0 KH |
643 | spin_unlock_irqrestore(&bank->lock, flags); |
644 | ||
645 | return 0; | |
92105bb7 TL |
646 | } |
647 | ||
a0e827c6 | 648 | static void omap_reset_gpio(struct gpio_bank *bank, int gpio) |
4196dd6b | 649 | { |
a0e827c6 JMC |
650 | omap_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
651 | omap_set_gpio_irqenable(bank, gpio, 0); | |
652 | omap_clear_gpio_irqstatus(bank, gpio); | |
653 | omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); | |
654 | omap_clear_gpio_debounce(bank, gpio); | |
4196dd6b TL |
655 | } |
656 | ||
92105bb7 | 657 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
a0e827c6 | 658 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 659 | { |
a0e827c6 JMC |
660 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
661 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); | |
92105bb7 | 662 | |
a0e827c6 | 663 | return omap_set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
664 | } |
665 | ||
3ff164e1 | 666 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 667 | { |
3ff164e1 | 668 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 669 | unsigned long flags; |
52e31344 | 670 | |
55b93c32 TKD |
671 | /* |
672 | * If this is the first gpio_request for the bank, | |
673 | * enable the bank module. | |
674 | */ | |
fa365e4d | 675 | if (!BANK_USED(bank)) |
55b93c32 | 676 | pm_runtime_get_sync(bank->dev); |
92105bb7 | 677 | |
55b93c32 | 678 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 679 | /* Set trigger to none. You need to enable the desired trigger with |
fac7fa16 JMC |
680 | * request_irq() or set_irq_type(). Only do this if the IRQ line has |
681 | * not already been requested. | |
4196dd6b | 682 | */ |
fac7fa16 | 683 | if (!LINE_USED(bank->irq_usage, offset)) { |
a0e827c6 JMC |
684 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
685 | omap_enable_gpio_module(bank, offset); | |
5e1c5ff4 | 686 | } |
b1e9fec2 | 687 | bank->mod_usage |= BIT(offset); |
a6472533 | 688 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
689 | |
690 | return 0; | |
691 | } | |
692 | ||
3ff164e1 | 693 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 694 | { |
3ff164e1 | 695 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 696 | unsigned long flags; |
5e1c5ff4 | 697 | |
a6472533 | 698 | spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 699 | bank->mod_usage &= ~(BIT(offset)); |
a0e827c6 JMC |
700 | omap_disable_gpio_module(bank, offset); |
701 | omap_reset_gpio(bank, bank->chip.base + offset); | |
a6472533 | 702 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
703 | |
704 | /* | |
705 | * If this is the last gpio to be freed in the bank, | |
706 | * disable the bank module. | |
707 | */ | |
fa365e4d | 708 | if (!BANK_USED(bank)) |
55b93c32 | 709 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
710 | } |
711 | ||
712 | /* | |
713 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
714 | * avoid missing GPIO interrupts for other lines in the bank. | |
715 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
716 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
717 | * If we wait to unmask individual GPIO lines in the bank after the | |
718 | * line's interrupt handler has been run, we may miss some nested | |
719 | * interrupts. | |
720 | */ | |
a0e827c6 | 721 | static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 722 | { |
92105bb7 | 723 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 724 | u32 isr; |
3513cdec | 725 | unsigned int bit; |
5e1c5ff4 | 726 | struct gpio_bank *bank; |
ea6dedd7 | 727 | int unmasked = 0; |
fb655f57 JMC |
728 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
729 | struct gpio_chip *chip = irq_get_handler_data(irq); | |
5e1c5ff4 | 730 | |
fb655f57 | 731 | chained_irq_enter(irqchip, desc); |
5e1c5ff4 | 732 | |
fb655f57 | 733 | bank = container_of(chip, struct gpio_bank, chip); |
eef4bec7 | 734 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 735 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
736 | |
737 | if (WARN_ON(!isr_reg)) | |
738 | goto exit; | |
739 | ||
e83507b7 | 740 | while (1) { |
6e60e79a | 741 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 742 | u32 enabled; |
6e60e79a | 743 | |
a0e827c6 | 744 | enabled = omap_get_gpio_irqbank_mask(bank); |
661553b9 | 745 | isr_saved = isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 746 | |
9ea14d8c | 747 | if (bank->level_mask) |
b144ff6f | 748 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
749 | |
750 | /* clear edge sensitive interrupts before handler(s) are | |
751 | called so that we don't miss any interrupt occurred while | |
752 | executing them */ | |
a0e827c6 JMC |
753 | omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
754 | omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
755 | omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask); | |
6e60e79a TL |
756 | |
757 | /* if there is only edge sensitive GPIO pin interrupts | |
758 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
759 | if (!level_mask && !unmasked) { |
760 | unmasked = 1; | |
fb655f57 | 761 | chained_irq_exit(irqchip, desc); |
ea6dedd7 | 762 | } |
92105bb7 TL |
763 | |
764 | if (!isr) | |
765 | break; | |
766 | ||
3513cdec JH |
767 | while (isr) { |
768 | bit = __ffs(isr); | |
b1e9fec2 | 769 | isr &= ~(BIT(bit)); |
25db711d | 770 | |
4318f36b CM |
771 | /* |
772 | * Some chips can't respond to both rising and falling | |
773 | * at the same time. If this irq was requested with | |
774 | * both flags, we need to flip the ICR data for the IRQ | |
775 | * to respond to the IRQ for the opposite direction. | |
776 | * This will be indicated in the bank toggle_mask. | |
777 | */ | |
b1e9fec2 | 778 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 779 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 780 | |
fb655f57 JMC |
781 | generic_handle_irq(irq_find_mapping(bank->chip.irqdomain, |
782 | bit)); | |
92105bb7 | 783 | } |
1a8bfa1e | 784 | } |
ea6dedd7 ID |
785 | /* if bank has any level sensitive GPIO pin interrupt |
786 | configured, we must unmask the bank interrupt only after | |
787 | handler(s) are executed in order to avoid spurious bank | |
788 | interrupt */ | |
b1cc4c55 | 789 | exit: |
ea6dedd7 | 790 | if (!unmasked) |
fb655f57 | 791 | chained_irq_exit(irqchip, desc); |
55b93c32 | 792 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
793 | } |
794 | ||
a0e827c6 | 795 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 796 | { |
a0e827c6 JMC |
797 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
798 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); | |
85ec7b97 | 799 | unsigned long flags; |
fa365e4d | 800 | unsigned offset = GPIO_INDEX(bank, gpio); |
4196dd6b | 801 | |
85ec7b97 | 802 | spin_lock_irqsave(&bank->lock, flags); |
e3a2e878 | 803 | gpiochip_unlock_as_irq(&bank->chip, offset); |
b1e9fec2 | 804 | bank->irq_usage &= ~(BIT(offset)); |
a0e827c6 JMC |
805 | omap_disable_gpio_module(bank, offset); |
806 | omap_reset_gpio(bank, gpio); | |
85ec7b97 | 807 | spin_unlock_irqrestore(&bank->lock, flags); |
fac7fa16 JMC |
808 | |
809 | /* | |
810 | * If this is the last IRQ to be freed in the bank, | |
811 | * disable the bank module. | |
812 | */ | |
813 | if (!BANK_USED(bank)) | |
814 | pm_runtime_put(bank->dev); | |
4196dd6b TL |
815 | } |
816 | ||
a0e827c6 | 817 | static void omap_gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 818 | { |
a0e827c6 JMC |
819 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
820 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); | |
5e1c5ff4 | 821 | |
a0e827c6 | 822 | omap_clear_gpio_irqstatus(bank, gpio); |
5e1c5ff4 TL |
823 | } |
824 | ||
a0e827c6 | 825 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 826 | { |
a0e827c6 JMC |
827 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
828 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); | |
85ec7b97 | 829 | unsigned long flags; |
5e1c5ff4 | 830 | |
85ec7b97 | 831 | spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 JMC |
832 | omap_set_gpio_irqenable(bank, gpio, 0); |
833 | omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); | |
85ec7b97 | 834 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
835 | } |
836 | ||
a0e827c6 | 837 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 838 | { |
a0e827c6 JMC |
839 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
840 | unsigned int gpio = omap_irq_to_gpio(bank, d->hwirq); | |
129fd223 | 841 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 842 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 843 | unsigned long flags; |
55b6019a | 844 | |
85ec7b97 | 845 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 846 | if (trigger) |
a0e827c6 | 847 | omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
848 | |
849 | /* For level-triggered GPIOs, the clearing must be done after | |
850 | * the HW source is cleared, thus after the handler has run */ | |
851 | if (bank->level_mask & irq_mask) { | |
a0e827c6 JMC |
852 | omap_set_gpio_irqenable(bank, gpio, 0); |
853 | omap_clear_gpio_irqstatus(bank, gpio); | |
b144ff6f | 854 | } |
5e1c5ff4 | 855 | |
a0e827c6 | 856 | omap_set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 857 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
858 | } |
859 | ||
e5c56ed3 DB |
860 | /*---------------------------------------------------------------------*/ |
861 | ||
79ee031f | 862 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 863 | { |
79ee031f | 864 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 865 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
866 | void __iomem *mask_reg = bank->base + |
867 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 868 | unsigned long flags; |
11a78b79 | 869 | |
a6472533 | 870 | spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 871 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
a6472533 | 872 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
873 | |
874 | return 0; | |
875 | } | |
876 | ||
79ee031f | 877 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 878 | { |
79ee031f | 879 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 880 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
881 | void __iomem *mask_reg = bank->base + |
882 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 883 | unsigned long flags; |
11a78b79 | 884 | |
a6472533 | 885 | spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 886 | writel_relaxed(bank->context.wake_en, mask_reg); |
a6472533 | 887 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
888 | |
889 | return 0; | |
890 | } | |
891 | ||
47145210 | 892 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
893 | .suspend_noirq = omap_mpuio_suspend_noirq, |
894 | .resume_noirq = omap_mpuio_resume_noirq, | |
895 | }; | |
896 | ||
3c437ffd | 897 | /* use platform_driver for this. */ |
11a78b79 | 898 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
899 | .driver = { |
900 | .name = "mpuio", | |
79ee031f | 901 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
902 | }, |
903 | }; | |
904 | ||
905 | static struct platform_device omap_mpuio_device = { | |
906 | .name = "mpuio", | |
907 | .id = -1, | |
908 | .dev = { | |
909 | .driver = &omap_mpuio_driver.driver, | |
910 | } | |
911 | /* could list the /proc/iomem resources */ | |
912 | }; | |
913 | ||
a0e827c6 | 914 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 915 | { |
77640aab | 916 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 917 | |
11a78b79 DB |
918 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
919 | (void) platform_device_register(&omap_mpuio_device); | |
920 | } | |
921 | ||
e5c56ed3 | 922 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 923 | |
a0e827c6 | 924 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e YY |
925 | { |
926 | struct gpio_bank *bank; | |
927 | unsigned long flags; | |
928 | void __iomem *reg; | |
929 | int dir; | |
930 | ||
931 | bank = container_of(chip, struct gpio_bank, chip); | |
932 | reg = bank->base + bank->regs->direction; | |
933 | spin_lock_irqsave(&bank->lock, flags); | |
934 | dir = !!(readl_relaxed(reg) & BIT(offset)); | |
935 | spin_unlock_irqrestore(&bank->lock, flags); | |
936 | return dir; | |
937 | } | |
938 | ||
a0e827c6 | 939 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
940 | { |
941 | struct gpio_bank *bank; | |
942 | unsigned long flags; | |
943 | ||
944 | bank = container_of(chip, struct gpio_bank, chip); | |
945 | spin_lock_irqsave(&bank->lock, flags); | |
a0e827c6 | 946 | omap_set_gpio_direction(bank, offset, 1); |
52e31344 DB |
947 | spin_unlock_irqrestore(&bank->lock, flags); |
948 | return 0; | |
949 | } | |
950 | ||
a0e827c6 | 951 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 952 | { |
b37c45b8 | 953 | struct gpio_bank *bank; |
b37c45b8 RQ |
954 | u32 mask; |
955 | ||
a8be8daf | 956 | bank = container_of(chip, struct gpio_bank, chip); |
b1e9fec2 | 957 | mask = (BIT(offset)); |
b37c45b8 | 958 | |
a0e827c6 JMC |
959 | if (omap_gpio_is_input(bank, mask)) |
960 | return omap_get_gpio_datain(bank, offset); | |
b37c45b8 | 961 | else |
a0e827c6 | 962 | return omap_get_gpio_dataout(bank, offset); |
52e31344 DB |
963 | } |
964 | ||
a0e827c6 | 965 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
966 | { |
967 | struct gpio_bank *bank; | |
968 | unsigned long flags; | |
969 | ||
970 | bank = container_of(chip, struct gpio_bank, chip); | |
971 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 972 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 973 | omap_set_gpio_direction(bank, offset, 0); |
52e31344 | 974 | spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 975 | return 0; |
52e31344 DB |
976 | } |
977 | ||
a0e827c6 JMC |
978 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
979 | unsigned debounce) | |
168ef3d9 FB |
980 | { |
981 | struct gpio_bank *bank; | |
982 | unsigned long flags; | |
983 | ||
984 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab | 985 | |
168ef3d9 | 986 | spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 987 | omap2_set_gpio_debounce(bank, offset, debounce); |
168ef3d9 FB |
988 | spin_unlock_irqrestore(&bank->lock, flags); |
989 | ||
990 | return 0; | |
991 | } | |
992 | ||
a0e827c6 | 993 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
994 | { |
995 | struct gpio_bank *bank; | |
996 | unsigned long flags; | |
997 | ||
998 | bank = container_of(chip, struct gpio_bank, chip); | |
999 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 1000 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
1001 | spin_unlock_irqrestore(&bank->lock, flags); |
1002 | } | |
1003 | ||
1004 | /*---------------------------------------------------------------------*/ | |
1005 | ||
9a748053 | 1006 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1007 | { |
e5ff4440 | 1008 | static bool called; |
9f7065da TL |
1009 | u32 rev; |
1010 | ||
e5ff4440 | 1011 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1012 | return; |
1013 | ||
661553b9 | 1014 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1015 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1016 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1017 | |
1018 | called = true; | |
9f7065da TL |
1019 | } |
1020 | ||
03e128ca | 1021 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1022 | { |
ab985f0f TKD |
1023 | void __iomem *base = bank->base; |
1024 | u32 l = 0xffffffff; | |
2fae7fbe | 1025 | |
ab985f0f TKD |
1026 | if (bank->width == 16) |
1027 | l = 0xffff; | |
1028 | ||
d0d665a8 | 1029 | if (bank->is_mpuio) { |
661553b9 | 1030 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1031 | return; |
2fae7fbe | 1032 | } |
ab985f0f | 1033 | |
a0e827c6 JMC |
1034 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1035 | bank->regs->irqenable_inv); | |
1036 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | |
1037 | !bank->regs->irqenable_inv); | |
ab985f0f | 1038 | if (bank->regs->debounce_en) |
661553b9 | 1039 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1040 | |
2dc983c5 | 1041 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1042 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1043 | /* Initialize interface clk ungated, module enabled */ |
1044 | if (bank->regs->ctrl) | |
661553b9 | 1045 | writel_relaxed(0, base + bank->regs->ctrl); |
34672013 TKD |
1046 | |
1047 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1048 | if (IS_ERR(bank->dbck)) | |
1049 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
2fae7fbe VC |
1050 | } |
1051 | ||
3836309d | 1052 | static void |
f8b46b58 KH |
1053 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, |
1054 | unsigned int num) | |
1055 | { | |
1056 | struct irq_chip_generic *gc; | |
1057 | struct irq_chip_type *ct; | |
1058 | ||
1059 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
1060 | handle_simple_irq); | |
83233749 TP |
1061 | if (!gc) { |
1062 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
1063 | return; | |
1064 | } | |
1065 | ||
f8b46b58 KH |
1066 | ct = gc->chip_types; |
1067 | ||
1068 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
1069 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
1070 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
a0e827c6 | 1071 | ct->chip.irq_set_type = omap_gpio_irq_type; |
6ed87c5b TKD |
1072 | |
1073 | if (bank->regs->wkup_en) | |
a0e827c6 | 1074 | ct->chip.irq_set_wake = omap_gpio_wake_enable; |
f8b46b58 KH |
1075 | |
1076 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
1077 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
1078 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
1079 | } | |
1080 | ||
46824e22 | 1081 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 1082 | { |
77640aab | 1083 | int j; |
2fae7fbe | 1084 | static int gpio; |
fb655f57 | 1085 | int irq_base = 0; |
6ef7f385 | 1086 | int ret; |
2fae7fbe | 1087 | |
2fae7fbe VC |
1088 | /* |
1089 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1090 | * over to the generic ones | |
1091 | */ | |
1092 | bank->chip.request = omap_gpio_request; | |
1093 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1094 | bank->chip.get_direction = omap_gpio_get_direction; |
1095 | bank->chip.direction_input = omap_gpio_input; | |
1096 | bank->chip.get = omap_gpio_get; | |
1097 | bank->chip.direction_output = omap_gpio_output; | |
1098 | bank->chip.set_debounce = omap_gpio_debounce; | |
1099 | bank->chip.set = omap_gpio_set; | |
d0d665a8 | 1100 | if (bank->is_mpuio) { |
2fae7fbe | 1101 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
1102 | if (bank->regs->wkup_en) |
1103 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
1104 | bank->chip.base = OMAP_MPUIO(0); |
1105 | } else { | |
1106 | bank->chip.label = "gpio"; | |
1107 | bank->chip.base = gpio; | |
d5f46247 | 1108 | gpio += bank->width; |
2fae7fbe | 1109 | } |
d5f46247 | 1110 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1111 | |
6ef7f385 JMC |
1112 | ret = gpiochip_add(&bank->chip); |
1113 | if (ret) { | |
fb655f57 | 1114 | dev_err(bank->dev, "Could not register gpio chip %d\n", ret); |
6ef7f385 JMC |
1115 | return ret; |
1116 | } | |
2fae7fbe | 1117 | |
fb655f57 JMC |
1118 | #ifdef CONFIG_ARCH_OMAP1 |
1119 | /* | |
1120 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1121 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1122 | */ | |
1123 | irq_base = irq_alloc_descs(-1, 0, bank->width, 0); | |
1124 | if (irq_base < 0) { | |
1125 | dev_err(bank->dev, "Couldn't allocate IRQ numbers\n"); | |
1126 | return -ENODEV; | |
1127 | } | |
1128 | #endif | |
1129 | ||
46824e22 | 1130 | ret = gpiochip_irqchip_add(&bank->chip, irqc, |
a0e827c6 | 1131 | irq_base, omap_gpio_irq_handler, |
fb655f57 JMC |
1132 | IRQ_TYPE_NONE); |
1133 | ||
1134 | if (ret) { | |
1135 | dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret); | |
da26d5d8 | 1136 | gpiochip_remove(&bank->chip); |
fb655f57 JMC |
1137 | return -ENODEV; |
1138 | } | |
1139 | ||
46824e22 | 1140 | gpiochip_set_chained_irqchip(&bank->chip, irqc, |
a0e827c6 | 1141 | bank->irq, omap_gpio_irq_handler); |
fb655f57 | 1142 | |
ede4d7a5 | 1143 | for (j = 0; j < bank->width; j++) { |
fb655f57 | 1144 | int irq = irq_find_mapping(bank->chip.irqdomain, j); |
d0d665a8 | 1145 | if (bank->is_mpuio) { |
ede4d7a5 | 1146 | omap_mpuio_alloc_gc(bank, irq, bank->width); |
fb655f57 JMC |
1147 | irq_set_chip_and_handler(irq, NULL, NULL); |
1148 | set_irq_flags(irq, 0); | |
f8b46b58 | 1149 | } |
2fae7fbe | 1150 | } |
fb655f57 JMC |
1151 | |
1152 | return 0; | |
2fae7fbe VC |
1153 | } |
1154 | ||
384ebe1c BC |
1155 | static const struct of_device_id omap_gpio_match[]; |
1156 | ||
3836309d | 1157 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1158 | { |
862ff640 | 1159 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1160 | struct device_node *node = dev->of_node; |
1161 | const struct of_device_id *match; | |
f6817a2c | 1162 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1163 | struct resource *res; |
5e1c5ff4 | 1164 | struct gpio_bank *bank; |
46824e22 | 1165 | struct irq_chip *irqc; |
6ef7f385 | 1166 | int ret; |
5e1c5ff4 | 1167 | |
384ebe1c BC |
1168 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1169 | ||
e56aee18 | 1170 | pdata = match ? match->data : dev_get_platdata(dev); |
384ebe1c | 1171 | if (!pdata) |
96751fcb | 1172 | return -EINVAL; |
5492fb1a | 1173 | |
086d585f | 1174 | bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL); |
03e128ca | 1175 | if (!bank) { |
862ff640 | 1176 | dev_err(dev, "Memory alloc failed\n"); |
96751fcb | 1177 | return -ENOMEM; |
03e128ca | 1178 | } |
92105bb7 | 1179 | |
46824e22 NM |
1180 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); |
1181 | if (!irqc) | |
1182 | return -ENOMEM; | |
1183 | ||
1184 | irqc->irq_shutdown = omap_gpio_irq_shutdown, | |
1185 | irqc->irq_ack = omap_gpio_ack_irq, | |
1186 | irqc->irq_mask = omap_gpio_mask_irq, | |
1187 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1188 | irqc->irq_set_type = omap_gpio_irq_type, | |
1189 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
1190 | irqc->name = dev_name(&pdev->dev); | |
1191 | ||
77640aab VC |
1192 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1193 | if (unlikely(!res)) { | |
862ff640 | 1194 | dev_err(dev, "Invalid IRQ resource\n"); |
96751fcb | 1195 | return -ENODEV; |
44169075 | 1196 | } |
5e1c5ff4 | 1197 | |
77640aab | 1198 | bank->irq = res->start; |
862ff640 | 1199 | bank->dev = dev; |
fb655f57 | 1200 | bank->chip.dev = dev; |
77640aab | 1201 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1202 | bank->stride = pdata->bank_stride; |
d5f46247 | 1203 | bank->width = pdata->bank_width; |
d0d665a8 | 1204 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1205 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1206 | bank->regs = pdata->regs; |
384ebe1c BC |
1207 | #ifdef CONFIG_OF_GPIO |
1208 | bank->chip.of_node = of_node_get(node); | |
1209 | #endif | |
a2797bea JH |
1210 | if (node) { |
1211 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1212 | bank->loses_context = true; | |
1213 | } else { | |
1214 | bank->loses_context = pdata->loses_context; | |
352a2d5b JH |
1215 | |
1216 | if (bank->loses_context) | |
1217 | bank->get_context_loss_count = | |
1218 | pdata->get_context_loss_count; | |
384ebe1c BC |
1219 | } |
1220 | ||
fa87931a | 1221 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
a0e827c6 | 1222 | bank->set_dataout = omap_set_gpio_dataout_reg; |
fa87931a | 1223 | else |
a0e827c6 | 1224 | bank->set_dataout = omap_set_gpio_dataout_mask; |
9f7065da | 1225 | |
77640aab | 1226 | spin_lock_init(&bank->lock); |
9f7065da | 1227 | |
77640aab VC |
1228 | /* Static mapping, never released */ |
1229 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
717f70e3 JH |
1230 | bank->base = devm_ioremap_resource(dev, res); |
1231 | if (IS_ERR(bank->base)) { | |
fb655f57 | 1232 | irq_domain_remove(bank->chip.irqdomain); |
717f70e3 | 1233 | return PTR_ERR(bank->base); |
5e1c5ff4 TL |
1234 | } |
1235 | ||
065cd795 TKD |
1236 | platform_set_drvdata(pdev, bank); |
1237 | ||
77640aab | 1238 | pm_runtime_enable(bank->dev); |
55b93c32 | 1239 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1240 | pm_runtime_get_sync(bank->dev); |
1241 | ||
d0d665a8 | 1242 | if (bank->is_mpuio) |
a0e827c6 | 1243 | omap_mpuio_init(bank); |
ab985f0f | 1244 | |
03e128ca | 1245 | omap_gpio_mod_init(bank); |
6ef7f385 | 1246 | |
46824e22 | 1247 | ret = omap_gpio_chip_init(bank, irqc); |
6ef7f385 JMC |
1248 | if (ret) |
1249 | return ret; | |
1250 | ||
9a748053 | 1251 | omap_gpio_show_rev(bank); |
9f7065da | 1252 | |
55b93c32 TKD |
1253 | pm_runtime_put(bank->dev); |
1254 | ||
03e128ca | 1255 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1256 | |
879fe324 | 1257 | return 0; |
5e1c5ff4 TL |
1258 | } |
1259 | ||
55b93c32 TKD |
1260 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1261 | ||
ecb2312f | 1262 | #if defined(CONFIG_PM) |
60a3437d | 1263 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1264 | |
2dc983c5 | 1265 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1266 | { |
2dc983c5 TKD |
1267 | struct platform_device *pdev = to_platform_device(dev); |
1268 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1269 | u32 l1 = 0, l2 = 0; | |
1270 | unsigned long flags; | |
68942edb | 1271 | u32 wake_low, wake_hi; |
8865b9b6 | 1272 | |
2dc983c5 | 1273 | spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1274 | |
1275 | /* | |
1276 | * Only edges can generate a wakeup event to the PRCM. | |
1277 | * | |
1278 | * Therefore, ensure any wake-up capable GPIOs have | |
1279 | * edge-detection enabled before going idle to ensure a wakeup | |
1280 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1281 | * NDA TRM 25.5.3.1) | |
1282 | * | |
1283 | * The normal values will be restored upon ->runtime_resume() | |
1284 | * by writing back the values saved in bank->context. | |
1285 | */ | |
1286 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1287 | if (wake_low) | |
661553b9 | 1288 | writel_relaxed(wake_low | bank->context.fallingdetect, |
68942edb KH |
1289 | bank->base + bank->regs->fallingdetect); |
1290 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1291 | if (wake_hi) | |
661553b9 | 1292 | writel_relaxed(wake_hi | bank->context.risingdetect, |
68942edb KH |
1293 | bank->base + bank->regs->risingdetect); |
1294 | ||
b3c64bc3 KH |
1295 | if (!bank->enabled_non_wakeup_gpios) |
1296 | goto update_gpio_context_count; | |
1297 | ||
2dc983c5 TKD |
1298 | if (bank->power_mode != OFF_MODE) { |
1299 | bank->power_mode = 0; | |
41d87cbd | 1300 | goto update_gpio_context_count; |
2dc983c5 TKD |
1301 | } |
1302 | /* | |
1303 | * If going to OFF, remove triggering for all | |
1304 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1305 | * generated. See OMAP2420 Errata item 1.101. | |
1306 | */ | |
661553b9 | 1307 | bank->saved_datain = readl_relaxed(bank->base + |
2dc983c5 | 1308 | bank->regs->datain); |
c6f31c9e TKD |
1309 | l1 = bank->context.fallingdetect; |
1310 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1311 | |
2dc983c5 TKD |
1312 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1313 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1314 | |
661553b9 VK |
1315 | writel_relaxed(l1, bank->base + bank->regs->fallingdetect); |
1316 | writel_relaxed(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1317 | |
2dc983c5 | 1318 | bank->workaround_enabled = true; |
3f1686a9 | 1319 | |
41d87cbd | 1320 | update_gpio_context_count: |
2dc983c5 TKD |
1321 | if (bank->get_context_loss_count) |
1322 | bank->context_loss_count = | |
60a3437d TKD |
1323 | bank->get_context_loss_count(bank->dev); |
1324 | ||
a0e827c6 | 1325 | omap_gpio_dbck_disable(bank); |
2dc983c5 | 1326 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1327 | |
2dc983c5 | 1328 | return 0; |
3ac4fa99 JY |
1329 | } |
1330 | ||
352a2d5b JH |
1331 | static void omap_gpio_init_context(struct gpio_bank *p); |
1332 | ||
2dc983c5 | 1333 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1334 | { |
2dc983c5 TKD |
1335 | struct platform_device *pdev = to_platform_device(dev); |
1336 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
2dc983c5 TKD |
1337 | u32 l = 0, gen, gen0, gen1; |
1338 | unsigned long flags; | |
a2797bea | 1339 | int c; |
8865b9b6 | 1340 | |
2dc983c5 | 1341 | spin_lock_irqsave(&bank->lock, flags); |
352a2d5b JH |
1342 | |
1343 | /* | |
1344 | * On the first resume during the probe, the context has not | |
1345 | * been initialised and so initialise it now. Also initialise | |
1346 | * the context loss count. | |
1347 | */ | |
1348 | if (bank->loses_context && !bank->context_valid) { | |
1349 | omap_gpio_init_context(bank); | |
1350 | ||
1351 | if (bank->get_context_loss_count) | |
1352 | bank->context_loss_count = | |
1353 | bank->get_context_loss_count(bank->dev); | |
1354 | } | |
1355 | ||
a0e827c6 | 1356 | omap_gpio_dbck_enable(bank); |
68942edb KH |
1357 | |
1358 | /* | |
1359 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1360 | * GPIOs were set to edge trigger also in order to be able to | |
1361 | * generate a PRCM wakeup. Here we restore the | |
1362 | * pre-runtime_suspend() values for edge triggering. | |
1363 | */ | |
661553b9 | 1364 | writel_relaxed(bank->context.fallingdetect, |
68942edb | 1365 | bank->base + bank->regs->fallingdetect); |
661553b9 | 1366 | writel_relaxed(bank->context.risingdetect, |
68942edb KH |
1367 | bank->base + bank->regs->risingdetect); |
1368 | ||
a2797bea JH |
1369 | if (bank->loses_context) { |
1370 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1371 | omap_gpio_restore_context(bank); |
1372 | } else { | |
a2797bea JH |
1373 | c = bank->get_context_loss_count(bank->dev); |
1374 | if (c != bank->context_loss_count) { | |
1375 | omap_gpio_restore_context(bank); | |
1376 | } else { | |
1377 | spin_unlock_irqrestore(&bank->lock, flags); | |
1378 | return 0; | |
1379 | } | |
60a3437d | 1380 | } |
2dc983c5 | 1381 | } |
43ffcd9a | 1382 | |
1b128703 TKD |
1383 | if (!bank->workaround_enabled) { |
1384 | spin_unlock_irqrestore(&bank->lock, flags); | |
1385 | return 0; | |
1386 | } | |
1387 | ||
661553b9 | 1388 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1389 | |
2dc983c5 TKD |
1390 | /* |
1391 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1392 | * state. If so, generate an IRQ by software. This is | |
1393 | * horribly racy, but it's the best we can do to work around | |
1394 | * this silicon bug. | |
1395 | */ | |
1396 | l ^= bank->saved_datain; | |
1397 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1398 | |
2dc983c5 TKD |
1399 | /* |
1400 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1401 | * configured with falling edge only; and vice versa. | |
1402 | */ | |
c6f31c9e | 1403 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1404 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1405 | |
c6f31c9e | 1406 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1407 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1408 | |
2dc983c5 | 1409 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1410 | gen = l & (~(bank->context.fallingdetect) & |
1411 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1412 | /* Consider all GPIO IRQs needed to be updated */ |
1413 | gen |= gen0 | gen1; | |
82dbb9d3 | 1414 | |
2dc983c5 TKD |
1415 | if (gen) { |
1416 | u32 old0, old1; | |
82dbb9d3 | 1417 | |
661553b9 VK |
1418 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1419 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1420 | |
4e962e89 | 1421 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1422 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1423 | bank->regs->leveldetect0); |
661553b9 | 1424 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1425 | bank->regs->leveldetect1); |
2dc983c5 | 1426 | } |
9ea14d8c | 1427 | |
4e962e89 | 1428 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1429 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1430 | bank->regs->leveldetect0); |
661553b9 | 1431 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1432 | bank->regs->leveldetect1); |
3ac4fa99 | 1433 | } |
661553b9 VK |
1434 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1435 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 TKD |
1436 | } |
1437 | ||
1438 | bank->workaround_enabled = false; | |
1439 | spin_unlock_irqrestore(&bank->lock, flags); | |
1440 | ||
1441 | return 0; | |
1442 | } | |
ecb2312f | 1443 | #endif /* CONFIG_PM */ |
2dc983c5 TKD |
1444 | |
1445 | void omap2_gpio_prepare_for_idle(int pwr_mode) | |
1446 | { | |
1447 | struct gpio_bank *bank; | |
1448 | ||
1449 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1450 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1451 | continue; |
1452 | ||
1453 | bank->power_mode = pwr_mode; | |
1454 | ||
2dc983c5 TKD |
1455 | pm_runtime_put_sync_suspend(bank->dev); |
1456 | } | |
1457 | } | |
1458 | ||
1459 | void omap2_gpio_resume_after_idle(void) | |
1460 | { | |
1461 | struct gpio_bank *bank; | |
1462 | ||
1463 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1464 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1465 | continue; |
1466 | ||
2dc983c5 | 1467 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1468 | } |
3ac4fa99 JY |
1469 | } |
1470 | ||
ecb2312f | 1471 | #if defined(CONFIG_PM) |
352a2d5b JH |
1472 | static void omap_gpio_init_context(struct gpio_bank *p) |
1473 | { | |
1474 | struct omap_gpio_reg_offs *regs = p->regs; | |
1475 | void __iomem *base = p->base; | |
1476 | ||
661553b9 VK |
1477 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1478 | p->context.oe = readl_relaxed(base + regs->direction); | |
1479 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1480 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1481 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1482 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1483 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1484 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1485 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
352a2d5b JH |
1486 | |
1487 | if (regs->set_dataout && p->regs->clr_dataout) | |
661553b9 | 1488 | p->context.dataout = readl_relaxed(base + regs->set_dataout); |
352a2d5b | 1489 | else |
661553b9 | 1490 | p->context.dataout = readl_relaxed(base + regs->dataout); |
352a2d5b JH |
1491 | |
1492 | p->context_valid = true; | |
1493 | } | |
1494 | ||
60a3437d | 1495 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1496 | { |
661553b9 | 1497 | writel_relaxed(bank->context.wake_en, |
ae10f233 | 1498 | bank->base + bank->regs->wkup_en); |
661553b9 VK |
1499 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); |
1500 | writel_relaxed(bank->context.leveldetect0, | |
ae10f233 | 1501 | bank->base + bank->regs->leveldetect0); |
661553b9 | 1502 | writel_relaxed(bank->context.leveldetect1, |
ae10f233 | 1503 | bank->base + bank->regs->leveldetect1); |
661553b9 | 1504 | writel_relaxed(bank->context.risingdetect, |
ae10f233 | 1505 | bank->base + bank->regs->risingdetect); |
661553b9 | 1506 | writel_relaxed(bank->context.fallingdetect, |
ae10f233 | 1507 | bank->base + bank->regs->fallingdetect); |
f86bcc30 | 1508 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
661553b9 | 1509 | writel_relaxed(bank->context.dataout, |
f86bcc30 NM |
1510 | bank->base + bank->regs->set_dataout); |
1511 | else | |
661553b9 | 1512 | writel_relaxed(bank->context.dataout, |
f86bcc30 | 1513 | bank->base + bank->regs->dataout); |
661553b9 | 1514 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); |
6d13eaaf | 1515 | |
ae547354 | 1516 | if (bank->dbck_enable_mask) { |
661553b9 | 1517 | writel_relaxed(bank->context.debounce, bank->base + |
ae547354 | 1518 | bank->regs->debounce); |
661553b9 | 1519 | writel_relaxed(bank->context.debounce_en, |
ae547354 NM |
1520 | bank->base + bank->regs->debounce_en); |
1521 | } | |
ba805be5 | 1522 | |
661553b9 | 1523 | writel_relaxed(bank->context.irqenable1, |
ba805be5 | 1524 | bank->base + bank->regs->irqenable); |
661553b9 | 1525 | writel_relaxed(bank->context.irqenable2, |
ba805be5 | 1526 | bank->base + bank->regs->irqenable2); |
40c670f0 | 1527 | } |
ecb2312f | 1528 | #endif /* CONFIG_PM */ |
55b93c32 | 1529 | #else |
2dc983c5 TKD |
1530 | #define omap_gpio_runtime_suspend NULL |
1531 | #define omap_gpio_runtime_resume NULL | |
ea4a21a2 | 1532 | static inline void omap_gpio_init_context(struct gpio_bank *p) {} |
40c670f0 RN |
1533 | #endif |
1534 | ||
55b93c32 | 1535 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1536 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1537 | NULL) | |
55b93c32 TKD |
1538 | }; |
1539 | ||
384ebe1c BC |
1540 | #if defined(CONFIG_OF) |
1541 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1542 | .revision = OMAP24XX_GPIO_REVISION, | |
1543 | .direction = OMAP24XX_GPIO_OE, | |
1544 | .datain = OMAP24XX_GPIO_DATAIN, | |
1545 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1546 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1547 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1548 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1549 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1550 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1551 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1552 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1553 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1554 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1555 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1556 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1557 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1558 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1559 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1560 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1561 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1562 | }; | |
1563 | ||
1564 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1565 | .revision = OMAP4_GPIO_REVISION, | |
1566 | .direction = OMAP4_GPIO_OE, | |
1567 | .datain = OMAP4_GPIO_DATAIN, | |
1568 | .dataout = OMAP4_GPIO_DATAOUT, | |
1569 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1570 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1571 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1572 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1573 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1574 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1575 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1576 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1577 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1578 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1579 | .ctrl = OMAP4_GPIO_CTRL, | |
1580 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1581 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1582 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1583 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1584 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1585 | }; | |
1586 | ||
e9a65bb6 | 1587 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1588 | .regs = &omap2_gpio_regs, |
1589 | .bank_width = 32, | |
1590 | .dbck_flag = false, | |
1591 | }; | |
1592 | ||
e9a65bb6 | 1593 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1594 | .regs = &omap2_gpio_regs, |
1595 | .bank_width = 32, | |
1596 | .dbck_flag = true, | |
1597 | }; | |
1598 | ||
e9a65bb6 | 1599 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1600 | .regs = &omap4_gpio_regs, |
1601 | .bank_width = 32, | |
1602 | .dbck_flag = true, | |
1603 | }; | |
1604 | ||
1605 | static const struct of_device_id omap_gpio_match[] = { | |
1606 | { | |
1607 | .compatible = "ti,omap4-gpio", | |
1608 | .data = &omap4_pdata, | |
1609 | }, | |
1610 | { | |
1611 | .compatible = "ti,omap3-gpio", | |
1612 | .data = &omap3_pdata, | |
1613 | }, | |
1614 | { | |
1615 | .compatible = "ti,omap2-gpio", | |
1616 | .data = &omap2_pdata, | |
1617 | }, | |
1618 | { }, | |
1619 | }; | |
1620 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1621 | #endif | |
1622 | ||
77640aab VC |
1623 | static struct platform_driver omap_gpio_driver = { |
1624 | .probe = omap_gpio_probe, | |
1625 | .driver = { | |
1626 | .name = "omap_gpio", | |
55b93c32 | 1627 | .pm = &gpio_pm_ops, |
384ebe1c | 1628 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1629 | }, |
1630 | }; | |
1631 | ||
5e1c5ff4 | 1632 | /* |
77640aab VC |
1633 | * gpio driver register needs to be done before |
1634 | * machine_init functions access gpio APIs. | |
1635 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1636 | */ |
77640aab | 1637 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1638 | { |
77640aab | 1639 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1640 | } |
77640aab | 1641 | postcore_initcall(omap_gpio_drv_reg); |