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Commit | Line | Data |
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5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
4b25408f | 27 | #include <linux/gpio.h> |
9370084e | 28 | #include <linux/bitops.h> |
4b25408f | 29 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 30 | |
2dc983c5 | 31 | #define OFF_MODE 1 |
e85ec6c3 | 32 | #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF |
2dc983c5 | 33 | |
03e128ca C |
34 | static LIST_HEAD(omap_gpio_list); |
35 | ||
6d62e216 C |
36 | struct gpio_regs { |
37 | u32 irqenable1; | |
38 | u32 irqenable2; | |
39 | u32 wake_en; | |
40 | u32 ctrl; | |
41 | u32 oe; | |
42 | u32 leveldetect0; | |
43 | u32 leveldetect1; | |
44 | u32 risingdetect; | |
45 | u32 fallingdetect; | |
46 | u32 dataout; | |
ae547354 NM |
47 | u32 debounce; |
48 | u32 debounce_en; | |
6d62e216 C |
49 | }; |
50 | ||
5e1c5ff4 | 51 | struct gpio_bank { |
03e128ca | 52 | struct list_head node; |
92105bb7 | 53 | void __iomem *base; |
30cefeac | 54 | int irq; |
3ac4fa99 JY |
55 | u32 non_wakeup_gpios; |
56 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 57 | struct gpio_regs context; |
3ac4fa99 | 58 | u32 saved_datain; |
b144ff6f | 59 | u32 level_mask; |
4318f36b | 60 | u32 toggle_mask; |
4dbada2b | 61 | raw_spinlock_t lock; |
450fa54c | 62 | raw_spinlock_t wa_lock; |
52e31344 | 63 | struct gpio_chip chip; |
89db9482 | 64 | struct clk *dbck; |
058af1ea | 65 | u32 mod_usage; |
fa365e4d | 66 | u32 irq_usage; |
8865b9b6 | 67 | u32 dbck_enable_mask; |
72f83af9 | 68 | bool dbck_enabled; |
d0d665a8 | 69 | bool is_mpuio; |
77640aab | 70 | bool dbck_flag; |
0cde8d03 | 71 | bool loses_context; |
352a2d5b | 72 | bool context_valid; |
5de62b86 | 73 | int stride; |
d5f46247 | 74 | u32 width; |
60a3437d | 75 | int context_loss_count; |
2dc983c5 TKD |
76 | int power_mode; |
77 | bool workaround_enabled; | |
fa87931a | 78 | |
04ebcbd8 | 79 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
60a3437d | 80 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
81 | |
82 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
83 | }; |
84 | ||
c8eef65a | 85 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 86 | |
fa365e4d | 87 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 88 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 89 | |
3d009c8c TL |
90 | static void omap_gpio_unmask_irq(struct irq_data *d); |
91 | ||
a0e827c6 | 92 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 93 | { |
fb655f57 | 94 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
d99f7aec | 95 | return gpiochip_get_data(chip); |
25db711d BC |
96 | } |
97 | ||
a0e827c6 JMC |
98 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
99 | int is_input) | |
5e1c5ff4 | 100 | { |
92105bb7 | 101 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
102 | u32 l; |
103 | ||
fa87931a | 104 | reg += bank->regs->direction; |
661553b9 | 105 | l = readl_relaxed(reg); |
5e1c5ff4 | 106 | if (is_input) |
b1e9fec2 | 107 | l |= BIT(gpio); |
5e1c5ff4 | 108 | else |
b1e9fec2 | 109 | l &= ~(BIT(gpio)); |
661553b9 | 110 | writel_relaxed(l, reg); |
41d87cbd | 111 | bank->context.oe = l; |
5e1c5ff4 TL |
112 | } |
113 | ||
fa87931a KH |
114 | |
115 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 116 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 117 | int enable) |
5e1c5ff4 | 118 | { |
92105bb7 | 119 | void __iomem *reg = bank->base; |
04ebcbd8 | 120 | u32 l = BIT(offset); |
5e1c5ff4 | 121 | |
2c836f7e | 122 | if (enable) { |
fa87931a | 123 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
124 | bank->context.dataout |= l; |
125 | } else { | |
fa87931a | 126 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
127 | bank->context.dataout &= ~l; |
128 | } | |
5e1c5ff4 | 129 | |
661553b9 | 130 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
131 | } |
132 | ||
fa87931a | 133 | /* set data out value using mask register */ |
04ebcbd8 | 134 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 135 | int enable) |
5e1c5ff4 | 136 | { |
fa87931a | 137 | void __iomem *reg = bank->base + bank->regs->dataout; |
04ebcbd8 | 138 | u32 gpio_bit = BIT(offset); |
fa87931a | 139 | u32 l; |
5e1c5ff4 | 140 | |
661553b9 | 141 | l = readl_relaxed(reg); |
fa87931a KH |
142 | if (enable) |
143 | l |= gpio_bit; | |
144 | else | |
145 | l &= ~gpio_bit; | |
661553b9 | 146 | writel_relaxed(l, reg); |
41d87cbd | 147 | bank->context.dataout = l; |
5e1c5ff4 TL |
148 | } |
149 | ||
a0e827c6 | 150 | static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 151 | { |
fa87931a | 152 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 153 | |
b1e9fec2 | 154 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
5e1c5ff4 | 155 | } |
b37c45b8 | 156 | |
a0e827c6 | 157 | static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 158 | { |
fa87931a | 159 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 160 | |
b1e9fec2 | 161 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
b37c45b8 RQ |
162 | } |
163 | ||
a0e827c6 | 164 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
ece9528e | 165 | { |
661553b9 | 166 | int l = readl_relaxed(base + reg); |
ece9528e | 167 | |
862ff640 | 168 | if (set) |
ece9528e KH |
169 | l |= mask; |
170 | else | |
171 | l &= ~mask; | |
172 | ||
661553b9 | 173 | writel_relaxed(l, base + reg); |
ece9528e | 174 | } |
92105bb7 | 175 | |
a0e827c6 | 176 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
177 | { |
178 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
5d9452e7 | 179 | clk_enable(bank->dbck); |
72f83af9 | 180 | bank->dbck_enabled = true; |
9e303f22 | 181 | |
661553b9 | 182 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 183 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
184 | } |
185 | } | |
186 | ||
a0e827c6 | 187 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
188 | { |
189 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
190 | /* |
191 | * Disable debounce before cutting it's clock. If debounce is | |
192 | * enabled but the clock is not, GPIO module seems to be unable | |
193 | * to detect events and generate interrupts at least on OMAP3. | |
194 | */ | |
661553b9 | 195 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 196 | |
5d9452e7 | 197 | clk_disable(bank->dbck); |
72f83af9 TKD |
198 | bank->dbck_enabled = false; |
199 | } | |
200 | } | |
201 | ||
168ef3d9 | 202 | /** |
a0e827c6 | 203 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 204 | * @bank: the gpio bank we're acting upon |
4a58d229 | 205 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
206 | * @debounce: debounce time to use |
207 | * | |
e85ec6c3 GS |
208 | * OMAP's debounce time is in 31us steps |
209 | * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 | |
210 | * so we need to convert and round up to the closest unit. | |
168ef3d9 | 211 | */ |
4a58d229 | 212 | static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 213 | unsigned debounce) |
168ef3d9 | 214 | { |
9942da0e | 215 | void __iomem *reg; |
168ef3d9 FB |
216 | u32 val; |
217 | u32 l; | |
e85ec6c3 | 218 | bool enable = !!debounce; |
168ef3d9 | 219 | |
77640aab VC |
220 | if (!bank->dbck_flag) |
221 | return; | |
222 | ||
e85ec6c3 GS |
223 | if (enable) { |
224 | debounce = DIV_ROUND_UP(debounce, 31) - 1; | |
225 | debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK; | |
226 | } | |
168ef3d9 | 227 | |
4a58d229 | 228 | l = BIT(offset); |
168ef3d9 | 229 | |
5d9452e7 | 230 | clk_enable(bank->dbck); |
9942da0e | 231 | reg = bank->base + bank->regs->debounce; |
661553b9 | 232 | writel_relaxed(debounce, reg); |
168ef3d9 | 233 | |
9942da0e | 234 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 235 | val = readl_relaxed(reg); |
168ef3d9 | 236 | |
e85ec6c3 | 237 | if (enable) |
168ef3d9 | 238 | val |= l; |
6fd9c421 | 239 | else |
168ef3d9 | 240 | val &= ~l; |
f7ec0b0b | 241 | bank->dbck_enable_mask = val; |
168ef3d9 | 242 | |
661553b9 | 243 | writel_relaxed(val, reg); |
5d9452e7 | 244 | clk_disable(bank->dbck); |
6fd9c421 TKD |
245 | /* |
246 | * Enable debounce clock per module. | |
247 | * This call is mandatory because in omap_gpio_request() when | |
248 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
249 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
250 | * used within _gpio_dbck_enable() is still not initialized at | |
251 | * that point. Therefore we have to enable dbck here. | |
252 | */ | |
a0e827c6 | 253 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
254 | if (bank->dbck_enable_mask) { |
255 | bank->context.debounce = debounce; | |
256 | bank->context.debounce_en = val; | |
257 | } | |
168ef3d9 FB |
258 | } |
259 | ||
c9c55d92 | 260 | /** |
a0e827c6 | 261 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 262 | * @bank: the gpio bank we're acting upon |
4a58d229 | 263 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
264 | * |
265 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
266 | * this is the only gpio in this bank using debounce, then clear the debounce | |
267 | * time too. The debounce clock will also be disabled when calling this function | |
268 | * if this is the only gpio in the bank using debounce. | |
269 | */ | |
4a58d229 | 270 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 271 | { |
4a58d229 | 272 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
273 | |
274 | if (!bank->dbck_flag) | |
275 | return; | |
276 | ||
277 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
278 | return; | |
279 | ||
280 | bank->dbck_enable_mask &= ~gpio_bit; | |
281 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 282 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
283 | bank->base + bank->regs->debounce_en); |
284 | ||
285 | if (!bank->dbck_enable_mask) { | |
286 | bank->context.debounce = 0; | |
661553b9 | 287 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 288 | bank->regs->debounce); |
5d9452e7 | 289 | clk_disable(bank->dbck); |
c9c55d92 JH |
290 | bank->dbck_enabled = false; |
291 | } | |
292 | } | |
293 | ||
a0e827c6 | 294 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 295 | unsigned trigger) |
5e1c5ff4 | 296 | { |
3ac4fa99 | 297 | void __iomem *base = bank->base; |
b1e9fec2 | 298 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 299 | |
a0e827c6 JMC |
300 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
301 | trigger & IRQ_TYPE_LEVEL_LOW); | |
302 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
303 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
304 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
305 | trigger & IRQ_TYPE_EDGE_RISING); | |
306 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
307 | trigger & IRQ_TYPE_EDGE_FALLING); | |
5e571f38 | 308 | |
41d87cbd | 309 | bank->context.leveldetect0 = |
661553b9 | 310 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 311 | bank->context.leveldetect1 = |
661553b9 | 312 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 313 | bank->context.risingdetect = |
661553b9 | 314 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 315 | bank->context.fallingdetect = |
661553b9 | 316 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
317 | |
318 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
a0e827c6 | 319 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd | 320 | bank->context.wake_en = |
661553b9 | 321 | readl_relaxed(bank->base + bank->regs->wkup_en); |
41d87cbd | 322 | } |
5e571f38 | 323 | |
55b220ca | 324 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
325 | if (!bank->regs->irqctrl) { |
326 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
327 | if (bank->non_wakeup_gpios) { | |
328 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
329 | goto exit; | |
330 | } | |
331 | ||
699117a6 CW |
332 | /* |
333 | * Log the edge gpio and manually trigger the IRQ | |
334 | * after resume if the input level changes | |
335 | * to avoid irq lost during PER RET/OFF mode | |
336 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
337 | */ | |
338 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
339 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
340 | else | |
341 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
342 | } | |
5eb3bb9c | 343 | |
5e571f38 | 344 | exit: |
9ea14d8c | 345 | bank->level_mask = |
661553b9 VK |
346 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
347 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
348 | } |
349 | ||
9198bcd3 | 350 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
351 | /* |
352 | * This only applies to chips that can't do both rising and falling edge | |
353 | * detection at once. For all other chips, this function is a noop. | |
354 | */ | |
a0e827c6 | 355 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b CM |
356 | { |
357 | void __iomem *reg = bank->base; | |
358 | u32 l = 0; | |
359 | ||
5e571f38 | 360 | if (!bank->regs->irqctrl) |
4318f36b | 361 | return; |
5e571f38 TKD |
362 | |
363 | reg += bank->regs->irqctrl; | |
4318f36b | 364 | |
661553b9 | 365 | l = readl_relaxed(reg); |
4318f36b | 366 | if ((l >> gpio) & 1) |
b1e9fec2 | 367 | l &= ~(BIT(gpio)); |
4318f36b | 368 | else |
b1e9fec2 | 369 | l |= BIT(gpio); |
4318f36b | 370 | |
661553b9 | 371 | writel_relaxed(l, reg); |
4318f36b | 372 | } |
5e571f38 | 373 | #else |
a0e827c6 | 374 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
9198bcd3 | 375 | #endif |
4318f36b | 376 | |
a0e827c6 JMC |
377 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
378 | unsigned trigger) | |
92105bb7 TL |
379 | { |
380 | void __iomem *reg = bank->base; | |
5e571f38 | 381 | void __iomem *base = bank->base; |
92105bb7 | 382 | u32 l = 0; |
5e1c5ff4 | 383 | |
5e571f38 | 384 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 385 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
386 | } else if (bank->regs->irqctrl) { |
387 | reg += bank->regs->irqctrl; | |
388 | ||
661553b9 | 389 | l = readl_relaxed(reg); |
29501577 | 390 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 391 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 392 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 393 | l |= BIT(gpio); |
6cab4860 | 394 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 395 | l &= ~(BIT(gpio)); |
92105bb7 | 396 | else |
5e571f38 TKD |
397 | return -EINVAL; |
398 | ||
661553b9 | 399 | writel_relaxed(l, reg); |
5e571f38 | 400 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 401 | if (gpio & 0x08) |
5e571f38 | 402 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 403 | else |
5e571f38 TKD |
404 | reg += bank->regs->edgectrl1; |
405 | ||
5e1c5ff4 | 406 | gpio &= 0x07; |
661553b9 | 407 | l = readl_relaxed(reg); |
5e1c5ff4 | 408 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 409 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 410 | l |= 2 << (gpio << 1); |
6cab4860 | 411 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 412 | l |= BIT(gpio << 1); |
5e571f38 TKD |
413 | |
414 | /* Enable wake-up during idle for dynamic tick */ | |
a0e827c6 | 415 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 416 | bank->context.wake_en = |
661553b9 VK |
417 | readl_relaxed(bank->base + bank->regs->wkup_en); |
418 | writel_relaxed(l, reg); | |
5e1c5ff4 | 419 | } |
92105bb7 | 420 | return 0; |
5e1c5ff4 TL |
421 | } |
422 | ||
a0e827c6 | 423 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
424 | { |
425 | if (bank->regs->pinctrl) { | |
426 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
427 | ||
428 | /* Claim the pin for MPU */ | |
b1e9fec2 | 429 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
430 | } |
431 | ||
432 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
433 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
434 | u32 ctrl; | |
435 | ||
661553b9 | 436 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
437 | /* Module is enabled, clocks are not gated */ |
438 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 439 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
440 | bank->context.ctrl = ctrl; |
441 | } | |
442 | } | |
443 | ||
a0e827c6 | 444 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
445 | { |
446 | void __iomem *base = bank->base; | |
447 | ||
448 | if (bank->regs->wkup_en && | |
449 | !LINE_USED(bank->mod_usage, offset) && | |
450 | !LINE_USED(bank->irq_usage, offset)) { | |
451 | /* Disable wake-up during idle for dynamic tick */ | |
a0e827c6 | 452 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 453 | bank->context.wake_en = |
661553b9 | 454 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
455 | } |
456 | ||
457 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
458 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
459 | u32 ctrl; | |
460 | ||
661553b9 | 461 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
462 | /* Module is disabled, clocks are gated */ |
463 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 464 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
465 | bank->context.ctrl = ctrl; |
466 | } | |
467 | } | |
468 | ||
b2b20045 | 469 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
470 | { |
471 | void __iomem *reg = bank->base + bank->regs->direction; | |
472 | ||
b2b20045 | 473 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
474 | } |
475 | ||
37e14ecf | 476 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
477 | { |
478 | if (!LINE_USED(bank->mod_usage, offset)) { | |
479 | omap_enable_gpio_module(bank, offset); | |
480 | omap_set_gpio_direction(bank, offset, 1); | |
481 | } | |
37e14ecf | 482 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
483 | } |
484 | ||
a0e827c6 | 485 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 486 | { |
a0e827c6 | 487 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 488 | int retval; |
a6472533 | 489 | unsigned long flags; |
ea5fbe8d | 490 | unsigned offset = d->hwirq; |
92105bb7 | 491 | |
e5c56ed3 | 492 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 493 | return -EINVAL; |
e5c56ed3 | 494 | |
9ea14d8c TKD |
495 | if (!bank->regs->leveldetect0 && |
496 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
497 | return -EINVAL; |
498 | ||
4dbada2b | 499 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 500 | retval = omap_set_gpio_triggering(bank, offset, type); |
977bd8a9 | 501 | if (retval) { |
627c89b4 | 502 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 | 503 | goto error; |
977bd8a9 | 504 | } |
37e14ecf | 505 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 506 | if (!omap_gpio_is_input(bank, offset)) { |
4dbada2b | 507 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 GS |
508 | retval = -EINVAL; |
509 | goto error; | |
fac7fa16 | 510 | } |
4dbada2b | 511 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
512 | |
513 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
43ec2e43 | 514 | irq_set_handler_locked(d, handle_level_irq); |
672e302e | 515 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
43ec2e43 | 516 | irq_set_handler_locked(d, handle_edge_irq); |
672e302e | 517 | |
1562e461 GS |
518 | return 0; |
519 | ||
520 | error: | |
92105bb7 | 521 | return retval; |
5e1c5ff4 TL |
522 | } |
523 | ||
a0e827c6 | 524 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 525 | { |
92105bb7 | 526 | void __iomem *reg = bank->base; |
5e1c5ff4 | 527 | |
eef4bec7 | 528 | reg += bank->regs->irqstatus; |
661553b9 | 529 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
530 | |
531 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
532 | if (bank->regs->irqstatus2) { |
533 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 534 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 535 | } |
bedfd154 RQ |
536 | |
537 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 538 | readl_relaxed(reg); |
5e1c5ff4 TL |
539 | } |
540 | ||
9943f261 GS |
541 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
542 | unsigned offset) | |
5e1c5ff4 | 543 | { |
9943f261 | 544 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
545 | } |
546 | ||
a0e827c6 | 547 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
548 | { |
549 | void __iomem *reg = bank->base; | |
99c47707 | 550 | u32 l; |
b1e9fec2 | 551 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 552 | |
28f3b5a0 | 553 | reg += bank->regs->irqenable; |
661553b9 | 554 | l = readl_relaxed(reg); |
28f3b5a0 | 555 | if (bank->regs->irqenable_inv) |
99c47707 ID |
556 | l = ~l; |
557 | l &= mask; | |
558 | return l; | |
ea6dedd7 ID |
559 | } |
560 | ||
a0e827c6 | 561 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 562 | { |
92105bb7 | 563 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
564 | u32 l; |
565 | ||
28f3b5a0 KH |
566 | if (bank->regs->set_irqenable) { |
567 | reg += bank->regs->set_irqenable; | |
568 | l = gpio_mask; | |
2a900eb7 | 569 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
570 | } else { |
571 | reg += bank->regs->irqenable; | |
661553b9 | 572 | l = readl_relaxed(reg); |
28f3b5a0 KH |
573 | if (bank->regs->irqenable_inv) |
574 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
575 | else |
576 | l |= gpio_mask; | |
2a900eb7 | 577 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
578 | } |
579 | ||
661553b9 | 580 | writel_relaxed(l, reg); |
28f3b5a0 KH |
581 | } |
582 | ||
a0e827c6 | 583 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
28f3b5a0 KH |
584 | { |
585 | void __iomem *reg = bank->base; | |
586 | u32 l; | |
587 | ||
588 | if (bank->regs->clr_irqenable) { | |
589 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 590 | l = gpio_mask; |
2a900eb7 | 591 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
592 | } else { |
593 | reg += bank->regs->irqenable; | |
661553b9 | 594 | l = readl_relaxed(reg); |
28f3b5a0 | 595 | if (bank->regs->irqenable_inv) |
56739a69 | 596 | l |= gpio_mask; |
92105bb7 | 597 | else |
28f3b5a0 | 598 | l &= ~gpio_mask; |
2a900eb7 | 599 | bank->context.irqenable1 = l; |
5e1c5ff4 | 600 | } |
28f3b5a0 | 601 | |
661553b9 | 602 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
603 | } |
604 | ||
9943f261 GS |
605 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
606 | unsigned offset, int enable) | |
5e1c5ff4 | 607 | { |
8276536c | 608 | if (enable) |
9943f261 | 609 | omap_enable_gpio_irqbank(bank, BIT(offset)); |
8276536c | 610 | else |
9943f261 | 611 | omap_disable_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
612 | } |
613 | ||
92105bb7 TL |
614 | /* |
615 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
616 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
617 | * to the target, system will wake up always on GPIO events. While | |
618 | * system is running all registered GPIO interrupts need to have wake-up | |
619 | * enabled. When system is suspended, only selected GPIO interrupts need | |
620 | * to have wake-up enabled. | |
621 | */ | |
9943f261 GS |
622 | static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset, |
623 | int enable) | |
92105bb7 | 624 | { |
9943f261 | 625 | u32 gpio_bit = BIT(offset); |
f64ad1a0 | 626 | unsigned long flags; |
a6472533 | 627 | |
f64ad1a0 | 628 | if (bank->non_wakeup_gpios & gpio_bit) { |
7b1e5dc8 | 629 | dev_err(bank->chip.parent, |
9943f261 GS |
630 | "Unable to modify wakeup on non-wakeup GPIO%d\n", |
631 | offset); | |
92105bb7 TL |
632 | return -EINVAL; |
633 | } | |
f64ad1a0 | 634 | |
4dbada2b | 635 | raw_spin_lock_irqsave(&bank->lock, flags); |
f64ad1a0 | 636 | if (enable) |
0aa27273 | 637 | bank->context.wake_en |= gpio_bit; |
f64ad1a0 | 638 | else |
0aa27273 | 639 | bank->context.wake_en &= ~gpio_bit; |
f64ad1a0 | 640 | |
661553b9 | 641 | writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en); |
4dbada2b | 642 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
f64ad1a0 KH |
643 | |
644 | return 0; | |
92105bb7 TL |
645 | } |
646 | ||
647 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ | |
a0e827c6 | 648 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 649 | { |
a0e827c6 | 650 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 651 | unsigned offset = d->hwirq; |
450fa54c GS |
652 | int ret; |
653 | ||
654 | ret = omap_set_gpio_wakeup(bank, offset, enable); | |
655 | if (!ret) | |
656 | ret = irq_set_irq_wake(bank->irq, enable); | |
92105bb7 | 657 | |
450fa54c | 658 | return ret; |
92105bb7 TL |
659 | } |
660 | ||
3ff164e1 | 661 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 662 | { |
d99f7aec | 663 | struct gpio_bank *bank = gpiochip_get_data(chip); |
a6472533 | 664 | unsigned long flags; |
52e31344 | 665 | |
55b93c32 TKD |
666 | /* |
667 | * If this is the first gpio_request for the bank, | |
668 | * enable the bank module. | |
669 | */ | |
fa365e4d | 670 | if (!BANK_USED(bank)) |
7b1e5dc8 | 671 | pm_runtime_get_sync(chip->parent); |
92105bb7 | 672 | |
4dbada2b | 673 | raw_spin_lock_irqsave(&bank->lock, flags); |
c3518172 | 674 | omap_enable_gpio_module(bank, offset); |
b1e9fec2 | 675 | bank->mod_usage |= BIT(offset); |
4dbada2b | 676 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
677 | |
678 | return 0; | |
679 | } | |
680 | ||
3ff164e1 | 681 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 682 | { |
d99f7aec | 683 | struct gpio_bank *bank = gpiochip_get_data(chip); |
a6472533 | 684 | unsigned long flags; |
5e1c5ff4 | 685 | |
4dbada2b | 686 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 687 | bank->mod_usage &= ~(BIT(offset)); |
5f982c70 GS |
688 | if (!LINE_USED(bank->irq_usage, offset)) { |
689 | omap_set_gpio_direction(bank, offset, 1); | |
690 | omap_clear_gpio_debounce(bank, offset); | |
691 | } | |
a0e827c6 | 692 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 693 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
694 | |
695 | /* | |
696 | * If this is the last gpio to be freed in the bank, | |
697 | * disable the bank module. | |
698 | */ | |
fa365e4d | 699 | if (!BANK_USED(bank)) |
7b1e5dc8 | 700 | pm_runtime_put(chip->parent); |
5e1c5ff4 TL |
701 | } |
702 | ||
703 | /* | |
704 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
705 | * avoid missing GPIO interrupts for other lines in the bank. | |
706 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
707 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
708 | * If we wait to unmask individual GPIO lines in the bank after the | |
709 | * line's interrupt handler has been run, we may miss some nested | |
710 | * interrupts. | |
711 | */ | |
450fa54c | 712 | static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) |
5e1c5ff4 | 713 | { |
92105bb7 | 714 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 715 | u32 isr; |
3513cdec | 716 | unsigned int bit; |
450fa54c GS |
717 | struct gpio_bank *bank = gpiobank; |
718 | unsigned long wa_lock_flags; | |
235f1eb1 | 719 | unsigned long lock_flags; |
5e1c5ff4 | 720 | |
eef4bec7 | 721 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
722 | if (WARN_ON(!isr_reg)) |
723 | goto exit; | |
724 | ||
7b1e5dc8 | 725 | pm_runtime_get_sync(bank->chip.parent); |
450fa54c | 726 | |
e83507b7 | 727 | while (1) { |
6e60e79a | 728 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 729 | u32 enabled; |
6e60e79a | 730 | |
235f1eb1 GS |
731 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
732 | ||
a0e827c6 | 733 | enabled = omap_get_gpio_irqbank_mask(bank); |
661553b9 | 734 | isr_saved = isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 735 | |
9ea14d8c | 736 | if (bank->level_mask) |
b144ff6f | 737 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
738 | |
739 | /* clear edge sensitive interrupts before handler(s) are | |
740 | called so that we don't miss any interrupt occurred while | |
741 | executing them */ | |
a0e827c6 JMC |
742 | omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
743 | omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
744 | omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask); | |
6e60e79a | 745 | |
235f1eb1 GS |
746 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
747 | ||
92105bb7 TL |
748 | if (!isr) |
749 | break; | |
750 | ||
3513cdec JH |
751 | while (isr) { |
752 | bit = __ffs(isr); | |
b1e9fec2 | 753 | isr &= ~(BIT(bit)); |
25db711d | 754 | |
235f1eb1 | 755 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
4318f36b CM |
756 | /* |
757 | * Some chips can't respond to both rising and falling | |
758 | * at the same time. If this irq was requested with | |
759 | * both flags, we need to flip the ICR data for the IRQ | |
760 | * to respond to the IRQ for the opposite direction. | |
761 | * This will be indicated in the bank toggle_mask. | |
762 | */ | |
b1e9fec2 | 763 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 764 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 765 | |
235f1eb1 GS |
766 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
767 | ||
450fa54c GS |
768 | raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); |
769 | ||
fb655f57 JMC |
770 | generic_handle_irq(irq_find_mapping(bank->chip.irqdomain, |
771 | bit)); | |
450fa54c GS |
772 | |
773 | raw_spin_unlock_irqrestore(&bank->wa_lock, | |
774 | wa_lock_flags); | |
92105bb7 | 775 | } |
1a8bfa1e | 776 | } |
b1cc4c55 | 777 | exit: |
7b1e5dc8 | 778 | pm_runtime_put(bank->chip.parent); |
450fa54c | 779 | return IRQ_HANDLED; |
5e1c5ff4 TL |
780 | } |
781 | ||
3d009c8c TL |
782 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
783 | { | |
784 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 785 | unsigned long flags; |
37e14ecf | 786 | unsigned offset = d->hwirq; |
3d009c8c | 787 | |
4dbada2b | 788 | raw_spin_lock_irqsave(&bank->lock, flags); |
121dcb76 GS |
789 | |
790 | if (!LINE_USED(bank->mod_usage, offset)) | |
791 | omap_set_gpio_direction(bank, offset, 1); | |
792 | else if (!omap_gpio_is_input(bank, offset)) | |
793 | goto err; | |
794 | omap_enable_gpio_module(bank, offset); | |
795 | bank->irq_usage |= BIT(offset); | |
796 | ||
4dbada2b | 797 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
3d009c8c TL |
798 | omap_gpio_unmask_irq(d); |
799 | ||
800 | return 0; | |
121dcb76 | 801 | err: |
4dbada2b | 802 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
121dcb76 | 803 | return -EINVAL; |
3d009c8c TL |
804 | } |
805 | ||
a0e827c6 | 806 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 807 | { |
a0e827c6 | 808 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 809 | unsigned long flags; |
9943f261 | 810 | unsigned offset = d->hwirq; |
4196dd6b | 811 | |
4dbada2b | 812 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 813 | bank->irq_usage &= ~(BIT(offset)); |
6e96c1b5 GS |
814 | omap_set_gpio_irqenable(bank, offset, 0); |
815 | omap_clear_gpio_irqstatus(bank, offset); | |
816 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
817 | if (!LINE_USED(bank->mod_usage, offset)) | |
818 | omap_clear_gpio_debounce(bank, offset); | |
a0e827c6 | 819 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 820 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
aca82d1c GS |
821 | } |
822 | ||
823 | static void omap_gpio_irq_bus_lock(struct irq_data *data) | |
824 | { | |
825 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
826 | ||
827 | if (!BANK_USED(bank)) | |
7b1e5dc8 | 828 | pm_runtime_get_sync(bank->chip.parent); |
aca82d1c GS |
829 | } |
830 | ||
831 | static void gpio_irq_bus_sync_unlock(struct irq_data *data) | |
832 | { | |
833 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
fac7fa16 JMC |
834 | |
835 | /* | |
836 | * If this is the last IRQ to be freed in the bank, | |
837 | * disable the bank module. | |
838 | */ | |
839 | if (!BANK_USED(bank)) | |
7b1e5dc8 | 840 | pm_runtime_put(bank->chip.parent); |
4196dd6b TL |
841 | } |
842 | ||
a0e827c6 | 843 | static void omap_gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 844 | { |
a0e827c6 | 845 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 846 | unsigned offset = d->hwirq; |
5e1c5ff4 | 847 | |
9943f261 | 848 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 TL |
849 | } |
850 | ||
a0e827c6 | 851 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 852 | { |
a0e827c6 | 853 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 854 | unsigned offset = d->hwirq; |
85ec7b97 | 855 | unsigned long flags; |
5e1c5ff4 | 856 | |
4dbada2b | 857 | raw_spin_lock_irqsave(&bank->lock, flags); |
9943f261 GS |
858 | omap_set_gpio_irqenable(bank, offset, 0); |
859 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
4dbada2b | 860 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
861 | } |
862 | ||
a0e827c6 | 863 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 864 | { |
a0e827c6 | 865 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 866 | unsigned offset = d->hwirq; |
8c04a176 | 867 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 868 | unsigned long flags; |
55b6019a | 869 | |
4dbada2b | 870 | raw_spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 871 | if (trigger) |
9943f261 | 872 | omap_set_gpio_triggering(bank, offset, trigger); |
b144ff6f KH |
873 | |
874 | /* For level-triggered GPIOs, the clearing must be done after | |
875 | * the HW source is cleared, thus after the handler has run */ | |
9943f261 GS |
876 | if (bank->level_mask & BIT(offset)) { |
877 | omap_set_gpio_irqenable(bank, offset, 0); | |
878 | omap_clear_gpio_irqstatus(bank, offset); | |
b144ff6f | 879 | } |
5e1c5ff4 | 880 | |
9943f261 | 881 | omap_set_gpio_irqenable(bank, offset, 1); |
4dbada2b | 882 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
883 | } |
884 | ||
e5c56ed3 DB |
885 | /*---------------------------------------------------------------------*/ |
886 | ||
79ee031f | 887 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 888 | { |
79ee031f | 889 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 890 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
891 | void __iomem *mask_reg = bank->base + |
892 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 893 | unsigned long flags; |
11a78b79 | 894 | |
4dbada2b | 895 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 896 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
4dbada2b | 897 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
898 | |
899 | return 0; | |
900 | } | |
901 | ||
79ee031f | 902 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 903 | { |
79ee031f | 904 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 905 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
906 | void __iomem *mask_reg = bank->base + |
907 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 908 | unsigned long flags; |
11a78b79 | 909 | |
4dbada2b | 910 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 911 | writel_relaxed(bank->context.wake_en, mask_reg); |
4dbada2b | 912 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
913 | |
914 | return 0; | |
915 | } | |
916 | ||
47145210 | 917 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
918 | .suspend_noirq = omap_mpuio_suspend_noirq, |
919 | .resume_noirq = omap_mpuio_resume_noirq, | |
920 | }; | |
921 | ||
3c437ffd | 922 | /* use platform_driver for this. */ |
11a78b79 | 923 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
924 | .driver = { |
925 | .name = "mpuio", | |
79ee031f | 926 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
927 | }, |
928 | }; | |
929 | ||
930 | static struct platform_device omap_mpuio_device = { | |
931 | .name = "mpuio", | |
932 | .id = -1, | |
933 | .dev = { | |
934 | .driver = &omap_mpuio_driver.driver, | |
935 | } | |
936 | /* could list the /proc/iomem resources */ | |
937 | }; | |
938 | ||
a0e827c6 | 939 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 940 | { |
77640aab | 941 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 942 | |
11a78b79 DB |
943 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
944 | (void) platform_device_register(&omap_mpuio_device); | |
945 | } | |
946 | ||
e5c56ed3 | 947 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 948 | |
a0e827c6 | 949 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e YY |
950 | { |
951 | struct gpio_bank *bank; | |
952 | unsigned long flags; | |
953 | void __iomem *reg; | |
954 | int dir; | |
955 | ||
d99f7aec | 956 | bank = gpiochip_get_data(chip); |
9370084e | 957 | reg = bank->base + bank->regs->direction; |
4dbada2b | 958 | raw_spin_lock_irqsave(&bank->lock, flags); |
9370084e | 959 | dir = !!(readl_relaxed(reg) & BIT(offset)); |
4dbada2b | 960 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
9370084e YY |
961 | return dir; |
962 | } | |
963 | ||
a0e827c6 | 964 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
965 | { |
966 | struct gpio_bank *bank; | |
967 | unsigned long flags; | |
968 | ||
d99f7aec | 969 | bank = gpiochip_get_data(chip); |
4dbada2b | 970 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 971 | omap_set_gpio_direction(bank, offset, 1); |
4dbada2b | 972 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
973 | return 0; |
974 | } | |
975 | ||
a0e827c6 | 976 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 977 | { |
b37c45b8 | 978 | struct gpio_bank *bank; |
b37c45b8 | 979 | |
d99f7aec | 980 | bank = gpiochip_get_data(chip); |
b37c45b8 | 981 | |
b2b20045 | 982 | if (omap_gpio_is_input(bank, offset)) |
a0e827c6 | 983 | return omap_get_gpio_datain(bank, offset); |
b37c45b8 | 984 | else |
a0e827c6 | 985 | return omap_get_gpio_dataout(bank, offset); |
52e31344 DB |
986 | } |
987 | ||
a0e827c6 | 988 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
989 | { |
990 | struct gpio_bank *bank; | |
991 | unsigned long flags; | |
992 | ||
d99f7aec | 993 | bank = gpiochip_get_data(chip); |
4dbada2b | 994 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 995 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 996 | omap_set_gpio_direction(bank, offset, 0); |
4dbada2b | 997 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 998 | return 0; |
52e31344 DB |
999 | } |
1000 | ||
a0e827c6 JMC |
1001 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1002 | unsigned debounce) | |
168ef3d9 FB |
1003 | { |
1004 | struct gpio_bank *bank; | |
1005 | unsigned long flags; | |
1006 | ||
d99f7aec | 1007 | bank = gpiochip_get_data(chip); |
77640aab | 1008 | |
4dbada2b | 1009 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 1010 | omap2_set_gpio_debounce(bank, offset, debounce); |
4dbada2b | 1011 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
168ef3d9 FB |
1012 | |
1013 | return 0; | |
1014 | } | |
1015 | ||
a0e827c6 | 1016 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
1017 | { |
1018 | struct gpio_bank *bank; | |
1019 | unsigned long flags; | |
1020 | ||
d99f7aec | 1021 | bank = gpiochip_get_data(chip); |
4dbada2b | 1022 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 1023 | bank->set_dataout(bank, offset, value); |
4dbada2b | 1024 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
1025 | } |
1026 | ||
1027 | /*---------------------------------------------------------------------*/ | |
1028 | ||
9a748053 | 1029 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1030 | { |
e5ff4440 | 1031 | static bool called; |
9f7065da TL |
1032 | u32 rev; |
1033 | ||
e5ff4440 | 1034 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1035 | return; |
1036 | ||
661553b9 | 1037 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1038 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1039 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1040 | |
1041 | called = true; | |
9f7065da TL |
1042 | } |
1043 | ||
03e128ca | 1044 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1045 | { |
ab985f0f TKD |
1046 | void __iomem *base = bank->base; |
1047 | u32 l = 0xffffffff; | |
2fae7fbe | 1048 | |
ab985f0f TKD |
1049 | if (bank->width == 16) |
1050 | l = 0xffff; | |
1051 | ||
d0d665a8 | 1052 | if (bank->is_mpuio) { |
661553b9 | 1053 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1054 | return; |
2fae7fbe | 1055 | } |
ab985f0f | 1056 | |
a0e827c6 JMC |
1057 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1058 | bank->regs->irqenable_inv); | |
1059 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | |
1060 | !bank->regs->irqenable_inv); | |
ab985f0f | 1061 | if (bank->regs->debounce_en) |
661553b9 | 1062 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1063 | |
2dc983c5 | 1064 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1065 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1066 | /* Initialize interface clk ungated, module enabled */ |
1067 | if (bank->regs->ctrl) | |
661553b9 | 1068 | writel_relaxed(0, base + bank->regs->ctrl); |
2fae7fbe VC |
1069 | } |
1070 | ||
46824e22 | 1071 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 1072 | { |
2fae7fbe | 1073 | static int gpio; |
fb655f57 | 1074 | int irq_base = 0; |
6ef7f385 | 1075 | int ret; |
2fae7fbe | 1076 | |
2fae7fbe VC |
1077 | /* |
1078 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1079 | * over to the generic ones | |
1080 | */ | |
1081 | bank->chip.request = omap_gpio_request; | |
1082 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1083 | bank->chip.get_direction = omap_gpio_get_direction; |
1084 | bank->chip.direction_input = omap_gpio_input; | |
1085 | bank->chip.get = omap_gpio_get; | |
1086 | bank->chip.direction_output = omap_gpio_output; | |
1087 | bank->chip.set_debounce = omap_gpio_debounce; | |
1088 | bank->chip.set = omap_gpio_set; | |
d0d665a8 | 1089 | if (bank->is_mpuio) { |
2fae7fbe | 1090 | bank->chip.label = "mpuio"; |
6ed87c5b | 1091 | if (bank->regs->wkup_en) |
58383c78 | 1092 | bank->chip.parent = &omap_mpuio_device.dev; |
2fae7fbe VC |
1093 | bank->chip.base = OMAP_MPUIO(0); |
1094 | } else { | |
1095 | bank->chip.label = "gpio"; | |
1096 | bank->chip.base = gpio; | |
2fae7fbe | 1097 | } |
d5f46247 | 1098 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1099 | |
d99f7aec | 1100 | ret = gpiochip_add_data(&bank->chip, bank); |
6ef7f385 | 1101 | if (ret) { |
7b1e5dc8 GS |
1102 | dev_err(bank->chip.parent, |
1103 | "Could not register gpio chip %d\n", ret); | |
6ef7f385 JMC |
1104 | return ret; |
1105 | } | |
2fae7fbe | 1106 | |
46d4f7c2 TL |
1107 | if (!bank->is_mpuio) |
1108 | gpio += bank->width; | |
1109 | ||
fb655f57 JMC |
1110 | #ifdef CONFIG_ARCH_OMAP1 |
1111 | /* | |
1112 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1113 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1114 | */ | |
1115 | irq_base = irq_alloc_descs(-1, 0, bank->width, 0); | |
1116 | if (irq_base < 0) { | |
7b1e5dc8 | 1117 | dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); |
fb655f57 JMC |
1118 | return -ENODEV; |
1119 | } | |
1120 | #endif | |
1121 | ||
d2d05c65 TL |
1122 | /* MPUIO is a bit different, reading IRQ status clears it */ |
1123 | if (bank->is_mpuio) { | |
1124 | irqc->irq_ack = dummy_irq_chip.irq_ack; | |
d2d05c65 TL |
1125 | if (!bank->regs->wkup_en) |
1126 | irqc->irq_set_wake = NULL; | |
1127 | } | |
1128 | ||
46824e22 | 1129 | ret = gpiochip_irqchip_add(&bank->chip, irqc, |
450fa54c | 1130 | irq_base, handle_bad_irq, |
fb655f57 JMC |
1131 | IRQ_TYPE_NONE); |
1132 | ||
1133 | if (ret) { | |
7b1e5dc8 GS |
1134 | dev_err(bank->chip.parent, |
1135 | "Couldn't add irqchip to gpiochip %d\n", ret); | |
da26d5d8 | 1136 | gpiochip_remove(&bank->chip); |
fb655f57 JMC |
1137 | return -ENODEV; |
1138 | } | |
1139 | ||
450fa54c | 1140 | gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL); |
fb655f57 | 1141 | |
7b1e5dc8 GS |
1142 | ret = devm_request_irq(bank->chip.parent, bank->irq, |
1143 | omap_gpio_irq_handler, | |
1144 | 0, dev_name(bank->chip.parent), bank); | |
450fa54c GS |
1145 | if (ret) |
1146 | gpiochip_remove(&bank->chip); | |
1147 | ||
1148 | return ret; | |
2fae7fbe VC |
1149 | } |
1150 | ||
384ebe1c BC |
1151 | static const struct of_device_id omap_gpio_match[]; |
1152 | ||
3836309d | 1153 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1154 | { |
862ff640 | 1155 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1156 | struct device_node *node = dev->of_node; |
1157 | const struct of_device_id *match; | |
f6817a2c | 1158 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1159 | struct resource *res; |
5e1c5ff4 | 1160 | struct gpio_bank *bank; |
46824e22 | 1161 | struct irq_chip *irqc; |
6ef7f385 | 1162 | int ret; |
5e1c5ff4 | 1163 | |
384ebe1c BC |
1164 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1165 | ||
e56aee18 | 1166 | pdata = match ? match->data : dev_get_platdata(dev); |
384ebe1c | 1167 | if (!pdata) |
96751fcb | 1168 | return -EINVAL; |
5492fb1a | 1169 | |
086d585f | 1170 | bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL); |
03e128ca | 1171 | if (!bank) { |
862ff640 | 1172 | dev_err(dev, "Memory alloc failed\n"); |
96751fcb | 1173 | return -ENOMEM; |
03e128ca | 1174 | } |
92105bb7 | 1175 | |
46824e22 NM |
1176 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); |
1177 | if (!irqc) | |
1178 | return -ENOMEM; | |
1179 | ||
3d009c8c | 1180 | irqc->irq_startup = omap_gpio_irq_startup, |
46824e22 NM |
1181 | irqc->irq_shutdown = omap_gpio_irq_shutdown, |
1182 | irqc->irq_ack = omap_gpio_ack_irq, | |
1183 | irqc->irq_mask = omap_gpio_mask_irq, | |
1184 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1185 | irqc->irq_set_type = omap_gpio_irq_type, | |
1186 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
aca82d1c GS |
1187 | irqc->irq_bus_lock = omap_gpio_irq_bus_lock, |
1188 | irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, | |
46824e22 NM |
1189 | irqc->name = dev_name(&pdev->dev); |
1190 | ||
89d18e3a GS |
1191 | bank->irq = platform_get_irq(pdev, 0); |
1192 | if (bank->irq <= 0) { | |
1193 | if (!bank->irq) | |
1194 | bank->irq = -ENXIO; | |
1195 | if (bank->irq != -EPROBE_DEFER) | |
1196 | dev_err(dev, | |
1197 | "can't get irq resource ret=%d\n", bank->irq); | |
1198 | return bank->irq; | |
44169075 | 1199 | } |
5e1c5ff4 | 1200 | |
58383c78 | 1201 | bank->chip.parent = dev; |
c23837ce | 1202 | bank->chip.owner = THIS_MODULE; |
77640aab | 1203 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1204 | bank->stride = pdata->bank_stride; |
d5f46247 | 1205 | bank->width = pdata->bank_width; |
d0d665a8 | 1206 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1207 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1208 | bank->regs = pdata->regs; |
384ebe1c BC |
1209 | #ifdef CONFIG_OF_GPIO |
1210 | bank->chip.of_node = of_node_get(node); | |
1211 | #endif | |
a2797bea JH |
1212 | if (node) { |
1213 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1214 | bank->loses_context = true; | |
1215 | } else { | |
1216 | bank->loses_context = pdata->loses_context; | |
352a2d5b JH |
1217 | |
1218 | if (bank->loses_context) | |
1219 | bank->get_context_loss_count = | |
1220 | pdata->get_context_loss_count; | |
384ebe1c BC |
1221 | } |
1222 | ||
fa87931a | 1223 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
a0e827c6 | 1224 | bank->set_dataout = omap_set_gpio_dataout_reg; |
fa87931a | 1225 | else |
a0e827c6 | 1226 | bank->set_dataout = omap_set_gpio_dataout_mask; |
9f7065da | 1227 | |
4dbada2b | 1228 | raw_spin_lock_init(&bank->lock); |
450fa54c | 1229 | raw_spin_lock_init(&bank->wa_lock); |
9f7065da | 1230 | |
77640aab VC |
1231 | /* Static mapping, never released */ |
1232 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
717f70e3 JH |
1233 | bank->base = devm_ioremap_resource(dev, res); |
1234 | if (IS_ERR(bank->base)) { | |
717f70e3 | 1235 | return PTR_ERR(bank->base); |
5e1c5ff4 TL |
1236 | } |
1237 | ||
5d9452e7 | 1238 | if (bank->dbck_flag) { |
7b1e5dc8 | 1239 | bank->dbck = devm_clk_get(dev, "dbclk"); |
5d9452e7 | 1240 | if (IS_ERR(bank->dbck)) { |
7b1e5dc8 | 1241 | dev_err(dev, |
5d9452e7 GS |
1242 | "Could not get gpio dbck. Disable debounce\n"); |
1243 | bank->dbck_flag = false; | |
1244 | } else { | |
1245 | clk_prepare(bank->dbck); | |
1246 | } | |
1247 | } | |
1248 | ||
065cd795 TKD |
1249 | platform_set_drvdata(pdev, bank); |
1250 | ||
7b1e5dc8 GS |
1251 | pm_runtime_enable(dev); |
1252 | pm_runtime_irq_safe(dev); | |
1253 | pm_runtime_get_sync(dev); | |
77640aab | 1254 | |
d0d665a8 | 1255 | if (bank->is_mpuio) |
a0e827c6 | 1256 | omap_mpuio_init(bank); |
ab985f0f | 1257 | |
03e128ca | 1258 | omap_gpio_mod_init(bank); |
6ef7f385 | 1259 | |
46824e22 | 1260 | ret = omap_gpio_chip_init(bank, irqc); |
5e606abe | 1261 | if (ret) { |
7b1e5dc8 GS |
1262 | pm_runtime_put_sync(dev); |
1263 | pm_runtime_disable(dev); | |
6ef7f385 | 1264 | return ret; |
5e606abe | 1265 | } |
6ef7f385 | 1266 | |
9a748053 | 1267 | omap_gpio_show_rev(bank); |
9f7065da | 1268 | |
7b1e5dc8 | 1269 | pm_runtime_put(dev); |
55b93c32 | 1270 | |
03e128ca | 1271 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1272 | |
879fe324 | 1273 | return 0; |
5e1c5ff4 TL |
1274 | } |
1275 | ||
cac089f9 TL |
1276 | static int omap_gpio_remove(struct platform_device *pdev) |
1277 | { | |
1278 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1279 | ||
1280 | list_del(&bank->node); | |
1281 | gpiochip_remove(&bank->chip); | |
7b1e5dc8 | 1282 | pm_runtime_disable(&pdev->dev); |
5d9452e7 GS |
1283 | if (bank->dbck_flag) |
1284 | clk_unprepare(bank->dbck); | |
cac089f9 TL |
1285 | |
1286 | return 0; | |
1287 | } | |
1288 | ||
55b93c32 TKD |
1289 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1290 | ||
ecb2312f | 1291 | #if defined(CONFIG_PM) |
60a3437d | 1292 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1293 | |
2dc983c5 | 1294 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1295 | { |
2dc983c5 TKD |
1296 | struct platform_device *pdev = to_platform_device(dev); |
1297 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1298 | u32 l1 = 0, l2 = 0; | |
1299 | unsigned long flags; | |
68942edb | 1300 | u32 wake_low, wake_hi; |
8865b9b6 | 1301 | |
4dbada2b | 1302 | raw_spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1303 | |
1304 | /* | |
1305 | * Only edges can generate a wakeup event to the PRCM. | |
1306 | * | |
1307 | * Therefore, ensure any wake-up capable GPIOs have | |
1308 | * edge-detection enabled before going idle to ensure a wakeup | |
1309 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1310 | * NDA TRM 25.5.3.1) | |
1311 | * | |
1312 | * The normal values will be restored upon ->runtime_resume() | |
1313 | * by writing back the values saved in bank->context. | |
1314 | */ | |
1315 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1316 | if (wake_low) | |
661553b9 | 1317 | writel_relaxed(wake_low | bank->context.fallingdetect, |
68942edb KH |
1318 | bank->base + bank->regs->fallingdetect); |
1319 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1320 | if (wake_hi) | |
661553b9 | 1321 | writel_relaxed(wake_hi | bank->context.risingdetect, |
68942edb KH |
1322 | bank->base + bank->regs->risingdetect); |
1323 | ||
b3c64bc3 KH |
1324 | if (!bank->enabled_non_wakeup_gpios) |
1325 | goto update_gpio_context_count; | |
1326 | ||
2dc983c5 TKD |
1327 | if (bank->power_mode != OFF_MODE) { |
1328 | bank->power_mode = 0; | |
41d87cbd | 1329 | goto update_gpio_context_count; |
2dc983c5 TKD |
1330 | } |
1331 | /* | |
1332 | * If going to OFF, remove triggering for all | |
1333 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1334 | * generated. See OMAP2420 Errata item 1.101. | |
1335 | */ | |
661553b9 | 1336 | bank->saved_datain = readl_relaxed(bank->base + |
2dc983c5 | 1337 | bank->regs->datain); |
c6f31c9e TKD |
1338 | l1 = bank->context.fallingdetect; |
1339 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1340 | |
2dc983c5 TKD |
1341 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1342 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1343 | |
661553b9 VK |
1344 | writel_relaxed(l1, bank->base + bank->regs->fallingdetect); |
1345 | writel_relaxed(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1346 | |
2dc983c5 | 1347 | bank->workaround_enabled = true; |
3f1686a9 | 1348 | |
41d87cbd | 1349 | update_gpio_context_count: |
2dc983c5 TKD |
1350 | if (bank->get_context_loss_count) |
1351 | bank->context_loss_count = | |
7b1e5dc8 | 1352 | bank->get_context_loss_count(dev); |
60a3437d | 1353 | |
a0e827c6 | 1354 | omap_gpio_dbck_disable(bank); |
4dbada2b | 1355 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1356 | |
2dc983c5 | 1357 | return 0; |
3ac4fa99 JY |
1358 | } |
1359 | ||
352a2d5b JH |
1360 | static void omap_gpio_init_context(struct gpio_bank *p); |
1361 | ||
2dc983c5 | 1362 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1363 | { |
2dc983c5 TKD |
1364 | struct platform_device *pdev = to_platform_device(dev); |
1365 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
2dc983c5 TKD |
1366 | u32 l = 0, gen, gen0, gen1; |
1367 | unsigned long flags; | |
a2797bea | 1368 | int c; |
8865b9b6 | 1369 | |
4dbada2b | 1370 | raw_spin_lock_irqsave(&bank->lock, flags); |
352a2d5b JH |
1371 | |
1372 | /* | |
1373 | * On the first resume during the probe, the context has not | |
1374 | * been initialised and so initialise it now. Also initialise | |
1375 | * the context loss count. | |
1376 | */ | |
1377 | if (bank->loses_context && !bank->context_valid) { | |
1378 | omap_gpio_init_context(bank); | |
1379 | ||
1380 | if (bank->get_context_loss_count) | |
1381 | bank->context_loss_count = | |
7b1e5dc8 | 1382 | bank->get_context_loss_count(dev); |
352a2d5b JH |
1383 | } |
1384 | ||
a0e827c6 | 1385 | omap_gpio_dbck_enable(bank); |
68942edb KH |
1386 | |
1387 | /* | |
1388 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1389 | * GPIOs were set to edge trigger also in order to be able to | |
1390 | * generate a PRCM wakeup. Here we restore the | |
1391 | * pre-runtime_suspend() values for edge triggering. | |
1392 | */ | |
661553b9 | 1393 | writel_relaxed(bank->context.fallingdetect, |
68942edb | 1394 | bank->base + bank->regs->fallingdetect); |
661553b9 | 1395 | writel_relaxed(bank->context.risingdetect, |
68942edb KH |
1396 | bank->base + bank->regs->risingdetect); |
1397 | ||
a2797bea JH |
1398 | if (bank->loses_context) { |
1399 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1400 | omap_gpio_restore_context(bank); |
1401 | } else { | |
7b1e5dc8 | 1402 | c = bank->get_context_loss_count(dev); |
a2797bea JH |
1403 | if (c != bank->context_loss_count) { |
1404 | omap_gpio_restore_context(bank); | |
1405 | } else { | |
4dbada2b | 1406 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
a2797bea JH |
1407 | return 0; |
1408 | } | |
60a3437d | 1409 | } |
2dc983c5 | 1410 | } |
43ffcd9a | 1411 | |
1b128703 | 1412 | if (!bank->workaround_enabled) { |
4dbada2b | 1413 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1b128703 TKD |
1414 | return 0; |
1415 | } | |
1416 | ||
661553b9 | 1417 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1418 | |
2dc983c5 TKD |
1419 | /* |
1420 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1421 | * state. If so, generate an IRQ by software. This is | |
1422 | * horribly racy, but it's the best we can do to work around | |
1423 | * this silicon bug. | |
1424 | */ | |
1425 | l ^= bank->saved_datain; | |
1426 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1427 | |
2dc983c5 TKD |
1428 | /* |
1429 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1430 | * configured with falling edge only; and vice versa. | |
1431 | */ | |
c6f31c9e | 1432 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1433 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1434 | |
c6f31c9e | 1435 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1436 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1437 | |
2dc983c5 | 1438 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1439 | gen = l & (~(bank->context.fallingdetect) & |
1440 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1441 | /* Consider all GPIO IRQs needed to be updated */ |
1442 | gen |= gen0 | gen1; | |
82dbb9d3 | 1443 | |
2dc983c5 TKD |
1444 | if (gen) { |
1445 | u32 old0, old1; | |
82dbb9d3 | 1446 | |
661553b9 VK |
1447 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1448 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1449 | |
4e962e89 | 1450 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1451 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1452 | bank->regs->leveldetect0); |
661553b9 | 1453 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1454 | bank->regs->leveldetect1); |
2dc983c5 | 1455 | } |
9ea14d8c | 1456 | |
4e962e89 | 1457 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1458 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1459 | bank->regs->leveldetect0); |
661553b9 | 1460 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1461 | bank->regs->leveldetect1); |
3ac4fa99 | 1462 | } |
661553b9 VK |
1463 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1464 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 TKD |
1465 | } |
1466 | ||
1467 | bank->workaround_enabled = false; | |
4dbada2b | 1468 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2dc983c5 TKD |
1469 | |
1470 | return 0; | |
1471 | } | |
ecb2312f | 1472 | #endif /* CONFIG_PM */ |
2dc983c5 | 1473 | |
cac089f9 | 1474 | #if IS_BUILTIN(CONFIG_GPIO_OMAP) |
2dc983c5 TKD |
1475 | void omap2_gpio_prepare_for_idle(int pwr_mode) |
1476 | { | |
1477 | struct gpio_bank *bank; | |
1478 | ||
1479 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1480 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1481 | continue; |
1482 | ||
1483 | bank->power_mode = pwr_mode; | |
1484 | ||
7b1e5dc8 | 1485 | pm_runtime_put_sync_suspend(bank->chip.parent); |
2dc983c5 TKD |
1486 | } |
1487 | } | |
1488 | ||
1489 | void omap2_gpio_resume_after_idle(void) | |
1490 | { | |
1491 | struct gpio_bank *bank; | |
1492 | ||
1493 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1494 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1495 | continue; |
1496 | ||
7b1e5dc8 | 1497 | pm_runtime_get_sync(bank->chip.parent); |
3ac4fa99 | 1498 | } |
3ac4fa99 | 1499 | } |
cac089f9 | 1500 | #endif |
3ac4fa99 | 1501 | |
ecb2312f | 1502 | #if defined(CONFIG_PM) |
352a2d5b JH |
1503 | static void omap_gpio_init_context(struct gpio_bank *p) |
1504 | { | |
1505 | struct omap_gpio_reg_offs *regs = p->regs; | |
1506 | void __iomem *base = p->base; | |
1507 | ||
661553b9 VK |
1508 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1509 | p->context.oe = readl_relaxed(base + regs->direction); | |
1510 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1511 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1512 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1513 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1514 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1515 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1516 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
352a2d5b JH |
1517 | |
1518 | if (regs->set_dataout && p->regs->clr_dataout) | |
661553b9 | 1519 | p->context.dataout = readl_relaxed(base + regs->set_dataout); |
352a2d5b | 1520 | else |
661553b9 | 1521 | p->context.dataout = readl_relaxed(base + regs->dataout); |
352a2d5b JH |
1522 | |
1523 | p->context_valid = true; | |
1524 | } | |
1525 | ||
60a3437d | 1526 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1527 | { |
661553b9 | 1528 | writel_relaxed(bank->context.wake_en, |
ae10f233 | 1529 | bank->base + bank->regs->wkup_en); |
661553b9 VK |
1530 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); |
1531 | writel_relaxed(bank->context.leveldetect0, | |
ae10f233 | 1532 | bank->base + bank->regs->leveldetect0); |
661553b9 | 1533 | writel_relaxed(bank->context.leveldetect1, |
ae10f233 | 1534 | bank->base + bank->regs->leveldetect1); |
661553b9 | 1535 | writel_relaxed(bank->context.risingdetect, |
ae10f233 | 1536 | bank->base + bank->regs->risingdetect); |
661553b9 | 1537 | writel_relaxed(bank->context.fallingdetect, |
ae10f233 | 1538 | bank->base + bank->regs->fallingdetect); |
f86bcc30 | 1539 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
661553b9 | 1540 | writel_relaxed(bank->context.dataout, |
f86bcc30 NM |
1541 | bank->base + bank->regs->set_dataout); |
1542 | else | |
661553b9 | 1543 | writel_relaxed(bank->context.dataout, |
f86bcc30 | 1544 | bank->base + bank->regs->dataout); |
661553b9 | 1545 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); |
6d13eaaf | 1546 | |
ae547354 | 1547 | if (bank->dbck_enable_mask) { |
661553b9 | 1548 | writel_relaxed(bank->context.debounce, bank->base + |
ae547354 | 1549 | bank->regs->debounce); |
661553b9 | 1550 | writel_relaxed(bank->context.debounce_en, |
ae547354 NM |
1551 | bank->base + bank->regs->debounce_en); |
1552 | } | |
ba805be5 | 1553 | |
661553b9 | 1554 | writel_relaxed(bank->context.irqenable1, |
ba805be5 | 1555 | bank->base + bank->regs->irqenable); |
661553b9 | 1556 | writel_relaxed(bank->context.irqenable2, |
ba805be5 | 1557 | bank->base + bank->regs->irqenable2); |
40c670f0 | 1558 | } |
ecb2312f | 1559 | #endif /* CONFIG_PM */ |
55b93c32 | 1560 | #else |
2dc983c5 TKD |
1561 | #define omap_gpio_runtime_suspend NULL |
1562 | #define omap_gpio_runtime_resume NULL | |
ea4a21a2 | 1563 | static inline void omap_gpio_init_context(struct gpio_bank *p) {} |
40c670f0 RN |
1564 | #endif |
1565 | ||
55b93c32 | 1566 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1567 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1568 | NULL) | |
55b93c32 TKD |
1569 | }; |
1570 | ||
384ebe1c BC |
1571 | #if defined(CONFIG_OF) |
1572 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1573 | .revision = OMAP24XX_GPIO_REVISION, | |
1574 | .direction = OMAP24XX_GPIO_OE, | |
1575 | .datain = OMAP24XX_GPIO_DATAIN, | |
1576 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1577 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1578 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1579 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1580 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1581 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1582 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1583 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1584 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1585 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1586 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1587 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1588 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1589 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1590 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1591 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1592 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1593 | }; | |
1594 | ||
1595 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1596 | .revision = OMAP4_GPIO_REVISION, | |
1597 | .direction = OMAP4_GPIO_OE, | |
1598 | .datain = OMAP4_GPIO_DATAIN, | |
1599 | .dataout = OMAP4_GPIO_DATAOUT, | |
1600 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1601 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1602 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1603 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1604 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1605 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1606 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1607 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1608 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1609 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1610 | .ctrl = OMAP4_GPIO_CTRL, | |
1611 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1612 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1613 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1614 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1615 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1616 | }; | |
1617 | ||
e9a65bb6 | 1618 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1619 | .regs = &omap2_gpio_regs, |
1620 | .bank_width = 32, | |
1621 | .dbck_flag = false, | |
1622 | }; | |
1623 | ||
e9a65bb6 | 1624 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1625 | .regs = &omap2_gpio_regs, |
1626 | .bank_width = 32, | |
1627 | .dbck_flag = true, | |
1628 | }; | |
1629 | ||
e9a65bb6 | 1630 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1631 | .regs = &omap4_gpio_regs, |
1632 | .bank_width = 32, | |
1633 | .dbck_flag = true, | |
1634 | }; | |
1635 | ||
1636 | static const struct of_device_id omap_gpio_match[] = { | |
1637 | { | |
1638 | .compatible = "ti,omap4-gpio", | |
1639 | .data = &omap4_pdata, | |
1640 | }, | |
1641 | { | |
1642 | .compatible = "ti,omap3-gpio", | |
1643 | .data = &omap3_pdata, | |
1644 | }, | |
1645 | { | |
1646 | .compatible = "ti,omap2-gpio", | |
1647 | .data = &omap2_pdata, | |
1648 | }, | |
1649 | { }, | |
1650 | }; | |
1651 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1652 | #endif | |
1653 | ||
77640aab VC |
1654 | static struct platform_driver omap_gpio_driver = { |
1655 | .probe = omap_gpio_probe, | |
cac089f9 | 1656 | .remove = omap_gpio_remove, |
77640aab VC |
1657 | .driver = { |
1658 | .name = "omap_gpio", | |
55b93c32 | 1659 | .pm = &gpio_pm_ops, |
384ebe1c | 1660 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1661 | }, |
1662 | }; | |
1663 | ||
5e1c5ff4 | 1664 | /* |
77640aab VC |
1665 | * gpio driver register needs to be done before |
1666 | * machine_init functions access gpio APIs. | |
1667 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1668 | */ |
77640aab | 1669 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1670 | { |
77640aab | 1671 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1672 | } |
77640aab | 1673 | postcore_initcall(omap_gpio_drv_reg); |
cac089f9 TL |
1674 | |
1675 | static void __exit omap_gpio_exit(void) | |
1676 | { | |
1677 | platform_driver_unregister(&omap_gpio_driver); | |
1678 | } | |
1679 | module_exit(omap_gpio_exit); | |
1680 | ||
1681 | MODULE_DESCRIPTION("omap gpio driver"); | |
1682 | MODULE_ALIAS("platform:gpio-omap"); | |
1683 | MODULE_LICENSE("GPL v2"); |