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Commit | Line | Data |
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5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
77640aab VC |
22 | #include <linux/slab.h> |
23 | #include <linux/pm_runtime.h> | |
5e1c5ff4 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e1c5ff4 | 26 | #include <asm/irq.h> |
a09e64fb RK |
27 | #include <mach/irqs.h> |
28 | #include <mach/gpio.h> | |
5e1c5ff4 TL |
29 | #include <asm/mach/irq.h> |
30 | ||
5e1c5ff4 | 31 | struct gpio_bank { |
9f7065da | 32 | unsigned long pbase; |
92105bb7 | 33 | void __iomem *base; |
5e1c5ff4 TL |
34 | u16 irq; |
35 | u16 virtual_irq_start; | |
92105bb7 | 36 | int method; |
140455fa | 37 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 TL |
38 | u32 suspend_wakeup; |
39 | u32 saved_wakeup; | |
3ac4fa99 | 40 | #endif |
3ac4fa99 JY |
41 | u32 non_wakeup_gpios; |
42 | u32 enabled_non_wakeup_gpios; | |
43 | ||
44 | u32 saved_datain; | |
45 | u32 saved_fallingdetect; | |
46 | u32 saved_risingdetect; | |
b144ff6f | 47 | u32 level_mask; |
4318f36b | 48 | u32 toggle_mask; |
5e1c5ff4 | 49 | spinlock_t lock; |
52e31344 | 50 | struct gpio_chip chip; |
89db9482 | 51 | struct clk *dbck; |
058af1ea | 52 | u32 mod_usage; |
8865b9b6 | 53 | u32 dbck_enable_mask; |
77640aab VC |
54 | struct device *dev; |
55 | bool dbck_flag; | |
5de62b86 | 56 | int stride; |
d5f46247 | 57 | u32 width; |
fa87931a KH |
58 | |
59 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60 | ||
61 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
62 | }; |
63 | ||
a8eb7ca0 | 64 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 | 65 | struct omap3_gpio_regs { |
40c670f0 RN |
66 | u32 irqenable1; |
67 | u32 irqenable2; | |
68 | u32 wake_en; | |
69 | u32 ctrl; | |
70 | u32 oe; | |
71 | u32 leveldetect0; | |
72 | u32 leveldetect1; | |
73 | u32 risingdetect; | |
74 | u32 fallingdetect; | |
75 | u32 dataout; | |
5492fb1a SMK |
76 | }; |
77 | ||
40c670f0 | 78 | static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; |
5492fb1a SMK |
79 | #endif |
80 | ||
77640aab VC |
81 | /* |
82 | * TODO: Cleanup gpio_bank usage as it is having information | |
83 | * related to all instances of the device | |
84 | */ | |
85 | static struct gpio_bank *gpio_bank; | |
44169075 | 86 | |
c95d10bc VC |
87 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ |
88 | int gpio_bank_count; | |
5e1c5ff4 | 89 | |
129fd223 KH |
90 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
91 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
92 | ||
5e1c5ff4 TL |
93 | static inline int gpio_valid(int gpio) |
94 | { | |
95 | if (gpio < 0) | |
96 | return -1; | |
d11ac979 | 97 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 98 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
99 | return -1; |
100 | return 0; | |
101 | } | |
6e60e79a | 102 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 103 | return 0; |
5e1c5ff4 TL |
104 | if ((cpu_is_omap16xx()) && gpio < 64) |
105 | return 0; | |
56739a69 | 106 | if (cpu_is_omap7xx() && gpio < 192) |
5e1c5ff4 | 107 | return 0; |
25d6f630 TL |
108 | if (cpu_is_omap2420() && gpio < 128) |
109 | return 0; | |
110 | if (cpu_is_omap2430() && gpio < 160) | |
92105bb7 | 111 | return 0; |
44169075 | 112 | if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) |
5492fb1a | 113 | return 0; |
5e1c5ff4 TL |
114 | return -1; |
115 | } | |
116 | ||
117 | static int check_gpio(int gpio) | |
118 | { | |
d32b20fc | 119 | if (unlikely(gpio_valid(gpio) < 0)) { |
5e1c5ff4 TL |
120 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); |
121 | dump_stack(); | |
122 | return -1; | |
123 | } | |
124 | return 0; | |
125 | } | |
126 | ||
127 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
128 | { | |
92105bb7 | 129 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
130 | u32 l; |
131 | ||
fa87931a | 132 | reg += bank->regs->direction; |
5e1c5ff4 TL |
133 | l = __raw_readl(reg); |
134 | if (is_input) | |
135 | l |= 1 << gpio; | |
136 | else | |
137 | l &= ~(1 << gpio); | |
138 | __raw_writel(l, reg); | |
139 | } | |
140 | ||
fa87931a KH |
141 | |
142 | /* set data out value using dedicate set/clear register */ | |
143 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 144 | { |
92105bb7 | 145 | void __iomem *reg = bank->base; |
fa87931a | 146 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 147 | |
fa87931a KH |
148 | if (enable) |
149 | reg += bank->regs->set_dataout; | |
150 | else | |
151 | reg += bank->regs->clr_dataout; | |
152 | ||
153 | __raw_writel(l, reg); | |
154 | } | |
155 | ||
156 | /* set data out value using mask register */ | |
157 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
158 | { | |
159 | void __iomem *reg = bank->base + bank->regs->dataout; | |
160 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
161 | u32 l; | |
162 | ||
163 | l = __raw_readl(reg); | |
164 | if (enable) | |
165 | l |= gpio_bit; | |
166 | else | |
167 | l &= ~gpio_bit; | |
5e1c5ff4 TL |
168 | __raw_writel(l, reg); |
169 | } | |
170 | ||
b37c45b8 | 171 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
5e1c5ff4 | 172 | { |
fa87931a | 173 | void __iomem *reg = bank->base + bank->regs->datain; |
5e1c5ff4 TL |
174 | |
175 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 176 | return -EINVAL; |
fa87931a KH |
177 | |
178 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; | |
5e1c5ff4 TL |
179 | } |
180 | ||
b37c45b8 RQ |
181 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
182 | { | |
fa87931a | 183 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 RQ |
184 | |
185 | if (check_gpio(gpio) < 0) | |
186 | return -EINVAL; | |
b37c45b8 | 187 | |
129fd223 | 188 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
b37c45b8 RQ |
189 | } |
190 | ||
92105bb7 TL |
191 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
192 | do { \ | |
193 | int l = __raw_readl(base + reg); \ | |
194 | if (set) l |= bit_mask; \ | |
195 | else l &= ~bit_mask; \ | |
196 | __raw_writel(l, base + reg); \ | |
197 | } while(0) | |
198 | ||
168ef3d9 FB |
199 | /** |
200 | * _set_gpio_debounce - low level gpio debounce time | |
201 | * @bank: the gpio bank we're acting upon | |
202 | * @gpio: the gpio number on this @gpio | |
203 | * @debounce: debounce time to use | |
204 | * | |
205 | * OMAP's debounce time is in 31us steps so we need | |
206 | * to convert and round up to the closest unit. | |
207 | */ | |
208 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
209 | unsigned debounce) | |
210 | { | |
211 | void __iomem *reg = bank->base; | |
212 | u32 val; | |
213 | u32 l; | |
214 | ||
77640aab VC |
215 | if (!bank->dbck_flag) |
216 | return; | |
217 | ||
168ef3d9 FB |
218 | if (debounce < 32) |
219 | debounce = 0x01; | |
220 | else if (debounce > 7936) | |
221 | debounce = 0xff; | |
222 | else | |
223 | debounce = (debounce / 0x1f) - 1; | |
224 | ||
129fd223 | 225 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 226 | |
77640aab | 227 | if (bank->method == METHOD_GPIO_44XX) |
168ef3d9 FB |
228 | reg += OMAP4_GPIO_DEBOUNCINGTIME; |
229 | else | |
230 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
231 | ||
232 | __raw_writel(debounce, reg); | |
233 | ||
234 | reg = bank->base; | |
77640aab | 235 | if (bank->method == METHOD_GPIO_44XX) |
168ef3d9 FB |
236 | reg += OMAP4_GPIO_DEBOUNCENABLE; |
237 | else | |
238 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | |
239 | ||
240 | val = __raw_readl(reg); | |
241 | ||
242 | if (debounce) { | |
243 | val |= l; | |
77640aab | 244 | clk_enable(bank->dbck); |
168ef3d9 FB |
245 | } else { |
246 | val &= ~l; | |
77640aab | 247 | clk_disable(bank->dbck); |
168ef3d9 | 248 | } |
f7ec0b0b | 249 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
250 | |
251 | __raw_writel(val, reg); | |
252 | } | |
253 | ||
140455fa | 254 | #ifdef CONFIG_ARCH_OMAP2PLUS |
5eb3bb9c KH |
255 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
256 | int trigger) | |
5e1c5ff4 | 257 | { |
3ac4fa99 | 258 | void __iomem *base = bank->base; |
92105bb7 TL |
259 | u32 gpio_bit = 1 << gpio; |
260 | ||
78a1a6d3 SR |
261 | if (cpu_is_omap44xx()) { |
262 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit, | |
263 | trigger & IRQ_TYPE_LEVEL_LOW); | |
264 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit, | |
265 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
266 | MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit, | |
267 | trigger & IRQ_TYPE_EDGE_RISING); | |
268 | MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit, | |
269 | trigger & IRQ_TYPE_EDGE_FALLING); | |
270 | } else { | |
271 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
272 | trigger & IRQ_TYPE_LEVEL_LOW); | |
273 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, | |
274 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
275 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, | |
276 | trigger & IRQ_TYPE_EDGE_RISING); | |
277 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, | |
278 | trigger & IRQ_TYPE_EDGE_FALLING); | |
279 | } | |
3ac4fa99 | 280 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
78a1a6d3 | 281 | if (cpu_is_omap44xx()) { |
0622b25b CC |
282 | MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit, |
283 | trigger != 0); | |
78a1a6d3 | 284 | } else { |
699117a6 CW |
285 | /* |
286 | * GPIO wakeup request can only be generated on edge | |
287 | * transitions | |
288 | */ | |
289 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
78a1a6d3 | 290 | __raw_writel(1 << gpio, bank->base |
5eb3bb9c | 291 | + OMAP24XX_GPIO_SETWKUENA); |
78a1a6d3 SR |
292 | else |
293 | __raw_writel(1 << gpio, bank->base | |
5eb3bb9c | 294 | + OMAP24XX_GPIO_CLEARWKUENA); |
78a1a6d3 | 295 | } |
a118b5f3 TK |
296 | } |
297 | /* This part needs to be executed always for OMAP34xx */ | |
298 | if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) { | |
699117a6 CW |
299 | /* |
300 | * Log the edge gpio and manually trigger the IRQ | |
301 | * after resume if the input level changes | |
302 | * to avoid irq lost during PER RET/OFF mode | |
303 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
304 | */ | |
305 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
306 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
307 | else | |
308 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
309 | } | |
5eb3bb9c | 310 | |
78a1a6d3 SR |
311 | if (cpu_is_omap44xx()) { |
312 | bank->level_mask = | |
313 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | | |
314 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); | |
315 | } else { | |
316 | bank->level_mask = | |
317 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
318 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
319 | } | |
92105bb7 | 320 | } |
3ac4fa99 | 321 | #endif |
92105bb7 | 322 | |
9198bcd3 | 323 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
324 | /* |
325 | * This only applies to chips that can't do both rising and falling edge | |
326 | * detection at once. For all other chips, this function is a noop. | |
327 | */ | |
328 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
329 | { | |
330 | void __iomem *reg = bank->base; | |
331 | u32 l = 0; | |
332 | ||
333 | switch (bank->method) { | |
4318f36b | 334 | case METHOD_MPUIO: |
5de62b86 | 335 | reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; |
4318f36b | 336 | break; |
4318f36b CM |
337 | #ifdef CONFIG_ARCH_OMAP15XX |
338 | case METHOD_GPIO_1510: | |
339 | reg += OMAP1510_GPIO_INT_CONTROL; | |
340 | break; | |
341 | #endif | |
342 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | |
343 | case METHOD_GPIO_7XX: | |
344 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
345 | break; | |
346 | #endif | |
347 | default: | |
348 | return; | |
349 | } | |
350 | ||
351 | l = __raw_readl(reg); | |
352 | if ((l >> gpio) & 1) | |
353 | l &= ~(1 << gpio); | |
354 | else | |
355 | l |= 1 << gpio; | |
356 | ||
357 | __raw_writel(l, reg); | |
358 | } | |
9198bcd3 | 359 | #endif |
4318f36b | 360 | |
92105bb7 TL |
361 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
362 | { | |
363 | void __iomem *reg = bank->base; | |
364 | u32 l = 0; | |
5e1c5ff4 TL |
365 | |
366 | switch (bank->method) { | |
e5c56ed3 | 367 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 368 | case METHOD_MPUIO: |
5de62b86 | 369 | reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; |
5e1c5ff4 | 370 | l = __raw_readl(reg); |
29501577 | 371 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 372 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 373 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 374 | l |= 1 << gpio; |
6cab4860 | 375 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 376 | l &= ~(1 << gpio); |
92105bb7 TL |
377 | else |
378 | goto bad; | |
5e1c5ff4 | 379 | break; |
e5c56ed3 DB |
380 | #endif |
381 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
382 | case METHOD_GPIO_1510: |
383 | reg += OMAP1510_GPIO_INT_CONTROL; | |
384 | l = __raw_readl(reg); | |
29501577 | 385 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 386 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 387 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 388 | l |= 1 << gpio; |
6cab4860 | 389 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 390 | l &= ~(1 << gpio); |
92105bb7 TL |
391 | else |
392 | goto bad; | |
5e1c5ff4 | 393 | break; |
e5c56ed3 | 394 | #endif |
3ac4fa99 | 395 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 396 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
397 | if (gpio & 0x08) |
398 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
399 | else | |
400 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
401 | gpio &= 0x07; | |
402 | l = __raw_readl(reg); | |
403 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 404 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 405 | l |= 2 << (gpio << 1); |
6cab4860 | 406 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 407 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
408 | if (trigger) |
409 | /* Enable wake-up during idle for dynamic tick */ | |
410 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
411 | else | |
412 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 413 | break; |
3ac4fa99 | 414 | #endif |
b718aa81 | 415 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
416 | case METHOD_GPIO_7XX: |
417 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
56739a69 | 418 | l = __raw_readl(reg); |
29501577 | 419 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 420 | bank->toggle_mask |= 1 << gpio; |
56739a69 ZM |
421 | if (trigger & IRQ_TYPE_EDGE_RISING) |
422 | l |= 1 << gpio; | |
423 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | |
424 | l &= ~(1 << gpio); | |
425 | else | |
426 | goto bad; | |
427 | break; | |
428 | #endif | |
140455fa | 429 | #ifdef CONFIG_ARCH_OMAP2PLUS |
92105bb7 | 430 | case METHOD_GPIO_24XX: |
3f1686a9 | 431 | case METHOD_GPIO_44XX: |
3ac4fa99 | 432 | set_24xx_gpio_triggering(bank, gpio, trigger); |
f7c5cc45 | 433 | return 0; |
3ac4fa99 | 434 | #endif |
5e1c5ff4 | 435 | default: |
92105bb7 | 436 | goto bad; |
5e1c5ff4 | 437 | } |
92105bb7 TL |
438 | __raw_writel(l, reg); |
439 | return 0; | |
440 | bad: | |
441 | return -EINVAL; | |
5e1c5ff4 TL |
442 | } |
443 | ||
e9191028 | 444 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 TL |
445 | { |
446 | struct gpio_bank *bank; | |
92105bb7 TL |
447 | unsigned gpio; |
448 | int retval; | |
a6472533 | 449 | unsigned long flags; |
92105bb7 | 450 | |
e9191028 LB |
451 | if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) |
452 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | |
92105bb7 | 453 | else |
e9191028 | 454 | gpio = d->irq - IH_GPIO_BASE; |
5e1c5ff4 TL |
455 | |
456 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
457 | return -EINVAL; |
458 | ||
e5c56ed3 | 459 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 460 | return -EINVAL; |
e5c56ed3 DB |
461 | |
462 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 463 | if (!cpu_class_is_omap2() |
e5c56ed3 | 464 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
465 | return -EINVAL; |
466 | ||
e9191028 | 467 | bank = irq_data_get_irq_chip_data(d); |
a6472533 | 468 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 469 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
a6472533 | 470 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
471 | |
472 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 473 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 474 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 475 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 476 | |
92105bb7 | 477 | return retval; |
5e1c5ff4 TL |
478 | } |
479 | ||
480 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
481 | { | |
92105bb7 | 482 | void __iomem *reg = bank->base; |
5e1c5ff4 | 483 | |
eef4bec7 | 484 | reg += bank->regs->irqstatus; |
5e1c5ff4 | 485 | __raw_writel(gpio_mask, reg); |
bee7930f HD |
486 | |
487 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
488 | if (bank->regs->irqstatus2) { |
489 | reg = bank->base + bank->regs->irqstatus2; | |
bedfd154 | 490 | __raw_writel(gpio_mask, reg); |
eef4bec7 | 491 | } |
bedfd154 RQ |
492 | |
493 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
494 | __raw_readl(reg); | |
5e1c5ff4 TL |
495 | } |
496 | ||
497 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
498 | { | |
129fd223 | 499 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
500 | } |
501 | ||
ea6dedd7 ID |
502 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
503 | { | |
504 | void __iomem *reg = bank->base; | |
99c47707 | 505 | u32 l; |
c390aad0 | 506 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 507 | |
28f3b5a0 | 508 | reg += bank->regs->irqenable; |
99c47707 | 509 | l = __raw_readl(reg); |
28f3b5a0 | 510 | if (bank->regs->irqenable_inv) |
99c47707 ID |
511 | l = ~l; |
512 | l &= mask; | |
513 | return l; | |
ea6dedd7 ID |
514 | } |
515 | ||
28f3b5a0 | 516 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 517 | { |
92105bb7 | 518 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
519 | u32 l; |
520 | ||
28f3b5a0 KH |
521 | if (bank->regs->set_irqenable) { |
522 | reg += bank->regs->set_irqenable; | |
523 | l = gpio_mask; | |
524 | } else { | |
525 | reg += bank->regs->irqenable; | |
5e1c5ff4 | 526 | l = __raw_readl(reg); |
28f3b5a0 KH |
527 | if (bank->regs->irqenable_inv) |
528 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
529 | else |
530 | l |= gpio_mask; | |
28f3b5a0 KH |
531 | } |
532 | ||
533 | __raw_writel(l, reg); | |
534 | } | |
535 | ||
536 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
537 | { | |
538 | void __iomem *reg = bank->base; | |
539 | u32 l; | |
540 | ||
541 | if (bank->regs->clr_irqenable) { | |
542 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 543 | l = gpio_mask; |
28f3b5a0 KH |
544 | } else { |
545 | reg += bank->regs->irqenable; | |
56739a69 | 546 | l = __raw_readl(reg); |
28f3b5a0 | 547 | if (bank->regs->irqenable_inv) |
56739a69 | 548 | l |= gpio_mask; |
78a1a6d3 | 549 | else |
28f3b5a0 | 550 | l &= ~gpio_mask; |
5e1c5ff4 | 551 | } |
28f3b5a0 | 552 | |
5e1c5ff4 TL |
553 | __raw_writel(l, reg); |
554 | } | |
555 | ||
556 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
557 | { | |
28f3b5a0 | 558 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
559 | } |
560 | ||
92105bb7 TL |
561 | /* |
562 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
563 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
564 | * to the target, system will wake up always on GPIO events. While | |
565 | * system is running all registered GPIO interrupts need to have wake-up | |
566 | * enabled. When system is suspended, only selected GPIO interrupts need | |
567 | * to have wake-up enabled. | |
568 | */ | |
569 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
570 | { | |
4cc6420c | 571 | unsigned long uninitialized_var(flags); |
a6472533 | 572 | |
92105bb7 | 573 | switch (bank->method) { |
3ac4fa99 | 574 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 575 | case METHOD_MPUIO: |
92105bb7 | 576 | case METHOD_GPIO_1610: |
a6472533 | 577 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 578 | if (enable) |
92105bb7 | 579 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 580 | else |
92105bb7 | 581 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 582 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 583 | return 0; |
3ac4fa99 | 584 | #endif |
140455fa | 585 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 | 586 | case METHOD_GPIO_24XX: |
3f1686a9 | 587 | case METHOD_GPIO_44XX: |
11a78b79 DB |
588 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
589 | printk(KERN_ERR "Unable to modify wakeup on " | |
590 | "non-wakeup GPIO%d\n", | |
d5f46247 | 591 | (bank - gpio_bank) * bank->width + gpio); |
11a78b79 DB |
592 | return -EINVAL; |
593 | } | |
a6472533 | 594 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 595 | if (enable) |
3ac4fa99 | 596 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 597 | else |
3ac4fa99 | 598 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 599 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
600 | return 0; |
601 | #endif | |
92105bb7 TL |
602 | default: |
603 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
604 | bank->method); | |
605 | return -EINVAL; | |
606 | } | |
607 | } | |
608 | ||
4196dd6b TL |
609 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
610 | { | |
129fd223 | 611 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
612 | _set_gpio_irqenable(bank, gpio, 0); |
613 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 614 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
615 | } |
616 | ||
92105bb7 | 617 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 618 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 619 | { |
e9191028 | 620 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
92105bb7 TL |
621 | struct gpio_bank *bank; |
622 | int retval; | |
623 | ||
624 | if (check_gpio(gpio) < 0) | |
625 | return -ENODEV; | |
e9191028 | 626 | bank = irq_data_get_irq_chip_data(d); |
129fd223 | 627 | retval = _set_gpio_wakeup(bank, GPIO_INDEX(bank, gpio), enable); |
92105bb7 TL |
628 | |
629 | return retval; | |
630 | } | |
631 | ||
3ff164e1 | 632 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 633 | { |
3ff164e1 | 634 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 635 | unsigned long flags; |
52e31344 | 636 | |
a6472533 | 637 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 638 | |
4196dd6b TL |
639 | /* Set trigger to none. You need to enable the desired trigger with |
640 | * request_irq() or set_irq_type(). | |
641 | */ | |
3ff164e1 | 642 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 643 | |
1a8bfa1e | 644 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 645 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 646 | void __iomem *reg; |
5e1c5ff4 | 647 | |
92105bb7 | 648 | /* Claim the pin for MPU */ |
5e1c5ff4 | 649 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 650 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
651 | } |
652 | #endif | |
058af1ea C |
653 | if (!cpu_class_is_omap1()) { |
654 | if (!bank->mod_usage) { | |
9f096868 | 655 | void __iomem *reg = bank->base; |
058af1ea | 656 | u32 ctrl; |
9f096868 C |
657 | |
658 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
659 | reg += OMAP24XX_GPIO_CTRL; | |
660 | else if (cpu_is_omap44xx()) | |
661 | reg += OMAP4_GPIO_CTRL; | |
662 | ctrl = __raw_readl(reg); | |
058af1ea | 663 | /* Module is enabled, clocks are not gated */ |
9f096868 C |
664 | ctrl &= 0xFFFFFFFE; |
665 | __raw_writel(ctrl, reg); | |
058af1ea C |
666 | } |
667 | bank->mod_usage |= 1 << offset; | |
668 | } | |
a6472533 | 669 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
670 | |
671 | return 0; | |
672 | } | |
673 | ||
3ff164e1 | 674 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 675 | { |
3ff164e1 | 676 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 677 | unsigned long flags; |
5e1c5ff4 | 678 | |
a6472533 | 679 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
680 | #ifdef CONFIG_ARCH_OMAP16XX |
681 | if (bank->method == METHOD_GPIO_1610) { | |
682 | /* Disable wake-up during idle for dynamic tick */ | |
683 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 684 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
685 | } |
686 | #endif | |
9f096868 C |
687 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
688 | if (bank->method == METHOD_GPIO_24XX) { | |
92105bb7 TL |
689 | /* Disable wake-up during idle for dynamic tick */ |
690 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 691 | __raw_writel(1 << offset, reg); |
92105bb7 | 692 | } |
9f096868 C |
693 | #endif |
694 | #ifdef CONFIG_ARCH_OMAP4 | |
695 | if (bank->method == METHOD_GPIO_44XX) { | |
696 | /* Disable wake-up during idle for dynamic tick */ | |
697 | void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
698 | __raw_writel(1 << offset, reg); | |
699 | } | |
92105bb7 | 700 | #endif |
058af1ea C |
701 | if (!cpu_class_is_omap1()) { |
702 | bank->mod_usage &= ~(1 << offset); | |
703 | if (!bank->mod_usage) { | |
9f096868 | 704 | void __iomem *reg = bank->base; |
058af1ea | 705 | u32 ctrl; |
9f096868 C |
706 | |
707 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
708 | reg += OMAP24XX_GPIO_CTRL; | |
709 | else if (cpu_is_omap44xx()) | |
710 | reg += OMAP4_GPIO_CTRL; | |
711 | ctrl = __raw_readl(reg); | |
058af1ea C |
712 | /* Module is disabled, clocks are gated */ |
713 | ctrl |= 1; | |
9f096868 | 714 | __raw_writel(ctrl, reg); |
058af1ea C |
715 | } |
716 | } | |
3ff164e1 | 717 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 718 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
719 | } |
720 | ||
721 | /* | |
722 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
723 | * avoid missing GPIO interrupts for other lines in the bank. | |
724 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
725 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
726 | * If we wait to unmask individual GPIO lines in the bank after the | |
727 | * line's interrupt handler has been run, we may miss some nested | |
728 | * interrupts. | |
729 | */ | |
10dd5ce2 | 730 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 731 | { |
92105bb7 | 732 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 733 | u32 isr; |
4318f36b | 734 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 735 | struct gpio_bank *bank; |
ea6dedd7 ID |
736 | u32 retrigger = 0; |
737 | int unmasked = 0; | |
ee144182 | 738 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 739 | |
ee144182 | 740 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 741 | |
6845664a | 742 | bank = irq_get_handler_data(irq); |
eef4bec7 | 743 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
744 | |
745 | if (WARN_ON(!isr_reg)) | |
746 | goto exit; | |
747 | ||
92105bb7 | 748 | while(1) { |
6e60e79a | 749 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 750 | u32 enabled; |
6e60e79a | 751 | |
ea6dedd7 ID |
752 | enabled = _get_gpio_irqbank_mask(bank); |
753 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
754 | |
755 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
756 | isr &= 0x0000ffff; | |
757 | ||
5492fb1a | 758 | if (cpu_class_is_omap2()) { |
b144ff6f | 759 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 760 | } |
6e60e79a TL |
761 | |
762 | /* clear edge sensitive interrupts before handler(s) are | |
763 | called so that we don't miss any interrupt occurred while | |
764 | executing them */ | |
28f3b5a0 | 765 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 766 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 767 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
768 | |
769 | /* if there is only edge sensitive GPIO pin interrupts | |
770 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
771 | if (!level_mask && !unmasked) { |
772 | unmasked = 1; | |
ee144182 | 773 | chained_irq_exit(chip, desc); |
ea6dedd7 | 774 | } |
92105bb7 | 775 | |
ea6dedd7 ID |
776 | isr |= retrigger; |
777 | retrigger = 0; | |
92105bb7 TL |
778 | if (!isr) |
779 | break; | |
780 | ||
781 | gpio_irq = bank->virtual_irq_start; | |
782 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
129fd223 | 783 | gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq)); |
4318f36b | 784 | |
92105bb7 TL |
785 | if (!(isr & 1)) |
786 | continue; | |
29454dde | 787 | |
4318f36b CM |
788 | #ifdef CONFIG_ARCH_OMAP1 |
789 | /* | |
790 | * Some chips can't respond to both rising and falling | |
791 | * at the same time. If this irq was requested with | |
792 | * both flags, we need to flip the ICR data for the IRQ | |
793 | * to respond to the IRQ for the opposite direction. | |
794 | * This will be indicated in the bank toggle_mask. | |
795 | */ | |
796 | if (bank->toggle_mask & (1 << gpio_index)) | |
797 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
798 | #endif | |
799 | ||
d8aa0251 | 800 | generic_handle_irq(gpio_irq); |
92105bb7 | 801 | } |
1a8bfa1e | 802 | } |
ea6dedd7 ID |
803 | /* if bank has any level sensitive GPIO pin interrupt |
804 | configured, we must unmask the bank interrupt only after | |
805 | handler(s) are executed in order to avoid spurious bank | |
806 | interrupt */ | |
b1cc4c55 | 807 | exit: |
ea6dedd7 | 808 | if (!unmasked) |
ee144182 | 809 | chained_irq_exit(chip, desc); |
5e1c5ff4 TL |
810 | } |
811 | ||
e9191028 | 812 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 813 | { |
e9191028 LB |
814 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
815 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 816 | unsigned long flags; |
4196dd6b | 817 | |
85ec7b97 | 818 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 819 | _reset_gpio(bank, gpio); |
85ec7b97 | 820 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
821 | } |
822 | ||
e9191028 | 823 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 824 | { |
e9191028 LB |
825 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
826 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
827 | |
828 | _clear_gpio_irqstatus(bank, gpio); | |
829 | } | |
830 | ||
e9191028 | 831 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 832 | { |
e9191028 LB |
833 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
834 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 835 | unsigned long flags; |
5e1c5ff4 | 836 | |
85ec7b97 | 837 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 838 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 839 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 840 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
841 | } |
842 | ||
e9191028 | 843 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 844 | { |
e9191028 LB |
845 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
846 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
129fd223 | 847 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 848 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 849 | unsigned long flags; |
55b6019a | 850 | |
85ec7b97 | 851 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 852 | if (trigger) |
129fd223 | 853 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
854 | |
855 | /* For level-triggered GPIOs, the clearing must be done after | |
856 | * the HW source is cleared, thus after the handler has run */ | |
857 | if (bank->level_mask & irq_mask) { | |
858 | _set_gpio_irqenable(bank, gpio, 0); | |
859 | _clear_gpio_irqstatus(bank, gpio); | |
860 | } | |
5e1c5ff4 | 861 | |
4de8c75b | 862 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 863 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
864 | } |
865 | ||
e5c56ed3 DB |
866 | static struct irq_chip gpio_irq_chip = { |
867 | .name = "GPIO", | |
e9191028 LB |
868 | .irq_shutdown = gpio_irq_shutdown, |
869 | .irq_ack = gpio_ack_irq, | |
870 | .irq_mask = gpio_mask_irq, | |
871 | .irq_unmask = gpio_unmask_irq, | |
872 | .irq_set_type = gpio_irq_type, | |
873 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
874 | }; |
875 | ||
876 | /*---------------------------------------------------------------------*/ | |
877 | ||
878 | #ifdef CONFIG_ARCH_OMAP1 | |
879 | ||
880 | /* MPUIO uses the always-on 32k clock */ | |
881 | ||
e9191028 | 882 | static void mpuio_ack_irq(struct irq_data *d) |
5e1c5ff4 TL |
883 | { |
884 | /* The ISR is reset automatically, so do nothing here. */ | |
885 | } | |
886 | ||
e9191028 | 887 | static void mpuio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 888 | { |
e9191028 LB |
889 | unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
890 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
891 | |
892 | _set_gpio_irqenable(bank, gpio, 0); | |
893 | } | |
894 | ||
e9191028 | 895 | static void mpuio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 896 | { |
e9191028 LB |
897 | unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
898 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
899 | |
900 | _set_gpio_irqenable(bank, gpio, 1); | |
901 | } | |
902 | ||
e5c56ed3 DB |
903 | static struct irq_chip mpuio_irq_chip = { |
904 | .name = "MPUIO", | |
e9191028 LB |
905 | .irq_ack = mpuio_ack_irq, |
906 | .irq_mask = mpuio_mask_irq, | |
907 | .irq_unmask = mpuio_unmask_irq, | |
908 | .irq_set_type = gpio_irq_type, | |
11a78b79 DB |
909 | #ifdef CONFIG_ARCH_OMAP16XX |
910 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
e9191028 | 911 | .irq_set_wake = gpio_wake_enable, |
11a78b79 | 912 | #endif |
5e1c5ff4 TL |
913 | }; |
914 | ||
e5c56ed3 DB |
915 | |
916 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
917 | ||
11a78b79 DB |
918 | |
919 | #ifdef CONFIG_ARCH_OMAP16XX | |
920 | ||
921 | #include <linux/platform_device.h> | |
922 | ||
79ee031f | 923 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 924 | { |
79ee031f | 925 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 926 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
927 | void __iomem *mask_reg = bank->base + |
928 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 929 | unsigned long flags; |
11a78b79 | 930 | |
a6472533 | 931 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
932 | bank->saved_wakeup = __raw_readl(mask_reg); |
933 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 934 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
935 | |
936 | return 0; | |
937 | } | |
938 | ||
79ee031f | 939 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 940 | { |
79ee031f | 941 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 942 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
943 | void __iomem *mask_reg = bank->base + |
944 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 945 | unsigned long flags; |
11a78b79 | 946 | |
a6472533 | 947 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 948 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 949 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
950 | |
951 | return 0; | |
952 | } | |
953 | ||
47145210 | 954 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
955 | .suspend_noirq = omap_mpuio_suspend_noirq, |
956 | .resume_noirq = omap_mpuio_resume_noirq, | |
957 | }; | |
958 | ||
3c437ffd | 959 | /* use platform_driver for this. */ |
11a78b79 | 960 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
961 | .driver = { |
962 | .name = "mpuio", | |
79ee031f | 963 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
964 | }, |
965 | }; | |
966 | ||
967 | static struct platform_device omap_mpuio_device = { | |
968 | .name = "mpuio", | |
969 | .id = -1, | |
970 | .dev = { | |
971 | .driver = &omap_mpuio_driver.driver, | |
972 | } | |
973 | /* could list the /proc/iomem resources */ | |
974 | }; | |
975 | ||
976 | static inline void mpuio_init(void) | |
977 | { | |
a8be8daf | 978 | struct gpio_bank *bank = &gpio_bank[0]; |
77640aab | 979 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 980 | |
11a78b79 DB |
981 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
982 | (void) platform_device_register(&omap_mpuio_device); | |
983 | } | |
984 | ||
985 | #else | |
986 | static inline void mpuio_init(void) {} | |
987 | #endif /* 16xx */ | |
988 | ||
e5c56ed3 DB |
989 | #else |
990 | ||
991 | extern struct irq_chip mpuio_irq_chip; | |
992 | ||
993 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 994 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
995 | |
996 | #endif | |
997 | ||
998 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 999 | |
52e31344 DB |
1000 | /* REVISIT these are stupid implementations! replace by ones that |
1001 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1002 | */ | |
1003 | ||
1004 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1005 | { | |
1006 | struct gpio_bank *bank; | |
1007 | unsigned long flags; | |
1008 | ||
1009 | bank = container_of(chip, struct gpio_bank, chip); | |
1010 | spin_lock_irqsave(&bank->lock, flags); | |
1011 | _set_gpio_direction(bank, offset, 1); | |
1012 | spin_unlock_irqrestore(&bank->lock, flags); | |
1013 | return 0; | |
1014 | } | |
1015 | ||
b37c45b8 RQ |
1016 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
1017 | { | |
fa87931a | 1018 | void __iomem *reg = bank->base + bank->regs->direction; |
b37c45b8 | 1019 | |
b37c45b8 RQ |
1020 | return __raw_readl(reg) & mask; |
1021 | } | |
1022 | ||
52e31344 DB |
1023 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
1024 | { | |
b37c45b8 RQ |
1025 | struct gpio_bank *bank; |
1026 | void __iomem *reg; | |
1027 | int gpio; | |
1028 | u32 mask; | |
1029 | ||
1030 | gpio = chip->base + offset; | |
a8be8daf | 1031 | bank = container_of(chip, struct gpio_bank, chip); |
b37c45b8 | 1032 | reg = bank->base; |
129fd223 | 1033 | mask = GPIO_BIT(bank, gpio); |
b37c45b8 RQ |
1034 | |
1035 | if (gpio_is_input(bank, mask)) | |
1036 | return _get_gpio_datain(bank, gpio); | |
1037 | else | |
1038 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
1039 | } |
1040 | ||
1041 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1042 | { | |
1043 | struct gpio_bank *bank; | |
1044 | unsigned long flags; | |
1045 | ||
1046 | bank = container_of(chip, struct gpio_bank, chip); | |
1047 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 1048 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
1049 | _set_gpio_direction(bank, offset, 0); |
1050 | spin_unlock_irqrestore(&bank->lock, flags); | |
1051 | return 0; | |
1052 | } | |
1053 | ||
168ef3d9 FB |
1054 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1055 | unsigned debounce) | |
1056 | { | |
1057 | struct gpio_bank *bank; | |
1058 | unsigned long flags; | |
1059 | ||
1060 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab VC |
1061 | |
1062 | if (!bank->dbck) { | |
1063 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1064 | if (IS_ERR(bank->dbck)) | |
1065 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
1066 | } | |
1067 | ||
168ef3d9 FB |
1068 | spin_lock_irqsave(&bank->lock, flags); |
1069 | _set_gpio_debounce(bank, offset, debounce); | |
1070 | spin_unlock_irqrestore(&bank->lock, flags); | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
52e31344 DB |
1075 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
1076 | { | |
1077 | struct gpio_bank *bank; | |
1078 | unsigned long flags; | |
1079 | ||
1080 | bank = container_of(chip, struct gpio_bank, chip); | |
1081 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 1082 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
1083 | spin_unlock_irqrestore(&bank->lock, flags); |
1084 | } | |
1085 | ||
a007b709 DB |
1086 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
1087 | { | |
1088 | struct gpio_bank *bank; | |
1089 | ||
1090 | bank = container_of(chip, struct gpio_bank, chip); | |
1091 | return bank->virtual_irq_start + offset; | |
1092 | } | |
1093 | ||
52e31344 DB |
1094 | /*---------------------------------------------------------------------*/ |
1095 | ||
9a748053 | 1096 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da TL |
1097 | { |
1098 | u32 rev; | |
1099 | ||
9a748053 TL |
1100 | if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO)) |
1101 | rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION); | |
9f7065da | 1102 | else if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
9a748053 | 1103 | rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION); |
9f7065da | 1104 | else if (cpu_is_omap44xx()) |
9a748053 | 1105 | rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION); |
9f7065da TL |
1106 | else |
1107 | return; | |
1108 | ||
1109 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | |
1110 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1111 | } | |
1112 | ||
8ba55c5c DB |
1113 | /* This lock class tells lockdep that GPIO irqs are in a different |
1114 | * category than their parents, so it won't report false recursion. | |
1115 | */ | |
1116 | static struct lock_class_key gpio_lock_class; | |
1117 | ||
77640aab VC |
1118 | static inline int init_gpio_info(struct platform_device *pdev) |
1119 | { | |
1120 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ | |
1121 | gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank), | |
1122 | GFP_KERNEL); | |
1123 | if (!gpio_bank) { | |
1124 | dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); | |
1125 | return -ENOMEM; | |
1126 | } | |
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | /* TODO: Cleanup cpu_is_* checks */ | |
2fae7fbe VC |
1131 | static void omap_gpio_mod_init(struct gpio_bank *bank, int id) |
1132 | { | |
1133 | if (cpu_class_is_omap2()) { | |
1134 | if (cpu_is_omap44xx()) { | |
1135 | __raw_writel(0xffffffff, bank->base + | |
1136 | OMAP4_GPIO_IRQSTATUSCLR0); | |
1137 | __raw_writel(0x00000000, bank->base + | |
1138 | OMAP4_GPIO_DEBOUNCENABLE); | |
1139 | /* Initialize interface clk ungated, module enabled */ | |
1140 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); | |
1141 | } else if (cpu_is_omap34xx()) { | |
1142 | __raw_writel(0x00000000, bank->base + | |
1143 | OMAP24XX_GPIO_IRQENABLE1); | |
1144 | __raw_writel(0xffffffff, bank->base + | |
1145 | OMAP24XX_GPIO_IRQSTATUS1); | |
1146 | __raw_writel(0x00000000, bank->base + | |
1147 | OMAP24XX_GPIO_DEBOUNCE_EN); | |
1148 | ||
1149 | /* Initialize interface clk ungated, module enabled */ | |
1150 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
1151 | } else if (cpu_is_omap24xx()) { | |
1152 | static const u32 non_wakeup_gpios[] = { | |
1153 | 0xe203ffc0, 0x08700040 | |
1154 | }; | |
1155 | if (id < ARRAY_SIZE(non_wakeup_gpios)) | |
1156 | bank->non_wakeup_gpios = non_wakeup_gpios[id]; | |
1157 | } | |
1158 | } else if (cpu_class_is_omap1()) { | |
1159 | if (bank_is_mpuio(bank)) | |
5de62b86 TL |
1160 | __raw_writew(0xffff, bank->base + |
1161 | OMAP_MPUIO_GPIO_MASKIT / bank->stride); | |
2fae7fbe VC |
1162 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
1163 | __raw_writew(0xffff, bank->base | |
1164 | + OMAP1510_GPIO_INT_MASK); | |
1165 | __raw_writew(0x0000, bank->base | |
1166 | + OMAP1510_GPIO_INT_STATUS); | |
1167 | } | |
1168 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { | |
1169 | __raw_writew(0x0000, bank->base | |
1170 | + OMAP1610_GPIO_IRQENABLE1); | |
1171 | __raw_writew(0xffff, bank->base | |
1172 | + OMAP1610_GPIO_IRQSTATUS1); | |
1173 | __raw_writew(0x0014, bank->base | |
1174 | + OMAP1610_GPIO_SYSCONFIG); | |
1175 | ||
1176 | /* | |
1177 | * Enable system clock for GPIO module. | |
1178 | * The CAM_CLK_CTRL *is* really the right place. | |
1179 | */ | |
1180 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, | |
1181 | ULPD_CAM_CLK_CTRL); | |
1182 | } | |
1183 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { | |
1184 | __raw_writel(0xffffffff, bank->base | |
1185 | + OMAP7XX_GPIO_INT_MASK); | |
1186 | __raw_writel(0x00000000, bank->base | |
1187 | + OMAP7XX_GPIO_INT_STATUS); | |
1188 | } | |
1189 | } | |
1190 | } | |
1191 | ||
d52b31de | 1192 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 1193 | { |
77640aab | 1194 | int j; |
2fae7fbe VC |
1195 | static int gpio; |
1196 | ||
2fae7fbe VC |
1197 | bank->mod_usage = 0; |
1198 | /* | |
1199 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1200 | * over to the generic ones | |
1201 | */ | |
1202 | bank->chip.request = omap_gpio_request; | |
1203 | bank->chip.free = omap_gpio_free; | |
1204 | bank->chip.direction_input = gpio_input; | |
1205 | bank->chip.get = gpio_get; | |
1206 | bank->chip.direction_output = gpio_output; | |
1207 | bank->chip.set_debounce = gpio_debounce; | |
1208 | bank->chip.set = gpio_set; | |
1209 | bank->chip.to_irq = gpio_2irq; | |
1210 | if (bank_is_mpuio(bank)) { | |
1211 | bank->chip.label = "mpuio"; | |
1212 | #ifdef CONFIG_ARCH_OMAP16XX | |
1213 | bank->chip.dev = &omap_mpuio_device.dev; | |
1214 | #endif | |
1215 | bank->chip.base = OMAP_MPUIO(0); | |
1216 | } else { | |
1217 | bank->chip.label = "gpio"; | |
1218 | bank->chip.base = gpio; | |
d5f46247 | 1219 | gpio += bank->width; |
2fae7fbe | 1220 | } |
d5f46247 | 1221 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
1222 | |
1223 | gpiochip_add(&bank->chip); | |
1224 | ||
1225 | for (j = bank->virtual_irq_start; | |
d5f46247 | 1226 | j < bank->virtual_irq_start + bank->width; j++) { |
1475b85d | 1227 | irq_set_lockdep_class(j, &gpio_lock_class); |
6845664a | 1228 | irq_set_chip_data(j, bank); |
2fae7fbe | 1229 | if (bank_is_mpuio(bank)) |
6845664a | 1230 | irq_set_chip(j, &mpuio_irq_chip); |
2fae7fbe | 1231 | else |
6845664a TG |
1232 | irq_set_chip(j, &gpio_irq_chip); |
1233 | irq_set_handler(j, handle_simple_irq); | |
2fae7fbe VC |
1234 | set_irq_flags(j, IRQF_VALID); |
1235 | } | |
6845664a TG |
1236 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1237 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
1238 | } |
1239 | ||
77640aab | 1240 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1241 | { |
77640aab VC |
1242 | static int gpio_init_done; |
1243 | struct omap_gpio_platform_data *pdata; | |
1244 | struct resource *res; | |
1245 | int id; | |
5e1c5ff4 TL |
1246 | struct gpio_bank *bank; |
1247 | ||
77640aab VC |
1248 | if (!pdev->dev.platform_data) |
1249 | return -EINVAL; | |
5e1c5ff4 | 1250 | |
77640aab | 1251 | pdata = pdev->dev.platform_data; |
56a25641 | 1252 | |
77640aab VC |
1253 | if (!gpio_init_done) { |
1254 | int ret; | |
5492fb1a | 1255 | |
77640aab VC |
1256 | ret = init_gpio_info(pdev); |
1257 | if (ret) | |
1258 | return ret; | |
5492fb1a | 1259 | } |
5492fb1a | 1260 | |
77640aab VC |
1261 | id = pdev->id; |
1262 | bank = &gpio_bank[id]; | |
92105bb7 | 1263 | |
77640aab VC |
1264 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1265 | if (unlikely(!res)) { | |
1266 | dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id); | |
1267 | return -ENODEV; | |
44169075 | 1268 | } |
5e1c5ff4 | 1269 | |
77640aab VC |
1270 | bank->irq = res->start; |
1271 | bank->virtual_irq_start = pdata->virtual_irq_start; | |
1272 | bank->method = pdata->bank_type; | |
1273 | bank->dev = &pdev->dev; | |
1274 | bank->dbck_flag = pdata->dbck_flag; | |
5de62b86 | 1275 | bank->stride = pdata->bank_stride; |
d5f46247 | 1276 | bank->width = pdata->bank_width; |
9f7065da | 1277 | |
fa87931a KH |
1278 | bank->regs = pdata->regs; |
1279 | ||
1280 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1281 | bank->set_dataout = _set_gpio_dataout_reg; | |
1282 | else | |
1283 | bank->set_dataout = _set_gpio_dataout_mask; | |
1284 | ||
77640aab | 1285 | spin_lock_init(&bank->lock); |
9f7065da | 1286 | |
77640aab VC |
1287 | /* Static mapping, never released */ |
1288 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1289 | if (unlikely(!res)) { | |
1290 | dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id); | |
1291 | return -ENODEV; | |
1292 | } | |
89db9482 | 1293 | |
77640aab VC |
1294 | bank->base = ioremap(res->start, resource_size(res)); |
1295 | if (!bank->base) { | |
1296 | dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id); | |
1297 | return -ENOMEM; | |
5e1c5ff4 TL |
1298 | } |
1299 | ||
77640aab VC |
1300 | pm_runtime_enable(bank->dev); |
1301 | pm_runtime_get_sync(bank->dev); | |
1302 | ||
1303 | omap_gpio_mod_init(bank, id); | |
1304 | omap_gpio_chip_init(bank); | |
9a748053 | 1305 | omap_gpio_show_rev(bank); |
9f7065da | 1306 | |
77640aab VC |
1307 | if (!gpio_init_done) |
1308 | gpio_init_done = 1; | |
1309 | ||
5e1c5ff4 TL |
1310 | return 0; |
1311 | } | |
1312 | ||
140455fa | 1313 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
3c437ffd | 1314 | static int omap_gpio_suspend(void) |
92105bb7 TL |
1315 | { |
1316 | int i; | |
1317 | ||
5492fb1a | 1318 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1319 | return 0; |
1320 | ||
1321 | for (i = 0; i < gpio_bank_count; i++) { | |
1322 | struct gpio_bank *bank = &gpio_bank[i]; | |
1323 | void __iomem *wake_status; | |
1324 | void __iomem *wake_clear; | |
1325 | void __iomem *wake_set; | |
a6472533 | 1326 | unsigned long flags; |
92105bb7 TL |
1327 | |
1328 | switch (bank->method) { | |
e5c56ed3 | 1329 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1330 | case METHOD_GPIO_1610: |
1331 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1332 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1333 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1334 | break; | |
e5c56ed3 | 1335 | #endif |
a8eb7ca0 | 1336 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1337 | case METHOD_GPIO_24XX: |
723fdb78 | 1338 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1339 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1340 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1341 | break; | |
78a1a6d3 SR |
1342 | #endif |
1343 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1344 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1345 | wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1346 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1347 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1348 | break; | |
e5c56ed3 | 1349 | #endif |
92105bb7 TL |
1350 | default: |
1351 | continue; | |
1352 | } | |
1353 | ||
a6472533 | 1354 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1355 | bank->saved_wakeup = __raw_readl(wake_status); |
1356 | __raw_writel(0xffffffff, wake_clear); | |
1357 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1358 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1359 | } |
1360 | ||
1361 | return 0; | |
1362 | } | |
1363 | ||
3c437ffd | 1364 | static void omap_gpio_resume(void) |
92105bb7 TL |
1365 | { |
1366 | int i; | |
1367 | ||
723fdb78 | 1368 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
3c437ffd | 1369 | return; |
92105bb7 TL |
1370 | |
1371 | for (i = 0; i < gpio_bank_count; i++) { | |
1372 | struct gpio_bank *bank = &gpio_bank[i]; | |
1373 | void __iomem *wake_clear; | |
1374 | void __iomem *wake_set; | |
a6472533 | 1375 | unsigned long flags; |
92105bb7 TL |
1376 | |
1377 | switch (bank->method) { | |
e5c56ed3 | 1378 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1379 | case METHOD_GPIO_1610: |
1380 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1381 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1382 | break; | |
e5c56ed3 | 1383 | #endif |
a8eb7ca0 | 1384 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1385 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1386 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1387 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1388 | break; |
78a1a6d3 SR |
1389 | #endif |
1390 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1391 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1392 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1393 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1394 | break; | |
e5c56ed3 | 1395 | #endif |
92105bb7 TL |
1396 | default: |
1397 | continue; | |
1398 | } | |
1399 | ||
a6472533 | 1400 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1401 | __raw_writel(0xffffffff, wake_clear); |
1402 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 1403 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1404 | } |
92105bb7 TL |
1405 | } |
1406 | ||
3c437ffd | 1407 | static struct syscore_ops omap_gpio_syscore_ops = { |
92105bb7 TL |
1408 | .suspend = omap_gpio_suspend, |
1409 | .resume = omap_gpio_resume, | |
1410 | }; | |
1411 | ||
3ac4fa99 JY |
1412 | #endif |
1413 | ||
140455fa | 1414 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 JY |
1415 | |
1416 | static int workaround_enabled; | |
1417 | ||
72e06d08 | 1418 | void omap2_gpio_prepare_for_idle(int off_mode) |
3ac4fa99 JY |
1419 | { |
1420 | int i, c = 0; | |
a118b5f3 | 1421 | int min = 0; |
3ac4fa99 | 1422 | |
a118b5f3 TK |
1423 | if (cpu_is_omap34xx()) |
1424 | min = 1; | |
43ffcd9a | 1425 | |
a118b5f3 | 1426 | for (i = min; i < gpio_bank_count; i++) { |
3ac4fa99 | 1427 | struct gpio_bank *bank = &gpio_bank[i]; |
ca828760 | 1428 | u32 l1 = 0, l2 = 0; |
0aed0435 | 1429 | int j; |
3ac4fa99 | 1430 | |
0aed0435 | 1431 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1432 | clk_disable(bank->dbck); |
1433 | ||
72e06d08 | 1434 | if (!off_mode) |
43ffcd9a KH |
1435 | continue; |
1436 | ||
1437 | /* If going to OFF, remove triggering for all | |
1438 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1439 | * generated. See OMAP2420 Errata item 1.101. */ | |
3ac4fa99 JY |
1440 | if (!(bank->enabled_non_wakeup_gpios)) |
1441 | continue; | |
3f1686a9 TL |
1442 | |
1443 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1444 | bank->saved_datain = __raw_readl(bank->base + | |
1445 | OMAP24XX_GPIO_DATAIN); | |
1446 | l1 = __raw_readl(bank->base + | |
1447 | OMAP24XX_GPIO_FALLINGDETECT); | |
1448 | l2 = __raw_readl(bank->base + | |
1449 | OMAP24XX_GPIO_RISINGDETECT); | |
1450 | } | |
1451 | ||
1452 | if (cpu_is_omap44xx()) { | |
1453 | bank->saved_datain = __raw_readl(bank->base + | |
1454 | OMAP4_GPIO_DATAIN); | |
1455 | l1 = __raw_readl(bank->base + | |
1456 | OMAP4_GPIO_FALLINGDETECT); | |
1457 | l2 = __raw_readl(bank->base + | |
1458 | OMAP4_GPIO_RISINGDETECT); | |
1459 | } | |
1460 | ||
3ac4fa99 JY |
1461 | bank->saved_fallingdetect = l1; |
1462 | bank->saved_risingdetect = l2; | |
1463 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1464 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 TL |
1465 | |
1466 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1467 | __raw_writel(l1, bank->base + | |
1468 | OMAP24XX_GPIO_FALLINGDETECT); | |
1469 | __raw_writel(l2, bank->base + | |
1470 | OMAP24XX_GPIO_RISINGDETECT); | |
1471 | } | |
1472 | ||
1473 | if (cpu_is_omap44xx()) { | |
1474 | __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); | |
1475 | __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); | |
1476 | } | |
1477 | ||
3ac4fa99 JY |
1478 | c++; |
1479 | } | |
1480 | if (!c) { | |
1481 | workaround_enabled = 0; | |
1482 | return; | |
1483 | } | |
1484 | workaround_enabled = 1; | |
1485 | } | |
1486 | ||
43ffcd9a | 1487 | void omap2_gpio_resume_after_idle(void) |
3ac4fa99 JY |
1488 | { |
1489 | int i; | |
a118b5f3 | 1490 | int min = 0; |
3ac4fa99 | 1491 | |
a118b5f3 TK |
1492 | if (cpu_is_omap34xx()) |
1493 | min = 1; | |
1494 | for (i = min; i < gpio_bank_count; i++) { | |
3ac4fa99 | 1495 | struct gpio_bank *bank = &gpio_bank[i]; |
ca828760 | 1496 | u32 l = 0, gen, gen0, gen1; |
0aed0435 | 1497 | int j; |
3ac4fa99 | 1498 | |
0aed0435 | 1499 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1500 | clk_enable(bank->dbck); |
1501 | ||
43ffcd9a KH |
1502 | if (!workaround_enabled) |
1503 | continue; | |
1504 | ||
3ac4fa99 JY |
1505 | if (!(bank->enabled_non_wakeup_gpios)) |
1506 | continue; | |
3f1686a9 TL |
1507 | |
1508 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1509 | __raw_writel(bank->saved_fallingdetect, | |
3ac4fa99 | 1510 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
3f1686a9 | 1511 | __raw_writel(bank->saved_risingdetect, |
3ac4fa99 | 1512 | bank->base + OMAP24XX_GPIO_RISINGDETECT); |
3f1686a9 TL |
1513 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
1514 | } | |
1515 | ||
1516 | if (cpu_is_omap44xx()) { | |
1517 | __raw_writel(bank->saved_fallingdetect, | |
78a1a6d3 | 1518 | bank->base + OMAP4_GPIO_FALLINGDETECT); |
3f1686a9 | 1519 | __raw_writel(bank->saved_risingdetect, |
78a1a6d3 | 1520 | bank->base + OMAP4_GPIO_RISINGDETECT); |
3f1686a9 TL |
1521 | l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); |
1522 | } | |
1523 | ||
3ac4fa99 JY |
1524 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1525 | * state. If so, generate an IRQ by software. This is | |
1526 | * horribly racy, but it's the best we can do to work around | |
1527 | * this silicon bug. */ | |
3ac4fa99 | 1528 | l ^= bank->saved_datain; |
a118b5f3 | 1529 | l &= bank->enabled_non_wakeup_gpios; |
82dbb9d3 EN |
1530 | |
1531 | /* | |
1532 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1533 | * configured with falling edge only; and vice versa. | |
1534 | */ | |
1535 | gen0 = l & bank->saved_fallingdetect; | |
1536 | gen0 &= bank->saved_datain; | |
1537 | ||
1538 | gen1 = l & bank->saved_risingdetect; | |
1539 | gen1 &= ~(bank->saved_datain); | |
1540 | ||
1541 | /* FIXME: Consider GPIO IRQs with level detections properly! */ | |
1542 | gen = l & (~(bank->saved_fallingdetect) & | |
1543 | ~(bank->saved_risingdetect)); | |
1544 | /* Consider all GPIO IRQs needed to be updated */ | |
1545 | gen |= gen0 | gen1; | |
1546 | ||
1547 | if (gen) { | |
3ac4fa99 | 1548 | u32 old0, old1; |
3f1686a9 | 1549 | |
f00d6497 | 1550 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
3f1686a9 TL |
1551 | old0 = __raw_readl(bank->base + |
1552 | OMAP24XX_GPIO_LEVELDETECT0); | |
1553 | old1 = __raw_readl(bank->base + | |
1554 | OMAP24XX_GPIO_LEVELDETECT1); | |
f00d6497 | 1555 | __raw_writel(old0 | gen, bank->base + |
82dbb9d3 | 1556 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 1557 | __raw_writel(old1 | gen, bank->base + |
82dbb9d3 | 1558 | OMAP24XX_GPIO_LEVELDETECT1); |
f00d6497 | 1559 | __raw_writel(old0, bank->base + |
3f1686a9 | 1560 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 1561 | __raw_writel(old1, bank->base + |
3f1686a9 TL |
1562 | OMAP24XX_GPIO_LEVELDETECT1); |
1563 | } | |
1564 | ||
1565 | if (cpu_is_omap44xx()) { | |
1566 | old0 = __raw_readl(bank->base + | |
78a1a6d3 | 1567 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1568 | old1 = __raw_readl(bank->base + |
78a1a6d3 | 1569 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1570 | __raw_writel(old0 | l, bank->base + |
78a1a6d3 | 1571 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1572 | __raw_writel(old1 | l, bank->base + |
78a1a6d3 | 1573 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1574 | __raw_writel(old0, bank->base + |
78a1a6d3 | 1575 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1576 | __raw_writel(old1, bank->base + |
78a1a6d3 | 1577 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1578 | } |
3ac4fa99 JY |
1579 | } |
1580 | } | |
1581 | ||
1582 | } | |
1583 | ||
92105bb7 TL |
1584 | #endif |
1585 | ||
a8eb7ca0 | 1586 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 RN |
1587 | /* save the registers of bank 2-6 */ |
1588 | void omap_gpio_save_context(void) | |
1589 | { | |
1590 | int i; | |
1591 | ||
1592 | /* saving banks from 2-6 only since GPIO1 is in WKUP */ | |
1593 | for (i = 1; i < gpio_bank_count; i++) { | |
1594 | struct gpio_bank *bank = &gpio_bank[i]; | |
40c670f0 RN |
1595 | gpio_context[i].irqenable1 = |
1596 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
1597 | gpio_context[i].irqenable2 = | |
1598 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
1599 | gpio_context[i].wake_en = | |
1600 | __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); | |
1601 | gpio_context[i].ctrl = | |
1602 | __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
1603 | gpio_context[i].oe = | |
1604 | __raw_readl(bank->base + OMAP24XX_GPIO_OE); | |
1605 | gpio_context[i].leveldetect0 = | |
1606 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1607 | gpio_context[i].leveldetect1 = | |
1608 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1609 | gpio_context[i].risingdetect = | |
1610 | __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
1611 | gpio_context[i].fallingdetect = | |
1612 | __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1613 | gpio_context[i].dataout = | |
1614 | __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
1615 | } |
1616 | } | |
1617 | ||
1618 | /* restore the required registers of bank 2-6 */ | |
1619 | void omap_gpio_restore_context(void) | |
1620 | { | |
1621 | int i; | |
1622 | ||
1623 | for (i = 1; i < gpio_bank_count; i++) { | |
1624 | struct gpio_bank *bank = &gpio_bank[i]; | |
40c670f0 RN |
1625 | __raw_writel(gpio_context[i].irqenable1, |
1626 | bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
1627 | __raw_writel(gpio_context[i].irqenable2, | |
1628 | bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
1629 | __raw_writel(gpio_context[i].wake_en, | |
1630 | bank->base + OMAP24XX_GPIO_WAKE_EN); | |
1631 | __raw_writel(gpio_context[i].ctrl, | |
1632 | bank->base + OMAP24XX_GPIO_CTRL); | |
1633 | __raw_writel(gpio_context[i].oe, | |
1634 | bank->base + OMAP24XX_GPIO_OE); | |
1635 | __raw_writel(gpio_context[i].leveldetect0, | |
1636 | bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1637 | __raw_writel(gpio_context[i].leveldetect1, | |
1638 | bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1639 | __raw_writel(gpio_context[i].risingdetect, | |
1640 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
1641 | __raw_writel(gpio_context[i].fallingdetect, | |
1642 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1643 | __raw_writel(gpio_context[i].dataout, | |
1644 | bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
1645 | } |
1646 | } | |
1647 | #endif | |
1648 | ||
77640aab VC |
1649 | static struct platform_driver omap_gpio_driver = { |
1650 | .probe = omap_gpio_probe, | |
1651 | .driver = { | |
1652 | .name = "omap_gpio", | |
1653 | }, | |
1654 | }; | |
1655 | ||
5e1c5ff4 | 1656 | /* |
77640aab VC |
1657 | * gpio driver register needs to be done before |
1658 | * machine_init functions access gpio APIs. | |
1659 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1660 | */ |
77640aab | 1661 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1662 | { |
77640aab | 1663 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1664 | } |
77640aab | 1665 | postcore_initcall(omap_gpio_drv_reg); |
5e1c5ff4 | 1666 | |
92105bb7 TL |
1667 | static int __init omap_gpio_sysinit(void) |
1668 | { | |
11a78b79 DB |
1669 | mpuio_init(); |
1670 | ||
140455fa | 1671 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
3c437ffd RW |
1672 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) |
1673 | register_syscore_ops(&omap_gpio_syscore_ops); | |
92105bb7 TL |
1674 | #endif |
1675 | ||
3c437ffd | 1676 | return 0; |
92105bb7 TL |
1677 | } |
1678 | ||
92105bb7 | 1679 | arch_initcall(omap_gpio_sysinit); |