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Commit | Line | Data |
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5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
77640aab VC |
22 | #include <linux/slab.h> |
23 | #include <linux/pm_runtime.h> | |
55b93c32 | 24 | #include <linux/pm.h> |
5e1c5ff4 | 25 | |
a09e64fb | 26 | #include <mach/hardware.h> |
5e1c5ff4 | 27 | #include <asm/irq.h> |
a09e64fb | 28 | #include <mach/irqs.h> |
1bc857f7 | 29 | #include <asm/gpio.h> |
5e1c5ff4 TL |
30 | #include <asm/mach/irq.h> |
31 | ||
03e128ca C |
32 | static LIST_HEAD(omap_gpio_list); |
33 | ||
6d62e216 C |
34 | struct gpio_regs { |
35 | u32 irqenable1; | |
36 | u32 irqenable2; | |
37 | u32 wake_en; | |
38 | u32 ctrl; | |
39 | u32 oe; | |
40 | u32 leveldetect0; | |
41 | u32 leveldetect1; | |
42 | u32 risingdetect; | |
43 | u32 fallingdetect; | |
44 | u32 dataout; | |
45 | }; | |
46 | ||
5e1c5ff4 | 47 | struct gpio_bank { |
03e128ca | 48 | struct list_head node; |
9f7065da | 49 | unsigned long pbase; |
92105bb7 | 50 | void __iomem *base; |
5e1c5ff4 TL |
51 | u16 irq; |
52 | u16 virtual_irq_start; | |
92105bb7 TL |
53 | u32 suspend_wakeup; |
54 | u32 saved_wakeup; | |
3ac4fa99 JY |
55 | u32 non_wakeup_gpios; |
56 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 57 | struct gpio_regs context; |
3ac4fa99 JY |
58 | u32 saved_datain; |
59 | u32 saved_fallingdetect; | |
60 | u32 saved_risingdetect; | |
b144ff6f | 61 | u32 level_mask; |
4318f36b | 62 | u32 toggle_mask; |
5e1c5ff4 | 63 | spinlock_t lock; |
52e31344 | 64 | struct gpio_chip chip; |
89db9482 | 65 | struct clk *dbck; |
058af1ea | 66 | u32 mod_usage; |
8865b9b6 | 67 | u32 dbck_enable_mask; |
77640aab | 68 | struct device *dev; |
d0d665a8 | 69 | bool is_mpuio; |
77640aab | 70 | bool dbck_flag; |
0cde8d03 | 71 | bool loses_context; |
5de62b86 | 72 | int stride; |
d5f46247 | 73 | u32 width; |
60a3437d | 74 | int context_loss_count; |
03e128ca | 75 | u16 id; |
fa87931a KH |
76 | |
77 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60a3437d | 78 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
79 | |
80 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
81 | }; |
82 | ||
129fd223 KH |
83 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
84 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
c8eef65a | 85 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 TL |
86 | |
87 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
88 | { | |
92105bb7 | 89 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
90 | u32 l; |
91 | ||
fa87931a | 92 | reg += bank->regs->direction; |
5e1c5ff4 TL |
93 | l = __raw_readl(reg); |
94 | if (is_input) | |
95 | l |= 1 << gpio; | |
96 | else | |
97 | l &= ~(1 << gpio); | |
98 | __raw_writel(l, reg); | |
99 | } | |
100 | ||
fa87931a KH |
101 | |
102 | /* set data out value using dedicate set/clear register */ | |
103 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 104 | { |
92105bb7 | 105 | void __iomem *reg = bank->base; |
fa87931a | 106 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 107 | |
fa87931a KH |
108 | if (enable) |
109 | reg += bank->regs->set_dataout; | |
110 | else | |
111 | reg += bank->regs->clr_dataout; | |
5e1c5ff4 | 112 | |
5e1c5ff4 TL |
113 | __raw_writel(l, reg); |
114 | } | |
115 | ||
fa87931a KH |
116 | /* set data out value using mask register */ |
117 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 118 | { |
fa87931a KH |
119 | void __iomem *reg = bank->base + bank->regs->dataout; |
120 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
121 | u32 l; | |
5e1c5ff4 | 122 | |
fa87931a KH |
123 | l = __raw_readl(reg); |
124 | if (enable) | |
125 | l |= gpio_bit; | |
126 | else | |
127 | l &= ~gpio_bit; | |
5e1c5ff4 | 128 | __raw_writel(l, reg); |
5e1c5ff4 TL |
129 | } |
130 | ||
b37c45b8 | 131 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
b37c45b8 | 132 | { |
fa87931a | 133 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 134 | |
fa87931a | 135 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
5e1c5ff4 | 136 | } |
b37c45b8 | 137 | |
b37c45b8 RQ |
138 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
139 | { | |
fa87931a | 140 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 141 | |
129fd223 | 142 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
b37c45b8 RQ |
143 | } |
144 | ||
ece9528e KH |
145 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
146 | { | |
147 | int l = __raw_readl(base + reg); | |
148 | ||
149 | if (set) | |
150 | l |= mask; | |
151 | else | |
152 | l &= ~mask; | |
153 | ||
154 | __raw_writel(l, base + reg); | |
155 | } | |
92105bb7 | 156 | |
168ef3d9 FB |
157 | /** |
158 | * _set_gpio_debounce - low level gpio debounce time | |
159 | * @bank: the gpio bank we're acting upon | |
160 | * @gpio: the gpio number on this @gpio | |
161 | * @debounce: debounce time to use | |
162 | * | |
163 | * OMAP's debounce time is in 31us steps so we need | |
164 | * to convert and round up to the closest unit. | |
165 | */ | |
166 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
167 | unsigned debounce) | |
168 | { | |
9942da0e | 169 | void __iomem *reg; |
168ef3d9 FB |
170 | u32 val; |
171 | u32 l; | |
172 | ||
77640aab VC |
173 | if (!bank->dbck_flag) |
174 | return; | |
175 | ||
168ef3d9 FB |
176 | if (debounce < 32) |
177 | debounce = 0x01; | |
178 | else if (debounce > 7936) | |
179 | debounce = 0xff; | |
180 | else | |
181 | debounce = (debounce / 0x1f) - 1; | |
182 | ||
129fd223 | 183 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 184 | |
9942da0e | 185 | reg = bank->base + bank->regs->debounce; |
168ef3d9 FB |
186 | __raw_writel(debounce, reg); |
187 | ||
9942da0e | 188 | reg = bank->base + bank->regs->debounce_en; |
168ef3d9 FB |
189 | val = __raw_readl(reg); |
190 | ||
191 | if (debounce) { | |
192 | val |= l; | |
77640aab | 193 | clk_enable(bank->dbck); |
168ef3d9 FB |
194 | } else { |
195 | val &= ~l; | |
77640aab | 196 | clk_disable(bank->dbck); |
168ef3d9 | 197 | } |
f7ec0b0b | 198 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
199 | |
200 | __raw_writel(val, reg); | |
201 | } | |
202 | ||
5e571f38 | 203 | static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, |
5eb3bb9c | 204 | int trigger) |
5e1c5ff4 | 205 | { |
3ac4fa99 | 206 | void __iomem *base = bank->base; |
92105bb7 TL |
207 | u32 gpio_bit = 1 << gpio; |
208 | ||
5e571f38 TKD |
209 | _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
210 | trigger & IRQ_TYPE_LEVEL_LOW); | |
211 | _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
212 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
213 | _gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
214 | trigger & IRQ_TYPE_EDGE_RISING); | |
215 | _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
216 | trigger & IRQ_TYPE_EDGE_FALLING); | |
217 | ||
218 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) | |
219 | _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); | |
220 | ||
55b220ca | 221 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
222 | if (!bank->regs->irqctrl) { |
223 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
224 | if (bank->non_wakeup_gpios) { | |
225 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
226 | goto exit; | |
227 | } | |
228 | ||
699117a6 CW |
229 | /* |
230 | * Log the edge gpio and manually trigger the IRQ | |
231 | * after resume if the input level changes | |
232 | * to avoid irq lost during PER RET/OFF mode | |
233 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
234 | */ | |
235 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
236 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
237 | else | |
238 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
239 | } | |
5eb3bb9c | 240 | |
5e571f38 | 241 | exit: |
9ea14d8c TKD |
242 | bank->level_mask = |
243 | __raw_readl(bank->base + bank->regs->leveldetect0) | | |
244 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
245 | } |
246 | ||
9198bcd3 | 247 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
248 | /* |
249 | * This only applies to chips that can't do both rising and falling edge | |
250 | * detection at once. For all other chips, this function is a noop. | |
251 | */ | |
252 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
253 | { | |
254 | void __iomem *reg = bank->base; | |
255 | u32 l = 0; | |
256 | ||
5e571f38 | 257 | if (!bank->regs->irqctrl) |
4318f36b | 258 | return; |
5e571f38 TKD |
259 | |
260 | reg += bank->regs->irqctrl; | |
4318f36b CM |
261 | |
262 | l = __raw_readl(reg); | |
263 | if ((l >> gpio) & 1) | |
264 | l &= ~(1 << gpio); | |
265 | else | |
266 | l |= 1 << gpio; | |
267 | ||
268 | __raw_writel(l, reg); | |
269 | } | |
5e571f38 TKD |
270 | #else |
271 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} | |
9198bcd3 | 272 | #endif |
4318f36b | 273 | |
92105bb7 TL |
274 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
275 | { | |
276 | void __iomem *reg = bank->base; | |
5e571f38 | 277 | void __iomem *base = bank->base; |
92105bb7 | 278 | u32 l = 0; |
5e1c5ff4 | 279 | |
5e571f38 TKD |
280 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
281 | set_gpio_trigger(bank, gpio, trigger); | |
282 | } else if (bank->regs->irqctrl) { | |
283 | reg += bank->regs->irqctrl; | |
284 | ||
5e1c5ff4 | 285 | l = __raw_readl(reg); |
29501577 | 286 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 287 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 288 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 289 | l |= 1 << gpio; |
6cab4860 | 290 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 291 | l &= ~(1 << gpio); |
92105bb7 | 292 | else |
5e571f38 TKD |
293 | return -EINVAL; |
294 | ||
295 | __raw_writel(l, reg); | |
296 | } else if (bank->regs->edgectrl1) { | |
5e1c5ff4 | 297 | if (gpio & 0x08) |
5e571f38 | 298 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 299 | else |
5e571f38 TKD |
300 | reg += bank->regs->edgectrl1; |
301 | ||
5e1c5ff4 TL |
302 | gpio &= 0x07; |
303 | l = __raw_readl(reg); | |
304 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 305 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 306 | l |= 2 << (gpio << 1); |
6cab4860 | 307 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 308 | l |= 1 << (gpio << 1); |
5e571f38 TKD |
309 | |
310 | /* Enable wake-up during idle for dynamic tick */ | |
311 | _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger); | |
312 | __raw_writel(l, reg); | |
5e1c5ff4 | 313 | } |
92105bb7 | 314 | return 0; |
5e1c5ff4 TL |
315 | } |
316 | ||
e9191028 | 317 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 TL |
318 | { |
319 | struct gpio_bank *bank; | |
92105bb7 TL |
320 | unsigned gpio; |
321 | int retval; | |
a6472533 | 322 | unsigned long flags; |
92105bb7 | 323 | |
e9191028 LB |
324 | if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) |
325 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | |
92105bb7 | 326 | else |
e9191028 | 327 | gpio = d->irq - IH_GPIO_BASE; |
5e1c5ff4 | 328 | |
e5c56ed3 | 329 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 330 | return -EINVAL; |
e5c56ed3 | 331 | |
9ea14d8c TKD |
332 | bank = irq_data_get_irq_chip_data(d); |
333 | ||
334 | if (!bank->regs->leveldetect0 && | |
335 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
336 | return -EINVAL; |
337 | ||
a6472533 | 338 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 339 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
a6472533 | 340 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
341 | |
342 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 343 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 344 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 345 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 346 | |
92105bb7 | 347 | return retval; |
5e1c5ff4 TL |
348 | } |
349 | ||
350 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
351 | { | |
92105bb7 | 352 | void __iomem *reg = bank->base; |
5e1c5ff4 | 353 | |
eef4bec7 | 354 | reg += bank->regs->irqstatus; |
5e1c5ff4 | 355 | __raw_writel(gpio_mask, reg); |
bee7930f HD |
356 | |
357 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
358 | if (bank->regs->irqstatus2) { |
359 | reg = bank->base + bank->regs->irqstatus2; | |
bedfd154 | 360 | __raw_writel(gpio_mask, reg); |
eef4bec7 | 361 | } |
bedfd154 RQ |
362 | |
363 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
364 | __raw_readl(reg); | |
5e1c5ff4 TL |
365 | } |
366 | ||
367 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
368 | { | |
129fd223 | 369 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
370 | } |
371 | ||
ea6dedd7 ID |
372 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
373 | { | |
374 | void __iomem *reg = bank->base; | |
99c47707 | 375 | u32 l; |
c390aad0 | 376 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 377 | |
28f3b5a0 | 378 | reg += bank->regs->irqenable; |
99c47707 | 379 | l = __raw_readl(reg); |
28f3b5a0 | 380 | if (bank->regs->irqenable_inv) |
99c47707 ID |
381 | l = ~l; |
382 | l &= mask; | |
383 | return l; | |
ea6dedd7 ID |
384 | } |
385 | ||
28f3b5a0 | 386 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 387 | { |
92105bb7 | 388 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
389 | u32 l; |
390 | ||
28f3b5a0 KH |
391 | if (bank->regs->set_irqenable) { |
392 | reg += bank->regs->set_irqenable; | |
393 | l = gpio_mask; | |
394 | } else { | |
395 | reg += bank->regs->irqenable; | |
5e1c5ff4 | 396 | l = __raw_readl(reg); |
28f3b5a0 KH |
397 | if (bank->regs->irqenable_inv) |
398 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
399 | else |
400 | l |= gpio_mask; | |
28f3b5a0 KH |
401 | } |
402 | ||
403 | __raw_writel(l, reg); | |
404 | } | |
405 | ||
406 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
407 | { | |
408 | void __iomem *reg = bank->base; | |
409 | u32 l; | |
410 | ||
411 | if (bank->regs->clr_irqenable) { | |
412 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 413 | l = gpio_mask; |
28f3b5a0 KH |
414 | } else { |
415 | reg += bank->regs->irqenable; | |
56739a69 | 416 | l = __raw_readl(reg); |
28f3b5a0 | 417 | if (bank->regs->irqenable_inv) |
56739a69 | 418 | l |= gpio_mask; |
92105bb7 | 419 | else |
28f3b5a0 | 420 | l &= ~gpio_mask; |
5e1c5ff4 | 421 | } |
28f3b5a0 | 422 | |
5e1c5ff4 TL |
423 | __raw_writel(l, reg); |
424 | } | |
425 | ||
426 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
427 | { | |
28f3b5a0 | 428 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
429 | } |
430 | ||
92105bb7 TL |
431 | /* |
432 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
433 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
434 | * to the target, system will wake up always on GPIO events. While | |
435 | * system is running all registered GPIO interrupts need to have wake-up | |
436 | * enabled. When system is suspended, only selected GPIO interrupts need | |
437 | * to have wake-up enabled. | |
438 | */ | |
439 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
440 | { | |
f64ad1a0 KH |
441 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
442 | unsigned long flags; | |
a6472533 | 443 | |
f64ad1a0 KH |
444 | if (bank->non_wakeup_gpios & gpio_bit) { |
445 | dev_err(bank->dev, | |
446 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); | |
92105bb7 TL |
447 | return -EINVAL; |
448 | } | |
f64ad1a0 KH |
449 | |
450 | spin_lock_irqsave(&bank->lock, flags); | |
451 | if (enable) | |
452 | bank->suspend_wakeup |= gpio_bit; | |
453 | else | |
454 | bank->suspend_wakeup &= ~gpio_bit; | |
455 | ||
456 | spin_unlock_irqrestore(&bank->lock, flags); | |
457 | ||
458 | return 0; | |
92105bb7 TL |
459 | } |
460 | ||
4196dd6b TL |
461 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
462 | { | |
129fd223 | 463 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
464 | _set_gpio_irqenable(bank, gpio, 0); |
465 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 466 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
467 | } |
468 | ||
92105bb7 | 469 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 470 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 471 | { |
e9191028 | 472 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
92105bb7 TL |
473 | struct gpio_bank *bank; |
474 | int retval; | |
475 | ||
e9191028 | 476 | bank = irq_data_get_irq_chip_data(d); |
f64ad1a0 | 477 | retval = _set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
478 | |
479 | return retval; | |
480 | } | |
481 | ||
3ff164e1 | 482 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 483 | { |
3ff164e1 | 484 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 485 | unsigned long flags; |
52e31344 | 486 | |
55b93c32 TKD |
487 | /* |
488 | * If this is the first gpio_request for the bank, | |
489 | * enable the bank module. | |
490 | */ | |
491 | if (!bank->mod_usage) | |
492 | pm_runtime_get_sync(bank->dev); | |
92105bb7 | 493 | |
55b93c32 | 494 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b TL |
495 | /* Set trigger to none. You need to enable the desired trigger with |
496 | * request_irq() or set_irq_type(). | |
497 | */ | |
3ff164e1 | 498 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 499 | |
fad96ea8 C |
500 | if (bank->regs->pinctrl) { |
501 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
5e1c5ff4 | 502 | |
92105bb7 | 503 | /* Claim the pin for MPU */ |
3ff164e1 | 504 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 | 505 | } |
fad96ea8 | 506 | |
c8eef65a C |
507 | if (bank->regs->ctrl && !bank->mod_usage) { |
508 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
509 | u32 ctrl; | |
510 | ||
511 | ctrl = __raw_readl(reg); | |
512 | /* Module is enabled, clocks are not gated */ | |
513 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
514 | __raw_writel(ctrl, reg); | |
058af1ea | 515 | } |
c8eef65a C |
516 | |
517 | bank->mod_usage |= 1 << offset; | |
518 | ||
a6472533 | 519 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
520 | |
521 | return 0; | |
522 | } | |
523 | ||
3ff164e1 | 524 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 525 | { |
3ff164e1 | 526 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
6ed87c5b | 527 | void __iomem *base = bank->base; |
a6472533 | 528 | unsigned long flags; |
5e1c5ff4 | 529 | |
a6472533 | 530 | spin_lock_irqsave(&bank->lock, flags); |
6ed87c5b TKD |
531 | |
532 | if (bank->regs->wkup_en) | |
9f096868 | 533 | /* Disable wake-up during idle for dynamic tick */ |
6ed87c5b TKD |
534 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); |
535 | ||
c8eef65a C |
536 | bank->mod_usage &= ~(1 << offset); |
537 | ||
538 | if (bank->regs->ctrl && !bank->mod_usage) { | |
539 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
540 | u32 ctrl; | |
541 | ||
542 | ctrl = __raw_readl(reg); | |
543 | /* Module is disabled, clocks are gated */ | |
544 | ctrl |= GPIO_MOD_CTRL_BIT; | |
545 | __raw_writel(ctrl, reg); | |
058af1ea | 546 | } |
c8eef65a | 547 | |
3ff164e1 | 548 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 549 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
550 | |
551 | /* | |
552 | * If this is the last gpio to be freed in the bank, | |
553 | * disable the bank module. | |
554 | */ | |
555 | if (!bank->mod_usage) | |
556 | pm_runtime_put(bank->dev); | |
5e1c5ff4 TL |
557 | } |
558 | ||
559 | /* | |
560 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
561 | * avoid missing GPIO interrupts for other lines in the bank. | |
562 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
563 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
564 | * If we wait to unmask individual GPIO lines in the bank after the | |
565 | * line's interrupt handler has been run, we may miss some nested | |
566 | * interrupts. | |
567 | */ | |
10dd5ce2 | 568 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 569 | { |
92105bb7 | 570 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 571 | u32 isr; |
4318f36b | 572 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 573 | struct gpio_bank *bank; |
ea6dedd7 ID |
574 | u32 retrigger = 0; |
575 | int unmasked = 0; | |
ee144182 | 576 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 577 | |
ee144182 | 578 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 579 | |
6845664a | 580 | bank = irq_get_handler_data(irq); |
eef4bec7 | 581 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 582 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
583 | |
584 | if (WARN_ON(!isr_reg)) | |
585 | goto exit; | |
586 | ||
92105bb7 | 587 | while(1) { |
6e60e79a | 588 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 589 | u32 enabled; |
6e60e79a | 590 | |
ea6dedd7 ID |
591 | enabled = _get_gpio_irqbank_mask(bank); |
592 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a | 593 | |
9ea14d8c | 594 | if (bank->level_mask) |
b144ff6f | 595 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
596 | |
597 | /* clear edge sensitive interrupts before handler(s) are | |
598 | called so that we don't miss any interrupt occurred while | |
599 | executing them */ | |
28f3b5a0 | 600 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 601 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 602 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
603 | |
604 | /* if there is only edge sensitive GPIO pin interrupts | |
605 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
606 | if (!level_mask && !unmasked) { |
607 | unmasked = 1; | |
ee144182 | 608 | chained_irq_exit(chip, desc); |
ea6dedd7 | 609 | } |
92105bb7 | 610 | |
ea6dedd7 ID |
611 | isr |= retrigger; |
612 | retrigger = 0; | |
92105bb7 TL |
613 | if (!isr) |
614 | break; | |
615 | ||
616 | gpio_irq = bank->virtual_irq_start; | |
617 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
129fd223 | 618 | gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq)); |
4318f36b | 619 | |
92105bb7 TL |
620 | if (!(isr & 1)) |
621 | continue; | |
29454dde | 622 | |
4318f36b CM |
623 | /* |
624 | * Some chips can't respond to both rising and falling | |
625 | * at the same time. If this irq was requested with | |
626 | * both flags, we need to flip the ICR data for the IRQ | |
627 | * to respond to the IRQ for the opposite direction. | |
628 | * This will be indicated in the bank toggle_mask. | |
629 | */ | |
630 | if (bank->toggle_mask & (1 << gpio_index)) | |
631 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
4318f36b | 632 | |
d8aa0251 | 633 | generic_handle_irq(gpio_irq); |
92105bb7 | 634 | } |
1a8bfa1e | 635 | } |
ea6dedd7 ID |
636 | /* if bank has any level sensitive GPIO pin interrupt |
637 | configured, we must unmask the bank interrupt only after | |
638 | handler(s) are executed in order to avoid spurious bank | |
639 | interrupt */ | |
b1cc4c55 | 640 | exit: |
ea6dedd7 | 641 | if (!unmasked) |
ee144182 | 642 | chained_irq_exit(chip, desc); |
55b93c32 | 643 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
644 | } |
645 | ||
e9191028 | 646 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 647 | { |
e9191028 LB |
648 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
649 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 650 | unsigned long flags; |
4196dd6b | 651 | |
85ec7b97 | 652 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 653 | _reset_gpio(bank, gpio); |
85ec7b97 | 654 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
655 | } |
656 | ||
e9191028 | 657 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 658 | { |
e9191028 LB |
659 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
660 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
661 | |
662 | _clear_gpio_irqstatus(bank, gpio); | |
663 | } | |
664 | ||
e9191028 | 665 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 666 | { |
e9191028 LB |
667 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
668 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 669 | unsigned long flags; |
5e1c5ff4 | 670 | |
85ec7b97 | 671 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 672 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 673 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 674 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
675 | } |
676 | ||
e9191028 | 677 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 678 | { |
e9191028 LB |
679 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
680 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
129fd223 | 681 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 682 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 683 | unsigned long flags; |
55b6019a | 684 | |
85ec7b97 | 685 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 686 | if (trigger) |
129fd223 | 687 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
688 | |
689 | /* For level-triggered GPIOs, the clearing must be done after | |
690 | * the HW source is cleared, thus after the handler has run */ | |
691 | if (bank->level_mask & irq_mask) { | |
692 | _set_gpio_irqenable(bank, gpio, 0); | |
693 | _clear_gpio_irqstatus(bank, gpio); | |
694 | } | |
5e1c5ff4 | 695 | |
4de8c75b | 696 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 697 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
698 | } |
699 | ||
e5c56ed3 DB |
700 | static struct irq_chip gpio_irq_chip = { |
701 | .name = "GPIO", | |
e9191028 LB |
702 | .irq_shutdown = gpio_irq_shutdown, |
703 | .irq_ack = gpio_ack_irq, | |
704 | .irq_mask = gpio_mask_irq, | |
705 | .irq_unmask = gpio_unmask_irq, | |
706 | .irq_set_type = gpio_irq_type, | |
707 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
708 | }; |
709 | ||
710 | /*---------------------------------------------------------------------*/ | |
711 | ||
79ee031f | 712 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 713 | { |
79ee031f | 714 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 715 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
716 | void __iomem *mask_reg = bank->base + |
717 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 718 | unsigned long flags; |
11a78b79 | 719 | |
a6472533 | 720 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
721 | bank->saved_wakeup = __raw_readl(mask_reg); |
722 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 723 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
724 | |
725 | return 0; | |
726 | } | |
727 | ||
79ee031f | 728 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 729 | { |
79ee031f | 730 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 731 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
732 | void __iomem *mask_reg = bank->base + |
733 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 734 | unsigned long flags; |
11a78b79 | 735 | |
a6472533 | 736 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 737 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 738 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
739 | |
740 | return 0; | |
741 | } | |
742 | ||
47145210 | 743 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
744 | .suspend_noirq = omap_mpuio_suspend_noirq, |
745 | .resume_noirq = omap_mpuio_resume_noirq, | |
746 | }; | |
747 | ||
3c437ffd | 748 | /* use platform_driver for this. */ |
11a78b79 | 749 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
750 | .driver = { |
751 | .name = "mpuio", | |
79ee031f | 752 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
753 | }, |
754 | }; | |
755 | ||
756 | static struct platform_device omap_mpuio_device = { | |
757 | .name = "mpuio", | |
758 | .id = -1, | |
759 | .dev = { | |
760 | .driver = &omap_mpuio_driver.driver, | |
761 | } | |
762 | /* could list the /proc/iomem resources */ | |
763 | }; | |
764 | ||
03e128ca | 765 | static inline void mpuio_init(struct gpio_bank *bank) |
11a78b79 | 766 | { |
77640aab | 767 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 768 | |
11a78b79 DB |
769 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
770 | (void) platform_device_register(&omap_mpuio_device); | |
771 | } | |
772 | ||
e5c56ed3 | 773 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 774 | |
52e31344 DB |
775 | static int gpio_input(struct gpio_chip *chip, unsigned offset) |
776 | { | |
777 | struct gpio_bank *bank; | |
778 | unsigned long flags; | |
779 | ||
780 | bank = container_of(chip, struct gpio_bank, chip); | |
781 | spin_lock_irqsave(&bank->lock, flags); | |
782 | _set_gpio_direction(bank, offset, 1); | |
783 | spin_unlock_irqrestore(&bank->lock, flags); | |
784 | return 0; | |
785 | } | |
786 | ||
b37c45b8 RQ |
787 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
788 | { | |
fa87931a | 789 | void __iomem *reg = bank->base + bank->regs->direction; |
b37c45b8 | 790 | |
b37c45b8 RQ |
791 | return __raw_readl(reg) & mask; |
792 | } | |
793 | ||
52e31344 DB |
794 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
795 | { | |
b37c45b8 RQ |
796 | struct gpio_bank *bank; |
797 | void __iomem *reg; | |
798 | int gpio; | |
799 | u32 mask; | |
800 | ||
801 | gpio = chip->base + offset; | |
a8be8daf | 802 | bank = container_of(chip, struct gpio_bank, chip); |
b37c45b8 | 803 | reg = bank->base; |
129fd223 | 804 | mask = GPIO_BIT(bank, gpio); |
b37c45b8 RQ |
805 | |
806 | if (gpio_is_input(bank, mask)) | |
807 | return _get_gpio_datain(bank, gpio); | |
808 | else | |
809 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
810 | } |
811 | ||
812 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
813 | { | |
814 | struct gpio_bank *bank; | |
815 | unsigned long flags; | |
816 | ||
817 | bank = container_of(chip, struct gpio_bank, chip); | |
818 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 819 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
820 | _set_gpio_direction(bank, offset, 0); |
821 | spin_unlock_irqrestore(&bank->lock, flags); | |
822 | return 0; | |
823 | } | |
824 | ||
168ef3d9 FB |
825 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
826 | unsigned debounce) | |
827 | { | |
828 | struct gpio_bank *bank; | |
829 | unsigned long flags; | |
830 | ||
831 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab VC |
832 | |
833 | if (!bank->dbck) { | |
834 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
835 | if (IS_ERR(bank->dbck)) | |
836 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
837 | } | |
838 | ||
168ef3d9 FB |
839 | spin_lock_irqsave(&bank->lock, flags); |
840 | _set_gpio_debounce(bank, offset, debounce); | |
841 | spin_unlock_irqrestore(&bank->lock, flags); | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
52e31344 DB |
846 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
847 | { | |
848 | struct gpio_bank *bank; | |
849 | unsigned long flags; | |
850 | ||
851 | bank = container_of(chip, struct gpio_bank, chip); | |
852 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 853 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
854 | spin_unlock_irqrestore(&bank->lock, flags); |
855 | } | |
856 | ||
a007b709 DB |
857 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
858 | { | |
859 | struct gpio_bank *bank; | |
860 | ||
861 | bank = container_of(chip, struct gpio_bank, chip); | |
862 | return bank->virtual_irq_start + offset; | |
863 | } | |
864 | ||
52e31344 DB |
865 | /*---------------------------------------------------------------------*/ |
866 | ||
9a748053 | 867 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 868 | { |
e5ff4440 | 869 | static bool called; |
9f7065da TL |
870 | u32 rev; |
871 | ||
e5ff4440 | 872 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
873 | return; |
874 | ||
e5ff4440 KH |
875 | rev = __raw_readw(bank->base + bank->regs->revision); |
876 | pr_info("OMAP GPIO hardware version %d.%d\n", | |
9f7065da | 877 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
878 | |
879 | called = true; | |
9f7065da TL |
880 | } |
881 | ||
8ba55c5c DB |
882 | /* This lock class tells lockdep that GPIO irqs are in a different |
883 | * category than their parents, so it won't report false recursion. | |
884 | */ | |
885 | static struct lock_class_key gpio_lock_class; | |
886 | ||
03e128ca | 887 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 888 | { |
ab985f0f TKD |
889 | void __iomem *base = bank->base; |
890 | u32 l = 0xffffffff; | |
2fae7fbe | 891 | |
ab985f0f TKD |
892 | if (bank->width == 16) |
893 | l = 0xffff; | |
894 | ||
d0d665a8 | 895 | if (bank->is_mpuio) { |
ab985f0f TKD |
896 | __raw_writel(l, bank->base + bank->regs->irqenable); |
897 | return; | |
2fae7fbe | 898 | } |
ab985f0f TKD |
899 | |
900 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv); | |
901 | _gpio_rmw(base, bank->regs->irqstatus, l, | |
902 | bank->regs->irqenable_inv == false); | |
903 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0); | |
904 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0); | |
905 | if (bank->regs->debounce_en) | |
906 | _gpio_rmw(base, bank->regs->debounce_en, 0, 1); | |
907 | ||
908 | /* Initialize interface clk ungated, module enabled */ | |
909 | if (bank->regs->ctrl) | |
910 | _gpio_rmw(base, bank->regs->ctrl, 0, 1); | |
2fae7fbe VC |
911 | } |
912 | ||
f8b46b58 KH |
913 | static __init void |
914 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, | |
915 | unsigned int num) | |
916 | { | |
917 | struct irq_chip_generic *gc; | |
918 | struct irq_chip_type *ct; | |
919 | ||
920 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
921 | handle_simple_irq); | |
83233749 TP |
922 | if (!gc) { |
923 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
924 | return; | |
925 | } | |
926 | ||
f8b46b58 KH |
927 | ct = gc->chip_types; |
928 | ||
929 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
930 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
931 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
932 | ct->chip.irq_set_type = gpio_irq_type; | |
6ed87c5b TKD |
933 | |
934 | if (bank->regs->wkup_en) | |
f8b46b58 KH |
935 | ct->chip.irq_set_wake = gpio_wake_enable, |
936 | ||
937 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
938 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
939 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
940 | } | |
941 | ||
d52b31de | 942 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 943 | { |
77640aab | 944 | int j; |
2fae7fbe VC |
945 | static int gpio; |
946 | ||
2fae7fbe VC |
947 | /* |
948 | * REVISIT eventually switch from OMAP-specific gpio structs | |
949 | * over to the generic ones | |
950 | */ | |
951 | bank->chip.request = omap_gpio_request; | |
952 | bank->chip.free = omap_gpio_free; | |
953 | bank->chip.direction_input = gpio_input; | |
954 | bank->chip.get = gpio_get; | |
955 | bank->chip.direction_output = gpio_output; | |
956 | bank->chip.set_debounce = gpio_debounce; | |
957 | bank->chip.set = gpio_set; | |
958 | bank->chip.to_irq = gpio_2irq; | |
d0d665a8 | 959 | if (bank->is_mpuio) { |
2fae7fbe | 960 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
961 | if (bank->regs->wkup_en) |
962 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
963 | bank->chip.base = OMAP_MPUIO(0); |
964 | } else { | |
965 | bank->chip.label = "gpio"; | |
966 | bank->chip.base = gpio; | |
d5f46247 | 967 | gpio += bank->width; |
2fae7fbe | 968 | } |
d5f46247 | 969 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
970 | |
971 | gpiochip_add(&bank->chip); | |
972 | ||
973 | for (j = bank->virtual_irq_start; | |
d5f46247 | 974 | j < bank->virtual_irq_start + bank->width; j++) { |
1475b85d | 975 | irq_set_lockdep_class(j, &gpio_lock_class); |
6845664a | 976 | irq_set_chip_data(j, bank); |
d0d665a8 | 977 | if (bank->is_mpuio) { |
f8b46b58 KH |
978 | omap_mpuio_alloc_gc(bank, j, bank->width); |
979 | } else { | |
6845664a | 980 | irq_set_chip(j, &gpio_irq_chip); |
f8b46b58 KH |
981 | irq_set_handler(j, handle_simple_irq); |
982 | set_irq_flags(j, IRQF_VALID); | |
983 | } | |
2fae7fbe | 984 | } |
6845664a TG |
985 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
986 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
987 | } |
988 | ||
77640aab | 989 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 990 | { |
77640aab VC |
991 | struct omap_gpio_platform_data *pdata; |
992 | struct resource *res; | |
5e1c5ff4 | 993 | struct gpio_bank *bank; |
03e128ca | 994 | int ret = 0; |
5e1c5ff4 | 995 | |
03e128ca C |
996 | if (!pdev->dev.platform_data) { |
997 | ret = -EINVAL; | |
998 | goto err_exit; | |
5492fb1a | 999 | } |
5492fb1a | 1000 | |
03e128ca C |
1001 | bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL); |
1002 | if (!bank) { | |
1003 | dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); | |
1004 | ret = -ENOMEM; | |
1005 | goto err_exit; | |
1006 | } | |
92105bb7 | 1007 | |
77640aab VC |
1008 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1009 | if (unlikely(!res)) { | |
03e128ca C |
1010 | dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", |
1011 | pdev->id); | |
1012 | ret = -ENODEV; | |
1013 | goto err_free; | |
44169075 | 1014 | } |
5e1c5ff4 | 1015 | |
77640aab | 1016 | bank->irq = res->start; |
03e128ca C |
1017 | bank->id = pdev->id; |
1018 | ||
1019 | pdata = pdev->dev.platform_data; | |
77640aab | 1020 | bank->virtual_irq_start = pdata->virtual_irq_start; |
77640aab VC |
1021 | bank->dev = &pdev->dev; |
1022 | bank->dbck_flag = pdata->dbck_flag; | |
5de62b86 | 1023 | bank->stride = pdata->bank_stride; |
d5f46247 | 1024 | bank->width = pdata->bank_width; |
d0d665a8 | 1025 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1026 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
0cde8d03 | 1027 | bank->loses_context = pdata->loses_context; |
60a3437d | 1028 | bank->get_context_loss_count = pdata->get_context_loss_count; |
fa87931a KH |
1029 | bank->regs = pdata->regs; |
1030 | ||
1031 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1032 | bank->set_dataout = _set_gpio_dataout_reg; | |
1033 | else | |
1034 | bank->set_dataout = _set_gpio_dataout_mask; | |
9f7065da | 1035 | |
77640aab | 1036 | spin_lock_init(&bank->lock); |
9f7065da | 1037 | |
77640aab VC |
1038 | /* Static mapping, never released */ |
1039 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1040 | if (unlikely(!res)) { | |
03e128ca C |
1041 | dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", |
1042 | pdev->id); | |
1043 | ret = -ENODEV; | |
1044 | goto err_free; | |
77640aab | 1045 | } |
89db9482 | 1046 | |
77640aab VC |
1047 | bank->base = ioremap(res->start, resource_size(res)); |
1048 | if (!bank->base) { | |
03e128ca C |
1049 | dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", |
1050 | pdev->id); | |
1051 | ret = -ENOMEM; | |
1052 | goto err_free; | |
5e1c5ff4 TL |
1053 | } |
1054 | ||
77640aab | 1055 | pm_runtime_enable(bank->dev); |
55b93c32 | 1056 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1057 | pm_runtime_get_sync(bank->dev); |
1058 | ||
d0d665a8 | 1059 | if (bank->is_mpuio) |
ab985f0f TKD |
1060 | mpuio_init(bank); |
1061 | ||
03e128ca | 1062 | omap_gpio_mod_init(bank); |
77640aab | 1063 | omap_gpio_chip_init(bank); |
9a748053 | 1064 | omap_gpio_show_rev(bank); |
9f7065da | 1065 | |
55b93c32 TKD |
1066 | pm_runtime_put(bank->dev); |
1067 | ||
03e128ca | 1068 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1069 | |
03e128ca C |
1070 | return ret; |
1071 | ||
1072 | err_free: | |
1073 | kfree(bank); | |
1074 | err_exit: | |
1075 | return ret; | |
5e1c5ff4 TL |
1076 | } |
1077 | ||
55b93c32 TKD |
1078 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1079 | ||
1080 | #if defined(CONFIG_PM_SLEEP) | |
1081 | static int omap_gpio_suspend(struct device *dev) | |
92105bb7 | 1082 | { |
03e128ca | 1083 | struct gpio_bank *bank; |
92105bb7 | 1084 | |
03e128ca | 1085 | list_for_each_entry(bank, &omap_gpio_list, node) { |
6ed87c5b | 1086 | void __iomem *base = bank->base; |
92105bb7 | 1087 | void __iomem *wake_status; |
a6472533 | 1088 | unsigned long flags; |
92105bb7 | 1089 | |
6ed87c5b TKD |
1090 | if (!bank->regs->wkup_en) |
1091 | return 0; | |
1092 | ||
1093 | wake_status = bank->base + bank->regs->wkup_en; | |
92105bb7 | 1094 | |
a6472533 | 1095 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 1096 | bank->saved_wakeup = __raw_readl(wake_status); |
6ed87c5b TKD |
1097 | _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0); |
1098 | _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1); | |
a6472533 | 1099 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1100 | } |
1101 | ||
1102 | return 0; | |
1103 | } | |
1104 | ||
55b93c32 | 1105 | static int omap_gpio_resume(struct device *dev) |
92105bb7 | 1106 | { |
03e128ca | 1107 | struct gpio_bank *bank; |
92105bb7 | 1108 | |
03e128ca | 1109 | list_for_each_entry(bank, &omap_gpio_list, node) { |
6ed87c5b | 1110 | void __iomem *base = bank->base; |
a6472533 | 1111 | unsigned long flags; |
92105bb7 | 1112 | |
6ed87c5b | 1113 | if (!bank->regs->wkup_en) |
55b93c32 | 1114 | return 0; |
92105bb7 | 1115 | |
a6472533 | 1116 | spin_lock_irqsave(&bank->lock, flags); |
6ed87c5b TKD |
1117 | _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0); |
1118 | _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1); | |
a6472533 | 1119 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1120 | } |
92105bb7 | 1121 | |
55b93c32 TKD |
1122 | return 0; |
1123 | } | |
1124 | #endif /* CONFIG_PM_SLEEP */ | |
3ac4fa99 | 1125 | |
60a3437d TKD |
1126 | static void omap_gpio_save_context(struct gpio_bank *bank); |
1127 | static void omap_gpio_restore_context(struct gpio_bank *bank); | |
3ac4fa99 | 1128 | |
72e06d08 | 1129 | void omap2_gpio_prepare_for_idle(int off_mode) |
3ac4fa99 | 1130 | { |
03e128ca | 1131 | struct gpio_bank *bank; |
43ffcd9a | 1132 | |
03e128ca | 1133 | list_for_each_entry(bank, &omap_gpio_list, node) { |
ca828760 | 1134 | u32 l1 = 0, l2 = 0; |
0aed0435 | 1135 | int j; |
3ac4fa99 | 1136 | |
0cde8d03 | 1137 | if (!bank->loses_context) |
03e128ca C |
1138 | continue; |
1139 | ||
0aed0435 | 1140 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1141 | clk_disable(bank->dbck); |
1142 | ||
72e06d08 | 1143 | if (!off_mode) |
43ffcd9a KH |
1144 | continue; |
1145 | ||
1146 | /* If going to OFF, remove triggering for all | |
1147 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1148 | * generated. See OMAP2420 Errata item 1.101. */ | |
3ac4fa99 | 1149 | if (!(bank->enabled_non_wakeup_gpios)) |
60a3437d | 1150 | goto save_gpio_context; |
3f1686a9 | 1151 | |
9ea14d8c TKD |
1152 | bank->saved_datain = __raw_readl(bank->base + |
1153 | bank->regs->datain); | |
1154 | l1 = __raw_readl(bank->base + bank->regs->fallingdetect); | |
1155 | l2 = __raw_readl(bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1156 | |
3ac4fa99 JY |
1157 | bank->saved_fallingdetect = l1; |
1158 | bank->saved_risingdetect = l2; | |
1159 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1160 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1161 | |
9ea14d8c TKD |
1162 | __raw_writel(l1, bank->base + bank->regs->fallingdetect); |
1163 | __raw_writel(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1164 | |
60a3437d | 1165 | save_gpio_context: |
55b93c32 | 1166 | |
60a3437d TKD |
1167 | if (bank->get_context_loss_count) |
1168 | bank->context_loss_count = | |
1169 | bank->get_context_loss_count(bank->dev); | |
1170 | ||
1171 | omap_gpio_save_context(bank); | |
55b93c32 TKD |
1172 | |
1173 | if (!pm_runtime_suspended(bank->dev)) | |
1174 | pm_runtime_put(bank->dev); | |
3ac4fa99 | 1175 | } |
3ac4fa99 JY |
1176 | } |
1177 | ||
43ffcd9a | 1178 | void omap2_gpio_resume_after_idle(void) |
3ac4fa99 | 1179 | { |
03e128ca | 1180 | struct gpio_bank *bank; |
3ac4fa99 | 1181 | |
03e128ca | 1182 | list_for_each_entry(bank, &omap_gpio_list, node) { |
60a3437d | 1183 | int context_lost_cnt_after; |
ca828760 | 1184 | u32 l = 0, gen, gen0, gen1; |
0aed0435 | 1185 | int j; |
3ac4fa99 | 1186 | |
0cde8d03 | 1187 | if (!bank->loses_context) |
03e128ca C |
1188 | continue; |
1189 | ||
0aed0435 | 1190 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1191 | clk_enable(bank->dbck); |
1192 | ||
55b93c32 TKD |
1193 | if (pm_runtime_suspended(bank->dev)) |
1194 | pm_runtime_get_sync(bank->dev); | |
1195 | ||
60a3437d TKD |
1196 | if (bank->get_context_loss_count) { |
1197 | context_lost_cnt_after = | |
1198 | bank->get_context_loss_count(bank->dev); | |
1199 | if (context_lost_cnt_after != bank->context_loss_count | |
1200 | || !context_lost_cnt_after) | |
1201 | omap_gpio_restore_context(bank); | |
1202 | } | |
43ffcd9a | 1203 | |
3ac4fa99 JY |
1204 | if (!(bank->enabled_non_wakeup_gpios)) |
1205 | continue; | |
3f1686a9 | 1206 | |
9ea14d8c TKD |
1207 | __raw_writel(bank->saved_fallingdetect, |
1208 | bank->base + bank->regs->fallingdetect); | |
1209 | __raw_writel(bank->saved_risingdetect, | |
1210 | bank->base + bank->regs->risingdetect); | |
1211 | l = __raw_readl(bank->base + bank->regs->datain); | |
3f1686a9 | 1212 | |
3ac4fa99 JY |
1213 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1214 | * state. If so, generate an IRQ by software. This is | |
1215 | * horribly racy, but it's the best we can do to work around | |
1216 | * this silicon bug. */ | |
3ac4fa99 | 1217 | l ^= bank->saved_datain; |
a118b5f3 | 1218 | l &= bank->enabled_non_wakeup_gpios; |
82dbb9d3 EN |
1219 | |
1220 | /* | |
1221 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1222 | * configured with falling edge only; and vice versa. | |
1223 | */ | |
1224 | gen0 = l & bank->saved_fallingdetect; | |
1225 | gen0 &= bank->saved_datain; | |
1226 | ||
1227 | gen1 = l & bank->saved_risingdetect; | |
1228 | gen1 &= ~(bank->saved_datain); | |
1229 | ||
1230 | /* FIXME: Consider GPIO IRQs with level detections properly! */ | |
1231 | gen = l & (~(bank->saved_fallingdetect) & | |
1232 | ~(bank->saved_risingdetect)); | |
1233 | /* Consider all GPIO IRQs needed to be updated */ | |
1234 | gen |= gen0 | gen1; | |
1235 | ||
1236 | if (gen) { | |
3ac4fa99 | 1237 | u32 old0, old1; |
3f1686a9 | 1238 | |
9ea14d8c TKD |
1239 | old0 = __raw_readl(bank->base + |
1240 | bank->regs->leveldetect0); | |
1241 | old1 = __raw_readl(bank->base + | |
1242 | bank->regs->leveldetect1); | |
1243 | ||
f00d6497 | 1244 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
9ea14d8c TKD |
1245 | old0 |= gen; |
1246 | old1 |= gen; | |
3f1686a9 TL |
1247 | } |
1248 | ||
1249 | if (cpu_is_omap44xx()) { | |
9ea14d8c TKD |
1250 | old0 |= l; |
1251 | old1 |= l; | |
3f1686a9 | 1252 | } |
9ea14d8c TKD |
1253 | __raw_writel(old0, bank->base + |
1254 | bank->regs->leveldetect0); | |
1255 | __raw_writel(old1, bank->base + | |
1256 | bank->regs->leveldetect1); | |
3ac4fa99 JY |
1257 | } |
1258 | } | |
3ac4fa99 JY |
1259 | } |
1260 | ||
60a3437d | 1261 | static void omap_gpio_save_context(struct gpio_bank *bank) |
40c670f0 | 1262 | { |
60a3437d | 1263 | bank->context.irqenable1 = |
ae10f233 | 1264 | __raw_readl(bank->base + bank->regs->irqenable); |
60a3437d | 1265 | bank->context.irqenable2 = |
ae10f233 | 1266 | __raw_readl(bank->base + bank->regs->irqenable2); |
60a3437d | 1267 | bank->context.wake_en = |
ae10f233 TKD |
1268 | __raw_readl(bank->base + bank->regs->wkup_en); |
1269 | bank->context.ctrl = __raw_readl(bank->base + bank->regs->ctrl); | |
1270 | bank->context.oe = __raw_readl(bank->base + bank->regs->direction); | |
60a3437d | 1271 | bank->context.leveldetect0 = |
ae10f233 | 1272 | __raw_readl(bank->base + bank->regs->leveldetect0); |
60a3437d | 1273 | bank->context.leveldetect1 = |
ae10f233 | 1274 | __raw_readl(bank->base + bank->regs->leveldetect1); |
60a3437d | 1275 | bank->context.risingdetect = |
ae10f233 | 1276 | __raw_readl(bank->base + bank->regs->risingdetect); |
60a3437d | 1277 | bank->context.fallingdetect = |
ae10f233 TKD |
1278 | __raw_readl(bank->base + bank->regs->fallingdetect); |
1279 | bank->context.dataout = __raw_readl(bank->base + bank->regs->dataout); | |
40c670f0 RN |
1280 | } |
1281 | ||
60a3437d | 1282 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1283 | { |
60a3437d | 1284 | __raw_writel(bank->context.irqenable1, |
ae10f233 | 1285 | bank->base + bank->regs->irqenable); |
60a3437d | 1286 | __raw_writel(bank->context.irqenable2, |
ae10f233 | 1287 | bank->base + bank->regs->irqenable2); |
60a3437d | 1288 | __raw_writel(bank->context.wake_en, |
ae10f233 TKD |
1289 | bank->base + bank->regs->wkup_en); |
1290 | __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
1291 | __raw_writel(bank->context.oe, bank->base + bank->regs->direction); | |
60a3437d | 1292 | __raw_writel(bank->context.leveldetect0, |
ae10f233 | 1293 | bank->base + bank->regs->leveldetect0); |
60a3437d | 1294 | __raw_writel(bank->context.leveldetect1, |
ae10f233 | 1295 | bank->base + bank->regs->leveldetect1); |
60a3437d | 1296 | __raw_writel(bank->context.risingdetect, |
ae10f233 | 1297 | bank->base + bank->regs->risingdetect); |
60a3437d | 1298 | __raw_writel(bank->context.fallingdetect, |
ae10f233 TKD |
1299 | bank->base + bank->regs->fallingdetect); |
1300 | __raw_writel(bank->context.dataout, bank->base + bank->regs->dataout); | |
40c670f0 | 1301 | } |
55b93c32 TKD |
1302 | #else |
1303 | #define omap_gpio_suspend NULL | |
1304 | #define omap_gpio_resume NULL | |
40c670f0 RN |
1305 | #endif |
1306 | ||
55b93c32 TKD |
1307 | static const struct dev_pm_ops gpio_pm_ops = { |
1308 | SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume) | |
1309 | }; | |
1310 | ||
77640aab VC |
1311 | static struct platform_driver omap_gpio_driver = { |
1312 | .probe = omap_gpio_probe, | |
1313 | .driver = { | |
1314 | .name = "omap_gpio", | |
55b93c32 | 1315 | .pm = &gpio_pm_ops, |
77640aab VC |
1316 | }, |
1317 | }; | |
1318 | ||
5e1c5ff4 | 1319 | /* |
77640aab VC |
1320 | * gpio driver register needs to be done before |
1321 | * machine_init functions access gpio APIs. | |
1322 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1323 | */ |
77640aab | 1324 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1325 | { |
77640aab | 1326 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1327 | } |
77640aab | 1328 | postcore_initcall(omap_gpio_drv_reg); |