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Commit | Line | Data |
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5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/irqdomain.h> | |
5e1c5ff4 | 28 | |
a09e64fb | 29 | #include <mach/hardware.h> |
5e1c5ff4 | 30 | #include <asm/irq.h> |
a09e64fb | 31 | #include <mach/irqs.h> |
1bc857f7 | 32 | #include <asm/gpio.h> |
5e1c5ff4 TL |
33 | #include <asm/mach/irq.h> |
34 | ||
2dc983c5 TKD |
35 | #define OFF_MODE 1 |
36 | ||
03e128ca C |
37 | static LIST_HEAD(omap_gpio_list); |
38 | ||
6d62e216 C |
39 | struct gpio_regs { |
40 | u32 irqenable1; | |
41 | u32 irqenable2; | |
42 | u32 wake_en; | |
43 | u32 ctrl; | |
44 | u32 oe; | |
45 | u32 leveldetect0; | |
46 | u32 leveldetect1; | |
47 | u32 risingdetect; | |
48 | u32 fallingdetect; | |
49 | u32 dataout; | |
ae547354 NM |
50 | u32 debounce; |
51 | u32 debounce_en; | |
6d62e216 C |
52 | }; |
53 | ||
5e1c5ff4 | 54 | struct gpio_bank { |
03e128ca | 55 | struct list_head node; |
92105bb7 | 56 | void __iomem *base; |
5e1c5ff4 | 57 | u16 irq; |
384ebe1c BC |
58 | int irq_base; |
59 | struct irq_domain *domain; | |
3ac4fa99 JY |
60 | u32 non_wakeup_gpios; |
61 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 62 | struct gpio_regs context; |
3ac4fa99 | 63 | u32 saved_datain; |
b144ff6f | 64 | u32 level_mask; |
4318f36b | 65 | u32 toggle_mask; |
5e1c5ff4 | 66 | spinlock_t lock; |
52e31344 | 67 | struct gpio_chip chip; |
89db9482 | 68 | struct clk *dbck; |
058af1ea | 69 | u32 mod_usage; |
8865b9b6 | 70 | u32 dbck_enable_mask; |
72f83af9 | 71 | bool dbck_enabled; |
77640aab | 72 | struct device *dev; |
d0d665a8 | 73 | bool is_mpuio; |
77640aab | 74 | bool dbck_flag; |
0cde8d03 | 75 | bool loses_context; |
5de62b86 | 76 | int stride; |
d5f46247 | 77 | u32 width; |
60a3437d | 78 | int context_loss_count; |
2dc983c5 TKD |
79 | int power_mode; |
80 | bool workaround_enabled; | |
fa87931a KH |
81 | |
82 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60a3437d | 83 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
84 | |
85 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
86 | }; |
87 | ||
129fd223 KH |
88 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
89 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
c8eef65a | 90 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 91 | |
25db711d BC |
92 | static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq) |
93 | { | |
94 | return gpio_irq - bank->irq_base + bank->chip.base; | |
95 | } | |
96 | ||
5e1c5ff4 TL |
97 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) |
98 | { | |
92105bb7 | 99 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
100 | u32 l; |
101 | ||
fa87931a | 102 | reg += bank->regs->direction; |
5e1c5ff4 TL |
103 | l = __raw_readl(reg); |
104 | if (is_input) | |
105 | l |= 1 << gpio; | |
106 | else | |
107 | l &= ~(1 << gpio); | |
108 | __raw_writel(l, reg); | |
41d87cbd | 109 | bank->context.oe = l; |
5e1c5ff4 TL |
110 | } |
111 | ||
fa87931a KH |
112 | |
113 | /* set data out value using dedicate set/clear register */ | |
114 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 115 | { |
92105bb7 | 116 | void __iomem *reg = bank->base; |
fa87931a | 117 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 118 | |
2c836f7e | 119 | if (enable) { |
fa87931a | 120 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
121 | bank->context.dataout |= l; |
122 | } else { | |
fa87931a | 123 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
124 | bank->context.dataout &= ~l; |
125 | } | |
5e1c5ff4 | 126 | |
5e1c5ff4 TL |
127 | __raw_writel(l, reg); |
128 | } | |
129 | ||
fa87931a KH |
130 | /* set data out value using mask register */ |
131 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 132 | { |
fa87931a KH |
133 | void __iomem *reg = bank->base + bank->regs->dataout; |
134 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
135 | u32 l; | |
5e1c5ff4 | 136 | |
fa87931a KH |
137 | l = __raw_readl(reg); |
138 | if (enable) | |
139 | l |= gpio_bit; | |
140 | else | |
141 | l &= ~gpio_bit; | |
5e1c5ff4 | 142 | __raw_writel(l, reg); |
41d87cbd | 143 | bank->context.dataout = l; |
5e1c5ff4 TL |
144 | } |
145 | ||
7fcca715 | 146 | static int _get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 147 | { |
fa87931a | 148 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 149 | |
7fcca715 | 150 | return (__raw_readl(reg) & (1 << offset)) != 0; |
5e1c5ff4 | 151 | } |
b37c45b8 | 152 | |
7fcca715 | 153 | static int _get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 154 | { |
fa87931a | 155 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 156 | |
7fcca715 | 157 | return (__raw_readl(reg) & (1 << offset)) != 0; |
b37c45b8 RQ |
158 | } |
159 | ||
ece9528e KH |
160 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
161 | { | |
162 | int l = __raw_readl(base + reg); | |
163 | ||
862ff640 | 164 | if (set) |
ece9528e KH |
165 | l |= mask; |
166 | else | |
167 | l &= ~mask; | |
168 | ||
169 | __raw_writel(l, base + reg); | |
170 | } | |
92105bb7 | 171 | |
72f83af9 TKD |
172 | static inline void _gpio_dbck_enable(struct gpio_bank *bank) |
173 | { | |
174 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
175 | clk_enable(bank->dbck); | |
176 | bank->dbck_enabled = true; | |
177 | } | |
178 | } | |
179 | ||
180 | static inline void _gpio_dbck_disable(struct gpio_bank *bank) | |
181 | { | |
182 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
183 | clk_disable(bank->dbck); | |
184 | bank->dbck_enabled = false; | |
185 | } | |
186 | } | |
187 | ||
168ef3d9 FB |
188 | /** |
189 | * _set_gpio_debounce - low level gpio debounce time | |
190 | * @bank: the gpio bank we're acting upon | |
191 | * @gpio: the gpio number on this @gpio | |
192 | * @debounce: debounce time to use | |
193 | * | |
194 | * OMAP's debounce time is in 31us steps so we need | |
195 | * to convert and round up to the closest unit. | |
196 | */ | |
197 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
198 | unsigned debounce) | |
199 | { | |
9942da0e | 200 | void __iomem *reg; |
168ef3d9 FB |
201 | u32 val; |
202 | u32 l; | |
203 | ||
77640aab VC |
204 | if (!bank->dbck_flag) |
205 | return; | |
206 | ||
168ef3d9 FB |
207 | if (debounce < 32) |
208 | debounce = 0x01; | |
209 | else if (debounce > 7936) | |
210 | debounce = 0xff; | |
211 | else | |
212 | debounce = (debounce / 0x1f) - 1; | |
213 | ||
129fd223 | 214 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 215 | |
6fd9c421 | 216 | clk_enable(bank->dbck); |
9942da0e | 217 | reg = bank->base + bank->regs->debounce; |
168ef3d9 FB |
218 | __raw_writel(debounce, reg); |
219 | ||
9942da0e | 220 | reg = bank->base + bank->regs->debounce_en; |
168ef3d9 FB |
221 | val = __raw_readl(reg); |
222 | ||
6fd9c421 | 223 | if (debounce) |
168ef3d9 | 224 | val |= l; |
6fd9c421 | 225 | else |
168ef3d9 | 226 | val &= ~l; |
f7ec0b0b | 227 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
228 | |
229 | __raw_writel(val, reg); | |
6fd9c421 TKD |
230 | clk_disable(bank->dbck); |
231 | /* | |
232 | * Enable debounce clock per module. | |
233 | * This call is mandatory because in omap_gpio_request() when | |
234 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
235 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
236 | * used within _gpio_dbck_enable() is still not initialized at | |
237 | * that point. Therefore we have to enable dbck here. | |
238 | */ | |
239 | _gpio_dbck_enable(bank); | |
ae547354 NM |
240 | if (bank->dbck_enable_mask) { |
241 | bank->context.debounce = debounce; | |
242 | bank->context.debounce_en = val; | |
243 | } | |
168ef3d9 FB |
244 | } |
245 | ||
5e571f38 | 246 | static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 247 | unsigned trigger) |
5e1c5ff4 | 248 | { |
3ac4fa99 | 249 | void __iomem *base = bank->base; |
92105bb7 TL |
250 | u32 gpio_bit = 1 << gpio; |
251 | ||
5e571f38 TKD |
252 | _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
253 | trigger & IRQ_TYPE_LEVEL_LOW); | |
254 | _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
255 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
256 | _gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
257 | trigger & IRQ_TYPE_EDGE_RISING); | |
258 | _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
259 | trigger & IRQ_TYPE_EDGE_FALLING); | |
260 | ||
41d87cbd TKD |
261 | bank->context.leveldetect0 = |
262 | __raw_readl(bank->base + bank->regs->leveldetect0); | |
263 | bank->context.leveldetect1 = | |
264 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
265 | bank->context.risingdetect = | |
266 | __raw_readl(bank->base + bank->regs->risingdetect); | |
267 | bank->context.fallingdetect = | |
268 | __raw_readl(bank->base + bank->regs->fallingdetect); | |
269 | ||
270 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
5e571f38 | 271 | _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd TKD |
272 | bank->context.wake_en = |
273 | __raw_readl(bank->base + bank->regs->wkup_en); | |
274 | } | |
5e571f38 | 275 | |
55b220ca | 276 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
277 | if (!bank->regs->irqctrl) { |
278 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
279 | if (bank->non_wakeup_gpios) { | |
280 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
281 | goto exit; | |
282 | } | |
283 | ||
699117a6 CW |
284 | /* |
285 | * Log the edge gpio and manually trigger the IRQ | |
286 | * after resume if the input level changes | |
287 | * to avoid irq lost during PER RET/OFF mode | |
288 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
289 | */ | |
290 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
291 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
292 | else | |
293 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
294 | } | |
5eb3bb9c | 295 | |
5e571f38 | 296 | exit: |
9ea14d8c TKD |
297 | bank->level_mask = |
298 | __raw_readl(bank->base + bank->regs->leveldetect0) | | |
299 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
300 | } |
301 | ||
9198bcd3 | 302 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
303 | /* |
304 | * This only applies to chips that can't do both rising and falling edge | |
305 | * detection at once. For all other chips, this function is a noop. | |
306 | */ | |
307 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
308 | { | |
309 | void __iomem *reg = bank->base; | |
310 | u32 l = 0; | |
311 | ||
5e571f38 | 312 | if (!bank->regs->irqctrl) |
4318f36b | 313 | return; |
5e571f38 TKD |
314 | |
315 | reg += bank->regs->irqctrl; | |
4318f36b CM |
316 | |
317 | l = __raw_readl(reg); | |
318 | if ((l >> gpio) & 1) | |
319 | l &= ~(1 << gpio); | |
320 | else | |
321 | l |= 1 << gpio; | |
322 | ||
323 | __raw_writel(l, reg); | |
324 | } | |
5e571f38 TKD |
325 | #else |
326 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} | |
9198bcd3 | 327 | #endif |
4318f36b | 328 | |
00ece7e4 TKD |
329 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, |
330 | unsigned trigger) | |
92105bb7 TL |
331 | { |
332 | void __iomem *reg = bank->base; | |
5e571f38 | 333 | void __iomem *base = bank->base; |
92105bb7 | 334 | u32 l = 0; |
5e1c5ff4 | 335 | |
5e571f38 TKD |
336 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
337 | set_gpio_trigger(bank, gpio, trigger); | |
338 | } else if (bank->regs->irqctrl) { | |
339 | reg += bank->regs->irqctrl; | |
340 | ||
5e1c5ff4 | 341 | l = __raw_readl(reg); |
29501577 | 342 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 343 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 344 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 345 | l |= 1 << gpio; |
6cab4860 | 346 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 347 | l &= ~(1 << gpio); |
92105bb7 | 348 | else |
5e571f38 TKD |
349 | return -EINVAL; |
350 | ||
351 | __raw_writel(l, reg); | |
352 | } else if (bank->regs->edgectrl1) { | |
5e1c5ff4 | 353 | if (gpio & 0x08) |
5e571f38 | 354 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 355 | else |
5e571f38 TKD |
356 | reg += bank->regs->edgectrl1; |
357 | ||
5e1c5ff4 TL |
358 | gpio &= 0x07; |
359 | l = __raw_readl(reg); | |
360 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 361 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 362 | l |= 2 << (gpio << 1); |
6cab4860 | 363 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 364 | l |= 1 << (gpio << 1); |
5e571f38 TKD |
365 | |
366 | /* Enable wake-up during idle for dynamic tick */ | |
367 | _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger); | |
41d87cbd TKD |
368 | bank->context.wake_en = |
369 | __raw_readl(bank->base + bank->regs->wkup_en); | |
5e571f38 | 370 | __raw_writel(l, reg); |
5e1c5ff4 | 371 | } |
92105bb7 | 372 | return 0; |
5e1c5ff4 TL |
373 | } |
374 | ||
e9191028 | 375 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 376 | { |
25db711d | 377 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
92105bb7 TL |
378 | unsigned gpio; |
379 | int retval; | |
a6472533 | 380 | unsigned long flags; |
92105bb7 | 381 | |
e9191028 LB |
382 | if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) |
383 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | |
92105bb7 | 384 | else |
25db711d | 385 | gpio = irq_to_gpio(bank, d->irq); |
5e1c5ff4 | 386 | |
e5c56ed3 | 387 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 388 | return -EINVAL; |
e5c56ed3 | 389 | |
9ea14d8c TKD |
390 | if (!bank->regs->leveldetect0 && |
391 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
392 | return -EINVAL; |
393 | ||
a6472533 | 394 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 395 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
a6472533 | 396 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
397 | |
398 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 399 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 400 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 401 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 402 | |
92105bb7 | 403 | return retval; |
5e1c5ff4 TL |
404 | } |
405 | ||
406 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
407 | { | |
92105bb7 | 408 | void __iomem *reg = bank->base; |
5e1c5ff4 | 409 | |
eef4bec7 | 410 | reg += bank->regs->irqstatus; |
5e1c5ff4 | 411 | __raw_writel(gpio_mask, reg); |
bee7930f HD |
412 | |
413 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
414 | if (bank->regs->irqstatus2) { |
415 | reg = bank->base + bank->regs->irqstatus2; | |
bedfd154 | 416 | __raw_writel(gpio_mask, reg); |
eef4bec7 | 417 | } |
bedfd154 RQ |
418 | |
419 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
420 | __raw_readl(reg); | |
5e1c5ff4 TL |
421 | } |
422 | ||
423 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
424 | { | |
129fd223 | 425 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
426 | } |
427 | ||
ea6dedd7 ID |
428 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
429 | { | |
430 | void __iomem *reg = bank->base; | |
99c47707 | 431 | u32 l; |
c390aad0 | 432 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 433 | |
28f3b5a0 | 434 | reg += bank->regs->irqenable; |
99c47707 | 435 | l = __raw_readl(reg); |
28f3b5a0 | 436 | if (bank->regs->irqenable_inv) |
99c47707 ID |
437 | l = ~l; |
438 | l &= mask; | |
439 | return l; | |
ea6dedd7 ID |
440 | } |
441 | ||
28f3b5a0 | 442 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 443 | { |
92105bb7 | 444 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
445 | u32 l; |
446 | ||
28f3b5a0 KH |
447 | if (bank->regs->set_irqenable) { |
448 | reg += bank->regs->set_irqenable; | |
449 | l = gpio_mask; | |
2a900eb7 | 450 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
451 | } else { |
452 | reg += bank->regs->irqenable; | |
5e1c5ff4 | 453 | l = __raw_readl(reg); |
28f3b5a0 KH |
454 | if (bank->regs->irqenable_inv) |
455 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
456 | else |
457 | l |= gpio_mask; | |
2a900eb7 | 458 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
459 | } |
460 | ||
461 | __raw_writel(l, reg); | |
462 | } | |
463 | ||
464 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
465 | { | |
466 | void __iomem *reg = bank->base; | |
467 | u32 l; | |
468 | ||
469 | if (bank->regs->clr_irqenable) { | |
470 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 471 | l = gpio_mask; |
2a900eb7 | 472 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
473 | } else { |
474 | reg += bank->regs->irqenable; | |
56739a69 | 475 | l = __raw_readl(reg); |
28f3b5a0 | 476 | if (bank->regs->irqenable_inv) |
56739a69 | 477 | l |= gpio_mask; |
92105bb7 | 478 | else |
28f3b5a0 | 479 | l &= ~gpio_mask; |
2a900eb7 | 480 | bank->context.irqenable1 = l; |
5e1c5ff4 | 481 | } |
28f3b5a0 | 482 | |
5e1c5ff4 TL |
483 | __raw_writel(l, reg); |
484 | } | |
485 | ||
486 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
487 | { | |
8276536c TKD |
488 | if (enable) |
489 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | |
490 | else | |
491 | _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | |
5e1c5ff4 TL |
492 | } |
493 | ||
92105bb7 TL |
494 | /* |
495 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
496 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
497 | * to the target, system will wake up always on GPIO events. While | |
498 | * system is running all registered GPIO interrupts need to have wake-up | |
499 | * enabled. When system is suspended, only selected GPIO interrupts need | |
500 | * to have wake-up enabled. | |
501 | */ | |
502 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
503 | { | |
f64ad1a0 KH |
504 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
505 | unsigned long flags; | |
a6472533 | 506 | |
f64ad1a0 | 507 | if (bank->non_wakeup_gpios & gpio_bit) { |
862ff640 | 508 | dev_err(bank->dev, |
f64ad1a0 | 509 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); |
92105bb7 TL |
510 | return -EINVAL; |
511 | } | |
f64ad1a0 KH |
512 | |
513 | spin_lock_irqsave(&bank->lock, flags); | |
514 | if (enable) | |
0aa27273 | 515 | bank->context.wake_en |= gpio_bit; |
f64ad1a0 | 516 | else |
0aa27273 | 517 | bank->context.wake_en &= ~gpio_bit; |
f64ad1a0 | 518 | |
0aa27273 | 519 | __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en); |
f64ad1a0 KH |
520 | spin_unlock_irqrestore(&bank->lock, flags); |
521 | ||
522 | return 0; | |
92105bb7 TL |
523 | } |
524 | ||
4196dd6b TL |
525 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
526 | { | |
129fd223 | 527 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
528 | _set_gpio_irqenable(bank, gpio, 0); |
529 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 530 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
531 | } |
532 | ||
92105bb7 | 533 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 534 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 535 | { |
25db711d BC |
536 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
537 | unsigned int gpio = irq_to_gpio(bank, d->irq); | |
92105bb7 | 538 | |
25db711d | 539 | return _set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
540 | } |
541 | ||
3ff164e1 | 542 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 543 | { |
3ff164e1 | 544 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 545 | unsigned long flags; |
52e31344 | 546 | |
55b93c32 TKD |
547 | /* |
548 | * If this is the first gpio_request for the bank, | |
549 | * enable the bank module. | |
550 | */ | |
551 | if (!bank->mod_usage) | |
552 | pm_runtime_get_sync(bank->dev); | |
92105bb7 | 553 | |
55b93c32 | 554 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b TL |
555 | /* Set trigger to none. You need to enable the desired trigger with |
556 | * request_irq() or set_irq_type(). | |
557 | */ | |
3ff164e1 | 558 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 559 | |
fad96ea8 C |
560 | if (bank->regs->pinctrl) { |
561 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
5e1c5ff4 | 562 | |
92105bb7 | 563 | /* Claim the pin for MPU */ |
3ff164e1 | 564 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 | 565 | } |
fad96ea8 | 566 | |
c8eef65a C |
567 | if (bank->regs->ctrl && !bank->mod_usage) { |
568 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
569 | u32 ctrl; | |
570 | ||
571 | ctrl = __raw_readl(reg); | |
572 | /* Module is enabled, clocks are not gated */ | |
573 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
574 | __raw_writel(ctrl, reg); | |
41d87cbd | 575 | bank->context.ctrl = ctrl; |
058af1ea | 576 | } |
c8eef65a C |
577 | |
578 | bank->mod_usage |= 1 << offset; | |
579 | ||
a6472533 | 580 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
581 | |
582 | return 0; | |
583 | } | |
584 | ||
3ff164e1 | 585 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 586 | { |
3ff164e1 | 587 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
6ed87c5b | 588 | void __iomem *base = bank->base; |
a6472533 | 589 | unsigned long flags; |
5e1c5ff4 | 590 | |
a6472533 | 591 | spin_lock_irqsave(&bank->lock, flags); |
6ed87c5b | 592 | |
41d87cbd | 593 | if (bank->regs->wkup_en) { |
9f096868 | 594 | /* Disable wake-up during idle for dynamic tick */ |
6ed87c5b | 595 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); |
41d87cbd TKD |
596 | bank->context.wake_en = |
597 | __raw_readl(bank->base + bank->regs->wkup_en); | |
598 | } | |
6ed87c5b | 599 | |
c8eef65a C |
600 | bank->mod_usage &= ~(1 << offset); |
601 | ||
602 | if (bank->regs->ctrl && !bank->mod_usage) { | |
603 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
604 | u32 ctrl; | |
605 | ||
606 | ctrl = __raw_readl(reg); | |
607 | /* Module is disabled, clocks are gated */ | |
608 | ctrl |= GPIO_MOD_CTRL_BIT; | |
609 | __raw_writel(ctrl, reg); | |
41d87cbd | 610 | bank->context.ctrl = ctrl; |
058af1ea | 611 | } |
c8eef65a | 612 | |
3ff164e1 | 613 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 614 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
615 | |
616 | /* | |
617 | * If this is the last gpio to be freed in the bank, | |
618 | * disable the bank module. | |
619 | */ | |
620 | if (!bank->mod_usage) | |
621 | pm_runtime_put(bank->dev); | |
5e1c5ff4 TL |
622 | } |
623 | ||
624 | /* | |
625 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
626 | * avoid missing GPIO interrupts for other lines in the bank. | |
627 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
628 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
629 | * If we wait to unmask individual GPIO lines in the bank after the | |
630 | * line's interrupt handler has been run, we may miss some nested | |
631 | * interrupts. | |
632 | */ | |
10dd5ce2 | 633 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 634 | { |
92105bb7 | 635 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 636 | u32 isr; |
4318f36b | 637 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 638 | struct gpio_bank *bank; |
ea6dedd7 | 639 | int unmasked = 0; |
ee144182 | 640 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 641 | |
ee144182 | 642 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 643 | |
6845664a | 644 | bank = irq_get_handler_data(irq); |
eef4bec7 | 645 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 646 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
647 | |
648 | if (WARN_ON(!isr_reg)) | |
649 | goto exit; | |
650 | ||
92105bb7 | 651 | while(1) { |
6e60e79a | 652 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 653 | u32 enabled; |
6e60e79a | 654 | |
ea6dedd7 ID |
655 | enabled = _get_gpio_irqbank_mask(bank); |
656 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a | 657 | |
9ea14d8c | 658 | if (bank->level_mask) |
b144ff6f | 659 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
660 | |
661 | /* clear edge sensitive interrupts before handler(s) are | |
662 | called so that we don't miss any interrupt occurred while | |
663 | executing them */ | |
28f3b5a0 | 664 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 665 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 666 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
667 | |
668 | /* if there is only edge sensitive GPIO pin interrupts | |
669 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
670 | if (!level_mask && !unmasked) { |
671 | unmasked = 1; | |
ee144182 | 672 | chained_irq_exit(chip, desc); |
ea6dedd7 | 673 | } |
92105bb7 TL |
674 | |
675 | if (!isr) | |
676 | break; | |
677 | ||
384ebe1c | 678 | gpio_irq = bank->irq_base; |
92105bb7 | 679 | for (; isr != 0; isr >>= 1, gpio_irq++) { |
25db711d | 680 | int gpio = irq_to_gpio(bank, gpio_irq); |
4318f36b | 681 | |
92105bb7 TL |
682 | if (!(isr & 1)) |
683 | continue; | |
29454dde | 684 | |
25db711d BC |
685 | gpio_index = GPIO_INDEX(bank, gpio); |
686 | ||
4318f36b CM |
687 | /* |
688 | * Some chips can't respond to both rising and falling | |
689 | * at the same time. If this irq was requested with | |
690 | * both flags, we need to flip the ICR data for the IRQ | |
691 | * to respond to the IRQ for the opposite direction. | |
692 | * This will be indicated in the bank toggle_mask. | |
693 | */ | |
694 | if (bank->toggle_mask & (1 << gpio_index)) | |
695 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
4318f36b | 696 | |
d8aa0251 | 697 | generic_handle_irq(gpio_irq); |
92105bb7 | 698 | } |
1a8bfa1e | 699 | } |
ea6dedd7 ID |
700 | /* if bank has any level sensitive GPIO pin interrupt |
701 | configured, we must unmask the bank interrupt only after | |
702 | handler(s) are executed in order to avoid spurious bank | |
703 | interrupt */ | |
b1cc4c55 | 704 | exit: |
ea6dedd7 | 705 | if (!unmasked) |
ee144182 | 706 | chained_irq_exit(chip, desc); |
55b93c32 | 707 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
708 | } |
709 | ||
e9191028 | 710 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 711 | { |
e9191028 | 712 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
25db711d | 713 | unsigned int gpio = irq_to_gpio(bank, d->irq); |
85ec7b97 | 714 | unsigned long flags; |
4196dd6b | 715 | |
85ec7b97 | 716 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 717 | _reset_gpio(bank, gpio); |
85ec7b97 | 718 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
719 | } |
720 | ||
e9191028 | 721 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 722 | { |
e9191028 | 723 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
25db711d | 724 | unsigned int gpio = irq_to_gpio(bank, d->irq); |
5e1c5ff4 TL |
725 | |
726 | _clear_gpio_irqstatus(bank, gpio); | |
727 | } | |
728 | ||
e9191028 | 729 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 730 | { |
e9191028 | 731 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
25db711d | 732 | unsigned int gpio = irq_to_gpio(bank, d->irq); |
85ec7b97 | 733 | unsigned long flags; |
5e1c5ff4 | 734 | |
85ec7b97 | 735 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 736 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 737 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 738 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
739 | } |
740 | ||
e9191028 | 741 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 742 | { |
e9191028 | 743 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
25db711d | 744 | unsigned int gpio = irq_to_gpio(bank, d->irq); |
129fd223 | 745 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 746 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 747 | unsigned long flags; |
55b6019a | 748 | |
85ec7b97 | 749 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 750 | if (trigger) |
129fd223 | 751 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
752 | |
753 | /* For level-triggered GPIOs, the clearing must be done after | |
754 | * the HW source is cleared, thus after the handler has run */ | |
755 | if (bank->level_mask & irq_mask) { | |
756 | _set_gpio_irqenable(bank, gpio, 0); | |
757 | _clear_gpio_irqstatus(bank, gpio); | |
758 | } | |
5e1c5ff4 | 759 | |
4de8c75b | 760 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 761 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
762 | } |
763 | ||
e5c56ed3 DB |
764 | static struct irq_chip gpio_irq_chip = { |
765 | .name = "GPIO", | |
e9191028 LB |
766 | .irq_shutdown = gpio_irq_shutdown, |
767 | .irq_ack = gpio_ack_irq, | |
768 | .irq_mask = gpio_mask_irq, | |
769 | .irq_unmask = gpio_unmask_irq, | |
770 | .irq_set_type = gpio_irq_type, | |
771 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
772 | }; |
773 | ||
774 | /*---------------------------------------------------------------------*/ | |
775 | ||
79ee031f | 776 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 777 | { |
79ee031f | 778 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 779 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
780 | void __iomem *mask_reg = bank->base + |
781 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 782 | unsigned long flags; |
11a78b79 | 783 | |
a6472533 | 784 | spin_lock_irqsave(&bank->lock, flags); |
0aa27273 | 785 | __raw_writel(0xffff & ~bank->context.wake_en, mask_reg); |
a6472533 | 786 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
787 | |
788 | return 0; | |
789 | } | |
790 | ||
79ee031f | 791 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 792 | { |
79ee031f | 793 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 794 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
795 | void __iomem *mask_reg = bank->base + |
796 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 797 | unsigned long flags; |
11a78b79 | 798 | |
a6472533 | 799 | spin_lock_irqsave(&bank->lock, flags); |
499fa287 | 800 | __raw_writel(bank->context.wake_en, mask_reg); |
a6472533 | 801 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
802 | |
803 | return 0; | |
804 | } | |
805 | ||
47145210 | 806 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
807 | .suspend_noirq = omap_mpuio_suspend_noirq, |
808 | .resume_noirq = omap_mpuio_resume_noirq, | |
809 | }; | |
810 | ||
3c437ffd | 811 | /* use platform_driver for this. */ |
11a78b79 | 812 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
813 | .driver = { |
814 | .name = "mpuio", | |
79ee031f | 815 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
816 | }, |
817 | }; | |
818 | ||
819 | static struct platform_device omap_mpuio_device = { | |
820 | .name = "mpuio", | |
821 | .id = -1, | |
822 | .dev = { | |
823 | .driver = &omap_mpuio_driver.driver, | |
824 | } | |
825 | /* could list the /proc/iomem resources */ | |
826 | }; | |
827 | ||
03e128ca | 828 | static inline void mpuio_init(struct gpio_bank *bank) |
11a78b79 | 829 | { |
77640aab | 830 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 831 | |
11a78b79 DB |
832 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
833 | (void) platform_device_register(&omap_mpuio_device); | |
834 | } | |
835 | ||
e5c56ed3 | 836 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 837 | |
52e31344 DB |
838 | static int gpio_input(struct gpio_chip *chip, unsigned offset) |
839 | { | |
840 | struct gpio_bank *bank; | |
841 | unsigned long flags; | |
842 | ||
843 | bank = container_of(chip, struct gpio_bank, chip); | |
844 | spin_lock_irqsave(&bank->lock, flags); | |
845 | _set_gpio_direction(bank, offset, 1); | |
846 | spin_unlock_irqrestore(&bank->lock, flags); | |
847 | return 0; | |
848 | } | |
849 | ||
b37c45b8 RQ |
850 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
851 | { | |
fa87931a | 852 | void __iomem *reg = bank->base + bank->regs->direction; |
b37c45b8 | 853 | |
b37c45b8 RQ |
854 | return __raw_readl(reg) & mask; |
855 | } | |
856 | ||
52e31344 DB |
857 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
858 | { | |
b37c45b8 | 859 | struct gpio_bank *bank; |
b37c45b8 RQ |
860 | u32 mask; |
861 | ||
a8be8daf | 862 | bank = container_of(chip, struct gpio_bank, chip); |
7fcca715 | 863 | mask = (1 << offset); |
b37c45b8 RQ |
864 | |
865 | if (gpio_is_input(bank, mask)) | |
7fcca715 | 866 | return _get_gpio_datain(bank, offset); |
b37c45b8 | 867 | else |
7fcca715 | 868 | return _get_gpio_dataout(bank, offset); |
52e31344 DB |
869 | } |
870 | ||
871 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
872 | { | |
873 | struct gpio_bank *bank; | |
874 | unsigned long flags; | |
875 | ||
876 | bank = container_of(chip, struct gpio_bank, chip); | |
877 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 878 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
879 | _set_gpio_direction(bank, offset, 0); |
880 | spin_unlock_irqrestore(&bank->lock, flags); | |
881 | return 0; | |
882 | } | |
883 | ||
168ef3d9 FB |
884 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
885 | unsigned debounce) | |
886 | { | |
887 | struct gpio_bank *bank; | |
888 | unsigned long flags; | |
889 | ||
890 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab VC |
891 | |
892 | if (!bank->dbck) { | |
893 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
894 | if (IS_ERR(bank->dbck)) | |
895 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
896 | } | |
897 | ||
168ef3d9 FB |
898 | spin_lock_irqsave(&bank->lock, flags); |
899 | _set_gpio_debounce(bank, offset, debounce); | |
900 | spin_unlock_irqrestore(&bank->lock, flags); | |
901 | ||
902 | return 0; | |
903 | } | |
904 | ||
52e31344 DB |
905 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
906 | { | |
907 | struct gpio_bank *bank; | |
908 | unsigned long flags; | |
909 | ||
910 | bank = container_of(chip, struct gpio_bank, chip); | |
911 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 912 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
913 | spin_unlock_irqrestore(&bank->lock, flags); |
914 | } | |
915 | ||
a007b709 DB |
916 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
917 | { | |
918 | struct gpio_bank *bank; | |
919 | ||
920 | bank = container_of(chip, struct gpio_bank, chip); | |
384ebe1c | 921 | return bank->irq_base + offset; |
a007b709 DB |
922 | } |
923 | ||
52e31344 DB |
924 | /*---------------------------------------------------------------------*/ |
925 | ||
9a748053 | 926 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 927 | { |
e5ff4440 | 928 | static bool called; |
9f7065da TL |
929 | u32 rev; |
930 | ||
e5ff4440 | 931 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
932 | return; |
933 | ||
e5ff4440 KH |
934 | rev = __raw_readw(bank->base + bank->regs->revision); |
935 | pr_info("OMAP GPIO hardware version %d.%d\n", | |
9f7065da | 936 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
937 | |
938 | called = true; | |
9f7065da TL |
939 | } |
940 | ||
8ba55c5c DB |
941 | /* This lock class tells lockdep that GPIO irqs are in a different |
942 | * category than their parents, so it won't report false recursion. | |
943 | */ | |
944 | static struct lock_class_key gpio_lock_class; | |
945 | ||
03e128ca | 946 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 947 | { |
ab985f0f TKD |
948 | void __iomem *base = bank->base; |
949 | u32 l = 0xffffffff; | |
2fae7fbe | 950 | |
ab985f0f TKD |
951 | if (bank->width == 16) |
952 | l = 0xffff; | |
953 | ||
d0d665a8 | 954 | if (bank->is_mpuio) { |
ab985f0f TKD |
955 | __raw_writel(l, bank->base + bank->regs->irqenable); |
956 | return; | |
2fae7fbe | 957 | } |
ab985f0f TKD |
958 | |
959 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv); | |
6edd94db | 960 | _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv); |
ab985f0f | 961 | if (bank->regs->debounce_en) |
6edd94db | 962 | __raw_writel(0, base + bank->regs->debounce_en); |
ab985f0f | 963 | |
2dc983c5 TKD |
964 | /* Save OE default value (0xffffffff) in the context */ |
965 | bank->context.oe = __raw_readl(bank->base + bank->regs->direction); | |
ab985f0f TKD |
966 | /* Initialize interface clk ungated, module enabled */ |
967 | if (bank->regs->ctrl) | |
6edd94db | 968 | __raw_writel(0, base + bank->regs->ctrl); |
2fae7fbe VC |
969 | } |
970 | ||
8805f410 | 971 | static __devinit void |
f8b46b58 KH |
972 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, |
973 | unsigned int num) | |
974 | { | |
975 | struct irq_chip_generic *gc; | |
976 | struct irq_chip_type *ct; | |
977 | ||
978 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
979 | handle_simple_irq); | |
83233749 TP |
980 | if (!gc) { |
981 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
982 | return; | |
983 | } | |
984 | ||
f8b46b58 KH |
985 | ct = gc->chip_types; |
986 | ||
987 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
988 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
989 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
990 | ct->chip.irq_set_type = gpio_irq_type; | |
6ed87c5b TKD |
991 | |
992 | if (bank->regs->wkup_en) | |
f8b46b58 KH |
993 | ct->chip.irq_set_wake = gpio_wake_enable, |
994 | ||
995 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
996 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
997 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
998 | } | |
999 | ||
d52b31de | 1000 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 1001 | { |
77640aab | 1002 | int j; |
2fae7fbe VC |
1003 | static int gpio; |
1004 | ||
2fae7fbe VC |
1005 | /* |
1006 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1007 | * over to the generic ones | |
1008 | */ | |
1009 | bank->chip.request = omap_gpio_request; | |
1010 | bank->chip.free = omap_gpio_free; | |
1011 | bank->chip.direction_input = gpio_input; | |
1012 | bank->chip.get = gpio_get; | |
1013 | bank->chip.direction_output = gpio_output; | |
1014 | bank->chip.set_debounce = gpio_debounce; | |
1015 | bank->chip.set = gpio_set; | |
1016 | bank->chip.to_irq = gpio_2irq; | |
d0d665a8 | 1017 | if (bank->is_mpuio) { |
2fae7fbe | 1018 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
1019 | if (bank->regs->wkup_en) |
1020 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
1021 | bank->chip.base = OMAP_MPUIO(0); |
1022 | } else { | |
1023 | bank->chip.label = "gpio"; | |
1024 | bank->chip.base = gpio; | |
d5f46247 | 1025 | gpio += bank->width; |
2fae7fbe | 1026 | } |
d5f46247 | 1027 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
1028 | |
1029 | gpiochip_add(&bank->chip); | |
1030 | ||
384ebe1c | 1031 | for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) { |
1475b85d | 1032 | irq_set_lockdep_class(j, &gpio_lock_class); |
6845664a | 1033 | irq_set_chip_data(j, bank); |
d0d665a8 | 1034 | if (bank->is_mpuio) { |
f8b46b58 KH |
1035 | omap_mpuio_alloc_gc(bank, j, bank->width); |
1036 | } else { | |
6845664a | 1037 | irq_set_chip(j, &gpio_irq_chip); |
f8b46b58 KH |
1038 | irq_set_handler(j, handle_simple_irq); |
1039 | set_irq_flags(j, IRQF_VALID); | |
1040 | } | |
2fae7fbe | 1041 | } |
6845664a TG |
1042 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1043 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
1044 | } |
1045 | ||
384ebe1c BC |
1046 | static const struct of_device_id omap_gpio_match[]; |
1047 | ||
77640aab | 1048 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1049 | { |
862ff640 | 1050 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1051 | struct device_node *node = dev->of_node; |
1052 | const struct of_device_id *match; | |
77640aab VC |
1053 | struct omap_gpio_platform_data *pdata; |
1054 | struct resource *res; | |
5e1c5ff4 | 1055 | struct gpio_bank *bank; |
03e128ca | 1056 | int ret = 0; |
5e1c5ff4 | 1057 | |
384ebe1c BC |
1058 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1059 | ||
1060 | pdata = match ? match->data : dev->platform_data; | |
1061 | if (!pdata) | |
96751fcb | 1062 | return -EINVAL; |
5492fb1a | 1063 | |
96751fcb | 1064 | bank = devm_kzalloc(&pdev->dev, sizeof(struct gpio_bank), GFP_KERNEL); |
03e128ca | 1065 | if (!bank) { |
862ff640 | 1066 | dev_err(dev, "Memory alloc failed\n"); |
96751fcb | 1067 | return -ENOMEM; |
03e128ca | 1068 | } |
92105bb7 | 1069 | |
77640aab VC |
1070 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1071 | if (unlikely(!res)) { | |
862ff640 | 1072 | dev_err(dev, "Invalid IRQ resource\n"); |
96751fcb | 1073 | return -ENODEV; |
44169075 | 1074 | } |
5e1c5ff4 | 1075 | |
77640aab | 1076 | bank->irq = res->start; |
862ff640 | 1077 | bank->dev = dev; |
77640aab | 1078 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1079 | bank->stride = pdata->bank_stride; |
d5f46247 | 1080 | bank->width = pdata->bank_width; |
d0d665a8 | 1081 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1082 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
0cde8d03 | 1083 | bank->loses_context = pdata->loses_context; |
60a3437d | 1084 | bank->get_context_loss_count = pdata->get_context_loss_count; |
fa87931a | 1085 | bank->regs = pdata->regs; |
384ebe1c BC |
1086 | #ifdef CONFIG_OF_GPIO |
1087 | bank->chip.of_node = of_node_get(node); | |
1088 | #endif | |
1089 | ||
1090 | bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0); | |
1091 | if (bank->irq_base < 0) { | |
1092 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
1093 | return -ENODEV; | |
1094 | } | |
1095 | ||
1096 | bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base, | |
1097 | 0, &irq_domain_simple_ops, NULL); | |
fa87931a KH |
1098 | |
1099 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1100 | bank->set_dataout = _set_gpio_dataout_reg; | |
1101 | else | |
1102 | bank->set_dataout = _set_gpio_dataout_mask; | |
9f7065da | 1103 | |
77640aab | 1104 | spin_lock_init(&bank->lock); |
9f7065da | 1105 | |
77640aab VC |
1106 | /* Static mapping, never released */ |
1107 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1108 | if (unlikely(!res)) { | |
862ff640 | 1109 | dev_err(dev, "Invalid mem resource\n"); |
96751fcb BC |
1110 | return -ENODEV; |
1111 | } | |
1112 | ||
1113 | if (!devm_request_mem_region(dev, res->start, resource_size(res), | |
1114 | pdev->name)) { | |
1115 | dev_err(dev, "Region already claimed\n"); | |
1116 | return -EBUSY; | |
77640aab | 1117 | } |
89db9482 | 1118 | |
96751fcb | 1119 | bank->base = devm_ioremap(dev, res->start, resource_size(res)); |
77640aab | 1120 | if (!bank->base) { |
862ff640 | 1121 | dev_err(dev, "Could not ioremap\n"); |
96751fcb | 1122 | return -ENOMEM; |
5e1c5ff4 TL |
1123 | } |
1124 | ||
065cd795 TKD |
1125 | platform_set_drvdata(pdev, bank); |
1126 | ||
77640aab | 1127 | pm_runtime_enable(bank->dev); |
55b93c32 | 1128 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1129 | pm_runtime_get_sync(bank->dev); |
1130 | ||
d0d665a8 | 1131 | if (bank->is_mpuio) |
ab985f0f TKD |
1132 | mpuio_init(bank); |
1133 | ||
03e128ca | 1134 | omap_gpio_mod_init(bank); |
77640aab | 1135 | omap_gpio_chip_init(bank); |
9a748053 | 1136 | omap_gpio_show_rev(bank); |
9f7065da | 1137 | |
55b93c32 TKD |
1138 | pm_runtime_put(bank->dev); |
1139 | ||
03e128ca | 1140 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1141 | |
03e128ca | 1142 | return ret; |
5e1c5ff4 TL |
1143 | } |
1144 | ||
55b93c32 TKD |
1145 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1146 | ||
2dc983c5 | 1147 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1148 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1149 | |
2dc983c5 | 1150 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1151 | { |
2dc983c5 TKD |
1152 | struct platform_device *pdev = to_platform_device(dev); |
1153 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1154 | u32 l1 = 0, l2 = 0; | |
1155 | unsigned long flags; | |
68942edb | 1156 | u32 wake_low, wake_hi; |
8865b9b6 | 1157 | |
2dc983c5 | 1158 | spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1159 | |
1160 | /* | |
1161 | * Only edges can generate a wakeup event to the PRCM. | |
1162 | * | |
1163 | * Therefore, ensure any wake-up capable GPIOs have | |
1164 | * edge-detection enabled before going idle to ensure a wakeup | |
1165 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1166 | * NDA TRM 25.5.3.1) | |
1167 | * | |
1168 | * The normal values will be restored upon ->runtime_resume() | |
1169 | * by writing back the values saved in bank->context. | |
1170 | */ | |
1171 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1172 | if (wake_low) | |
1173 | __raw_writel(wake_low | bank->context.fallingdetect, | |
1174 | bank->base + bank->regs->fallingdetect); | |
1175 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1176 | if (wake_hi) | |
1177 | __raw_writel(wake_hi | bank->context.risingdetect, | |
1178 | bank->base + bank->regs->risingdetect); | |
1179 | ||
b3c64bc3 KH |
1180 | if (!bank->enabled_non_wakeup_gpios) |
1181 | goto update_gpio_context_count; | |
1182 | ||
2dc983c5 TKD |
1183 | if (bank->power_mode != OFF_MODE) { |
1184 | bank->power_mode = 0; | |
41d87cbd | 1185 | goto update_gpio_context_count; |
2dc983c5 TKD |
1186 | } |
1187 | /* | |
1188 | * If going to OFF, remove triggering for all | |
1189 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1190 | * generated. See OMAP2420 Errata item 1.101. | |
1191 | */ | |
2dc983c5 TKD |
1192 | bank->saved_datain = __raw_readl(bank->base + |
1193 | bank->regs->datain); | |
c6f31c9e TKD |
1194 | l1 = bank->context.fallingdetect; |
1195 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1196 | |
2dc983c5 TKD |
1197 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1198 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1199 | |
2dc983c5 TKD |
1200 | __raw_writel(l1, bank->base + bank->regs->fallingdetect); |
1201 | __raw_writel(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1202 | |
2dc983c5 | 1203 | bank->workaround_enabled = true; |
3f1686a9 | 1204 | |
41d87cbd | 1205 | update_gpio_context_count: |
2dc983c5 TKD |
1206 | if (bank->get_context_loss_count) |
1207 | bank->context_loss_count = | |
60a3437d TKD |
1208 | bank->get_context_loss_count(bank->dev); |
1209 | ||
72f83af9 | 1210 | _gpio_dbck_disable(bank); |
2dc983c5 | 1211 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1212 | |
2dc983c5 | 1213 | return 0; |
3ac4fa99 JY |
1214 | } |
1215 | ||
2dc983c5 | 1216 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1217 | { |
2dc983c5 TKD |
1218 | struct platform_device *pdev = to_platform_device(dev); |
1219 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1220 | int context_lost_cnt_after; | |
1221 | u32 l = 0, gen, gen0, gen1; | |
1222 | unsigned long flags; | |
8865b9b6 | 1223 | |
2dc983c5 | 1224 | spin_lock_irqsave(&bank->lock, flags); |
72f83af9 | 1225 | _gpio_dbck_enable(bank); |
68942edb KH |
1226 | |
1227 | /* | |
1228 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1229 | * GPIOs were set to edge trigger also in order to be able to | |
1230 | * generate a PRCM wakeup. Here we restore the | |
1231 | * pre-runtime_suspend() values for edge triggering. | |
1232 | */ | |
1233 | __raw_writel(bank->context.fallingdetect, | |
1234 | bank->base + bank->regs->fallingdetect); | |
1235 | __raw_writel(bank->context.risingdetect, | |
1236 | bank->base + bank->regs->risingdetect); | |
1237 | ||
2dc983c5 TKD |
1238 | if (bank->get_context_loss_count) { |
1239 | context_lost_cnt_after = | |
1240 | bank->get_context_loss_count(bank->dev); | |
22770de1 | 1241 | if (context_lost_cnt_after != bank->context_loss_count) { |
2dc983c5 TKD |
1242 | omap_gpio_restore_context(bank); |
1243 | } else { | |
1244 | spin_unlock_irqrestore(&bank->lock, flags); | |
1245 | return 0; | |
60a3437d | 1246 | } |
2dc983c5 | 1247 | } |
43ffcd9a | 1248 | |
1b128703 TKD |
1249 | if (!bank->workaround_enabled) { |
1250 | spin_unlock_irqrestore(&bank->lock, flags); | |
1251 | return 0; | |
1252 | } | |
1253 | ||
c6f31c9e | 1254 | __raw_writel(bank->context.fallingdetect, |
2dc983c5 | 1255 | bank->base + bank->regs->fallingdetect); |
c6f31c9e | 1256 | __raw_writel(bank->context.risingdetect, |
2dc983c5 TKD |
1257 | bank->base + bank->regs->risingdetect); |
1258 | l = __raw_readl(bank->base + bank->regs->datain); | |
3f1686a9 | 1259 | |
2dc983c5 TKD |
1260 | /* |
1261 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1262 | * state. If so, generate an IRQ by software. This is | |
1263 | * horribly racy, but it's the best we can do to work around | |
1264 | * this silicon bug. | |
1265 | */ | |
1266 | l ^= bank->saved_datain; | |
1267 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1268 | |
2dc983c5 TKD |
1269 | /* |
1270 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1271 | * configured with falling edge only; and vice versa. | |
1272 | */ | |
c6f31c9e | 1273 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1274 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1275 | |
c6f31c9e | 1276 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1277 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1278 | |
2dc983c5 | 1279 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1280 | gen = l & (~(bank->context.fallingdetect) & |
1281 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1282 | /* Consider all GPIO IRQs needed to be updated */ |
1283 | gen |= gen0 | gen1; | |
82dbb9d3 | 1284 | |
2dc983c5 TKD |
1285 | if (gen) { |
1286 | u32 old0, old1; | |
82dbb9d3 | 1287 | |
2dc983c5 TKD |
1288 | old0 = __raw_readl(bank->base + bank->regs->leveldetect0); |
1289 | old1 = __raw_readl(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1290 | |
4e962e89 | 1291 | if (!bank->regs->irqstatus_raw0) { |
2dc983c5 | 1292 | __raw_writel(old0 | gen, bank->base + |
9ea14d8c | 1293 | bank->regs->leveldetect0); |
2dc983c5 | 1294 | __raw_writel(old1 | gen, bank->base + |
9ea14d8c | 1295 | bank->regs->leveldetect1); |
2dc983c5 | 1296 | } |
9ea14d8c | 1297 | |
4e962e89 | 1298 | if (bank->regs->irqstatus_raw0) { |
2dc983c5 | 1299 | __raw_writel(old0 | l, bank->base + |
9ea14d8c | 1300 | bank->regs->leveldetect0); |
2dc983c5 | 1301 | __raw_writel(old1 | l, bank->base + |
9ea14d8c | 1302 | bank->regs->leveldetect1); |
3ac4fa99 | 1303 | } |
2dc983c5 TKD |
1304 | __raw_writel(old0, bank->base + bank->regs->leveldetect0); |
1305 | __raw_writel(old1, bank->base + bank->regs->leveldetect1); | |
1306 | } | |
1307 | ||
1308 | bank->workaround_enabled = false; | |
1309 | spin_unlock_irqrestore(&bank->lock, flags); | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | #endif /* CONFIG_PM_RUNTIME */ | |
1314 | ||
1315 | void omap2_gpio_prepare_for_idle(int pwr_mode) | |
1316 | { | |
1317 | struct gpio_bank *bank; | |
1318 | ||
1319 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
2dc983c5 TKD |
1320 | if (!bank->mod_usage || !bank->loses_context) |
1321 | continue; | |
1322 | ||
1323 | bank->power_mode = pwr_mode; | |
1324 | ||
2dc983c5 TKD |
1325 | pm_runtime_put_sync_suspend(bank->dev); |
1326 | } | |
1327 | } | |
1328 | ||
1329 | void omap2_gpio_resume_after_idle(void) | |
1330 | { | |
1331 | struct gpio_bank *bank; | |
1332 | ||
1333 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
2dc983c5 TKD |
1334 | if (!bank->mod_usage || !bank->loses_context) |
1335 | continue; | |
1336 | ||
2dc983c5 | 1337 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1338 | } |
3ac4fa99 JY |
1339 | } |
1340 | ||
2dc983c5 | 1341 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1342 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1343 | { |
60a3437d | 1344 | __raw_writel(bank->context.wake_en, |
ae10f233 TKD |
1345 | bank->base + bank->regs->wkup_en); |
1346 | __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
60a3437d | 1347 | __raw_writel(bank->context.leveldetect0, |
ae10f233 | 1348 | bank->base + bank->regs->leveldetect0); |
60a3437d | 1349 | __raw_writel(bank->context.leveldetect1, |
ae10f233 | 1350 | bank->base + bank->regs->leveldetect1); |
60a3437d | 1351 | __raw_writel(bank->context.risingdetect, |
ae10f233 | 1352 | bank->base + bank->regs->risingdetect); |
60a3437d | 1353 | __raw_writel(bank->context.fallingdetect, |
ae10f233 | 1354 | bank->base + bank->regs->fallingdetect); |
f86bcc30 NM |
1355 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
1356 | __raw_writel(bank->context.dataout, | |
1357 | bank->base + bank->regs->set_dataout); | |
1358 | else | |
1359 | __raw_writel(bank->context.dataout, | |
1360 | bank->base + bank->regs->dataout); | |
6d13eaaf NM |
1361 | __raw_writel(bank->context.oe, bank->base + bank->regs->direction); |
1362 | ||
ae547354 NM |
1363 | if (bank->dbck_enable_mask) { |
1364 | __raw_writel(bank->context.debounce, bank->base + | |
1365 | bank->regs->debounce); | |
1366 | __raw_writel(bank->context.debounce_en, | |
1367 | bank->base + bank->regs->debounce_en); | |
1368 | } | |
ba805be5 NM |
1369 | |
1370 | __raw_writel(bank->context.irqenable1, | |
1371 | bank->base + bank->regs->irqenable); | |
1372 | __raw_writel(bank->context.irqenable2, | |
1373 | bank->base + bank->regs->irqenable2); | |
40c670f0 | 1374 | } |
2dc983c5 | 1375 | #endif /* CONFIG_PM_RUNTIME */ |
55b93c32 | 1376 | #else |
2dc983c5 TKD |
1377 | #define omap_gpio_runtime_suspend NULL |
1378 | #define omap_gpio_runtime_resume NULL | |
40c670f0 RN |
1379 | #endif |
1380 | ||
55b93c32 | 1381 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1382 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1383 | NULL) | |
55b93c32 TKD |
1384 | }; |
1385 | ||
384ebe1c BC |
1386 | #if defined(CONFIG_OF) |
1387 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1388 | .revision = OMAP24XX_GPIO_REVISION, | |
1389 | .direction = OMAP24XX_GPIO_OE, | |
1390 | .datain = OMAP24XX_GPIO_DATAIN, | |
1391 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1392 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1393 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1394 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1395 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1396 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1397 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1398 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1399 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1400 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1401 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1402 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1403 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1404 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1405 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1406 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1407 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1408 | }; | |
1409 | ||
1410 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1411 | .revision = OMAP4_GPIO_REVISION, | |
1412 | .direction = OMAP4_GPIO_OE, | |
1413 | .datain = OMAP4_GPIO_DATAIN, | |
1414 | .dataout = OMAP4_GPIO_DATAOUT, | |
1415 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1416 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1417 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1418 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1419 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1420 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1421 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1422 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1423 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1424 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1425 | .ctrl = OMAP4_GPIO_CTRL, | |
1426 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1427 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1428 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1429 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1430 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1431 | }; | |
1432 | ||
1433 | static struct omap_gpio_platform_data omap2_pdata = { | |
1434 | .regs = &omap2_gpio_regs, | |
1435 | .bank_width = 32, | |
1436 | .dbck_flag = false, | |
1437 | }; | |
1438 | ||
1439 | static struct omap_gpio_platform_data omap3_pdata = { | |
1440 | .regs = &omap2_gpio_regs, | |
1441 | .bank_width = 32, | |
1442 | .dbck_flag = true, | |
1443 | }; | |
1444 | ||
1445 | static struct omap_gpio_platform_data omap4_pdata = { | |
1446 | .regs = &omap4_gpio_regs, | |
1447 | .bank_width = 32, | |
1448 | .dbck_flag = true, | |
1449 | }; | |
1450 | ||
1451 | static const struct of_device_id omap_gpio_match[] = { | |
1452 | { | |
1453 | .compatible = "ti,omap4-gpio", | |
1454 | .data = &omap4_pdata, | |
1455 | }, | |
1456 | { | |
1457 | .compatible = "ti,omap3-gpio", | |
1458 | .data = &omap3_pdata, | |
1459 | }, | |
1460 | { | |
1461 | .compatible = "ti,omap2-gpio", | |
1462 | .data = &omap2_pdata, | |
1463 | }, | |
1464 | { }, | |
1465 | }; | |
1466 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1467 | #endif | |
1468 | ||
77640aab VC |
1469 | static struct platform_driver omap_gpio_driver = { |
1470 | .probe = omap_gpio_probe, | |
1471 | .driver = { | |
1472 | .name = "omap_gpio", | |
55b93c32 | 1473 | .pm = &gpio_pm_ops, |
384ebe1c | 1474 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1475 | }, |
1476 | }; | |
1477 | ||
5e1c5ff4 | 1478 | /* |
77640aab VC |
1479 | * gpio driver register needs to be done before |
1480 | * machine_init functions access gpio APIs. | |
1481 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1482 | */ |
77640aab | 1483 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1484 | { |
77640aab | 1485 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1486 | } |
77640aab | 1487 | postcore_initcall(omap_gpio_drv_reg); |