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gpio/omap: further cleanup using wkup_en register
[mirror_ubuntu-bionic-kernel.git] / drivers / gpio / gpio-omap.c
CommitLineData
5e1c5ff4 1/*
5e1c5ff4
TL		 2 * Support functions for OMAP GPIO
3 *
92105bb7 4 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 6 *
44169075
SS		 7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
5e1c5ff4
TL		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
5e1c5ff4
TL		 15#include <linux/init.h>
16#include <linux/module.h>
5e1c5ff4 17#include <linux/interrupt.h>
3c437ffd 18#include <linux/syscore_ops.h>
92105bb7 19#include <linux/err.h>
f8ce2547 20#include <linux/clk.h>
fced80c7 21#include <linux/io.h>
77640aab
VC		 22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb 27#include <mach/irqs.h>
1bc857f7 28#include <asm/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
03e128ca
C		 31static LIST_HEAD(omap_gpio_list);
32
6d62e216
C		 33struct gpio_regs {
34 u32 irqenable1;
35 u32 irqenable2;
36 u32 wake_en;
37 u32 ctrl;
38 u32 oe;
39 u32 leveldetect0;
40 u32 leveldetect1;
41 u32 risingdetect;
42 u32 fallingdetect;
43 u32 dataout;
44};
45
5e1c5ff4 46struct gpio_bank {
03e128ca 47 struct list_head node;
9f7065da 48 unsigned long pbase;
92105bb7 49 void __iomem *base;
5e1c5ff4
TL		 50 u16 irq;
51 u16 virtual_irq_start;
92105bb7 52 int method;
92105bb7
TL		 53 u32 suspend_wakeup;
54 u32 saved_wakeup;
3ac4fa99
JY		 55 u32 non_wakeup_gpios;
56 u32 enabled_non_wakeup_gpios;
6d62e216 57 struct gpio_regs context;
3ac4fa99
JY		 58 u32 saved_datain;
59 u32 saved_fallingdetect;
60 u32 saved_risingdetect;
b144ff6f 61 u32 level_mask;
4318f36b 62 u32 toggle_mask;
5e1c5ff4 63 spinlock_t lock;
52e31344 64 struct gpio_chip chip;
89db9482 65 struct clk *dbck;
058af1ea 66 u32 mod_usage;
8865b9b6 67 u32 dbck_enable_mask;
77640aab
VC		 68 struct device *dev;
69 bool dbck_flag;
0cde8d03 70 bool loses_context;
5de62b86 71 int stride;
d5f46247 72 u32 width;
60a3437d 73 int context_loss_count;
03e128ca 74 u16 id;
fa87931a
KH		 75
76 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60a3437d 77 int (*get_context_loss_count)(struct device *dev);
fa87931a
KH		 78
79 struct omap_gpio_reg_offs *regs;
5e1c5ff4
TL		 80};
81
129fd223
KH		 82#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
83#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
c8eef65a 84#define GPIO_MOD_CTRL_BIT BIT(0)
5e1c5ff4
TL		 85
86static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
87{
92105bb7 88 void __iomem *reg = bank->base;
5e1c5ff4
TL		 89 u32 l;
90
fa87931a 91 reg += bank->regs->direction;
5e1c5ff4
TL		 92 l = __raw_readl(reg);
93 if (is_input)
94 l |= 1 << gpio;
95 else
96 l &= ~(1 << gpio);
97 __raw_writel(l, reg);
98}
99
fa87931a
KH		 100
101/* set data out value using dedicate set/clear register */
102static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
5e1c5ff4 103{
92105bb7 104 void __iomem *reg = bank->base;
fa87931a 105 u32 l = GPIO_BIT(bank, gpio);
5e1c5ff4 106
fa87931a
KH		 107 if (enable)
108 reg += bank->regs->set_dataout;
109 else
110 reg += bank->regs->clr_dataout;
5e1c5ff4 111
5e1c5ff4
TL		 112 __raw_writel(l, reg);
113}
114
fa87931a
KH		 115/* set data out value using mask register */
116static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
5e1c5ff4 117{
fa87931a
KH		 118 void __iomem *reg = bank->base + bank->regs->dataout;
119 u32 gpio_bit = GPIO_BIT(bank, gpio);
120 u32 l;
5e1c5ff4 121
fa87931a
KH		 122 l = __raw_readl(reg);
123 if (enable)
124 l |= gpio_bit;
125 else
126 l &= ~gpio_bit;
5e1c5ff4 127 __raw_writel(l, reg);
5e1c5ff4
TL		 128}
129
b37c45b8 130static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
b37c45b8 131{
fa87931a 132 void __iomem *reg = bank->base + bank->regs->datain;
b37c45b8 133
fa87931a 134 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
5e1c5ff4 135}
b37c45b8 136
b37c45b8
RQ		 137static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
138{
fa87931a 139 void __iomem *reg = bank->base + bank->regs->dataout;
b37c45b8 140
129fd223 141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
b37c45b8
RQ		 142}
143
ece9528e
KH		 144static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
145{
146 int l = __raw_readl(base + reg);
147
148 if (set)
149 l |= mask;
150 else
151 l &= ~mask;
152
153 __raw_writel(l, base + reg);
154}
92105bb7 155
168ef3d9
FB		 156/**
157 * _set_gpio_debounce - low level gpio debounce time
158 * @bank: the gpio bank we're acting upon
159 * @gpio: the gpio number on this @gpio
160 * @debounce: debounce time to use
161 *
162 * OMAP's debounce time is in 31us steps so we need
163 * to convert and round up to the closest unit.
164 */
165static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
166 unsigned debounce)
167{
9942da0e 168 void __iomem *reg;
168ef3d9
FB		 169 u32 val;
170 u32 l;
171
77640aab
VC		 172 if (!bank->dbck_flag)
173 return;
174
168ef3d9
FB		 175 if (debounce < 32)
176 debounce = 0x01;
177 else if (debounce > 7936)
178 debounce = 0xff;
179 else
180 debounce = (debounce / 0x1f) - 1;
181
129fd223 182 l = GPIO_BIT(bank, gpio);
168ef3d9 183
9942da0e 184 reg = bank->base + bank->regs->debounce;
168ef3d9
FB		 185 __raw_writel(debounce, reg);
186
9942da0e 187 reg = bank->base + bank->regs->debounce_en;
168ef3d9
FB		 188 val = __raw_readl(reg);
189
190 if (debounce) {
191 val |= l;
77640aab 192 clk_enable(bank->dbck);
168ef3d9
FB		 193 } else {
194 val &= ~l;
77640aab 195 clk_disable(bank->dbck);
168ef3d9 196 }
f7ec0b0b 197 bank->dbck_enable_mask = val;
168ef3d9
FB		 198
199 __raw_writel(val, reg);
200}
201
140455fa 202#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 203static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
204 int trigger)
5e1c5ff4 205{
3ac4fa99 206 void __iomem *base = bank->base;
92105bb7
TL		 207 u32 gpio_bit = 1 << gpio;
208
78a1a6d3 209 if (cpu_is_omap44xx()) {
ece9528e
KH		 210 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
211 trigger & IRQ_TYPE_LEVEL_LOW);
212 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
213 trigger & IRQ_TYPE_LEVEL_HIGH);
214 _gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit,
215 trigger & IRQ_TYPE_EDGE_RISING);
216 _gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit,
217 trigger & IRQ_TYPE_EDGE_FALLING);
78a1a6d3 218 } else {
ece9528e
KH		 219 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
220 trigger & IRQ_TYPE_LEVEL_LOW);
221 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
222 trigger & IRQ_TYPE_LEVEL_HIGH);
223 _gpio_rmw(base, OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
224 trigger & IRQ_TYPE_EDGE_RISING);
225 _gpio_rmw(base, OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
226 trigger & IRQ_TYPE_EDGE_FALLING);
78a1a6d3 227 }
3ac4fa99 228 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3 229 if (cpu_is_omap44xx()) {
ece9528e
KH		 230 _gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit,
231 trigger != 0);
78a1a6d3 232 } else {
699117a6
CW		 233 /*
234 * GPIO wakeup request can only be generated on edge
235 * transitions
236 */
237 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 238 __raw_writel(1 << gpio, bank->base
5eb3bb9c 239 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 240 else
241 __raw_writel(1 << gpio, bank->base
5eb3bb9c 242 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 243 }
a118b5f3 244 }
55b220ca
A		 245 /* This part needs to be executed always for OMAP{34xx, 44xx} */
246 if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
247 (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 248 /*
249 * Log the edge gpio and manually trigger the IRQ
250 * after resume if the input level changes
251 * to avoid irq lost during PER RET/OFF mode
252 * Applies for omap2 non-wakeup gpio and all omap3 gpios
253 */
254 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 255 bank->enabled_non_wakeup_gpios |= gpio_bit;
256 else
257 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
258 }
5eb3bb9c 259
78a1a6d3
SR		 260 if (cpu_is_omap44xx()) {
261 bank->level_mask =
262 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
263 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
264 } else {
265 bank->level_mask =
266 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
267 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
268 }
92105bb7 269}
3ac4fa99 270#endif
92105bb7 271
9198bcd3 272#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 273/*
274 * This only applies to chips that can't do both rising and falling edge
275 * detection at once. For all other chips, this function is a noop.
276 */
277static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
278{
279 void __iomem *reg = bank->base;
280 u32 l = 0;
281
282 switch (bank->method) {
4318f36b 283 case METHOD_MPUIO:
5de62b86 284 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
4318f36b 285 break;
4318f36b
CM		 286#ifdef CONFIG_ARCH_OMAP15XX
287 case METHOD_GPIO_1510:
288 reg += OMAP1510_GPIO_INT_CONTROL;
289 break;
290#endif
291#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
292 case METHOD_GPIO_7XX:
293 reg += OMAP7XX_GPIO_INT_CONTROL;
294 break;
295#endif
296 default:
297 return;
298 }
299
300 l = __raw_readl(reg);
301 if ((l >> gpio) & 1)
302 l &= ~(1 << gpio);
303 else
304 l |= 1 << gpio;
305
306 __raw_writel(l, reg);
307}
9198bcd3 308#endif
4318f36b 309
92105bb7
TL		 310static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
311{
312 void __iomem *reg = bank->base;
313 u32 l = 0;
5e1c5ff4
TL		 314
315 switch (bank->method) {
e5c56ed3 316#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 317 case METHOD_MPUIO:
5de62b86 318 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
5e1c5ff4 319 l = __raw_readl(reg);
29501577 320 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 321 bank->toggle_mask |= 1 << gpio;
6cab4860 322 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 323 l |= 1 << gpio;
6cab4860 324 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 325 l &= ~(1 << gpio);
92105bb7
TL		 326 else
327 goto bad;
5e1c5ff4 328 break;
e5c56ed3
DB		 329#endif
330#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 331 case METHOD_GPIO_1510:
332 reg += OMAP1510_GPIO_INT_CONTROL;
333 l = __raw_readl(reg);
29501577 334 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 335 bank->toggle_mask |= 1 << gpio;
6cab4860 336 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 337 l |= 1 << gpio;
6cab4860 338 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 339 l &= ~(1 << gpio);
92105bb7
TL		 340 else
341 goto bad;
5e1c5ff4 342 break;
e5c56ed3 343#endif
3ac4fa99 344#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 345 case METHOD_GPIO_1610:
5e1c5ff4
TL		 346 if (gpio & 0x08)
347 reg += OMAP1610_GPIO_EDGE_CTRL2;
348 else
349 reg += OMAP1610_GPIO_EDGE_CTRL1;
350 gpio &= 0x07;
351 l = __raw_readl(reg);
352 l &= ~(3 << (gpio << 1));
6cab4860 353 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 354 l |= 2 << (gpio << 1);
6cab4860 355 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 356 l |= 1 << (gpio << 1);
3ac4fa99
JY		 357 if (trigger)
358 /* Enable wake-up during idle for dynamic tick */
359 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
360 else
361 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 362 break;
3ac4fa99 363#endif
b718aa81 364#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 365 case METHOD_GPIO_7XX:
366 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 367 l = __raw_readl(reg);
29501577 368 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 369 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 370 if (trigger & IRQ_TYPE_EDGE_RISING)
371 l |= 1 << gpio;
372 else if (trigger & IRQ_TYPE_EDGE_FALLING)
373 l &= ~(1 << gpio);
374 else
375 goto bad;
376 break;
377#endif
140455fa 378#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 379 case METHOD_GPIO_24XX:
3f1686a9 380 case METHOD_GPIO_44XX:
3ac4fa99 381 set_24xx_gpio_triggering(bank, gpio, trigger);
f7c5cc45 382 return 0;
3ac4fa99 383#endif
5e1c5ff4 384 default:
92105bb7 385 goto bad;
5e1c5ff4 386 }
92105bb7
TL		 387 __raw_writel(l, reg);
388 return 0;
389bad:
390 return -EINVAL;
5e1c5ff4
TL		 391}
392
e9191028 393static int gpio_irq_type(struct irq_data *d, unsigned type)
5e1c5ff4
TL		 394{
395 struct gpio_bank *bank;
92105bb7
TL		 396 unsigned gpio;
397 int retval;
a6472533 398 unsigned long flags;
92105bb7 399
e9191028
LB		 400 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
401 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
92105bb7 402 else
e9191028 403 gpio = d->irq - IH_GPIO_BASE;
5e1c5ff4 404
e5c56ed3 405 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 406 return -EINVAL;
e5c56ed3
DB		 407
408 /* OMAP1 allows only only edge triggering */
5492fb1a 409 if (!cpu_class_is_omap2()
e5c56ed3 410 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 411 return -EINVAL;
412
e9191028 413 bank = irq_data_get_irq_chip_data(d);
a6472533 414 spin_lock_irqsave(&bank->lock, flags);
129fd223 415 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
a6472533 416 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 417
418 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
6845664a 419 __irq_set_handler_locked(d->irq, handle_level_irq);
672e302e 420 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
6845664a 421 __irq_set_handler_locked(d->irq, handle_edge_irq);
672e302e 422
92105bb7 423 return retval;
5e1c5ff4
TL		 424}
425
426static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
427{
92105bb7 428 void __iomem *reg = bank->base;
5e1c5ff4 429
eef4bec7 430 reg += bank->regs->irqstatus;
5e1c5ff4 431 __raw_writel(gpio_mask, reg);
bee7930f
HD		 432
433 /* Workaround for clearing DSP GPIO interrupts to allow retention */
eef4bec7
KH		 434 if (bank->regs->irqstatus2) {
435 reg = bank->base + bank->regs->irqstatus2;
bedfd154 436 __raw_writel(gpio_mask, reg);
eef4bec7 437 }
bedfd154
RQ		 438
439 /* Flush posted write for the irq status to avoid spurious interrupts */
440 __raw_readl(reg);
5e1c5ff4
TL		 441}
442
443static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
444{
129fd223 445 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 446}
447
ea6dedd7
ID		 448static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
449{
450 void __iomem *reg = bank->base;
99c47707 451 u32 l;
c390aad0 452 u32 mask = (1 << bank->width) - 1;
ea6dedd7 453
28f3b5a0 454 reg += bank->regs->irqenable;
99c47707 455 l = __raw_readl(reg);
28f3b5a0 456 if (bank->regs->irqenable_inv)
99c47707
ID		 457 l = ~l;
458 l &= mask;
459 return l;
ea6dedd7
ID		 460}
461
28f3b5a0 462static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
5e1c5ff4 463{
92105bb7 464 void __iomem *reg = bank->base;
5e1c5ff4
TL		 465 u32 l;
466
28f3b5a0
KH		 467 if (bank->regs->set_irqenable) {
468 reg += bank->regs->set_irqenable;
469 l = gpio_mask;
470 } else {
471 reg += bank->regs->irqenable;
5e1c5ff4 472 l = __raw_readl(reg);
28f3b5a0
KH		 473 if (bank->regs->irqenable_inv)
474 l &= ~gpio_mask;
5e1c5ff4
TL		 475 else
476 l |= gpio_mask;
28f3b5a0
KH		 477 }
478
479 __raw_writel(l, reg);
480}
481
482static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
483{
484 void __iomem *reg = bank->base;
485 u32 l;
486
487 if (bank->regs->clr_irqenable) {
488 reg += bank->regs->clr_irqenable;
5e1c5ff4 489 l = gpio_mask;
28f3b5a0
KH		 490 } else {
491 reg += bank->regs->irqenable;
56739a69 492 l = __raw_readl(reg);
28f3b5a0 493 if (bank->regs->irqenable_inv)
56739a69 494 l |= gpio_mask;
92105bb7 495 else
28f3b5a0 496 l &= ~gpio_mask;
5e1c5ff4 497 }
28f3b5a0 498
5e1c5ff4
TL		 499 __raw_writel(l, reg);
500}
501
502static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
503{
28f3b5a0 504 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 505}
506
92105bb7
TL		 507/*
508 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
509 * 1510 does not seem to have a wake-up register. If JTAG is connected
510 * to the target, system will wake up always on GPIO events. While
511 * system is running all registered GPIO interrupts need to have wake-up
512 * enabled. When system is suspended, only selected GPIO interrupts need
513 * to have wake-up enabled.
514 */
515static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
516{
f64ad1a0
KH		 517 u32 gpio_bit = GPIO_BIT(bank, gpio);
518 unsigned long flags;
a6472533 519
f64ad1a0
KH		 520 if (bank->non_wakeup_gpios & gpio_bit) {
521 dev_err(bank->dev,
522 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
92105bb7
TL		 523 return -EINVAL;
524 }
f64ad1a0
KH		 525
526 spin_lock_irqsave(&bank->lock, flags);
527 if (enable)
528 bank->suspend_wakeup |= gpio_bit;
529 else
530 bank->suspend_wakeup &= ~gpio_bit;
531
532 spin_unlock_irqrestore(&bank->lock, flags);
533
534 return 0;
92105bb7
TL		 535}
536
4196dd6b
TL		 537static void _reset_gpio(struct gpio_bank *bank, int gpio)
538{
129fd223 539 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
4196dd6b
TL		 540 _set_gpio_irqenable(bank, gpio, 0);
541 _clear_gpio_irqstatus(bank, gpio);
129fd223 542 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 543}
544
92105bb7 545/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
e9191028 546static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
92105bb7 547{
e9191028 548 unsigned int gpio = d->irq - IH_GPIO_BASE;
92105bb7
TL		 549 struct gpio_bank *bank;
550 int retval;
551
e9191028 552 bank = irq_data_get_irq_chip_data(d);
f64ad1a0 553 retval = _set_gpio_wakeup(bank, gpio, enable);
92105bb7
TL		 554
555 return retval;
556}
557
3ff164e1 558static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 559{
3ff164e1 560 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 561 unsigned long flags;
52e31344 562
a6472533 563 spin_lock_irqsave(&bank->lock, flags);
92105bb7 564
4196dd6b
TL		 565 /* Set trigger to none. You need to enable the desired trigger with
566 * request_irq() or set_irq_type().
567 */
3ff164e1 568 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 569
1a8bfa1e 570#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 571 if (bank->method == METHOD_GPIO_1510) {
92105bb7 572 void __iomem *reg;
5e1c5ff4 573
92105bb7 574 /* Claim the pin for MPU */
5e1c5ff4 575 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 576 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 577 }
578#endif
c8eef65a
C		 579 if (bank->regs->ctrl && !bank->mod_usage) {
580 void __iomem *reg = bank->base + bank->regs->ctrl;
581 u32 ctrl;
582
583 ctrl = __raw_readl(reg);
584 /* Module is enabled, clocks are not gated */
585 ctrl &= ~GPIO_MOD_CTRL_BIT;
586 __raw_writel(ctrl, reg);
058af1ea 587 }
c8eef65a
C		 588
589 bank->mod_usage |= 1 << offset;
590
a6472533 591 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 592
593 return 0;
594}
595
3ff164e1 596static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 597{
3ff164e1 598 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
6ed87c5b 599 void __iomem *base = bank->base;
a6472533 600 unsigned long flags;
5e1c5ff4 601
a6472533 602 spin_lock_irqsave(&bank->lock, flags);
6ed87c5b
TKD		 603
604 if (bank->regs->wkup_en)
9f096868 605 /* Disable wake-up during idle for dynamic tick */
6ed87c5b
TKD		 606 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
607
c8eef65a
C		 608 bank->mod_usage &= ~(1 << offset);
609
610 if (bank->regs->ctrl && !bank->mod_usage) {
611 void __iomem *reg = bank->base + bank->regs->ctrl;
612 u32 ctrl;
613
614 ctrl = __raw_readl(reg);
615 /* Module is disabled, clocks are gated */
616 ctrl |= GPIO_MOD_CTRL_BIT;
617 __raw_writel(ctrl, reg);
058af1ea 618 }
c8eef65a 619
3ff164e1 620 _reset_gpio(bank, bank->chip.base + offset);
a6472533 621 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 622}
623
624/*
625 * We need to unmask the GPIO bank interrupt as soon as possible to
626 * avoid missing GPIO interrupts for other lines in the bank.
627 * Then we need to mask-read-clear-unmask the triggered GPIO lines
628 * in the bank to avoid missing nested interrupts for a GPIO line.
629 * If we wait to unmask individual GPIO lines in the bank after the
630 * line's interrupt handler has been run, we may miss some nested
631 * interrupts.
632 */
10dd5ce2 633static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 634{
92105bb7 635 void __iomem *isr_reg = NULL;
5e1c5ff4 636 u32 isr;
4318f36b 637 unsigned int gpio_irq, gpio_index;
5e1c5ff4 638 struct gpio_bank *bank;
ea6dedd7
ID		 639 u32 retrigger = 0;
640 int unmasked = 0;
ee144182 641 struct irq_chip *chip = irq_desc_get_chip(desc);
5e1c5ff4 642
ee144182 643 chained_irq_enter(chip, desc);
5e1c5ff4 644
6845664a 645 bank = irq_get_handler_data(irq);
eef4bec7 646 isr_reg = bank->base + bank->regs->irqstatus;
b1cc4c55
EK		 647
648 if (WARN_ON(!isr_reg))
649 goto exit;
650
92105bb7 651 while(1) {
6e60e79a 652 u32 isr_saved, level_mask = 0;
ea6dedd7 653 u32 enabled;
6e60e79a 654
ea6dedd7
ID		 655 enabled = _get_gpio_irqbank_mask(bank);
656 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 657
658 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
659 isr &= 0x0000ffff;
660
5492fb1a 661 if (cpu_class_is_omap2()) {
b144ff6f 662 level_mask = bank->level_mask & enabled;
ea6dedd7 663 }
6e60e79a
TL		 664
665 /* clear edge sensitive interrupts before handler(s) are
666 called so that we don't miss any interrupt occurred while
667 executing them */
28f3b5a0 668 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
6e60e79a 669 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
28f3b5a0 670 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
6e60e79a
TL		 671
672 /* if there is only edge sensitive GPIO pin interrupts
673 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 674 if (!level_mask && !unmasked) {
675 unmasked = 1;
ee144182 676 chained_irq_exit(chip, desc);
ea6dedd7 677 }
92105bb7 678
ea6dedd7
ID		 679 isr |= retrigger;
680 retrigger = 0;
92105bb7
TL		 681 if (!isr)
682 break;
683
684 gpio_irq = bank->virtual_irq_start;
685 for (; isr != 0; isr >>= 1, gpio_irq++) {
129fd223 686 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
4318f36b 687
92105bb7
TL		 688 if (!(isr & 1))
689 continue;
29454dde 690
4318f36b
CM		 691#ifdef CONFIG_ARCH_OMAP1
692 /*
693 * Some chips can't respond to both rising and falling
694 * at the same time. If this irq was requested with
695 * both flags, we need to flip the ICR data for the IRQ
696 * to respond to the IRQ for the opposite direction.
697 * This will be indicated in the bank toggle_mask.
698 */
699 if (bank->toggle_mask & (1 << gpio_index))
700 _toggle_gpio_edge_triggering(bank, gpio_index);
701#endif
702
d8aa0251 703 generic_handle_irq(gpio_irq);
92105bb7 704 }
1a8bfa1e 705 }
ea6dedd7
ID		 706 /* if bank has any level sensitive GPIO pin interrupt
707 configured, we must unmask the bank interrupt only after
708 handler(s) are executed in order to avoid spurious bank
709 interrupt */
b1cc4c55 710exit:
ea6dedd7 711 if (!unmasked)
ee144182 712 chained_irq_exit(chip, desc);
5e1c5ff4
TL		 713}
714
e9191028 715static void gpio_irq_shutdown(struct irq_data *d)
4196dd6b 716{
e9191028
LB		 717 unsigned int gpio = d->irq - IH_GPIO_BASE;
718 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 719 unsigned long flags;
4196dd6b 720
85ec7b97 721 spin_lock_irqsave(&bank->lock, flags);
4196dd6b 722 _reset_gpio(bank, gpio);
85ec7b97 723 spin_unlock_irqrestore(&bank->lock, flags);
4196dd6b
TL		 724}
725
e9191028 726static void gpio_ack_irq(struct irq_data *d)
5e1c5ff4 727{
e9191028
LB		 728 unsigned int gpio = d->irq - IH_GPIO_BASE;
729 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 730
731 _clear_gpio_irqstatus(bank, gpio);
732}
733
e9191028 734static void gpio_mask_irq(struct irq_data *d)
5e1c5ff4 735{
e9191028
LB		 736 unsigned int gpio = d->irq - IH_GPIO_BASE;
737 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 738 unsigned long flags;
5e1c5ff4 739
85ec7b97 740 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 741 _set_gpio_irqenable(bank, gpio, 0);
129fd223 742 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
85ec7b97 743 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 744}
745
e9191028 746static void gpio_unmask_irq(struct irq_data *d)
5e1c5ff4 747{
e9191028
LB		 748 unsigned int gpio = d->irq - IH_GPIO_BASE;
749 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
129fd223 750 unsigned int irq_mask = GPIO_BIT(bank, gpio);
8c04a176 751 u32 trigger = irqd_get_trigger_type(d);
85ec7b97 752 unsigned long flags;
55b6019a 753
85ec7b97 754 spin_lock_irqsave(&bank->lock, flags);
55b6019a 755 if (trigger)
129fd223 756 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
b144ff6f
KH		 757
758 /* For level-triggered GPIOs, the clearing must be done after
759 * the HW source is cleared, thus after the handler has run */
760 if (bank->level_mask & irq_mask) {
761 _set_gpio_irqenable(bank, gpio, 0);
762 _clear_gpio_irqstatus(bank, gpio);
763 }
5e1c5ff4 764
4de8c75b 765 _set_gpio_irqenable(bank, gpio, 1);
85ec7b97 766 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 767}
768
e5c56ed3
DB		 769static struct irq_chip gpio_irq_chip = {
770 .name = "GPIO",
e9191028
LB		 771 .irq_shutdown = gpio_irq_shutdown,
772 .irq_ack = gpio_ack_irq,
773 .irq_mask = gpio_mask_irq,
774 .irq_unmask = gpio_unmask_irq,
775 .irq_set_type = gpio_irq_type,
776 .irq_set_wake = gpio_wake_enable,
e5c56ed3
DB		 777};
778
779/*---------------------------------------------------------------------*/
780
781#ifdef CONFIG_ARCH_OMAP1
782
e5c56ed3
DB		 783#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
784
11a78b79
DB		 785#ifdef CONFIG_ARCH_OMAP16XX
786
787#include <linux/platform_device.h>
788
79ee031f 789static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 790{
79ee031f 791 struct platform_device *pdev = to_platform_device(dev);
11a78b79 792 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 793 void __iomem *mask_reg = bank->base +
794 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 795 unsigned long flags;
11a78b79 796
a6472533 797 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 798 bank->saved_wakeup = __raw_readl(mask_reg);
799 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 800 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 801
802 return 0;
803}
804
79ee031f 805static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 806{
79ee031f 807 struct platform_device *pdev = to_platform_device(dev);
11a78b79 808 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 809 void __iomem *mask_reg = bank->base +
810 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 811 unsigned long flags;
11a78b79 812
a6472533 813 spin_lock_irqsave(&bank->lock, flags);
11a78b79 814 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 815 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 816
817 return 0;
818}
819
47145210 820static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 821 .suspend_noirq = omap_mpuio_suspend_noirq,
822 .resume_noirq = omap_mpuio_resume_noirq,
823};
824
3c437ffd 825/* use platform_driver for this. */
11a78b79 826static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 827 .driver = {
828 .name = "mpuio",
79ee031f 829 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 830 },
831};
832
833static struct platform_device omap_mpuio_device = {
834 .name = "mpuio",
835 .id = -1,
836 .dev = {
837 .driver = &omap_mpuio_driver.driver,
838 }
839 /* could list the /proc/iomem resources */
840};
841
03e128ca 842static inline void mpuio_init(struct gpio_bank *bank)
11a78b79 843{
77640aab 844 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 845
11a78b79
DB		 846 if (platform_driver_register(&omap_mpuio_driver) == 0)
847 (void) platform_device_register(&omap_mpuio_device);
848}
849
850#else
03e128ca 851static inline void mpuio_init(struct gpio_bank *bank) {}
11a78b79
DB		 852#endif /* 16xx */
853
e5c56ed3
DB		 854#else
855
e5c56ed3 856#define bank_is_mpuio(bank) 0
03e128ca 857static inline void mpuio_init(struct gpio_bank *bank) {}
e5c56ed3
DB		 858
859#endif
860
861/*---------------------------------------------------------------------*/
5e1c5ff4 862
52e31344
DB		 863/* REVISIT these are stupid implementations! replace by ones that
864 * don't switch on METHOD_* and which mostly avoid spinlocks
865 */
866
867static int gpio_input(struct gpio_chip *chip, unsigned offset)
868{
869 struct gpio_bank *bank;
870 unsigned long flags;
871
872 bank = container_of(chip, struct gpio_bank, chip);
873 spin_lock_irqsave(&bank->lock, flags);
874 _set_gpio_direction(bank, offset, 1);
875 spin_unlock_irqrestore(&bank->lock, flags);
876 return 0;
877}
878
b37c45b8
RQ		 879static int gpio_is_input(struct gpio_bank *bank, int mask)
880{
fa87931a 881 void __iomem *reg = bank->base + bank->regs->direction;
b37c45b8 882
b37c45b8
RQ		 883 return __raw_readl(reg) & mask;
884}
885
52e31344
DB		 886static int gpio_get(struct gpio_chip *chip, unsigned offset)
887{
b37c45b8
RQ		 888 struct gpio_bank *bank;
889 void __iomem *reg;
890 int gpio;
891 u32 mask;
892
893 gpio = chip->base + offset;
a8be8daf 894 bank = container_of(chip, struct gpio_bank, chip);
b37c45b8 895 reg = bank->base;
129fd223 896 mask = GPIO_BIT(bank, gpio);
b37c45b8
RQ		 897
898 if (gpio_is_input(bank, mask))
899 return _get_gpio_datain(bank, gpio);
900 else
901 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 902}
903
904static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
905{
906 struct gpio_bank *bank;
907 unsigned long flags;
908
909 bank = container_of(chip, struct gpio_bank, chip);
910 spin_lock_irqsave(&bank->lock, flags);
fa87931a 911 bank->set_dataout(bank, offset, value);
52e31344
DB		 912 _set_gpio_direction(bank, offset, 0);
913 spin_unlock_irqrestore(&bank->lock, flags);
914 return 0;
915}
916
168ef3d9
FB		 917static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
918 unsigned debounce)
919{
920 struct gpio_bank *bank;
921 unsigned long flags;
922
923 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 924
925 if (!bank->dbck) {
926 bank->dbck = clk_get(bank->dev, "dbclk");
927 if (IS_ERR(bank->dbck))
928 dev_err(bank->dev, "Could not get gpio dbck\n");
929 }
930
168ef3d9
FB		 931 spin_lock_irqsave(&bank->lock, flags);
932 _set_gpio_debounce(bank, offset, debounce);
933 spin_unlock_irqrestore(&bank->lock, flags);
934
935 return 0;
936}
937
52e31344
DB		 938static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
939{
940 struct gpio_bank *bank;
941 unsigned long flags;
942
943 bank = container_of(chip, struct gpio_bank, chip);
944 spin_lock_irqsave(&bank->lock, flags);
fa87931a 945 bank->set_dataout(bank, offset, value);
52e31344
DB		 946 spin_unlock_irqrestore(&bank->lock, flags);
947}
948
a007b709
DB		 949static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
950{
951 struct gpio_bank *bank;
952
953 bank = container_of(chip, struct gpio_bank, chip);
954 return bank->virtual_irq_start + offset;
955}
956
52e31344
DB		 957/*---------------------------------------------------------------------*/
958
9a748053 959static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da 960{
e5ff4440 961 static bool called;
9f7065da
TL		 962 u32 rev;
963
e5ff4440 964 if (called || bank->regs->revision == USHRT_MAX)
9f7065da
TL		 965 return;
966
e5ff4440
KH		 967 rev = __raw_readw(bank->base + bank->regs->revision);
968 pr_info("OMAP GPIO hardware version %d.%d\n",
9f7065da 969 (rev >> 4) & 0x0f, rev & 0x0f);
e5ff4440
KH		 970
971 called = true;
9f7065da
TL		 972}
973
8ba55c5c
DB		 974/* This lock class tells lockdep that GPIO irqs are in a different
975 * category than their parents, so it won't report false recursion.
976 */
977static struct lock_class_key gpio_lock_class;
978
77640aab 979/* TODO: Cleanup cpu_is_* checks */
03e128ca 980static void omap_gpio_mod_init(struct gpio_bank *bank)
2fae7fbe
VC		 981{
982 if (cpu_class_is_omap2()) {
983 if (cpu_is_omap44xx()) {
984 __raw_writel(0xffffffff, bank->base +
985 OMAP4_GPIO_IRQSTATUSCLR0);
986 __raw_writel(0x00000000, bank->base +
987 OMAP4_GPIO_DEBOUNCENABLE);
988 /* Initialize interface clk ungated, module enabled */
989 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
990 } else if (cpu_is_omap34xx()) {
991 __raw_writel(0x00000000, bank->base +
992 OMAP24XX_GPIO_IRQENABLE1);
993 __raw_writel(0xffffffff, bank->base +
994 OMAP24XX_GPIO_IRQSTATUS1);
995 __raw_writel(0x00000000, bank->base +
996 OMAP24XX_GPIO_DEBOUNCE_EN);
997
998 /* Initialize interface clk ungated, module enabled */
999 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
2fae7fbe
VC		 1000 }
1001 } else if (cpu_class_is_omap1()) {
03e128ca 1002 if (bank_is_mpuio(bank)) {
5de62b86
TL		 1003 __raw_writew(0xffff, bank->base +
1004 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
03e128ca
C		 1005 mpuio_init(bank);
1006 }
2fae7fbe
VC		 1007 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1008 __raw_writew(0xffff, bank->base
1009 + OMAP1510_GPIO_INT_MASK);
1010 __raw_writew(0x0000, bank->base
1011 + OMAP1510_GPIO_INT_STATUS);
1012 }
1013 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1014 __raw_writew(0x0000, bank->base
1015 + OMAP1610_GPIO_IRQENABLE1);
1016 __raw_writew(0xffff, bank->base
1017 + OMAP1610_GPIO_IRQSTATUS1);
1018 __raw_writew(0x0014, bank->base
1019 + OMAP1610_GPIO_SYSCONFIG);
1020
1021 /*
1022 * Enable system clock for GPIO module.
1023 * The CAM_CLK_CTRL *is* really the right place.
1024 */
1025 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1026 ULPD_CAM_CLK_CTRL);
1027 }
1028 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1029 __raw_writel(0xffffffff, bank->base
1030 + OMAP7XX_GPIO_INT_MASK);
1031 __raw_writel(0x00000000, bank->base
1032 + OMAP7XX_GPIO_INT_STATUS);
1033 }
1034 }
1035}
1036
f8b46b58
KH		 1037static __init void
1038omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1039 unsigned int num)
1040{
1041 struct irq_chip_generic *gc;
1042 struct irq_chip_type *ct;
1043
1044 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1045 handle_simple_irq);
83233749
TP		 1046 if (!gc) {
1047 dev_err(bank->dev, "Memory alloc failed for gc\n");
1048 return;
1049 }
1050
f8b46b58
KH		 1051 ct = gc->chip_types;
1052
1053 /* NOTE: No ack required, reading IRQ status clears it. */
1054 ct->chip.irq_mask = irq_gc_mask_set_bit;
1055 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1056 ct->chip.irq_set_type = gpio_irq_type;
6ed87c5b
TKD		 1057
1058 if (bank->regs->wkup_en)
f8b46b58
KH		 1059 ct->chip.irq_set_wake = gpio_wake_enable,
1060
1061 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1062 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1063 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1064}
1065
d52b31de 1066static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
2fae7fbe 1067{
77640aab 1068 int j;
2fae7fbe
VC		 1069 static int gpio;
1070
2fae7fbe
VC		 1071 bank->mod_usage = 0;
1072 /*
1073 * REVISIT eventually switch from OMAP-specific gpio structs
1074 * over to the generic ones
1075 */
1076 bank->chip.request = omap_gpio_request;
1077 bank->chip.free = omap_gpio_free;
1078 bank->chip.direction_input = gpio_input;
1079 bank->chip.get = gpio_get;
1080 bank->chip.direction_output = gpio_output;
1081 bank->chip.set_debounce = gpio_debounce;
1082 bank->chip.set = gpio_set;
1083 bank->chip.to_irq = gpio_2irq;
1084 if (bank_is_mpuio(bank)) {
1085 bank->chip.label = "mpuio";
1086#ifdef CONFIG_ARCH_OMAP16XX
6ed87c5b
TKD		 1087 if (bank->regs->wkup_en)
1088 bank->chip.dev = &omap_mpuio_device.dev;
2fae7fbe
VC		 1089#endif
1090 bank->chip.base = OMAP_MPUIO(0);
1091 } else {
1092 bank->chip.label = "gpio";
1093 bank->chip.base = gpio;
d5f46247 1094 gpio += bank->width;
2fae7fbe 1095 }
d5f46247 1096 bank->chip.ngpio = bank->width;
2fae7fbe
VC		 1097
1098 gpiochip_add(&bank->chip);
1099
1100 for (j = bank->virtual_irq_start;
d5f46247 1101 j < bank->virtual_irq_start + bank->width; j++) {
1475b85d 1102 irq_set_lockdep_class(j, &gpio_lock_class);
6845664a 1103 irq_set_chip_data(j, bank);
f8b46b58
KH		 1104 if (bank_is_mpuio(bank)) {
1105 omap_mpuio_alloc_gc(bank, j, bank->width);
1106 } else {
6845664a 1107 irq_set_chip(j, &gpio_irq_chip);
f8b46b58
KH		 1108 irq_set_handler(j, handle_simple_irq);
1109 set_irq_flags(j, IRQF_VALID);
1110 }
2fae7fbe 1111 }
6845664a
TG		 1112 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1113 irq_set_handler_data(bank->irq, bank);
2fae7fbe
VC		 1114}
1115
77640aab 1116static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1117{
77640aab
VC		 1118 struct omap_gpio_platform_data *pdata;
1119 struct resource *res;
5e1c5ff4 1120 struct gpio_bank *bank;
03e128ca 1121 int ret = 0;
5e1c5ff4 1122
03e128ca
C		 1123 if (!pdev->dev.platform_data) {
1124 ret = -EINVAL;
1125 goto err_exit;
5492fb1a 1126 }
5492fb1a 1127
03e128ca
C		 1128 bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL);
1129 if (!bank) {
1130 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1131 ret = -ENOMEM;
1132 goto err_exit;
1133 }
92105bb7 1134
77640aab
VC		 1135 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1136 if (unlikely(!res)) {
03e128ca
C		 1137 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n",
1138 pdev->id);
1139 ret = -ENODEV;
1140 goto err_free;
44169075 1141 }
5e1c5ff4 1142
77640aab 1143 bank->irq = res->start;
03e128ca
C		 1144 bank->id = pdev->id;
1145
1146 pdata = pdev->dev.platform_data;
77640aab
VC		 1147 bank->virtual_irq_start = pdata->virtual_irq_start;
1148 bank->method = pdata->bank_type;
1149 bank->dev = &pdev->dev;
1150 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1151 bank->stride = pdata->bank_stride;
d5f46247 1152 bank->width = pdata->bank_width;
803a2434 1153 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
0cde8d03 1154 bank->loses_context = pdata->loses_context;
60a3437d 1155 bank->get_context_loss_count = pdata->get_context_loss_count;
fa87931a
KH		 1156 bank->regs = pdata->regs;
1157
1158 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1159 bank->set_dataout = _set_gpio_dataout_reg;
1160 else
1161 bank->set_dataout = _set_gpio_dataout_mask;
9f7065da 1162
77640aab 1163 spin_lock_init(&bank->lock);
9f7065da 1164
77640aab
VC		 1165 /* Static mapping, never released */
1166 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1167 if (unlikely(!res)) {
03e128ca
C		 1168 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n",
1169 pdev->id);
1170 ret = -ENODEV;
1171 goto err_free;
77640aab 1172 }
89db9482 1173
77640aab
VC		 1174 bank->base = ioremap(res->start, resource_size(res));
1175 if (!bank->base) {
03e128ca
C		 1176 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n",
1177 pdev->id);
1178 ret = -ENOMEM;
1179 goto err_free;
5e1c5ff4
TL		 1180 }
1181
77640aab
VC		 1182 pm_runtime_enable(bank->dev);
1183 pm_runtime_get_sync(bank->dev);
1184
03e128ca 1185 omap_gpio_mod_init(bank);
77640aab 1186 omap_gpio_chip_init(bank);
9a748053 1187 omap_gpio_show_rev(bank);
9f7065da 1188
03e128ca 1189 list_add_tail(&bank->node, &omap_gpio_list);
77640aab 1190
03e128ca
C		 1191 return ret;
1192
1193err_free:
1194 kfree(bank);
1195err_exit:
1196 return ret;
5e1c5ff4
TL		 1197}
1198
3c437ffd 1199static int omap_gpio_suspend(void)
92105bb7 1200{
03e128ca 1201 struct gpio_bank *bank;
92105bb7 1202
03e128ca 1203 list_for_each_entry(bank, &omap_gpio_list, node) {
6ed87c5b 1204 void __iomem *base = bank->base;
92105bb7 1205 void __iomem *wake_status;
a6472533 1206 unsigned long flags;
92105bb7 1207
6ed87c5b
TKD		 1208 if (!bank->regs->wkup_en)
1209 return 0;
1210
1211 wake_status = bank->base + bank->regs->wkup_en;
92105bb7 1212
a6472533 1213 spin_lock_irqsave(&bank->lock, flags);
92105bb7 1214 bank->saved_wakeup = __raw_readl(wake_status);
6ed87c5b
TKD		 1215 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1216 _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
a6472533 1217 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1218 }
1219
1220 return 0;
1221}
1222
3c437ffd 1223static void omap_gpio_resume(void)
92105bb7 1224{
03e128ca 1225 struct gpio_bank *bank;
92105bb7 1226
03e128ca 1227 list_for_each_entry(bank, &omap_gpio_list, node) {
6ed87c5b 1228 void __iomem *base = bank->base;
a6472533 1229 unsigned long flags;
92105bb7 1230
6ed87c5b
TKD		 1231 if (!bank->regs->wkup_en)
1232 return;
92105bb7 1233
a6472533 1234 spin_lock_irqsave(&bank->lock, flags);
6ed87c5b
TKD		 1235 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1236 _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
a6472533 1237 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1238 }
92105bb7
TL		 1239}
1240
3c437ffd 1241static struct syscore_ops omap_gpio_syscore_ops = {
92105bb7
TL		 1242 .suspend = omap_gpio_suspend,
1243 .resume = omap_gpio_resume,
1244};
1245
140455fa 1246#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 1247
60a3437d
TKD		 1248static void omap_gpio_save_context(struct gpio_bank *bank);
1249static void omap_gpio_restore_context(struct gpio_bank *bank);
3ac4fa99 1250
72e06d08 1251void omap2_gpio_prepare_for_idle(int off_mode)
3ac4fa99 1252{
03e128ca 1253 struct gpio_bank *bank;
43ffcd9a 1254
03e128ca 1255 list_for_each_entry(bank, &omap_gpio_list, node) {
ca828760 1256 u32 l1 = 0, l2 = 0;
0aed0435 1257 int j;
3ac4fa99 1258
0cde8d03 1259 if (!bank->loses_context)
03e128ca
C		 1260 continue;
1261
0aed0435 1262 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1263 clk_disable(bank->dbck);
1264
72e06d08 1265 if (!off_mode)
43ffcd9a
KH		 1266 continue;
1267
1268 /* If going to OFF, remove triggering for all
1269 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1270 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99 1271 if (!(bank->enabled_non_wakeup_gpios))
60a3437d 1272 goto save_gpio_context;
3f1686a9
TL		 1273
1274 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1275 bank->saved_datain = __raw_readl(bank->base +
1276 OMAP24XX_GPIO_DATAIN);
1277 l1 = __raw_readl(bank->base +
1278 OMAP24XX_GPIO_FALLINGDETECT);
1279 l2 = __raw_readl(bank->base +
1280 OMAP24XX_GPIO_RISINGDETECT);
1281 }
1282
1283 if (cpu_is_omap44xx()) {
1284 bank->saved_datain = __raw_readl(bank->base +
1285 OMAP4_GPIO_DATAIN);
1286 l1 = __raw_readl(bank->base +
1287 OMAP4_GPIO_FALLINGDETECT);
1288 l2 = __raw_readl(bank->base +
1289 OMAP4_GPIO_RISINGDETECT);
1290 }
1291
3ac4fa99
JY		 1292 bank->saved_fallingdetect = l1;
1293 bank->saved_risingdetect = l2;
1294 l1 &= ~bank->enabled_non_wakeup_gpios;
1295 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 1296
1297 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1298 __raw_writel(l1, bank->base +
1299 OMAP24XX_GPIO_FALLINGDETECT);
1300 __raw_writel(l2, bank->base +
1301 OMAP24XX_GPIO_RISINGDETECT);
1302 }
1303
1304 if (cpu_is_omap44xx()) {
1305 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1306 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1307 }
1308
60a3437d
TKD		 1309save_gpio_context:
1310 if (bank->get_context_loss_count)
1311 bank->context_loss_count =
1312 bank->get_context_loss_count(bank->dev);
1313
1314 omap_gpio_save_context(bank);
3ac4fa99 1315 }
3ac4fa99
JY		 1316}
1317
43ffcd9a 1318void omap2_gpio_resume_after_idle(void)
3ac4fa99 1319{
03e128ca 1320 struct gpio_bank *bank;
3ac4fa99 1321
03e128ca 1322 list_for_each_entry(bank, &omap_gpio_list, node) {
60a3437d 1323 int context_lost_cnt_after;
ca828760 1324 u32 l = 0, gen, gen0, gen1;
0aed0435 1325 int j;
3ac4fa99 1326
0cde8d03 1327 if (!bank->loses_context)
03e128ca
C		 1328 continue;
1329
0aed0435 1330 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1331 clk_enable(bank->dbck);
1332
60a3437d
TKD		 1333 if (bank->get_context_loss_count) {
1334 context_lost_cnt_after =
1335 bank->get_context_loss_count(bank->dev);
1336 if (context_lost_cnt_after != bank->context_loss_count
1337 || !context_lost_cnt_after)
1338 omap_gpio_restore_context(bank);
1339 }
43ffcd9a 1340
3ac4fa99
JY		 1341 if (!(bank->enabled_non_wakeup_gpios))
1342 continue;
3f1686a9
TL		 1343
1344 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1345 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 1346 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 1347 __raw_writel(bank->saved_risingdetect,
3ac4fa99 1348 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 1349 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1350 }
1351
1352 if (cpu_is_omap44xx()) {
1353 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 1354 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 1355 __raw_writel(bank->saved_risingdetect,
78a1a6d3 1356 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 1357 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1358 }
1359
3ac4fa99
JY		 1360 /* Check if any of the non-wakeup interrupt GPIOs have changed
1361 * state. If so, generate an IRQ by software. This is
1362 * horribly racy, but it's the best we can do to work around
1363 * this silicon bug. */
3ac4fa99 1364 l ^= bank->saved_datain;
a118b5f3 1365 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 1366
1367 /*
1368 * No need to generate IRQs for the rising edge for gpio IRQs
1369 * configured with falling edge only; and vice versa.
1370 */
1371 gen0 = l & bank->saved_fallingdetect;
1372 gen0 &= bank->saved_datain;
1373
1374 gen1 = l & bank->saved_risingdetect;
1375 gen1 &= ~(bank->saved_datain);
1376
1377 /* FIXME: Consider GPIO IRQs with level detections properly! */
1378 gen = l & (~(bank->saved_fallingdetect) &
1379 ~(bank->saved_risingdetect));
1380 /* Consider all GPIO IRQs needed to be updated */
1381 gen |= gen0 | gen1;
1382
1383 if (gen) {
3ac4fa99 1384 u32 old0, old1;
3f1686a9 1385
f00d6497 1386 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 1387 old0 = __raw_readl(bank->base +
1388 OMAP24XX_GPIO_LEVELDETECT0);
1389 old1 = __raw_readl(bank->base +
1390 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1391 __raw_writel(old0 | gen, bank->base +
82dbb9d3 1392 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1393 __raw_writel(old1 | gen, bank->base +
82dbb9d3 1394 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1395 __raw_writel(old0, bank->base +
3f1686a9 1396 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1397 __raw_writel(old1, bank->base +
3f1686a9
TL		 1398 OMAP24XX_GPIO_LEVELDETECT1);
1399 }
1400
1401 if (cpu_is_omap44xx()) {
1402 old0 = __raw_readl(bank->base +
78a1a6d3 1403 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1404 old1 = __raw_readl(bank->base +
78a1a6d3 1405 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1406 __raw_writel(old0 | l, bank->base +
78a1a6d3 1407 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1408 __raw_writel(old1 | l, bank->base +
78a1a6d3 1409 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1410 __raw_writel(old0, bank->base +
78a1a6d3 1411 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1412 __raw_writel(old1, bank->base +
78a1a6d3 1413 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1414 }
3ac4fa99
JY		 1415 }
1416 }
3ac4fa99
JY		 1417}
1418
60a3437d 1419static void omap_gpio_save_context(struct gpio_bank *bank)
40c670f0 1420{
60a3437d
TKD		 1421 bank->context.irqenable1 =
1422 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1423 bank->context.irqenable2 =
1424 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1425 bank->context.wake_en =
1426 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1427 bank->context.ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1428 bank->context.oe = __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1429 bank->context.leveldetect0 =
1430 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1431 bank->context.leveldetect1 =
1432 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1433 bank->context.risingdetect =
1434 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1435 bank->context.fallingdetect =
1436 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1437 bank->context.dataout =
1438 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1439}
1440
60a3437d 1441static void omap_gpio_restore_context(struct gpio_bank *bank)
40c670f0 1442{
60a3437d
TKD		 1443 __raw_writel(bank->context.irqenable1,
1444 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1445 __raw_writel(bank->context.irqenable2,
1446 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1447 __raw_writel(bank->context.wake_en,
1448 bank->base + OMAP24XX_GPIO_WAKE_EN);
1449 __raw_writel(bank->context.ctrl, bank->base + OMAP24XX_GPIO_CTRL);
1450 __raw_writel(bank->context.oe, bank->base + OMAP24XX_GPIO_OE);
1451 __raw_writel(bank->context.leveldetect0,
1452 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1453 __raw_writel(bank->context.leveldetect1,
1454 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1455 __raw_writel(bank->context.risingdetect,
1456 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1457 __raw_writel(bank->context.fallingdetect,
1458 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1459 __raw_writel(bank->context.dataout,
1460 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1461}
1462#endif
1463
77640aab
VC		 1464static struct platform_driver omap_gpio_driver = {
1465 .probe = omap_gpio_probe,
1466 .driver = {
1467 .name = "omap_gpio",
1468 },
1469};
1470
5e1c5ff4 1471/*
77640aab
VC		 1472 * gpio driver register needs to be done before
1473 * machine_init functions access gpio APIs.
1474 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 1475 */
77640aab 1476static int __init omap_gpio_drv_reg(void)
5e1c5ff4 1477{
77640aab 1478 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 1479}
77640aab 1480postcore_initcall(omap_gpio_drv_reg);
5e1c5ff4 1481
92105bb7
TL		 1482static int __init omap_gpio_sysinit(void)
1483{
11a78b79 1484
140455fa 1485#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd
RW		 1486 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1487 register_syscore_ops(&omap_gpio_syscore_ops);
92105bb7
TL		 1488#endif
1489
3c437ffd 1490 return 0;
92105bb7
TL		 1491}
1492
92105bb7 1493arch_initcall(omap_gpio_sysinit);
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