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Commit | Line | Data |
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5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
77640aab VC |
22 | #include <linux/slab.h> |
23 | #include <linux/pm_runtime.h> | |
55b93c32 | 24 | #include <linux/pm.h> |
5e1c5ff4 | 25 | |
a09e64fb | 26 | #include <mach/hardware.h> |
5e1c5ff4 | 27 | #include <asm/irq.h> |
a09e64fb | 28 | #include <mach/irqs.h> |
1bc857f7 | 29 | #include <asm/gpio.h> |
5e1c5ff4 TL |
30 | #include <asm/mach/irq.h> |
31 | ||
2dc983c5 TKD |
32 | #define OFF_MODE 1 |
33 | ||
03e128ca C |
34 | static LIST_HEAD(omap_gpio_list); |
35 | ||
6d62e216 C |
36 | struct gpio_regs { |
37 | u32 irqenable1; | |
38 | u32 irqenable2; | |
39 | u32 wake_en; | |
40 | u32 ctrl; | |
41 | u32 oe; | |
42 | u32 leveldetect0; | |
43 | u32 leveldetect1; | |
44 | u32 risingdetect; | |
45 | u32 fallingdetect; | |
46 | u32 dataout; | |
47 | }; | |
48 | ||
5e1c5ff4 | 49 | struct gpio_bank { |
03e128ca | 50 | struct list_head node; |
9f7065da | 51 | unsigned long pbase; |
92105bb7 | 52 | void __iomem *base; |
5e1c5ff4 TL |
53 | u16 irq; |
54 | u16 virtual_irq_start; | |
92105bb7 TL |
55 | u32 suspend_wakeup; |
56 | u32 saved_wakeup; | |
3ac4fa99 JY |
57 | u32 non_wakeup_gpios; |
58 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 59 | struct gpio_regs context; |
3ac4fa99 JY |
60 | u32 saved_datain; |
61 | u32 saved_fallingdetect; | |
62 | u32 saved_risingdetect; | |
b144ff6f | 63 | u32 level_mask; |
4318f36b | 64 | u32 toggle_mask; |
5e1c5ff4 | 65 | spinlock_t lock; |
52e31344 | 66 | struct gpio_chip chip; |
89db9482 | 67 | struct clk *dbck; |
058af1ea | 68 | u32 mod_usage; |
8865b9b6 | 69 | u32 dbck_enable_mask; |
72f83af9 | 70 | bool dbck_enabled; |
77640aab | 71 | struct device *dev; |
d0d665a8 | 72 | bool is_mpuio; |
77640aab | 73 | bool dbck_flag; |
0cde8d03 | 74 | bool loses_context; |
5de62b86 | 75 | int stride; |
d5f46247 | 76 | u32 width; |
60a3437d | 77 | int context_loss_count; |
03e128ca | 78 | u16 id; |
2dc983c5 TKD |
79 | int power_mode; |
80 | bool workaround_enabled; | |
fa87931a KH |
81 | |
82 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60a3437d | 83 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
84 | |
85 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
86 | }; |
87 | ||
129fd223 KH |
88 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
89 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
c8eef65a | 90 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 TL |
91 | |
92 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
93 | { | |
92105bb7 | 94 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
95 | u32 l; |
96 | ||
fa87931a | 97 | reg += bank->regs->direction; |
5e1c5ff4 TL |
98 | l = __raw_readl(reg); |
99 | if (is_input) | |
100 | l |= 1 << gpio; | |
101 | else | |
102 | l &= ~(1 << gpio); | |
103 | __raw_writel(l, reg); | |
104 | } | |
105 | ||
fa87931a KH |
106 | |
107 | /* set data out value using dedicate set/clear register */ | |
108 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 109 | { |
92105bb7 | 110 | void __iomem *reg = bank->base; |
fa87931a | 111 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 112 | |
fa87931a KH |
113 | if (enable) |
114 | reg += bank->regs->set_dataout; | |
115 | else | |
116 | reg += bank->regs->clr_dataout; | |
5e1c5ff4 | 117 | |
5e1c5ff4 TL |
118 | __raw_writel(l, reg); |
119 | } | |
120 | ||
fa87931a KH |
121 | /* set data out value using mask register */ |
122 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 123 | { |
fa87931a KH |
124 | void __iomem *reg = bank->base + bank->regs->dataout; |
125 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
126 | u32 l; | |
5e1c5ff4 | 127 | |
fa87931a KH |
128 | l = __raw_readl(reg); |
129 | if (enable) | |
130 | l |= gpio_bit; | |
131 | else | |
132 | l &= ~gpio_bit; | |
5e1c5ff4 | 133 | __raw_writel(l, reg); |
5e1c5ff4 TL |
134 | } |
135 | ||
b37c45b8 | 136 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
b37c45b8 | 137 | { |
fa87931a | 138 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 139 | |
fa87931a | 140 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
5e1c5ff4 | 141 | } |
b37c45b8 | 142 | |
b37c45b8 RQ |
143 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
144 | { | |
fa87931a | 145 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 146 | |
129fd223 | 147 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
b37c45b8 RQ |
148 | } |
149 | ||
ece9528e KH |
150 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
151 | { | |
152 | int l = __raw_readl(base + reg); | |
153 | ||
154 | if (set) | |
155 | l |= mask; | |
156 | else | |
157 | l &= ~mask; | |
158 | ||
159 | __raw_writel(l, base + reg); | |
160 | } | |
92105bb7 | 161 | |
72f83af9 TKD |
162 | static inline void _gpio_dbck_enable(struct gpio_bank *bank) |
163 | { | |
164 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
165 | clk_enable(bank->dbck); | |
166 | bank->dbck_enabled = true; | |
167 | } | |
168 | } | |
169 | ||
170 | static inline void _gpio_dbck_disable(struct gpio_bank *bank) | |
171 | { | |
172 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
173 | clk_disable(bank->dbck); | |
174 | bank->dbck_enabled = false; | |
175 | } | |
176 | } | |
177 | ||
168ef3d9 FB |
178 | /** |
179 | * _set_gpio_debounce - low level gpio debounce time | |
180 | * @bank: the gpio bank we're acting upon | |
181 | * @gpio: the gpio number on this @gpio | |
182 | * @debounce: debounce time to use | |
183 | * | |
184 | * OMAP's debounce time is in 31us steps so we need | |
185 | * to convert and round up to the closest unit. | |
186 | */ | |
187 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
188 | unsigned debounce) | |
189 | { | |
9942da0e | 190 | void __iomem *reg; |
168ef3d9 FB |
191 | u32 val; |
192 | u32 l; | |
193 | ||
77640aab VC |
194 | if (!bank->dbck_flag) |
195 | return; | |
196 | ||
168ef3d9 FB |
197 | if (debounce < 32) |
198 | debounce = 0x01; | |
199 | else if (debounce > 7936) | |
200 | debounce = 0xff; | |
201 | else | |
202 | debounce = (debounce / 0x1f) - 1; | |
203 | ||
129fd223 | 204 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 205 | |
6fd9c421 | 206 | clk_enable(bank->dbck); |
9942da0e | 207 | reg = bank->base + bank->regs->debounce; |
168ef3d9 FB |
208 | __raw_writel(debounce, reg); |
209 | ||
9942da0e | 210 | reg = bank->base + bank->regs->debounce_en; |
168ef3d9 FB |
211 | val = __raw_readl(reg); |
212 | ||
6fd9c421 | 213 | if (debounce) |
168ef3d9 | 214 | val |= l; |
6fd9c421 | 215 | else |
168ef3d9 | 216 | val &= ~l; |
f7ec0b0b | 217 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
218 | |
219 | __raw_writel(val, reg); | |
6fd9c421 TKD |
220 | clk_disable(bank->dbck); |
221 | /* | |
222 | * Enable debounce clock per module. | |
223 | * This call is mandatory because in omap_gpio_request() when | |
224 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
225 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
226 | * used within _gpio_dbck_enable() is still not initialized at | |
227 | * that point. Therefore we have to enable dbck here. | |
228 | */ | |
229 | _gpio_dbck_enable(bank); | |
168ef3d9 FB |
230 | } |
231 | ||
5e571f38 | 232 | static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, |
5eb3bb9c | 233 | int trigger) |
5e1c5ff4 | 234 | { |
3ac4fa99 | 235 | void __iomem *base = bank->base; |
92105bb7 TL |
236 | u32 gpio_bit = 1 << gpio; |
237 | ||
5e571f38 TKD |
238 | _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
239 | trigger & IRQ_TYPE_LEVEL_LOW); | |
240 | _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
241 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
242 | _gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
243 | trigger & IRQ_TYPE_EDGE_RISING); | |
244 | _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
245 | trigger & IRQ_TYPE_EDGE_FALLING); | |
246 | ||
247 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) | |
248 | _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); | |
249 | ||
55b220ca | 250 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
251 | if (!bank->regs->irqctrl) { |
252 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
253 | if (bank->non_wakeup_gpios) { | |
254 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
255 | goto exit; | |
256 | } | |
257 | ||
699117a6 CW |
258 | /* |
259 | * Log the edge gpio and manually trigger the IRQ | |
260 | * after resume if the input level changes | |
261 | * to avoid irq lost during PER RET/OFF mode | |
262 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
263 | */ | |
264 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
265 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
266 | else | |
267 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
268 | } | |
5eb3bb9c | 269 | |
5e571f38 | 270 | exit: |
9ea14d8c TKD |
271 | bank->level_mask = |
272 | __raw_readl(bank->base + bank->regs->leveldetect0) | | |
273 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
274 | } |
275 | ||
9198bcd3 | 276 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
277 | /* |
278 | * This only applies to chips that can't do both rising and falling edge | |
279 | * detection at once. For all other chips, this function is a noop. | |
280 | */ | |
281 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
282 | { | |
283 | void __iomem *reg = bank->base; | |
284 | u32 l = 0; | |
285 | ||
5e571f38 | 286 | if (!bank->regs->irqctrl) |
4318f36b | 287 | return; |
5e571f38 TKD |
288 | |
289 | reg += bank->regs->irqctrl; | |
4318f36b CM |
290 | |
291 | l = __raw_readl(reg); | |
292 | if ((l >> gpio) & 1) | |
293 | l &= ~(1 << gpio); | |
294 | else | |
295 | l |= 1 << gpio; | |
296 | ||
297 | __raw_writel(l, reg); | |
298 | } | |
5e571f38 TKD |
299 | #else |
300 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} | |
9198bcd3 | 301 | #endif |
4318f36b | 302 | |
92105bb7 TL |
303 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
304 | { | |
305 | void __iomem *reg = bank->base; | |
5e571f38 | 306 | void __iomem *base = bank->base; |
92105bb7 | 307 | u32 l = 0; |
5e1c5ff4 | 308 | |
5e571f38 TKD |
309 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
310 | set_gpio_trigger(bank, gpio, trigger); | |
311 | } else if (bank->regs->irqctrl) { | |
312 | reg += bank->regs->irqctrl; | |
313 | ||
5e1c5ff4 | 314 | l = __raw_readl(reg); |
29501577 | 315 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 316 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 317 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 318 | l |= 1 << gpio; |
6cab4860 | 319 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 320 | l &= ~(1 << gpio); |
92105bb7 | 321 | else |
5e571f38 TKD |
322 | return -EINVAL; |
323 | ||
324 | __raw_writel(l, reg); | |
325 | } else if (bank->regs->edgectrl1) { | |
5e1c5ff4 | 326 | if (gpio & 0x08) |
5e571f38 | 327 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 328 | else |
5e571f38 TKD |
329 | reg += bank->regs->edgectrl1; |
330 | ||
5e1c5ff4 TL |
331 | gpio &= 0x07; |
332 | l = __raw_readl(reg); | |
333 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 334 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 335 | l |= 2 << (gpio << 1); |
6cab4860 | 336 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 337 | l |= 1 << (gpio << 1); |
5e571f38 TKD |
338 | |
339 | /* Enable wake-up during idle for dynamic tick */ | |
340 | _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger); | |
341 | __raw_writel(l, reg); | |
5e1c5ff4 | 342 | } |
92105bb7 | 343 | return 0; |
5e1c5ff4 TL |
344 | } |
345 | ||
e9191028 | 346 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 TL |
347 | { |
348 | struct gpio_bank *bank; | |
92105bb7 TL |
349 | unsigned gpio; |
350 | int retval; | |
a6472533 | 351 | unsigned long flags; |
92105bb7 | 352 | |
e9191028 LB |
353 | if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) |
354 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | |
92105bb7 | 355 | else |
e9191028 | 356 | gpio = d->irq - IH_GPIO_BASE; |
5e1c5ff4 | 357 | |
e5c56ed3 | 358 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 359 | return -EINVAL; |
e5c56ed3 | 360 | |
9ea14d8c TKD |
361 | bank = irq_data_get_irq_chip_data(d); |
362 | ||
363 | if (!bank->regs->leveldetect0 && | |
364 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
365 | return -EINVAL; |
366 | ||
a6472533 | 367 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 368 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
a6472533 | 369 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
370 | |
371 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 372 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 373 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 374 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 375 | |
92105bb7 | 376 | return retval; |
5e1c5ff4 TL |
377 | } |
378 | ||
379 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
380 | { | |
92105bb7 | 381 | void __iomem *reg = bank->base; |
5e1c5ff4 | 382 | |
eef4bec7 | 383 | reg += bank->regs->irqstatus; |
5e1c5ff4 | 384 | __raw_writel(gpio_mask, reg); |
bee7930f HD |
385 | |
386 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
387 | if (bank->regs->irqstatus2) { |
388 | reg = bank->base + bank->regs->irqstatus2; | |
bedfd154 | 389 | __raw_writel(gpio_mask, reg); |
eef4bec7 | 390 | } |
bedfd154 RQ |
391 | |
392 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
393 | __raw_readl(reg); | |
5e1c5ff4 TL |
394 | } |
395 | ||
396 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
397 | { | |
129fd223 | 398 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
399 | } |
400 | ||
ea6dedd7 ID |
401 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
402 | { | |
403 | void __iomem *reg = bank->base; | |
99c47707 | 404 | u32 l; |
c390aad0 | 405 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 406 | |
28f3b5a0 | 407 | reg += bank->regs->irqenable; |
99c47707 | 408 | l = __raw_readl(reg); |
28f3b5a0 | 409 | if (bank->regs->irqenable_inv) |
99c47707 ID |
410 | l = ~l; |
411 | l &= mask; | |
412 | return l; | |
ea6dedd7 ID |
413 | } |
414 | ||
28f3b5a0 | 415 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 416 | { |
92105bb7 | 417 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
418 | u32 l; |
419 | ||
28f3b5a0 KH |
420 | if (bank->regs->set_irqenable) { |
421 | reg += bank->regs->set_irqenable; | |
422 | l = gpio_mask; | |
423 | } else { | |
424 | reg += bank->regs->irqenable; | |
5e1c5ff4 | 425 | l = __raw_readl(reg); |
28f3b5a0 KH |
426 | if (bank->regs->irqenable_inv) |
427 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
428 | else |
429 | l |= gpio_mask; | |
28f3b5a0 KH |
430 | } |
431 | ||
432 | __raw_writel(l, reg); | |
433 | } | |
434 | ||
435 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
436 | { | |
437 | void __iomem *reg = bank->base; | |
438 | u32 l; | |
439 | ||
440 | if (bank->regs->clr_irqenable) { | |
441 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 442 | l = gpio_mask; |
28f3b5a0 KH |
443 | } else { |
444 | reg += bank->regs->irqenable; | |
56739a69 | 445 | l = __raw_readl(reg); |
28f3b5a0 | 446 | if (bank->regs->irqenable_inv) |
56739a69 | 447 | l |= gpio_mask; |
92105bb7 | 448 | else |
28f3b5a0 | 449 | l &= ~gpio_mask; |
5e1c5ff4 | 450 | } |
28f3b5a0 | 451 | |
5e1c5ff4 TL |
452 | __raw_writel(l, reg); |
453 | } | |
454 | ||
455 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
456 | { | |
28f3b5a0 | 457 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
458 | } |
459 | ||
92105bb7 TL |
460 | /* |
461 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
462 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
463 | * to the target, system will wake up always on GPIO events. While | |
464 | * system is running all registered GPIO interrupts need to have wake-up | |
465 | * enabled. When system is suspended, only selected GPIO interrupts need | |
466 | * to have wake-up enabled. | |
467 | */ | |
468 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
469 | { | |
f64ad1a0 KH |
470 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
471 | unsigned long flags; | |
a6472533 | 472 | |
f64ad1a0 KH |
473 | if (bank->non_wakeup_gpios & gpio_bit) { |
474 | dev_err(bank->dev, | |
475 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); | |
92105bb7 TL |
476 | return -EINVAL; |
477 | } | |
f64ad1a0 KH |
478 | |
479 | spin_lock_irqsave(&bank->lock, flags); | |
480 | if (enable) | |
481 | bank->suspend_wakeup |= gpio_bit; | |
482 | else | |
483 | bank->suspend_wakeup &= ~gpio_bit; | |
484 | ||
485 | spin_unlock_irqrestore(&bank->lock, flags); | |
486 | ||
487 | return 0; | |
92105bb7 TL |
488 | } |
489 | ||
4196dd6b TL |
490 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
491 | { | |
129fd223 | 492 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
493 | _set_gpio_irqenable(bank, gpio, 0); |
494 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 495 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
496 | } |
497 | ||
92105bb7 | 498 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 499 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 500 | { |
e9191028 | 501 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
92105bb7 TL |
502 | struct gpio_bank *bank; |
503 | int retval; | |
504 | ||
e9191028 | 505 | bank = irq_data_get_irq_chip_data(d); |
f64ad1a0 | 506 | retval = _set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
507 | |
508 | return retval; | |
509 | } | |
510 | ||
3ff164e1 | 511 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 512 | { |
3ff164e1 | 513 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 514 | unsigned long flags; |
52e31344 | 515 | |
55b93c32 TKD |
516 | /* |
517 | * If this is the first gpio_request for the bank, | |
518 | * enable the bank module. | |
519 | */ | |
520 | if (!bank->mod_usage) | |
521 | pm_runtime_get_sync(bank->dev); | |
92105bb7 | 522 | |
55b93c32 | 523 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b TL |
524 | /* Set trigger to none. You need to enable the desired trigger with |
525 | * request_irq() or set_irq_type(). | |
526 | */ | |
3ff164e1 | 527 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 528 | |
fad96ea8 C |
529 | if (bank->regs->pinctrl) { |
530 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
5e1c5ff4 | 531 | |
92105bb7 | 532 | /* Claim the pin for MPU */ |
3ff164e1 | 533 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 | 534 | } |
fad96ea8 | 535 | |
c8eef65a C |
536 | if (bank->regs->ctrl && !bank->mod_usage) { |
537 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
538 | u32 ctrl; | |
539 | ||
540 | ctrl = __raw_readl(reg); | |
541 | /* Module is enabled, clocks are not gated */ | |
542 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
543 | __raw_writel(ctrl, reg); | |
058af1ea | 544 | } |
c8eef65a C |
545 | |
546 | bank->mod_usage |= 1 << offset; | |
547 | ||
a6472533 | 548 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
549 | |
550 | return 0; | |
551 | } | |
552 | ||
3ff164e1 | 553 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 554 | { |
3ff164e1 | 555 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
6ed87c5b | 556 | void __iomem *base = bank->base; |
a6472533 | 557 | unsigned long flags; |
5e1c5ff4 | 558 | |
a6472533 | 559 | spin_lock_irqsave(&bank->lock, flags); |
6ed87c5b TKD |
560 | |
561 | if (bank->regs->wkup_en) | |
9f096868 | 562 | /* Disable wake-up during idle for dynamic tick */ |
6ed87c5b TKD |
563 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); |
564 | ||
c8eef65a C |
565 | bank->mod_usage &= ~(1 << offset); |
566 | ||
567 | if (bank->regs->ctrl && !bank->mod_usage) { | |
568 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
569 | u32 ctrl; | |
570 | ||
571 | ctrl = __raw_readl(reg); | |
572 | /* Module is disabled, clocks are gated */ | |
573 | ctrl |= GPIO_MOD_CTRL_BIT; | |
574 | __raw_writel(ctrl, reg); | |
058af1ea | 575 | } |
c8eef65a | 576 | |
3ff164e1 | 577 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 578 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
579 | |
580 | /* | |
581 | * If this is the last gpio to be freed in the bank, | |
582 | * disable the bank module. | |
583 | */ | |
584 | if (!bank->mod_usage) | |
585 | pm_runtime_put(bank->dev); | |
5e1c5ff4 TL |
586 | } |
587 | ||
588 | /* | |
589 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
590 | * avoid missing GPIO interrupts for other lines in the bank. | |
591 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
592 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
593 | * If we wait to unmask individual GPIO lines in the bank after the | |
594 | * line's interrupt handler has been run, we may miss some nested | |
595 | * interrupts. | |
596 | */ | |
10dd5ce2 | 597 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 598 | { |
92105bb7 | 599 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 600 | u32 isr; |
4318f36b | 601 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 602 | struct gpio_bank *bank; |
ea6dedd7 ID |
603 | u32 retrigger = 0; |
604 | int unmasked = 0; | |
ee144182 | 605 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 606 | |
ee144182 | 607 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 608 | |
6845664a | 609 | bank = irq_get_handler_data(irq); |
eef4bec7 | 610 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 611 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
612 | |
613 | if (WARN_ON(!isr_reg)) | |
614 | goto exit; | |
615 | ||
92105bb7 | 616 | while(1) { |
6e60e79a | 617 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 618 | u32 enabled; |
6e60e79a | 619 | |
ea6dedd7 ID |
620 | enabled = _get_gpio_irqbank_mask(bank); |
621 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a | 622 | |
9ea14d8c | 623 | if (bank->level_mask) |
b144ff6f | 624 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
625 | |
626 | /* clear edge sensitive interrupts before handler(s) are | |
627 | called so that we don't miss any interrupt occurred while | |
628 | executing them */ | |
28f3b5a0 | 629 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 630 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 631 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
632 | |
633 | /* if there is only edge sensitive GPIO pin interrupts | |
634 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
635 | if (!level_mask && !unmasked) { |
636 | unmasked = 1; | |
ee144182 | 637 | chained_irq_exit(chip, desc); |
ea6dedd7 | 638 | } |
92105bb7 | 639 | |
ea6dedd7 ID |
640 | isr |= retrigger; |
641 | retrigger = 0; | |
92105bb7 TL |
642 | if (!isr) |
643 | break; | |
644 | ||
645 | gpio_irq = bank->virtual_irq_start; | |
646 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
129fd223 | 647 | gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq)); |
4318f36b | 648 | |
92105bb7 TL |
649 | if (!(isr & 1)) |
650 | continue; | |
29454dde | 651 | |
4318f36b CM |
652 | /* |
653 | * Some chips can't respond to both rising and falling | |
654 | * at the same time. If this irq was requested with | |
655 | * both flags, we need to flip the ICR data for the IRQ | |
656 | * to respond to the IRQ for the opposite direction. | |
657 | * This will be indicated in the bank toggle_mask. | |
658 | */ | |
659 | if (bank->toggle_mask & (1 << gpio_index)) | |
660 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
4318f36b | 661 | |
d8aa0251 | 662 | generic_handle_irq(gpio_irq); |
92105bb7 | 663 | } |
1a8bfa1e | 664 | } |
ea6dedd7 ID |
665 | /* if bank has any level sensitive GPIO pin interrupt |
666 | configured, we must unmask the bank interrupt only after | |
667 | handler(s) are executed in order to avoid spurious bank | |
668 | interrupt */ | |
b1cc4c55 | 669 | exit: |
ea6dedd7 | 670 | if (!unmasked) |
ee144182 | 671 | chained_irq_exit(chip, desc); |
55b93c32 | 672 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
673 | } |
674 | ||
e9191028 | 675 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 676 | { |
e9191028 LB |
677 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
678 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 679 | unsigned long flags; |
4196dd6b | 680 | |
85ec7b97 | 681 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 682 | _reset_gpio(bank, gpio); |
85ec7b97 | 683 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
684 | } |
685 | ||
e9191028 | 686 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 687 | { |
e9191028 LB |
688 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
689 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
690 | |
691 | _clear_gpio_irqstatus(bank, gpio); | |
692 | } | |
693 | ||
e9191028 | 694 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 695 | { |
e9191028 LB |
696 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
697 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 698 | unsigned long flags; |
5e1c5ff4 | 699 | |
85ec7b97 | 700 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 701 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 702 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 703 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
704 | } |
705 | ||
e9191028 | 706 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 707 | { |
e9191028 LB |
708 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
709 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
129fd223 | 710 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 711 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 712 | unsigned long flags; |
55b6019a | 713 | |
85ec7b97 | 714 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 715 | if (trigger) |
129fd223 | 716 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
717 | |
718 | /* For level-triggered GPIOs, the clearing must be done after | |
719 | * the HW source is cleared, thus after the handler has run */ | |
720 | if (bank->level_mask & irq_mask) { | |
721 | _set_gpio_irqenable(bank, gpio, 0); | |
722 | _clear_gpio_irqstatus(bank, gpio); | |
723 | } | |
5e1c5ff4 | 724 | |
4de8c75b | 725 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 726 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
727 | } |
728 | ||
e5c56ed3 DB |
729 | static struct irq_chip gpio_irq_chip = { |
730 | .name = "GPIO", | |
e9191028 LB |
731 | .irq_shutdown = gpio_irq_shutdown, |
732 | .irq_ack = gpio_ack_irq, | |
733 | .irq_mask = gpio_mask_irq, | |
734 | .irq_unmask = gpio_unmask_irq, | |
735 | .irq_set_type = gpio_irq_type, | |
736 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
737 | }; |
738 | ||
739 | /*---------------------------------------------------------------------*/ | |
740 | ||
79ee031f | 741 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 742 | { |
79ee031f | 743 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 744 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
745 | void __iomem *mask_reg = bank->base + |
746 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 747 | unsigned long flags; |
11a78b79 | 748 | |
a6472533 | 749 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
750 | bank->saved_wakeup = __raw_readl(mask_reg); |
751 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 752 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
753 | |
754 | return 0; | |
755 | } | |
756 | ||
79ee031f | 757 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 758 | { |
79ee031f | 759 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 760 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
761 | void __iomem *mask_reg = bank->base + |
762 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 763 | unsigned long flags; |
11a78b79 | 764 | |
a6472533 | 765 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 766 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 767 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
768 | |
769 | return 0; | |
770 | } | |
771 | ||
47145210 | 772 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
773 | .suspend_noirq = omap_mpuio_suspend_noirq, |
774 | .resume_noirq = omap_mpuio_resume_noirq, | |
775 | }; | |
776 | ||
3c437ffd | 777 | /* use platform_driver for this. */ |
11a78b79 | 778 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
779 | .driver = { |
780 | .name = "mpuio", | |
79ee031f | 781 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
782 | }, |
783 | }; | |
784 | ||
785 | static struct platform_device omap_mpuio_device = { | |
786 | .name = "mpuio", | |
787 | .id = -1, | |
788 | .dev = { | |
789 | .driver = &omap_mpuio_driver.driver, | |
790 | } | |
791 | /* could list the /proc/iomem resources */ | |
792 | }; | |
793 | ||
03e128ca | 794 | static inline void mpuio_init(struct gpio_bank *bank) |
11a78b79 | 795 | { |
77640aab | 796 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 797 | |
11a78b79 DB |
798 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
799 | (void) platform_device_register(&omap_mpuio_device); | |
800 | } | |
801 | ||
e5c56ed3 | 802 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 803 | |
52e31344 DB |
804 | static int gpio_input(struct gpio_chip *chip, unsigned offset) |
805 | { | |
806 | struct gpio_bank *bank; | |
807 | unsigned long flags; | |
808 | ||
809 | bank = container_of(chip, struct gpio_bank, chip); | |
810 | spin_lock_irqsave(&bank->lock, flags); | |
811 | _set_gpio_direction(bank, offset, 1); | |
812 | spin_unlock_irqrestore(&bank->lock, flags); | |
813 | return 0; | |
814 | } | |
815 | ||
b37c45b8 RQ |
816 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
817 | { | |
fa87931a | 818 | void __iomem *reg = bank->base + bank->regs->direction; |
b37c45b8 | 819 | |
b37c45b8 RQ |
820 | return __raw_readl(reg) & mask; |
821 | } | |
822 | ||
52e31344 DB |
823 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
824 | { | |
b37c45b8 RQ |
825 | struct gpio_bank *bank; |
826 | void __iomem *reg; | |
827 | int gpio; | |
828 | u32 mask; | |
829 | ||
830 | gpio = chip->base + offset; | |
a8be8daf | 831 | bank = container_of(chip, struct gpio_bank, chip); |
b37c45b8 | 832 | reg = bank->base; |
129fd223 | 833 | mask = GPIO_BIT(bank, gpio); |
b37c45b8 RQ |
834 | |
835 | if (gpio_is_input(bank, mask)) | |
836 | return _get_gpio_datain(bank, gpio); | |
837 | else | |
838 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
839 | } |
840 | ||
841 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
842 | { | |
843 | struct gpio_bank *bank; | |
844 | unsigned long flags; | |
845 | ||
846 | bank = container_of(chip, struct gpio_bank, chip); | |
847 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 848 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
849 | _set_gpio_direction(bank, offset, 0); |
850 | spin_unlock_irqrestore(&bank->lock, flags); | |
851 | return 0; | |
852 | } | |
853 | ||
168ef3d9 FB |
854 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
855 | unsigned debounce) | |
856 | { | |
857 | struct gpio_bank *bank; | |
858 | unsigned long flags; | |
859 | ||
860 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab VC |
861 | |
862 | if (!bank->dbck) { | |
863 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
864 | if (IS_ERR(bank->dbck)) | |
865 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
866 | } | |
867 | ||
168ef3d9 FB |
868 | spin_lock_irqsave(&bank->lock, flags); |
869 | _set_gpio_debounce(bank, offset, debounce); | |
870 | spin_unlock_irqrestore(&bank->lock, flags); | |
871 | ||
872 | return 0; | |
873 | } | |
874 | ||
52e31344 DB |
875 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
876 | { | |
877 | struct gpio_bank *bank; | |
878 | unsigned long flags; | |
879 | ||
880 | bank = container_of(chip, struct gpio_bank, chip); | |
881 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 882 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
883 | spin_unlock_irqrestore(&bank->lock, flags); |
884 | } | |
885 | ||
a007b709 DB |
886 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
887 | { | |
888 | struct gpio_bank *bank; | |
889 | ||
890 | bank = container_of(chip, struct gpio_bank, chip); | |
891 | return bank->virtual_irq_start + offset; | |
892 | } | |
893 | ||
52e31344 DB |
894 | /*---------------------------------------------------------------------*/ |
895 | ||
9a748053 | 896 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 897 | { |
e5ff4440 | 898 | static bool called; |
9f7065da TL |
899 | u32 rev; |
900 | ||
e5ff4440 | 901 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
902 | return; |
903 | ||
e5ff4440 KH |
904 | rev = __raw_readw(bank->base + bank->regs->revision); |
905 | pr_info("OMAP GPIO hardware version %d.%d\n", | |
9f7065da | 906 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
907 | |
908 | called = true; | |
9f7065da TL |
909 | } |
910 | ||
8ba55c5c DB |
911 | /* This lock class tells lockdep that GPIO irqs are in a different |
912 | * category than their parents, so it won't report false recursion. | |
913 | */ | |
914 | static struct lock_class_key gpio_lock_class; | |
915 | ||
03e128ca | 916 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 917 | { |
ab985f0f TKD |
918 | void __iomem *base = bank->base; |
919 | u32 l = 0xffffffff; | |
2fae7fbe | 920 | |
ab985f0f TKD |
921 | if (bank->width == 16) |
922 | l = 0xffff; | |
923 | ||
d0d665a8 | 924 | if (bank->is_mpuio) { |
ab985f0f TKD |
925 | __raw_writel(l, bank->base + bank->regs->irqenable); |
926 | return; | |
2fae7fbe | 927 | } |
ab985f0f TKD |
928 | |
929 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv); | |
930 | _gpio_rmw(base, bank->regs->irqstatus, l, | |
931 | bank->regs->irqenable_inv == false); | |
932 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0); | |
933 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0); | |
934 | if (bank->regs->debounce_en) | |
935 | _gpio_rmw(base, bank->regs->debounce_en, 0, 1); | |
936 | ||
2dc983c5 TKD |
937 | /* Save OE default value (0xffffffff) in the context */ |
938 | bank->context.oe = __raw_readl(bank->base + bank->regs->direction); | |
ab985f0f TKD |
939 | /* Initialize interface clk ungated, module enabled */ |
940 | if (bank->regs->ctrl) | |
941 | _gpio_rmw(base, bank->regs->ctrl, 0, 1); | |
2fae7fbe VC |
942 | } |
943 | ||
f8b46b58 KH |
944 | static __init void |
945 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, | |
946 | unsigned int num) | |
947 | { | |
948 | struct irq_chip_generic *gc; | |
949 | struct irq_chip_type *ct; | |
950 | ||
951 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
952 | handle_simple_irq); | |
83233749 TP |
953 | if (!gc) { |
954 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
955 | return; | |
956 | } | |
957 | ||
f8b46b58 KH |
958 | ct = gc->chip_types; |
959 | ||
960 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
961 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
962 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
963 | ct->chip.irq_set_type = gpio_irq_type; | |
6ed87c5b TKD |
964 | |
965 | if (bank->regs->wkup_en) | |
f8b46b58 KH |
966 | ct->chip.irq_set_wake = gpio_wake_enable, |
967 | ||
968 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
969 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
970 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
971 | } | |
972 | ||
d52b31de | 973 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 974 | { |
77640aab | 975 | int j; |
2fae7fbe VC |
976 | static int gpio; |
977 | ||
2fae7fbe VC |
978 | /* |
979 | * REVISIT eventually switch from OMAP-specific gpio structs | |
980 | * over to the generic ones | |
981 | */ | |
982 | bank->chip.request = omap_gpio_request; | |
983 | bank->chip.free = omap_gpio_free; | |
984 | bank->chip.direction_input = gpio_input; | |
985 | bank->chip.get = gpio_get; | |
986 | bank->chip.direction_output = gpio_output; | |
987 | bank->chip.set_debounce = gpio_debounce; | |
988 | bank->chip.set = gpio_set; | |
989 | bank->chip.to_irq = gpio_2irq; | |
d0d665a8 | 990 | if (bank->is_mpuio) { |
2fae7fbe | 991 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
992 | if (bank->regs->wkup_en) |
993 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
994 | bank->chip.base = OMAP_MPUIO(0); |
995 | } else { | |
996 | bank->chip.label = "gpio"; | |
997 | bank->chip.base = gpio; | |
d5f46247 | 998 | gpio += bank->width; |
2fae7fbe | 999 | } |
d5f46247 | 1000 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
1001 | |
1002 | gpiochip_add(&bank->chip); | |
1003 | ||
1004 | for (j = bank->virtual_irq_start; | |
d5f46247 | 1005 | j < bank->virtual_irq_start + bank->width; j++) { |
1475b85d | 1006 | irq_set_lockdep_class(j, &gpio_lock_class); |
6845664a | 1007 | irq_set_chip_data(j, bank); |
d0d665a8 | 1008 | if (bank->is_mpuio) { |
f8b46b58 KH |
1009 | omap_mpuio_alloc_gc(bank, j, bank->width); |
1010 | } else { | |
6845664a | 1011 | irq_set_chip(j, &gpio_irq_chip); |
f8b46b58 KH |
1012 | irq_set_handler(j, handle_simple_irq); |
1013 | set_irq_flags(j, IRQF_VALID); | |
1014 | } | |
2fae7fbe | 1015 | } |
6845664a TG |
1016 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1017 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
1018 | } |
1019 | ||
77640aab | 1020 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1021 | { |
77640aab VC |
1022 | struct omap_gpio_platform_data *pdata; |
1023 | struct resource *res; | |
5e1c5ff4 | 1024 | struct gpio_bank *bank; |
03e128ca | 1025 | int ret = 0; |
5e1c5ff4 | 1026 | |
03e128ca C |
1027 | if (!pdev->dev.platform_data) { |
1028 | ret = -EINVAL; | |
1029 | goto err_exit; | |
5492fb1a | 1030 | } |
5492fb1a | 1031 | |
03e128ca C |
1032 | bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL); |
1033 | if (!bank) { | |
1034 | dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); | |
1035 | ret = -ENOMEM; | |
1036 | goto err_exit; | |
1037 | } | |
92105bb7 | 1038 | |
77640aab VC |
1039 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1040 | if (unlikely(!res)) { | |
03e128ca C |
1041 | dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", |
1042 | pdev->id); | |
1043 | ret = -ENODEV; | |
1044 | goto err_free; | |
44169075 | 1045 | } |
5e1c5ff4 | 1046 | |
77640aab | 1047 | bank->irq = res->start; |
03e128ca C |
1048 | bank->id = pdev->id; |
1049 | ||
1050 | pdata = pdev->dev.platform_data; | |
77640aab | 1051 | bank->virtual_irq_start = pdata->virtual_irq_start; |
77640aab VC |
1052 | bank->dev = &pdev->dev; |
1053 | bank->dbck_flag = pdata->dbck_flag; | |
5de62b86 | 1054 | bank->stride = pdata->bank_stride; |
d5f46247 | 1055 | bank->width = pdata->bank_width; |
d0d665a8 | 1056 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1057 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
0cde8d03 | 1058 | bank->loses_context = pdata->loses_context; |
60a3437d | 1059 | bank->get_context_loss_count = pdata->get_context_loss_count; |
fa87931a KH |
1060 | bank->regs = pdata->regs; |
1061 | ||
1062 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1063 | bank->set_dataout = _set_gpio_dataout_reg; | |
1064 | else | |
1065 | bank->set_dataout = _set_gpio_dataout_mask; | |
9f7065da | 1066 | |
77640aab | 1067 | spin_lock_init(&bank->lock); |
9f7065da | 1068 | |
77640aab VC |
1069 | /* Static mapping, never released */ |
1070 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1071 | if (unlikely(!res)) { | |
03e128ca C |
1072 | dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", |
1073 | pdev->id); | |
1074 | ret = -ENODEV; | |
1075 | goto err_free; | |
77640aab | 1076 | } |
89db9482 | 1077 | |
77640aab VC |
1078 | bank->base = ioremap(res->start, resource_size(res)); |
1079 | if (!bank->base) { | |
03e128ca C |
1080 | dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", |
1081 | pdev->id); | |
1082 | ret = -ENOMEM; | |
1083 | goto err_free; | |
5e1c5ff4 TL |
1084 | } |
1085 | ||
065cd795 TKD |
1086 | platform_set_drvdata(pdev, bank); |
1087 | ||
77640aab | 1088 | pm_runtime_enable(bank->dev); |
55b93c32 | 1089 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1090 | pm_runtime_get_sync(bank->dev); |
1091 | ||
d0d665a8 | 1092 | if (bank->is_mpuio) |
ab985f0f TKD |
1093 | mpuio_init(bank); |
1094 | ||
03e128ca | 1095 | omap_gpio_mod_init(bank); |
77640aab | 1096 | omap_gpio_chip_init(bank); |
9a748053 | 1097 | omap_gpio_show_rev(bank); |
9f7065da | 1098 | |
55b93c32 TKD |
1099 | pm_runtime_put(bank->dev); |
1100 | ||
03e128ca | 1101 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1102 | |
03e128ca C |
1103 | return ret; |
1104 | ||
1105 | err_free: | |
1106 | kfree(bank); | |
1107 | err_exit: | |
1108 | return ret; | |
5e1c5ff4 TL |
1109 | } |
1110 | ||
55b93c32 TKD |
1111 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1112 | ||
1113 | #if defined(CONFIG_PM_SLEEP) | |
1114 | static int omap_gpio_suspend(struct device *dev) | |
92105bb7 | 1115 | { |
065cd795 TKD |
1116 | struct platform_device *pdev = to_platform_device(dev); |
1117 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1118 | void __iomem *base = bank->base; | |
1119 | void __iomem *wakeup_enable; | |
1120 | unsigned long flags; | |
92105bb7 | 1121 | |
065cd795 TKD |
1122 | if (!bank->mod_usage || !bank->loses_context) |
1123 | return 0; | |
92105bb7 | 1124 | |
065cd795 TKD |
1125 | if (!bank->regs->wkup_en || !bank->suspend_wakeup) |
1126 | return 0; | |
6ed87c5b | 1127 | |
065cd795 | 1128 | wakeup_enable = bank->base + bank->regs->wkup_en; |
92105bb7 | 1129 | |
065cd795 TKD |
1130 | spin_lock_irqsave(&bank->lock, flags); |
1131 | bank->saved_wakeup = __raw_readl(wakeup_enable); | |
1132 | _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0); | |
1133 | _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1); | |
1134 | spin_unlock_irqrestore(&bank->lock, flags); | |
92105bb7 TL |
1135 | |
1136 | return 0; | |
1137 | } | |
1138 | ||
55b93c32 | 1139 | static int omap_gpio_resume(struct device *dev) |
92105bb7 | 1140 | { |
065cd795 TKD |
1141 | struct platform_device *pdev = to_platform_device(dev); |
1142 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1143 | void __iomem *base = bank->base; | |
1144 | unsigned long flags; | |
92105bb7 | 1145 | |
065cd795 TKD |
1146 | if (!bank->mod_usage || !bank->loses_context) |
1147 | return 0; | |
92105bb7 | 1148 | |
065cd795 TKD |
1149 | if (!bank->regs->wkup_en || !bank->saved_wakeup) |
1150 | return 0; | |
92105bb7 | 1151 | |
065cd795 TKD |
1152 | spin_lock_irqsave(&bank->lock, flags); |
1153 | _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0); | |
1154 | _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1); | |
1155 | spin_unlock_irqrestore(&bank->lock, flags); | |
92105bb7 | 1156 | |
55b93c32 TKD |
1157 | return 0; |
1158 | } | |
1159 | #endif /* CONFIG_PM_SLEEP */ | |
3ac4fa99 | 1160 | |
2dc983c5 | 1161 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d TKD |
1162 | static void omap_gpio_save_context(struct gpio_bank *bank); |
1163 | static void omap_gpio_restore_context(struct gpio_bank *bank); | |
3ac4fa99 | 1164 | |
2dc983c5 | 1165 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1166 | { |
2dc983c5 TKD |
1167 | struct platform_device *pdev = to_platform_device(dev); |
1168 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1169 | u32 l1 = 0, l2 = 0; | |
1170 | unsigned long flags; | |
8865b9b6 | 1171 | |
2dc983c5 TKD |
1172 | spin_lock_irqsave(&bank->lock, flags); |
1173 | if (bank->power_mode != OFF_MODE) { | |
1174 | bank->power_mode = 0; | |
1175 | goto save_gpio_context; | |
1176 | } | |
1177 | /* | |
1178 | * If going to OFF, remove triggering for all | |
1179 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1180 | * generated. See OMAP2420 Errata item 1.101. | |
1181 | */ | |
1182 | if (!(bank->enabled_non_wakeup_gpios)) | |
1183 | goto save_gpio_context; | |
43ffcd9a | 1184 | |
2dc983c5 TKD |
1185 | bank->saved_datain = __raw_readl(bank->base + |
1186 | bank->regs->datain); | |
1187 | l1 = __raw_readl(bank->base + bank->regs->fallingdetect); | |
1188 | l2 = __raw_readl(bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1189 | |
2dc983c5 TKD |
1190 | bank->saved_fallingdetect = l1; |
1191 | bank->saved_risingdetect = l2; | |
1192 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1193 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1194 | |
2dc983c5 TKD |
1195 | __raw_writel(l1, bank->base + bank->regs->fallingdetect); |
1196 | __raw_writel(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1197 | |
2dc983c5 | 1198 | bank->workaround_enabled = true; |
3f1686a9 | 1199 | |
60a3437d | 1200 | save_gpio_context: |
2dc983c5 TKD |
1201 | if (bank->get_context_loss_count) |
1202 | bank->context_loss_count = | |
60a3437d TKD |
1203 | bank->get_context_loss_count(bank->dev); |
1204 | ||
2dc983c5 | 1205 | omap_gpio_save_context(bank); |
72f83af9 | 1206 | _gpio_dbck_disable(bank); |
2dc983c5 | 1207 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1208 | |
2dc983c5 | 1209 | return 0; |
3ac4fa99 JY |
1210 | } |
1211 | ||
2dc983c5 | 1212 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1213 | { |
2dc983c5 TKD |
1214 | struct platform_device *pdev = to_platform_device(dev); |
1215 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1216 | int context_lost_cnt_after; | |
1217 | u32 l = 0, gen, gen0, gen1; | |
1218 | unsigned long flags; | |
8865b9b6 | 1219 | |
2dc983c5 | 1220 | spin_lock_irqsave(&bank->lock, flags); |
72f83af9 | 1221 | _gpio_dbck_enable(bank); |
2dc983c5 TKD |
1222 | if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) { |
1223 | spin_unlock_irqrestore(&bank->lock, flags); | |
1224 | return 0; | |
1225 | } | |
55b93c32 | 1226 | |
2dc983c5 TKD |
1227 | if (bank->get_context_loss_count) { |
1228 | context_lost_cnt_after = | |
1229 | bank->get_context_loss_count(bank->dev); | |
1230 | if (context_lost_cnt_after != bank->context_loss_count || | |
1231 | !context_lost_cnt_after) { | |
1232 | omap_gpio_restore_context(bank); | |
1233 | } else { | |
1234 | spin_unlock_irqrestore(&bank->lock, flags); | |
1235 | return 0; | |
60a3437d | 1236 | } |
2dc983c5 | 1237 | } |
43ffcd9a | 1238 | |
2dc983c5 TKD |
1239 | __raw_writel(bank->saved_fallingdetect, |
1240 | bank->base + bank->regs->fallingdetect); | |
1241 | __raw_writel(bank->saved_risingdetect, | |
1242 | bank->base + bank->regs->risingdetect); | |
1243 | l = __raw_readl(bank->base + bank->regs->datain); | |
3f1686a9 | 1244 | |
2dc983c5 TKD |
1245 | /* |
1246 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1247 | * state. If so, generate an IRQ by software. This is | |
1248 | * horribly racy, but it's the best we can do to work around | |
1249 | * this silicon bug. | |
1250 | */ | |
1251 | l ^= bank->saved_datain; | |
1252 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1253 | |
2dc983c5 TKD |
1254 | /* |
1255 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1256 | * configured with falling edge only; and vice versa. | |
1257 | */ | |
1258 | gen0 = l & bank->saved_fallingdetect; | |
1259 | gen0 &= bank->saved_datain; | |
82dbb9d3 | 1260 | |
2dc983c5 TKD |
1261 | gen1 = l & bank->saved_risingdetect; |
1262 | gen1 &= ~(bank->saved_datain); | |
82dbb9d3 | 1263 | |
2dc983c5 TKD |
1264 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
1265 | gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect)); | |
1266 | /* Consider all GPIO IRQs needed to be updated */ | |
1267 | gen |= gen0 | gen1; | |
82dbb9d3 | 1268 | |
2dc983c5 TKD |
1269 | if (gen) { |
1270 | u32 old0, old1; | |
82dbb9d3 | 1271 | |
2dc983c5 TKD |
1272 | old0 = __raw_readl(bank->base + bank->regs->leveldetect0); |
1273 | old1 = __raw_readl(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1274 | |
2dc983c5 TKD |
1275 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
1276 | __raw_writel(old0 | gen, bank->base + | |
9ea14d8c | 1277 | bank->regs->leveldetect0); |
2dc983c5 | 1278 | __raw_writel(old1 | gen, bank->base + |
9ea14d8c | 1279 | bank->regs->leveldetect1); |
2dc983c5 | 1280 | } |
9ea14d8c | 1281 | |
2dc983c5 TKD |
1282 | if (cpu_is_omap44xx()) { |
1283 | __raw_writel(old0 | l, bank->base + | |
9ea14d8c | 1284 | bank->regs->leveldetect0); |
2dc983c5 | 1285 | __raw_writel(old1 | l, bank->base + |
9ea14d8c | 1286 | bank->regs->leveldetect1); |
3ac4fa99 | 1287 | } |
2dc983c5 TKD |
1288 | __raw_writel(old0, bank->base + bank->regs->leveldetect0); |
1289 | __raw_writel(old1, bank->base + bank->regs->leveldetect1); | |
1290 | } | |
1291 | ||
1292 | bank->workaround_enabled = false; | |
1293 | spin_unlock_irqrestore(&bank->lock, flags); | |
1294 | ||
1295 | return 0; | |
1296 | } | |
1297 | #endif /* CONFIG_PM_RUNTIME */ | |
1298 | ||
1299 | void omap2_gpio_prepare_for_idle(int pwr_mode) | |
1300 | { | |
1301 | struct gpio_bank *bank; | |
1302 | ||
1303 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
2dc983c5 TKD |
1304 | if (!bank->mod_usage || !bank->loses_context) |
1305 | continue; | |
1306 | ||
1307 | bank->power_mode = pwr_mode; | |
1308 | ||
2dc983c5 TKD |
1309 | pm_runtime_put_sync_suspend(bank->dev); |
1310 | } | |
1311 | } | |
1312 | ||
1313 | void omap2_gpio_resume_after_idle(void) | |
1314 | { | |
1315 | struct gpio_bank *bank; | |
1316 | ||
1317 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
2dc983c5 TKD |
1318 | if (!bank->mod_usage || !bank->loses_context) |
1319 | continue; | |
1320 | ||
2dc983c5 | 1321 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1322 | } |
3ac4fa99 JY |
1323 | } |
1324 | ||
2dc983c5 | 1325 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1326 | static void omap_gpio_save_context(struct gpio_bank *bank) |
40c670f0 | 1327 | { |
60a3437d | 1328 | bank->context.irqenable1 = |
ae10f233 | 1329 | __raw_readl(bank->base + bank->regs->irqenable); |
60a3437d | 1330 | bank->context.irqenable2 = |
ae10f233 | 1331 | __raw_readl(bank->base + bank->regs->irqenable2); |
60a3437d | 1332 | bank->context.wake_en = |
ae10f233 TKD |
1333 | __raw_readl(bank->base + bank->regs->wkup_en); |
1334 | bank->context.ctrl = __raw_readl(bank->base + bank->regs->ctrl); | |
1335 | bank->context.oe = __raw_readl(bank->base + bank->regs->direction); | |
60a3437d | 1336 | bank->context.leveldetect0 = |
ae10f233 | 1337 | __raw_readl(bank->base + bank->regs->leveldetect0); |
60a3437d | 1338 | bank->context.leveldetect1 = |
ae10f233 | 1339 | __raw_readl(bank->base + bank->regs->leveldetect1); |
60a3437d | 1340 | bank->context.risingdetect = |
ae10f233 | 1341 | __raw_readl(bank->base + bank->regs->risingdetect); |
60a3437d | 1342 | bank->context.fallingdetect = |
ae10f233 TKD |
1343 | __raw_readl(bank->base + bank->regs->fallingdetect); |
1344 | bank->context.dataout = __raw_readl(bank->base + bank->regs->dataout); | |
40c670f0 RN |
1345 | } |
1346 | ||
60a3437d | 1347 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1348 | { |
60a3437d | 1349 | __raw_writel(bank->context.irqenable1, |
ae10f233 | 1350 | bank->base + bank->regs->irqenable); |
60a3437d | 1351 | __raw_writel(bank->context.irqenable2, |
ae10f233 | 1352 | bank->base + bank->regs->irqenable2); |
60a3437d | 1353 | __raw_writel(bank->context.wake_en, |
ae10f233 TKD |
1354 | bank->base + bank->regs->wkup_en); |
1355 | __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
1356 | __raw_writel(bank->context.oe, bank->base + bank->regs->direction); | |
60a3437d | 1357 | __raw_writel(bank->context.leveldetect0, |
ae10f233 | 1358 | bank->base + bank->regs->leveldetect0); |
60a3437d | 1359 | __raw_writel(bank->context.leveldetect1, |
ae10f233 | 1360 | bank->base + bank->regs->leveldetect1); |
60a3437d | 1361 | __raw_writel(bank->context.risingdetect, |
ae10f233 | 1362 | bank->base + bank->regs->risingdetect); |
60a3437d | 1363 | __raw_writel(bank->context.fallingdetect, |
ae10f233 TKD |
1364 | bank->base + bank->regs->fallingdetect); |
1365 | __raw_writel(bank->context.dataout, bank->base + bank->regs->dataout); | |
40c670f0 | 1366 | } |
2dc983c5 | 1367 | #endif /* CONFIG_PM_RUNTIME */ |
55b93c32 TKD |
1368 | #else |
1369 | #define omap_gpio_suspend NULL | |
1370 | #define omap_gpio_resume NULL | |
2dc983c5 TKD |
1371 | #define omap_gpio_runtime_suspend NULL |
1372 | #define omap_gpio_runtime_resume NULL | |
40c670f0 RN |
1373 | #endif |
1374 | ||
55b93c32 TKD |
1375 | static const struct dev_pm_ops gpio_pm_ops = { |
1376 | SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume) | |
2dc983c5 TKD |
1377 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1378 | NULL) | |
55b93c32 TKD |
1379 | }; |
1380 | ||
77640aab VC |
1381 | static struct platform_driver omap_gpio_driver = { |
1382 | .probe = omap_gpio_probe, | |
1383 | .driver = { | |
1384 | .name = "omap_gpio", | |
55b93c32 | 1385 | .pm = &gpio_pm_ops, |
77640aab VC |
1386 | }, |
1387 | }; | |
1388 | ||
5e1c5ff4 | 1389 | /* |
77640aab VC |
1390 | * gpio driver register needs to be done before |
1391 | * machine_init functions access gpio APIs. | |
1392 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1393 | */ |
77640aab | 1394 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1395 | { |
77640aab | 1396 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1397 | } |
77640aab | 1398 | postcore_initcall(omap_gpio_drv_reg); |