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Commit | Line | Data |
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5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
4b25408f | 27 | #include <linux/gpio.h> |
9370084e | 28 | #include <linux/bitops.h> |
4b25408f | 29 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 30 | |
2dc983c5 | 31 | #define OFF_MODE 1 |
e85ec6c3 | 32 | #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF |
2dc983c5 | 33 | |
03e128ca C |
34 | static LIST_HEAD(omap_gpio_list); |
35 | ||
6d62e216 C |
36 | struct gpio_regs { |
37 | u32 irqenable1; | |
38 | u32 irqenable2; | |
39 | u32 wake_en; | |
40 | u32 ctrl; | |
41 | u32 oe; | |
42 | u32 leveldetect0; | |
43 | u32 leveldetect1; | |
44 | u32 risingdetect; | |
45 | u32 fallingdetect; | |
46 | u32 dataout; | |
ae547354 NM |
47 | u32 debounce; |
48 | u32 debounce_en; | |
6d62e216 C |
49 | }; |
50 | ||
5e1c5ff4 | 51 | struct gpio_bank { |
03e128ca | 52 | struct list_head node; |
92105bb7 | 53 | void __iomem *base; |
30cefeac | 54 | int irq; |
3ac4fa99 JY |
55 | u32 non_wakeup_gpios; |
56 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 57 | struct gpio_regs context; |
3ac4fa99 | 58 | u32 saved_datain; |
b144ff6f | 59 | u32 level_mask; |
4318f36b | 60 | u32 toggle_mask; |
4dbada2b | 61 | raw_spinlock_t lock; |
450fa54c | 62 | raw_spinlock_t wa_lock; |
52e31344 | 63 | struct gpio_chip chip; |
89db9482 | 64 | struct clk *dbck; |
058af1ea | 65 | u32 mod_usage; |
fa365e4d | 66 | u32 irq_usage; |
8865b9b6 | 67 | u32 dbck_enable_mask; |
72f83af9 | 68 | bool dbck_enabled; |
77640aab | 69 | struct device *dev; |
d0d665a8 | 70 | bool is_mpuio; |
77640aab | 71 | bool dbck_flag; |
0cde8d03 | 72 | bool loses_context; |
352a2d5b | 73 | bool context_valid; |
5de62b86 | 74 | int stride; |
d5f46247 | 75 | u32 width; |
60a3437d | 76 | int context_loss_count; |
2dc983c5 TKD |
77 | int power_mode; |
78 | bool workaround_enabled; | |
fa87931a | 79 | |
04ebcbd8 | 80 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
60a3437d | 81 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
82 | |
83 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
84 | }; |
85 | ||
c8eef65a | 86 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 87 | |
fa365e4d | 88 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 89 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 90 | |
3d009c8c TL |
91 | static void omap_gpio_unmask_irq(struct irq_data *d); |
92 | ||
a0e827c6 | 93 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 94 | { |
fb655f57 JMC |
95 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
96 | return container_of(chip, struct gpio_bank, chip); | |
25db711d BC |
97 | } |
98 | ||
a0e827c6 JMC |
99 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
100 | int is_input) | |
5e1c5ff4 | 101 | { |
92105bb7 | 102 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
103 | u32 l; |
104 | ||
fa87931a | 105 | reg += bank->regs->direction; |
661553b9 | 106 | l = readl_relaxed(reg); |
5e1c5ff4 | 107 | if (is_input) |
b1e9fec2 | 108 | l |= BIT(gpio); |
5e1c5ff4 | 109 | else |
b1e9fec2 | 110 | l &= ~(BIT(gpio)); |
661553b9 | 111 | writel_relaxed(l, reg); |
41d87cbd | 112 | bank->context.oe = l; |
5e1c5ff4 TL |
113 | } |
114 | ||
fa87931a KH |
115 | |
116 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 117 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 118 | int enable) |
5e1c5ff4 | 119 | { |
92105bb7 | 120 | void __iomem *reg = bank->base; |
04ebcbd8 | 121 | u32 l = BIT(offset); |
5e1c5ff4 | 122 | |
2c836f7e | 123 | if (enable) { |
fa87931a | 124 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
125 | bank->context.dataout |= l; |
126 | } else { | |
fa87931a | 127 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
128 | bank->context.dataout &= ~l; |
129 | } | |
5e1c5ff4 | 130 | |
661553b9 | 131 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
132 | } |
133 | ||
fa87931a | 134 | /* set data out value using mask register */ |
04ebcbd8 | 135 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 136 | int enable) |
5e1c5ff4 | 137 | { |
fa87931a | 138 | void __iomem *reg = bank->base + bank->regs->dataout; |
04ebcbd8 | 139 | u32 gpio_bit = BIT(offset); |
fa87931a | 140 | u32 l; |
5e1c5ff4 | 141 | |
661553b9 | 142 | l = readl_relaxed(reg); |
fa87931a KH |
143 | if (enable) |
144 | l |= gpio_bit; | |
145 | else | |
146 | l &= ~gpio_bit; | |
661553b9 | 147 | writel_relaxed(l, reg); |
41d87cbd | 148 | bank->context.dataout = l; |
5e1c5ff4 TL |
149 | } |
150 | ||
a0e827c6 | 151 | static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 152 | { |
fa87931a | 153 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 154 | |
b1e9fec2 | 155 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
5e1c5ff4 | 156 | } |
b37c45b8 | 157 | |
a0e827c6 | 158 | static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 159 | { |
fa87931a | 160 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 161 | |
b1e9fec2 | 162 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
b37c45b8 RQ |
163 | } |
164 | ||
a0e827c6 | 165 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
ece9528e | 166 | { |
661553b9 | 167 | int l = readl_relaxed(base + reg); |
ece9528e | 168 | |
862ff640 | 169 | if (set) |
ece9528e KH |
170 | l |= mask; |
171 | else | |
172 | l &= ~mask; | |
173 | ||
661553b9 | 174 | writel_relaxed(l, base + reg); |
ece9528e | 175 | } |
92105bb7 | 176 | |
a0e827c6 | 177 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
178 | { |
179 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
5d9452e7 | 180 | clk_enable(bank->dbck); |
72f83af9 | 181 | bank->dbck_enabled = true; |
9e303f22 | 182 | |
661553b9 | 183 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 184 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
185 | } |
186 | } | |
187 | ||
a0e827c6 | 188 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
189 | { |
190 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
191 | /* |
192 | * Disable debounce before cutting it's clock. If debounce is | |
193 | * enabled but the clock is not, GPIO module seems to be unable | |
194 | * to detect events and generate interrupts at least on OMAP3. | |
195 | */ | |
661553b9 | 196 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 197 | |
5d9452e7 | 198 | clk_disable(bank->dbck); |
72f83af9 TKD |
199 | bank->dbck_enabled = false; |
200 | } | |
201 | } | |
202 | ||
168ef3d9 | 203 | /** |
a0e827c6 | 204 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 205 | * @bank: the gpio bank we're acting upon |
4a58d229 | 206 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
207 | * @debounce: debounce time to use |
208 | * | |
e85ec6c3 GS |
209 | * OMAP's debounce time is in 31us steps |
210 | * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 | |
211 | * so we need to convert and round up to the closest unit. | |
168ef3d9 | 212 | */ |
4a58d229 | 213 | static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 214 | unsigned debounce) |
168ef3d9 | 215 | { |
9942da0e | 216 | void __iomem *reg; |
168ef3d9 FB |
217 | u32 val; |
218 | u32 l; | |
e85ec6c3 | 219 | bool enable = !!debounce; |
168ef3d9 | 220 | |
77640aab VC |
221 | if (!bank->dbck_flag) |
222 | return; | |
223 | ||
e85ec6c3 GS |
224 | if (enable) { |
225 | debounce = DIV_ROUND_UP(debounce, 31) - 1; | |
226 | debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK; | |
227 | } | |
168ef3d9 | 228 | |
4a58d229 | 229 | l = BIT(offset); |
168ef3d9 | 230 | |
5d9452e7 | 231 | clk_enable(bank->dbck); |
9942da0e | 232 | reg = bank->base + bank->regs->debounce; |
661553b9 | 233 | writel_relaxed(debounce, reg); |
168ef3d9 | 234 | |
9942da0e | 235 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 236 | val = readl_relaxed(reg); |
168ef3d9 | 237 | |
e85ec6c3 | 238 | if (enable) |
168ef3d9 | 239 | val |= l; |
6fd9c421 | 240 | else |
168ef3d9 | 241 | val &= ~l; |
f7ec0b0b | 242 | bank->dbck_enable_mask = val; |
168ef3d9 | 243 | |
661553b9 | 244 | writel_relaxed(val, reg); |
5d9452e7 | 245 | clk_disable(bank->dbck); |
6fd9c421 TKD |
246 | /* |
247 | * Enable debounce clock per module. | |
248 | * This call is mandatory because in omap_gpio_request() when | |
249 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
250 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
251 | * used within _gpio_dbck_enable() is still not initialized at | |
252 | * that point. Therefore we have to enable dbck here. | |
253 | */ | |
a0e827c6 | 254 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
255 | if (bank->dbck_enable_mask) { |
256 | bank->context.debounce = debounce; | |
257 | bank->context.debounce_en = val; | |
258 | } | |
168ef3d9 FB |
259 | } |
260 | ||
c9c55d92 | 261 | /** |
a0e827c6 | 262 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 263 | * @bank: the gpio bank we're acting upon |
4a58d229 | 264 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
265 | * |
266 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
267 | * this is the only gpio in this bank using debounce, then clear the debounce | |
268 | * time too. The debounce clock will also be disabled when calling this function | |
269 | * if this is the only gpio in the bank using debounce. | |
270 | */ | |
4a58d229 | 271 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 272 | { |
4a58d229 | 273 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
274 | |
275 | if (!bank->dbck_flag) | |
276 | return; | |
277 | ||
278 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
279 | return; | |
280 | ||
281 | bank->dbck_enable_mask &= ~gpio_bit; | |
282 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 283 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
284 | bank->base + bank->regs->debounce_en); |
285 | ||
286 | if (!bank->dbck_enable_mask) { | |
287 | bank->context.debounce = 0; | |
661553b9 | 288 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 289 | bank->regs->debounce); |
5d9452e7 | 290 | clk_disable(bank->dbck); |
c9c55d92 JH |
291 | bank->dbck_enabled = false; |
292 | } | |
293 | } | |
294 | ||
a0e827c6 | 295 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 296 | unsigned trigger) |
5e1c5ff4 | 297 | { |
3ac4fa99 | 298 | void __iomem *base = bank->base; |
b1e9fec2 | 299 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 300 | |
a0e827c6 JMC |
301 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
302 | trigger & IRQ_TYPE_LEVEL_LOW); | |
303 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
304 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
305 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
306 | trigger & IRQ_TYPE_EDGE_RISING); | |
307 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
308 | trigger & IRQ_TYPE_EDGE_FALLING); | |
5e571f38 | 309 | |
41d87cbd | 310 | bank->context.leveldetect0 = |
661553b9 | 311 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 312 | bank->context.leveldetect1 = |
661553b9 | 313 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 314 | bank->context.risingdetect = |
661553b9 | 315 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 316 | bank->context.fallingdetect = |
661553b9 | 317 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
318 | |
319 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
a0e827c6 | 320 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd | 321 | bank->context.wake_en = |
661553b9 | 322 | readl_relaxed(bank->base + bank->regs->wkup_en); |
41d87cbd | 323 | } |
5e571f38 | 324 | |
55b220ca | 325 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
326 | if (!bank->regs->irqctrl) { |
327 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
328 | if (bank->non_wakeup_gpios) { | |
329 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
330 | goto exit; | |
331 | } | |
332 | ||
699117a6 CW |
333 | /* |
334 | * Log the edge gpio and manually trigger the IRQ | |
335 | * after resume if the input level changes | |
336 | * to avoid irq lost during PER RET/OFF mode | |
337 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
338 | */ | |
339 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
340 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
341 | else | |
342 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
343 | } | |
5eb3bb9c | 344 | |
5e571f38 | 345 | exit: |
9ea14d8c | 346 | bank->level_mask = |
661553b9 VK |
347 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
348 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
349 | } |
350 | ||
9198bcd3 | 351 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
352 | /* |
353 | * This only applies to chips that can't do both rising and falling edge | |
354 | * detection at once. For all other chips, this function is a noop. | |
355 | */ | |
a0e827c6 | 356 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b CM |
357 | { |
358 | void __iomem *reg = bank->base; | |
359 | u32 l = 0; | |
360 | ||
5e571f38 | 361 | if (!bank->regs->irqctrl) |
4318f36b | 362 | return; |
5e571f38 TKD |
363 | |
364 | reg += bank->regs->irqctrl; | |
4318f36b | 365 | |
661553b9 | 366 | l = readl_relaxed(reg); |
4318f36b | 367 | if ((l >> gpio) & 1) |
b1e9fec2 | 368 | l &= ~(BIT(gpio)); |
4318f36b | 369 | else |
b1e9fec2 | 370 | l |= BIT(gpio); |
4318f36b | 371 | |
661553b9 | 372 | writel_relaxed(l, reg); |
4318f36b | 373 | } |
5e571f38 | 374 | #else |
a0e827c6 | 375 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
9198bcd3 | 376 | #endif |
4318f36b | 377 | |
a0e827c6 JMC |
378 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
379 | unsigned trigger) | |
92105bb7 TL |
380 | { |
381 | void __iomem *reg = bank->base; | |
5e571f38 | 382 | void __iomem *base = bank->base; |
92105bb7 | 383 | u32 l = 0; |
5e1c5ff4 | 384 | |
5e571f38 | 385 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 386 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
387 | } else if (bank->regs->irqctrl) { |
388 | reg += bank->regs->irqctrl; | |
389 | ||
661553b9 | 390 | l = readl_relaxed(reg); |
29501577 | 391 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 392 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 393 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 394 | l |= BIT(gpio); |
6cab4860 | 395 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 396 | l &= ~(BIT(gpio)); |
92105bb7 | 397 | else |
5e571f38 TKD |
398 | return -EINVAL; |
399 | ||
661553b9 | 400 | writel_relaxed(l, reg); |
5e571f38 | 401 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 402 | if (gpio & 0x08) |
5e571f38 | 403 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 404 | else |
5e571f38 TKD |
405 | reg += bank->regs->edgectrl1; |
406 | ||
5e1c5ff4 | 407 | gpio &= 0x07; |
661553b9 | 408 | l = readl_relaxed(reg); |
5e1c5ff4 | 409 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 410 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 411 | l |= 2 << (gpio << 1); |
6cab4860 | 412 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 413 | l |= BIT(gpio << 1); |
5e571f38 TKD |
414 | |
415 | /* Enable wake-up during idle for dynamic tick */ | |
a0e827c6 | 416 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 417 | bank->context.wake_en = |
661553b9 VK |
418 | readl_relaxed(bank->base + bank->regs->wkup_en); |
419 | writel_relaxed(l, reg); | |
5e1c5ff4 | 420 | } |
92105bb7 | 421 | return 0; |
5e1c5ff4 TL |
422 | } |
423 | ||
a0e827c6 | 424 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
425 | { |
426 | if (bank->regs->pinctrl) { | |
427 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
428 | ||
429 | /* Claim the pin for MPU */ | |
b1e9fec2 | 430 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
431 | } |
432 | ||
433 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
434 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
435 | u32 ctrl; | |
436 | ||
661553b9 | 437 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
438 | /* Module is enabled, clocks are not gated */ |
439 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 440 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
441 | bank->context.ctrl = ctrl; |
442 | } | |
443 | } | |
444 | ||
a0e827c6 | 445 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
446 | { |
447 | void __iomem *base = bank->base; | |
448 | ||
449 | if (bank->regs->wkup_en && | |
450 | !LINE_USED(bank->mod_usage, offset) && | |
451 | !LINE_USED(bank->irq_usage, offset)) { | |
452 | /* Disable wake-up during idle for dynamic tick */ | |
a0e827c6 | 453 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 454 | bank->context.wake_en = |
661553b9 | 455 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
456 | } |
457 | ||
458 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
459 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
460 | u32 ctrl; | |
461 | ||
661553b9 | 462 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
463 | /* Module is disabled, clocks are gated */ |
464 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 465 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
466 | bank->context.ctrl = ctrl; |
467 | } | |
468 | } | |
469 | ||
b2b20045 | 470 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
471 | { |
472 | void __iomem *reg = bank->base + bank->regs->direction; | |
473 | ||
b2b20045 | 474 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
475 | } |
476 | ||
37e14ecf | 477 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
478 | { |
479 | if (!LINE_USED(bank->mod_usage, offset)) { | |
480 | omap_enable_gpio_module(bank, offset); | |
481 | omap_set_gpio_direction(bank, offset, 1); | |
482 | } | |
37e14ecf | 483 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
484 | } |
485 | ||
a0e827c6 | 486 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 487 | { |
a0e827c6 | 488 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 489 | int retval; |
a6472533 | 490 | unsigned long flags; |
ea5fbe8d | 491 | unsigned offset = d->hwirq; |
92105bb7 | 492 | |
e5c56ed3 | 493 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 494 | return -EINVAL; |
e5c56ed3 | 495 | |
9ea14d8c TKD |
496 | if (!bank->regs->leveldetect0 && |
497 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
498 | return -EINVAL; |
499 | ||
4dbada2b | 500 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 501 | retval = omap_set_gpio_triggering(bank, offset, type); |
977bd8a9 | 502 | if (retval) { |
627c89b4 | 503 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 | 504 | goto error; |
977bd8a9 | 505 | } |
37e14ecf | 506 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 507 | if (!omap_gpio_is_input(bank, offset)) { |
4dbada2b | 508 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 GS |
509 | retval = -EINVAL; |
510 | goto error; | |
fac7fa16 | 511 | } |
4dbada2b | 512 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
513 | |
514 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
43ec2e43 | 515 | irq_set_handler_locked(d, handle_level_irq); |
672e302e | 516 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
43ec2e43 | 517 | irq_set_handler_locked(d, handle_edge_irq); |
672e302e | 518 | |
1562e461 GS |
519 | return 0; |
520 | ||
521 | error: | |
92105bb7 | 522 | return retval; |
5e1c5ff4 TL |
523 | } |
524 | ||
a0e827c6 | 525 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 526 | { |
92105bb7 | 527 | void __iomem *reg = bank->base; |
5e1c5ff4 | 528 | |
eef4bec7 | 529 | reg += bank->regs->irqstatus; |
661553b9 | 530 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
531 | |
532 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
533 | if (bank->regs->irqstatus2) { |
534 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 535 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 536 | } |
bedfd154 RQ |
537 | |
538 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 539 | readl_relaxed(reg); |
5e1c5ff4 TL |
540 | } |
541 | ||
9943f261 GS |
542 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
543 | unsigned offset) | |
5e1c5ff4 | 544 | { |
9943f261 | 545 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
546 | } |
547 | ||
a0e827c6 | 548 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
549 | { |
550 | void __iomem *reg = bank->base; | |
99c47707 | 551 | u32 l; |
b1e9fec2 | 552 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 553 | |
28f3b5a0 | 554 | reg += bank->regs->irqenable; |
661553b9 | 555 | l = readl_relaxed(reg); |
28f3b5a0 | 556 | if (bank->regs->irqenable_inv) |
99c47707 ID |
557 | l = ~l; |
558 | l &= mask; | |
559 | return l; | |
ea6dedd7 ID |
560 | } |
561 | ||
a0e827c6 | 562 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 563 | { |
92105bb7 | 564 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
565 | u32 l; |
566 | ||
28f3b5a0 KH |
567 | if (bank->regs->set_irqenable) { |
568 | reg += bank->regs->set_irqenable; | |
569 | l = gpio_mask; | |
2a900eb7 | 570 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
571 | } else { |
572 | reg += bank->regs->irqenable; | |
661553b9 | 573 | l = readl_relaxed(reg); |
28f3b5a0 KH |
574 | if (bank->regs->irqenable_inv) |
575 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
576 | else |
577 | l |= gpio_mask; | |
2a900eb7 | 578 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
579 | } |
580 | ||
661553b9 | 581 | writel_relaxed(l, reg); |
28f3b5a0 KH |
582 | } |
583 | ||
a0e827c6 | 584 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
28f3b5a0 KH |
585 | { |
586 | void __iomem *reg = bank->base; | |
587 | u32 l; | |
588 | ||
589 | if (bank->regs->clr_irqenable) { | |
590 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 591 | l = gpio_mask; |
2a900eb7 | 592 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
593 | } else { |
594 | reg += bank->regs->irqenable; | |
661553b9 | 595 | l = readl_relaxed(reg); |
28f3b5a0 | 596 | if (bank->regs->irqenable_inv) |
56739a69 | 597 | l |= gpio_mask; |
92105bb7 | 598 | else |
28f3b5a0 | 599 | l &= ~gpio_mask; |
2a900eb7 | 600 | bank->context.irqenable1 = l; |
5e1c5ff4 | 601 | } |
28f3b5a0 | 602 | |
661553b9 | 603 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
604 | } |
605 | ||
9943f261 GS |
606 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
607 | unsigned offset, int enable) | |
5e1c5ff4 | 608 | { |
8276536c | 609 | if (enable) |
9943f261 | 610 | omap_enable_gpio_irqbank(bank, BIT(offset)); |
8276536c | 611 | else |
9943f261 | 612 | omap_disable_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
613 | } |
614 | ||
92105bb7 TL |
615 | /* |
616 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
617 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
618 | * to the target, system will wake up always on GPIO events. While | |
619 | * system is running all registered GPIO interrupts need to have wake-up | |
620 | * enabled. When system is suspended, only selected GPIO interrupts need | |
621 | * to have wake-up enabled. | |
622 | */ | |
9943f261 GS |
623 | static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset, |
624 | int enable) | |
92105bb7 | 625 | { |
9943f261 | 626 | u32 gpio_bit = BIT(offset); |
f64ad1a0 | 627 | unsigned long flags; |
a6472533 | 628 | |
f64ad1a0 | 629 | if (bank->non_wakeup_gpios & gpio_bit) { |
862ff640 | 630 | dev_err(bank->dev, |
9943f261 GS |
631 | "Unable to modify wakeup on non-wakeup GPIO%d\n", |
632 | offset); | |
92105bb7 TL |
633 | return -EINVAL; |
634 | } | |
f64ad1a0 | 635 | |
4dbada2b | 636 | raw_spin_lock_irqsave(&bank->lock, flags); |
f64ad1a0 | 637 | if (enable) |
0aa27273 | 638 | bank->context.wake_en |= gpio_bit; |
f64ad1a0 | 639 | else |
0aa27273 | 640 | bank->context.wake_en &= ~gpio_bit; |
f64ad1a0 | 641 | |
661553b9 | 642 | writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en); |
4dbada2b | 643 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
f64ad1a0 KH |
644 | |
645 | return 0; | |
92105bb7 TL |
646 | } |
647 | ||
648 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ | |
a0e827c6 | 649 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 650 | { |
a0e827c6 | 651 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 652 | unsigned offset = d->hwirq; |
450fa54c GS |
653 | int ret; |
654 | ||
655 | ret = omap_set_gpio_wakeup(bank, offset, enable); | |
656 | if (!ret) | |
657 | ret = irq_set_irq_wake(bank->irq, enable); | |
92105bb7 | 658 | |
450fa54c | 659 | return ret; |
92105bb7 TL |
660 | } |
661 | ||
3ff164e1 | 662 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 663 | { |
3ff164e1 | 664 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 665 | unsigned long flags; |
52e31344 | 666 | |
55b93c32 TKD |
667 | /* |
668 | * If this is the first gpio_request for the bank, | |
669 | * enable the bank module. | |
670 | */ | |
fa365e4d | 671 | if (!BANK_USED(bank)) |
55b93c32 | 672 | pm_runtime_get_sync(bank->dev); |
92105bb7 | 673 | |
4dbada2b | 674 | raw_spin_lock_irqsave(&bank->lock, flags); |
c3518172 | 675 | omap_enable_gpio_module(bank, offset); |
b1e9fec2 | 676 | bank->mod_usage |= BIT(offset); |
4dbada2b | 677 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
678 | |
679 | return 0; | |
680 | } | |
681 | ||
3ff164e1 | 682 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 683 | { |
3ff164e1 | 684 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 685 | unsigned long flags; |
5e1c5ff4 | 686 | |
4dbada2b | 687 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 688 | bank->mod_usage &= ~(BIT(offset)); |
5f982c70 GS |
689 | if (!LINE_USED(bank->irq_usage, offset)) { |
690 | omap_set_gpio_direction(bank, offset, 1); | |
691 | omap_clear_gpio_debounce(bank, offset); | |
692 | } | |
a0e827c6 | 693 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 694 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
695 | |
696 | /* | |
697 | * If this is the last gpio to be freed in the bank, | |
698 | * disable the bank module. | |
699 | */ | |
fa365e4d | 700 | if (!BANK_USED(bank)) |
55b93c32 | 701 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
702 | } |
703 | ||
704 | /* | |
705 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
706 | * avoid missing GPIO interrupts for other lines in the bank. | |
707 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
708 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
709 | * If we wait to unmask individual GPIO lines in the bank after the | |
710 | * line's interrupt handler has been run, we may miss some nested | |
711 | * interrupts. | |
712 | */ | |
450fa54c | 713 | static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) |
5e1c5ff4 | 714 | { |
92105bb7 | 715 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 716 | u32 isr; |
3513cdec | 717 | unsigned int bit; |
450fa54c GS |
718 | struct gpio_bank *bank = gpiobank; |
719 | unsigned long wa_lock_flags; | |
235f1eb1 | 720 | unsigned long lock_flags; |
5e1c5ff4 | 721 | |
eef4bec7 | 722 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
723 | if (WARN_ON(!isr_reg)) |
724 | goto exit; | |
725 | ||
450fa54c GS |
726 | pm_runtime_get_sync(bank->dev); |
727 | ||
e83507b7 | 728 | while (1) { |
6e60e79a | 729 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 730 | u32 enabled; |
6e60e79a | 731 | |
235f1eb1 GS |
732 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
733 | ||
a0e827c6 | 734 | enabled = omap_get_gpio_irqbank_mask(bank); |
661553b9 | 735 | isr_saved = isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 736 | |
9ea14d8c | 737 | if (bank->level_mask) |
b144ff6f | 738 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
739 | |
740 | /* clear edge sensitive interrupts before handler(s) are | |
741 | called so that we don't miss any interrupt occurred while | |
742 | executing them */ | |
a0e827c6 JMC |
743 | omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
744 | omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
745 | omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask); | |
6e60e79a | 746 | |
235f1eb1 GS |
747 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
748 | ||
92105bb7 TL |
749 | if (!isr) |
750 | break; | |
751 | ||
3513cdec JH |
752 | while (isr) { |
753 | bit = __ffs(isr); | |
b1e9fec2 | 754 | isr &= ~(BIT(bit)); |
25db711d | 755 | |
235f1eb1 | 756 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
4318f36b CM |
757 | /* |
758 | * Some chips can't respond to both rising and falling | |
759 | * at the same time. If this irq was requested with | |
760 | * both flags, we need to flip the ICR data for the IRQ | |
761 | * to respond to the IRQ for the opposite direction. | |
762 | * This will be indicated in the bank toggle_mask. | |
763 | */ | |
b1e9fec2 | 764 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 765 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 766 | |
235f1eb1 GS |
767 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
768 | ||
450fa54c GS |
769 | raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); |
770 | ||
fb655f57 JMC |
771 | generic_handle_irq(irq_find_mapping(bank->chip.irqdomain, |
772 | bit)); | |
450fa54c GS |
773 | |
774 | raw_spin_unlock_irqrestore(&bank->wa_lock, | |
775 | wa_lock_flags); | |
92105bb7 | 776 | } |
1a8bfa1e | 777 | } |
b1cc4c55 | 778 | exit: |
55b93c32 | 779 | pm_runtime_put(bank->dev); |
450fa54c | 780 | return IRQ_HANDLED; |
5e1c5ff4 TL |
781 | } |
782 | ||
3d009c8c TL |
783 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
784 | { | |
785 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 786 | unsigned long flags; |
37e14ecf | 787 | unsigned offset = d->hwirq; |
3d009c8c | 788 | |
4dbada2b | 789 | raw_spin_lock_irqsave(&bank->lock, flags); |
121dcb76 GS |
790 | |
791 | if (!LINE_USED(bank->mod_usage, offset)) | |
792 | omap_set_gpio_direction(bank, offset, 1); | |
793 | else if (!omap_gpio_is_input(bank, offset)) | |
794 | goto err; | |
795 | omap_enable_gpio_module(bank, offset); | |
796 | bank->irq_usage |= BIT(offset); | |
797 | ||
4dbada2b | 798 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
3d009c8c TL |
799 | omap_gpio_unmask_irq(d); |
800 | ||
801 | return 0; | |
121dcb76 | 802 | err: |
4dbada2b | 803 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
121dcb76 | 804 | return -EINVAL; |
3d009c8c TL |
805 | } |
806 | ||
a0e827c6 | 807 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 808 | { |
a0e827c6 | 809 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 810 | unsigned long flags; |
9943f261 | 811 | unsigned offset = d->hwirq; |
4196dd6b | 812 | |
4dbada2b | 813 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 814 | bank->irq_usage &= ~(BIT(offset)); |
6e96c1b5 GS |
815 | omap_set_gpio_irqenable(bank, offset, 0); |
816 | omap_clear_gpio_irqstatus(bank, offset); | |
817 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
818 | if (!LINE_USED(bank->mod_usage, offset)) | |
819 | omap_clear_gpio_debounce(bank, offset); | |
a0e827c6 | 820 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 821 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
aca82d1c GS |
822 | } |
823 | ||
824 | static void omap_gpio_irq_bus_lock(struct irq_data *data) | |
825 | { | |
826 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
827 | ||
828 | if (!BANK_USED(bank)) | |
829 | pm_runtime_get_sync(bank->dev); | |
830 | } | |
831 | ||
832 | static void gpio_irq_bus_sync_unlock(struct irq_data *data) | |
833 | { | |
834 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
fac7fa16 JMC |
835 | |
836 | /* | |
837 | * If this is the last IRQ to be freed in the bank, | |
838 | * disable the bank module. | |
839 | */ | |
840 | if (!BANK_USED(bank)) | |
841 | pm_runtime_put(bank->dev); | |
4196dd6b TL |
842 | } |
843 | ||
a0e827c6 | 844 | static void omap_gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 845 | { |
a0e827c6 | 846 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 847 | unsigned offset = d->hwirq; |
5e1c5ff4 | 848 | |
9943f261 | 849 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 TL |
850 | } |
851 | ||
a0e827c6 | 852 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 853 | { |
a0e827c6 | 854 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 855 | unsigned offset = d->hwirq; |
85ec7b97 | 856 | unsigned long flags; |
5e1c5ff4 | 857 | |
4dbada2b | 858 | raw_spin_lock_irqsave(&bank->lock, flags); |
9943f261 GS |
859 | omap_set_gpio_irqenable(bank, offset, 0); |
860 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
4dbada2b | 861 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
862 | } |
863 | ||
a0e827c6 | 864 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 865 | { |
a0e827c6 | 866 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 867 | unsigned offset = d->hwirq; |
8c04a176 | 868 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 869 | unsigned long flags; |
55b6019a | 870 | |
4dbada2b | 871 | raw_spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 872 | if (trigger) |
9943f261 | 873 | omap_set_gpio_triggering(bank, offset, trigger); |
b144ff6f KH |
874 | |
875 | /* For level-triggered GPIOs, the clearing must be done after | |
876 | * the HW source is cleared, thus after the handler has run */ | |
9943f261 GS |
877 | if (bank->level_mask & BIT(offset)) { |
878 | omap_set_gpio_irqenable(bank, offset, 0); | |
879 | omap_clear_gpio_irqstatus(bank, offset); | |
b144ff6f | 880 | } |
5e1c5ff4 | 881 | |
9943f261 | 882 | omap_set_gpio_irqenable(bank, offset, 1); |
4dbada2b | 883 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
884 | } |
885 | ||
e5c56ed3 DB |
886 | /*---------------------------------------------------------------------*/ |
887 | ||
79ee031f | 888 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 889 | { |
79ee031f | 890 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 891 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
892 | void __iomem *mask_reg = bank->base + |
893 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 894 | unsigned long flags; |
11a78b79 | 895 | |
4dbada2b | 896 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 897 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
4dbada2b | 898 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
899 | |
900 | return 0; | |
901 | } | |
902 | ||
79ee031f | 903 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 904 | { |
79ee031f | 905 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 906 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
907 | void __iomem *mask_reg = bank->base + |
908 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 909 | unsigned long flags; |
11a78b79 | 910 | |
4dbada2b | 911 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 912 | writel_relaxed(bank->context.wake_en, mask_reg); |
4dbada2b | 913 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
914 | |
915 | return 0; | |
916 | } | |
917 | ||
47145210 | 918 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
919 | .suspend_noirq = omap_mpuio_suspend_noirq, |
920 | .resume_noirq = omap_mpuio_resume_noirq, | |
921 | }; | |
922 | ||
3c437ffd | 923 | /* use platform_driver for this. */ |
11a78b79 | 924 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
925 | .driver = { |
926 | .name = "mpuio", | |
79ee031f | 927 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
928 | }, |
929 | }; | |
930 | ||
931 | static struct platform_device omap_mpuio_device = { | |
932 | .name = "mpuio", | |
933 | .id = -1, | |
934 | .dev = { | |
935 | .driver = &omap_mpuio_driver.driver, | |
936 | } | |
937 | /* could list the /proc/iomem resources */ | |
938 | }; | |
939 | ||
a0e827c6 | 940 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 941 | { |
77640aab | 942 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 943 | |
11a78b79 DB |
944 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
945 | (void) platform_device_register(&omap_mpuio_device); | |
946 | } | |
947 | ||
e5c56ed3 | 948 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 949 | |
a0e827c6 | 950 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e YY |
951 | { |
952 | struct gpio_bank *bank; | |
953 | unsigned long flags; | |
954 | void __iomem *reg; | |
955 | int dir; | |
956 | ||
957 | bank = container_of(chip, struct gpio_bank, chip); | |
958 | reg = bank->base + bank->regs->direction; | |
4dbada2b | 959 | raw_spin_lock_irqsave(&bank->lock, flags); |
9370084e | 960 | dir = !!(readl_relaxed(reg) & BIT(offset)); |
4dbada2b | 961 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
9370084e YY |
962 | return dir; |
963 | } | |
964 | ||
a0e827c6 | 965 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
966 | { |
967 | struct gpio_bank *bank; | |
968 | unsigned long flags; | |
969 | ||
970 | bank = container_of(chip, struct gpio_bank, chip); | |
4dbada2b | 971 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 972 | omap_set_gpio_direction(bank, offset, 1); |
4dbada2b | 973 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
974 | return 0; |
975 | } | |
976 | ||
a0e827c6 | 977 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 978 | { |
b37c45b8 | 979 | struct gpio_bank *bank; |
b37c45b8 | 980 | |
a8be8daf | 981 | bank = container_of(chip, struct gpio_bank, chip); |
b37c45b8 | 982 | |
b2b20045 | 983 | if (omap_gpio_is_input(bank, offset)) |
a0e827c6 | 984 | return omap_get_gpio_datain(bank, offset); |
b37c45b8 | 985 | else |
a0e827c6 | 986 | return omap_get_gpio_dataout(bank, offset); |
52e31344 DB |
987 | } |
988 | ||
a0e827c6 | 989 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
990 | { |
991 | struct gpio_bank *bank; | |
992 | unsigned long flags; | |
993 | ||
994 | bank = container_of(chip, struct gpio_bank, chip); | |
4dbada2b | 995 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 996 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 997 | omap_set_gpio_direction(bank, offset, 0); |
4dbada2b | 998 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 999 | return 0; |
52e31344 DB |
1000 | } |
1001 | ||
a0e827c6 JMC |
1002 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1003 | unsigned debounce) | |
168ef3d9 FB |
1004 | { |
1005 | struct gpio_bank *bank; | |
1006 | unsigned long flags; | |
1007 | ||
1008 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab | 1009 | |
4dbada2b | 1010 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 1011 | omap2_set_gpio_debounce(bank, offset, debounce); |
4dbada2b | 1012 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
168ef3d9 FB |
1013 | |
1014 | return 0; | |
1015 | } | |
1016 | ||
a0e827c6 | 1017 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
1018 | { |
1019 | struct gpio_bank *bank; | |
1020 | unsigned long flags; | |
1021 | ||
1022 | bank = container_of(chip, struct gpio_bank, chip); | |
4dbada2b | 1023 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 1024 | bank->set_dataout(bank, offset, value); |
4dbada2b | 1025 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
1026 | } |
1027 | ||
1028 | /*---------------------------------------------------------------------*/ | |
1029 | ||
9a748053 | 1030 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1031 | { |
e5ff4440 | 1032 | static bool called; |
9f7065da TL |
1033 | u32 rev; |
1034 | ||
e5ff4440 | 1035 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1036 | return; |
1037 | ||
661553b9 | 1038 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1039 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1040 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1041 | |
1042 | called = true; | |
9f7065da TL |
1043 | } |
1044 | ||
03e128ca | 1045 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1046 | { |
ab985f0f TKD |
1047 | void __iomem *base = bank->base; |
1048 | u32 l = 0xffffffff; | |
2fae7fbe | 1049 | |
ab985f0f TKD |
1050 | if (bank->width == 16) |
1051 | l = 0xffff; | |
1052 | ||
d0d665a8 | 1053 | if (bank->is_mpuio) { |
661553b9 | 1054 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1055 | return; |
2fae7fbe | 1056 | } |
ab985f0f | 1057 | |
a0e827c6 JMC |
1058 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1059 | bank->regs->irqenable_inv); | |
1060 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | |
1061 | !bank->regs->irqenable_inv); | |
ab985f0f | 1062 | if (bank->regs->debounce_en) |
661553b9 | 1063 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1064 | |
2dc983c5 | 1065 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1066 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1067 | /* Initialize interface clk ungated, module enabled */ |
1068 | if (bank->regs->ctrl) | |
661553b9 | 1069 | writel_relaxed(0, base + bank->regs->ctrl); |
2fae7fbe VC |
1070 | } |
1071 | ||
46824e22 | 1072 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 1073 | { |
2fae7fbe | 1074 | static int gpio; |
fb655f57 | 1075 | int irq_base = 0; |
6ef7f385 | 1076 | int ret; |
2fae7fbe | 1077 | |
2fae7fbe VC |
1078 | /* |
1079 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1080 | * over to the generic ones | |
1081 | */ | |
1082 | bank->chip.request = omap_gpio_request; | |
1083 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1084 | bank->chip.get_direction = omap_gpio_get_direction; |
1085 | bank->chip.direction_input = omap_gpio_input; | |
1086 | bank->chip.get = omap_gpio_get; | |
1087 | bank->chip.direction_output = omap_gpio_output; | |
1088 | bank->chip.set_debounce = omap_gpio_debounce; | |
1089 | bank->chip.set = omap_gpio_set; | |
d0d665a8 | 1090 | if (bank->is_mpuio) { |
2fae7fbe | 1091 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
1092 | if (bank->regs->wkup_en) |
1093 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
1094 | bank->chip.base = OMAP_MPUIO(0); |
1095 | } else { | |
1096 | bank->chip.label = "gpio"; | |
1097 | bank->chip.base = gpio; | |
2fae7fbe | 1098 | } |
d5f46247 | 1099 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1100 | |
6ef7f385 JMC |
1101 | ret = gpiochip_add(&bank->chip); |
1102 | if (ret) { | |
fb655f57 | 1103 | dev_err(bank->dev, "Could not register gpio chip %d\n", ret); |
6ef7f385 JMC |
1104 | return ret; |
1105 | } | |
2fae7fbe | 1106 | |
46d4f7c2 TL |
1107 | if (!bank->is_mpuio) |
1108 | gpio += bank->width; | |
1109 | ||
fb655f57 JMC |
1110 | #ifdef CONFIG_ARCH_OMAP1 |
1111 | /* | |
1112 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1113 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1114 | */ | |
1115 | irq_base = irq_alloc_descs(-1, 0, bank->width, 0); | |
1116 | if (irq_base < 0) { | |
1117 | dev_err(bank->dev, "Couldn't allocate IRQ numbers\n"); | |
1118 | return -ENODEV; | |
1119 | } | |
1120 | #endif | |
1121 | ||
d2d05c65 TL |
1122 | /* MPUIO is a bit different, reading IRQ status clears it */ |
1123 | if (bank->is_mpuio) { | |
1124 | irqc->irq_ack = dummy_irq_chip.irq_ack; | |
1125 | irqc->irq_mask = irq_gc_mask_set_bit; | |
1126 | irqc->irq_unmask = irq_gc_mask_clr_bit; | |
1127 | if (!bank->regs->wkup_en) | |
1128 | irqc->irq_set_wake = NULL; | |
1129 | } | |
1130 | ||
46824e22 | 1131 | ret = gpiochip_irqchip_add(&bank->chip, irqc, |
450fa54c | 1132 | irq_base, handle_bad_irq, |
fb655f57 JMC |
1133 | IRQ_TYPE_NONE); |
1134 | ||
1135 | if (ret) { | |
1136 | dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret); | |
da26d5d8 | 1137 | gpiochip_remove(&bank->chip); |
fb655f57 JMC |
1138 | return -ENODEV; |
1139 | } | |
1140 | ||
450fa54c | 1141 | gpiochip_set_chained_irqchip(&bank->chip, irqc, bank->irq, NULL); |
fb655f57 | 1142 | |
450fa54c GS |
1143 | ret = devm_request_irq(bank->dev, bank->irq, omap_gpio_irq_handler, |
1144 | 0, dev_name(bank->dev), bank); | |
1145 | if (ret) | |
1146 | gpiochip_remove(&bank->chip); | |
1147 | ||
1148 | return ret; | |
2fae7fbe VC |
1149 | } |
1150 | ||
384ebe1c BC |
1151 | static const struct of_device_id omap_gpio_match[]; |
1152 | ||
3836309d | 1153 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1154 | { |
862ff640 | 1155 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1156 | struct device_node *node = dev->of_node; |
1157 | const struct of_device_id *match; | |
f6817a2c | 1158 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1159 | struct resource *res; |
5e1c5ff4 | 1160 | struct gpio_bank *bank; |
46824e22 | 1161 | struct irq_chip *irqc; |
6ef7f385 | 1162 | int ret; |
5e1c5ff4 | 1163 | |
384ebe1c BC |
1164 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1165 | ||
e56aee18 | 1166 | pdata = match ? match->data : dev_get_platdata(dev); |
384ebe1c | 1167 | if (!pdata) |
96751fcb | 1168 | return -EINVAL; |
5492fb1a | 1169 | |
086d585f | 1170 | bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL); |
03e128ca | 1171 | if (!bank) { |
862ff640 | 1172 | dev_err(dev, "Memory alloc failed\n"); |
96751fcb | 1173 | return -ENOMEM; |
03e128ca | 1174 | } |
92105bb7 | 1175 | |
46824e22 NM |
1176 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); |
1177 | if (!irqc) | |
1178 | return -ENOMEM; | |
1179 | ||
3d009c8c | 1180 | irqc->irq_startup = omap_gpio_irq_startup, |
46824e22 NM |
1181 | irqc->irq_shutdown = omap_gpio_irq_shutdown, |
1182 | irqc->irq_ack = omap_gpio_ack_irq, | |
1183 | irqc->irq_mask = omap_gpio_mask_irq, | |
1184 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1185 | irqc->irq_set_type = omap_gpio_irq_type, | |
1186 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
aca82d1c GS |
1187 | irqc->irq_bus_lock = omap_gpio_irq_bus_lock, |
1188 | irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, | |
46824e22 NM |
1189 | irqc->name = dev_name(&pdev->dev); |
1190 | ||
89d18e3a GS |
1191 | bank->irq = platform_get_irq(pdev, 0); |
1192 | if (bank->irq <= 0) { | |
1193 | if (!bank->irq) | |
1194 | bank->irq = -ENXIO; | |
1195 | if (bank->irq != -EPROBE_DEFER) | |
1196 | dev_err(dev, | |
1197 | "can't get irq resource ret=%d\n", bank->irq); | |
1198 | return bank->irq; | |
44169075 | 1199 | } |
5e1c5ff4 | 1200 | |
862ff640 | 1201 | bank->dev = dev; |
fb655f57 | 1202 | bank->chip.dev = dev; |
c23837ce | 1203 | bank->chip.owner = THIS_MODULE; |
77640aab | 1204 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1205 | bank->stride = pdata->bank_stride; |
d5f46247 | 1206 | bank->width = pdata->bank_width; |
d0d665a8 | 1207 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1208 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1209 | bank->regs = pdata->regs; |
384ebe1c BC |
1210 | #ifdef CONFIG_OF_GPIO |
1211 | bank->chip.of_node = of_node_get(node); | |
1212 | #endif | |
a2797bea JH |
1213 | if (node) { |
1214 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1215 | bank->loses_context = true; | |
1216 | } else { | |
1217 | bank->loses_context = pdata->loses_context; | |
352a2d5b JH |
1218 | |
1219 | if (bank->loses_context) | |
1220 | bank->get_context_loss_count = | |
1221 | pdata->get_context_loss_count; | |
384ebe1c BC |
1222 | } |
1223 | ||
fa87931a | 1224 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
a0e827c6 | 1225 | bank->set_dataout = omap_set_gpio_dataout_reg; |
fa87931a | 1226 | else |
a0e827c6 | 1227 | bank->set_dataout = omap_set_gpio_dataout_mask; |
9f7065da | 1228 | |
4dbada2b | 1229 | raw_spin_lock_init(&bank->lock); |
450fa54c | 1230 | raw_spin_lock_init(&bank->wa_lock); |
9f7065da | 1231 | |
77640aab VC |
1232 | /* Static mapping, never released */ |
1233 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
717f70e3 JH |
1234 | bank->base = devm_ioremap_resource(dev, res); |
1235 | if (IS_ERR(bank->base)) { | |
717f70e3 | 1236 | return PTR_ERR(bank->base); |
5e1c5ff4 TL |
1237 | } |
1238 | ||
5d9452e7 GS |
1239 | if (bank->dbck_flag) { |
1240 | bank->dbck = devm_clk_get(bank->dev, "dbclk"); | |
1241 | if (IS_ERR(bank->dbck)) { | |
1242 | dev_err(bank->dev, | |
1243 | "Could not get gpio dbck. Disable debounce\n"); | |
1244 | bank->dbck_flag = false; | |
1245 | } else { | |
1246 | clk_prepare(bank->dbck); | |
1247 | } | |
1248 | } | |
1249 | ||
065cd795 TKD |
1250 | platform_set_drvdata(pdev, bank); |
1251 | ||
77640aab | 1252 | pm_runtime_enable(bank->dev); |
55b93c32 | 1253 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1254 | pm_runtime_get_sync(bank->dev); |
1255 | ||
d0d665a8 | 1256 | if (bank->is_mpuio) |
a0e827c6 | 1257 | omap_mpuio_init(bank); |
ab985f0f | 1258 | |
03e128ca | 1259 | omap_gpio_mod_init(bank); |
6ef7f385 | 1260 | |
46824e22 | 1261 | ret = omap_gpio_chip_init(bank, irqc); |
5e606abe TL |
1262 | if (ret) { |
1263 | pm_runtime_put_sync(bank->dev); | |
1264 | pm_runtime_disable(bank->dev); | |
6ef7f385 | 1265 | return ret; |
5e606abe | 1266 | } |
6ef7f385 | 1267 | |
9a748053 | 1268 | omap_gpio_show_rev(bank); |
9f7065da | 1269 | |
55b93c32 TKD |
1270 | pm_runtime_put(bank->dev); |
1271 | ||
03e128ca | 1272 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1273 | |
879fe324 | 1274 | return 0; |
5e1c5ff4 TL |
1275 | } |
1276 | ||
cac089f9 TL |
1277 | static int omap_gpio_remove(struct platform_device *pdev) |
1278 | { | |
1279 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1280 | ||
1281 | list_del(&bank->node); | |
1282 | gpiochip_remove(&bank->chip); | |
1283 | pm_runtime_disable(bank->dev); | |
5d9452e7 GS |
1284 | if (bank->dbck_flag) |
1285 | clk_unprepare(bank->dbck); | |
cac089f9 TL |
1286 | |
1287 | return 0; | |
1288 | } | |
1289 | ||
55b93c32 TKD |
1290 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1291 | ||
ecb2312f | 1292 | #if defined(CONFIG_PM) |
60a3437d | 1293 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1294 | |
2dc983c5 | 1295 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1296 | { |
2dc983c5 TKD |
1297 | struct platform_device *pdev = to_platform_device(dev); |
1298 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1299 | u32 l1 = 0, l2 = 0; | |
1300 | unsigned long flags; | |
68942edb | 1301 | u32 wake_low, wake_hi; |
8865b9b6 | 1302 | |
4dbada2b | 1303 | raw_spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1304 | |
1305 | /* | |
1306 | * Only edges can generate a wakeup event to the PRCM. | |
1307 | * | |
1308 | * Therefore, ensure any wake-up capable GPIOs have | |
1309 | * edge-detection enabled before going idle to ensure a wakeup | |
1310 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1311 | * NDA TRM 25.5.3.1) | |
1312 | * | |
1313 | * The normal values will be restored upon ->runtime_resume() | |
1314 | * by writing back the values saved in bank->context. | |
1315 | */ | |
1316 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1317 | if (wake_low) | |
661553b9 | 1318 | writel_relaxed(wake_low | bank->context.fallingdetect, |
68942edb KH |
1319 | bank->base + bank->regs->fallingdetect); |
1320 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1321 | if (wake_hi) | |
661553b9 | 1322 | writel_relaxed(wake_hi | bank->context.risingdetect, |
68942edb KH |
1323 | bank->base + bank->regs->risingdetect); |
1324 | ||
b3c64bc3 KH |
1325 | if (!bank->enabled_non_wakeup_gpios) |
1326 | goto update_gpio_context_count; | |
1327 | ||
2dc983c5 TKD |
1328 | if (bank->power_mode != OFF_MODE) { |
1329 | bank->power_mode = 0; | |
41d87cbd | 1330 | goto update_gpio_context_count; |
2dc983c5 TKD |
1331 | } |
1332 | /* | |
1333 | * If going to OFF, remove triggering for all | |
1334 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1335 | * generated. See OMAP2420 Errata item 1.101. | |
1336 | */ | |
661553b9 | 1337 | bank->saved_datain = readl_relaxed(bank->base + |
2dc983c5 | 1338 | bank->regs->datain); |
c6f31c9e TKD |
1339 | l1 = bank->context.fallingdetect; |
1340 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1341 | |
2dc983c5 TKD |
1342 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1343 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1344 | |
661553b9 VK |
1345 | writel_relaxed(l1, bank->base + bank->regs->fallingdetect); |
1346 | writel_relaxed(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1347 | |
2dc983c5 | 1348 | bank->workaround_enabled = true; |
3f1686a9 | 1349 | |
41d87cbd | 1350 | update_gpio_context_count: |
2dc983c5 TKD |
1351 | if (bank->get_context_loss_count) |
1352 | bank->context_loss_count = | |
60a3437d TKD |
1353 | bank->get_context_loss_count(bank->dev); |
1354 | ||
a0e827c6 | 1355 | omap_gpio_dbck_disable(bank); |
4dbada2b | 1356 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1357 | |
2dc983c5 | 1358 | return 0; |
3ac4fa99 JY |
1359 | } |
1360 | ||
352a2d5b JH |
1361 | static void omap_gpio_init_context(struct gpio_bank *p); |
1362 | ||
2dc983c5 | 1363 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1364 | { |
2dc983c5 TKD |
1365 | struct platform_device *pdev = to_platform_device(dev); |
1366 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
2dc983c5 TKD |
1367 | u32 l = 0, gen, gen0, gen1; |
1368 | unsigned long flags; | |
a2797bea | 1369 | int c; |
8865b9b6 | 1370 | |
4dbada2b | 1371 | raw_spin_lock_irqsave(&bank->lock, flags); |
352a2d5b JH |
1372 | |
1373 | /* | |
1374 | * On the first resume during the probe, the context has not | |
1375 | * been initialised and so initialise it now. Also initialise | |
1376 | * the context loss count. | |
1377 | */ | |
1378 | if (bank->loses_context && !bank->context_valid) { | |
1379 | omap_gpio_init_context(bank); | |
1380 | ||
1381 | if (bank->get_context_loss_count) | |
1382 | bank->context_loss_count = | |
1383 | bank->get_context_loss_count(bank->dev); | |
1384 | } | |
1385 | ||
a0e827c6 | 1386 | omap_gpio_dbck_enable(bank); |
68942edb KH |
1387 | |
1388 | /* | |
1389 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1390 | * GPIOs were set to edge trigger also in order to be able to | |
1391 | * generate a PRCM wakeup. Here we restore the | |
1392 | * pre-runtime_suspend() values for edge triggering. | |
1393 | */ | |
661553b9 | 1394 | writel_relaxed(bank->context.fallingdetect, |
68942edb | 1395 | bank->base + bank->regs->fallingdetect); |
661553b9 | 1396 | writel_relaxed(bank->context.risingdetect, |
68942edb KH |
1397 | bank->base + bank->regs->risingdetect); |
1398 | ||
a2797bea JH |
1399 | if (bank->loses_context) { |
1400 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1401 | omap_gpio_restore_context(bank); |
1402 | } else { | |
a2797bea JH |
1403 | c = bank->get_context_loss_count(bank->dev); |
1404 | if (c != bank->context_loss_count) { | |
1405 | omap_gpio_restore_context(bank); | |
1406 | } else { | |
4dbada2b | 1407 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
a2797bea JH |
1408 | return 0; |
1409 | } | |
60a3437d | 1410 | } |
2dc983c5 | 1411 | } |
43ffcd9a | 1412 | |
1b128703 | 1413 | if (!bank->workaround_enabled) { |
4dbada2b | 1414 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1b128703 TKD |
1415 | return 0; |
1416 | } | |
1417 | ||
661553b9 | 1418 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1419 | |
2dc983c5 TKD |
1420 | /* |
1421 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1422 | * state. If so, generate an IRQ by software. This is | |
1423 | * horribly racy, but it's the best we can do to work around | |
1424 | * this silicon bug. | |
1425 | */ | |
1426 | l ^= bank->saved_datain; | |
1427 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1428 | |
2dc983c5 TKD |
1429 | /* |
1430 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1431 | * configured with falling edge only; and vice versa. | |
1432 | */ | |
c6f31c9e | 1433 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1434 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1435 | |
c6f31c9e | 1436 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1437 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1438 | |
2dc983c5 | 1439 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1440 | gen = l & (~(bank->context.fallingdetect) & |
1441 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1442 | /* Consider all GPIO IRQs needed to be updated */ |
1443 | gen |= gen0 | gen1; | |
82dbb9d3 | 1444 | |
2dc983c5 TKD |
1445 | if (gen) { |
1446 | u32 old0, old1; | |
82dbb9d3 | 1447 | |
661553b9 VK |
1448 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1449 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1450 | |
4e962e89 | 1451 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1452 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1453 | bank->regs->leveldetect0); |
661553b9 | 1454 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1455 | bank->regs->leveldetect1); |
2dc983c5 | 1456 | } |
9ea14d8c | 1457 | |
4e962e89 | 1458 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1459 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1460 | bank->regs->leveldetect0); |
661553b9 | 1461 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1462 | bank->regs->leveldetect1); |
3ac4fa99 | 1463 | } |
661553b9 VK |
1464 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1465 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 TKD |
1466 | } |
1467 | ||
1468 | bank->workaround_enabled = false; | |
4dbada2b | 1469 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2dc983c5 TKD |
1470 | |
1471 | return 0; | |
1472 | } | |
ecb2312f | 1473 | #endif /* CONFIG_PM */ |
2dc983c5 | 1474 | |
cac089f9 | 1475 | #if IS_BUILTIN(CONFIG_GPIO_OMAP) |
2dc983c5 TKD |
1476 | void omap2_gpio_prepare_for_idle(int pwr_mode) |
1477 | { | |
1478 | struct gpio_bank *bank; | |
1479 | ||
1480 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1481 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1482 | continue; |
1483 | ||
1484 | bank->power_mode = pwr_mode; | |
1485 | ||
2dc983c5 TKD |
1486 | pm_runtime_put_sync_suspend(bank->dev); |
1487 | } | |
1488 | } | |
1489 | ||
1490 | void omap2_gpio_resume_after_idle(void) | |
1491 | { | |
1492 | struct gpio_bank *bank; | |
1493 | ||
1494 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
fa365e4d | 1495 | if (!BANK_USED(bank) || !bank->loses_context) |
2dc983c5 TKD |
1496 | continue; |
1497 | ||
2dc983c5 | 1498 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1499 | } |
3ac4fa99 | 1500 | } |
cac089f9 | 1501 | #endif |
3ac4fa99 | 1502 | |
ecb2312f | 1503 | #if defined(CONFIG_PM) |
352a2d5b JH |
1504 | static void omap_gpio_init_context(struct gpio_bank *p) |
1505 | { | |
1506 | struct omap_gpio_reg_offs *regs = p->regs; | |
1507 | void __iomem *base = p->base; | |
1508 | ||
661553b9 VK |
1509 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1510 | p->context.oe = readl_relaxed(base + regs->direction); | |
1511 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1512 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1513 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1514 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1515 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1516 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1517 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
352a2d5b JH |
1518 | |
1519 | if (regs->set_dataout && p->regs->clr_dataout) | |
661553b9 | 1520 | p->context.dataout = readl_relaxed(base + regs->set_dataout); |
352a2d5b | 1521 | else |
661553b9 | 1522 | p->context.dataout = readl_relaxed(base + regs->dataout); |
352a2d5b JH |
1523 | |
1524 | p->context_valid = true; | |
1525 | } | |
1526 | ||
60a3437d | 1527 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1528 | { |
661553b9 | 1529 | writel_relaxed(bank->context.wake_en, |
ae10f233 | 1530 | bank->base + bank->regs->wkup_en); |
661553b9 VK |
1531 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); |
1532 | writel_relaxed(bank->context.leveldetect0, | |
ae10f233 | 1533 | bank->base + bank->regs->leveldetect0); |
661553b9 | 1534 | writel_relaxed(bank->context.leveldetect1, |
ae10f233 | 1535 | bank->base + bank->regs->leveldetect1); |
661553b9 | 1536 | writel_relaxed(bank->context.risingdetect, |
ae10f233 | 1537 | bank->base + bank->regs->risingdetect); |
661553b9 | 1538 | writel_relaxed(bank->context.fallingdetect, |
ae10f233 | 1539 | bank->base + bank->regs->fallingdetect); |
f86bcc30 | 1540 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
661553b9 | 1541 | writel_relaxed(bank->context.dataout, |
f86bcc30 NM |
1542 | bank->base + bank->regs->set_dataout); |
1543 | else | |
661553b9 | 1544 | writel_relaxed(bank->context.dataout, |
f86bcc30 | 1545 | bank->base + bank->regs->dataout); |
661553b9 | 1546 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); |
6d13eaaf | 1547 | |
ae547354 | 1548 | if (bank->dbck_enable_mask) { |
661553b9 | 1549 | writel_relaxed(bank->context.debounce, bank->base + |
ae547354 | 1550 | bank->regs->debounce); |
661553b9 | 1551 | writel_relaxed(bank->context.debounce_en, |
ae547354 NM |
1552 | bank->base + bank->regs->debounce_en); |
1553 | } | |
ba805be5 | 1554 | |
661553b9 | 1555 | writel_relaxed(bank->context.irqenable1, |
ba805be5 | 1556 | bank->base + bank->regs->irqenable); |
661553b9 | 1557 | writel_relaxed(bank->context.irqenable2, |
ba805be5 | 1558 | bank->base + bank->regs->irqenable2); |
40c670f0 | 1559 | } |
ecb2312f | 1560 | #endif /* CONFIG_PM */ |
55b93c32 | 1561 | #else |
2dc983c5 TKD |
1562 | #define omap_gpio_runtime_suspend NULL |
1563 | #define omap_gpio_runtime_resume NULL | |
ea4a21a2 | 1564 | static inline void omap_gpio_init_context(struct gpio_bank *p) {} |
40c670f0 RN |
1565 | #endif |
1566 | ||
55b93c32 | 1567 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1568 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1569 | NULL) | |
55b93c32 TKD |
1570 | }; |
1571 | ||
384ebe1c BC |
1572 | #if defined(CONFIG_OF) |
1573 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1574 | .revision = OMAP24XX_GPIO_REVISION, | |
1575 | .direction = OMAP24XX_GPIO_OE, | |
1576 | .datain = OMAP24XX_GPIO_DATAIN, | |
1577 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1578 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1579 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1580 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1581 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1582 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1583 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1584 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1585 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1586 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1587 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1588 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1589 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1590 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1591 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1592 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1593 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1594 | }; | |
1595 | ||
1596 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1597 | .revision = OMAP4_GPIO_REVISION, | |
1598 | .direction = OMAP4_GPIO_OE, | |
1599 | .datain = OMAP4_GPIO_DATAIN, | |
1600 | .dataout = OMAP4_GPIO_DATAOUT, | |
1601 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1602 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1603 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1604 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1605 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1606 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1607 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1608 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1609 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1610 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1611 | .ctrl = OMAP4_GPIO_CTRL, | |
1612 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1613 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1614 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1615 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1616 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1617 | }; | |
1618 | ||
e9a65bb6 | 1619 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1620 | .regs = &omap2_gpio_regs, |
1621 | .bank_width = 32, | |
1622 | .dbck_flag = false, | |
1623 | }; | |
1624 | ||
e9a65bb6 | 1625 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1626 | .regs = &omap2_gpio_regs, |
1627 | .bank_width = 32, | |
1628 | .dbck_flag = true, | |
1629 | }; | |
1630 | ||
e9a65bb6 | 1631 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1632 | .regs = &omap4_gpio_regs, |
1633 | .bank_width = 32, | |
1634 | .dbck_flag = true, | |
1635 | }; | |
1636 | ||
1637 | static const struct of_device_id omap_gpio_match[] = { | |
1638 | { | |
1639 | .compatible = "ti,omap4-gpio", | |
1640 | .data = &omap4_pdata, | |
1641 | }, | |
1642 | { | |
1643 | .compatible = "ti,omap3-gpio", | |
1644 | .data = &omap3_pdata, | |
1645 | }, | |
1646 | { | |
1647 | .compatible = "ti,omap2-gpio", | |
1648 | .data = &omap2_pdata, | |
1649 | }, | |
1650 | { }, | |
1651 | }; | |
1652 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1653 | #endif | |
1654 | ||
77640aab VC |
1655 | static struct platform_driver omap_gpio_driver = { |
1656 | .probe = omap_gpio_probe, | |
cac089f9 | 1657 | .remove = omap_gpio_remove, |
77640aab VC |
1658 | .driver = { |
1659 | .name = "omap_gpio", | |
55b93c32 | 1660 | .pm = &gpio_pm_ops, |
384ebe1c | 1661 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1662 | }, |
1663 | }; | |
1664 | ||
5e1c5ff4 | 1665 | /* |
77640aab VC |
1666 | * gpio driver register needs to be done before |
1667 | * machine_init functions access gpio APIs. | |
1668 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1669 | */ |
77640aab | 1670 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1671 | { |
77640aab | 1672 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1673 | } |
77640aab | 1674 | postcore_initcall(omap_gpio_drv_reg); |
cac089f9 TL |
1675 | |
1676 | static void __exit omap_gpio_exit(void) | |
1677 | { | |
1678 | platform_driver_unregister(&omap_gpio_driver); | |
1679 | } | |
1680 | module_exit(omap_gpio_exit); | |
1681 | ||
1682 | MODULE_DESCRIPTION("omap gpio driver"); | |
1683 | MODULE_ALIAS("platform:gpio-omap"); | |
1684 | MODULE_LICENSE("GPL v2"); |