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Commit | Line | Data |
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5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
96751fcb | 22 | #include <linux/device.h> |
77640aab | 23 | #include <linux/pm_runtime.h> |
55b93c32 | 24 | #include <linux/pm.h> |
384ebe1c BC |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/irqdomain.h> | |
4b25408f TL |
28 | #include <linux/gpio.h> |
29 | #include <linux/platform_data/gpio-omap.h> | |
5e1c5ff4 | 30 | |
5e1c5ff4 TL |
31 | #include <asm/mach/irq.h> |
32 | ||
2dc983c5 TKD |
33 | #define OFF_MODE 1 |
34 | ||
03e128ca C |
35 | static LIST_HEAD(omap_gpio_list); |
36 | ||
6d62e216 C |
37 | struct gpio_regs { |
38 | u32 irqenable1; | |
39 | u32 irqenable2; | |
40 | u32 wake_en; | |
41 | u32 ctrl; | |
42 | u32 oe; | |
43 | u32 leveldetect0; | |
44 | u32 leveldetect1; | |
45 | u32 risingdetect; | |
46 | u32 fallingdetect; | |
47 | u32 dataout; | |
ae547354 NM |
48 | u32 debounce; |
49 | u32 debounce_en; | |
6d62e216 C |
50 | }; |
51 | ||
5e1c5ff4 | 52 | struct gpio_bank { |
03e128ca | 53 | struct list_head node; |
92105bb7 | 54 | void __iomem *base; |
5e1c5ff4 | 55 | u16 irq; |
384ebe1c BC |
56 | int irq_base; |
57 | struct irq_domain *domain; | |
3ac4fa99 JY |
58 | u32 non_wakeup_gpios; |
59 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 60 | struct gpio_regs context; |
3ac4fa99 | 61 | u32 saved_datain; |
b144ff6f | 62 | u32 level_mask; |
4318f36b | 63 | u32 toggle_mask; |
5e1c5ff4 | 64 | spinlock_t lock; |
52e31344 | 65 | struct gpio_chip chip; |
89db9482 | 66 | struct clk *dbck; |
058af1ea | 67 | u32 mod_usage; |
8865b9b6 | 68 | u32 dbck_enable_mask; |
72f83af9 | 69 | bool dbck_enabled; |
77640aab | 70 | struct device *dev; |
d0d665a8 | 71 | bool is_mpuio; |
77640aab | 72 | bool dbck_flag; |
0cde8d03 | 73 | bool loses_context; |
5de62b86 | 74 | int stride; |
d5f46247 | 75 | u32 width; |
60a3437d | 76 | int context_loss_count; |
2dc983c5 TKD |
77 | int power_mode; |
78 | bool workaround_enabled; | |
fa87931a KH |
79 | |
80 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60a3437d | 81 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
82 | |
83 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
84 | }; |
85 | ||
129fd223 KH |
86 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
87 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
c8eef65a | 88 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 89 | |
25db711d BC |
90 | static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq) |
91 | { | |
92 | return gpio_irq - bank->irq_base + bank->chip.base; | |
93 | } | |
94 | ||
5e1c5ff4 TL |
95 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) |
96 | { | |
92105bb7 | 97 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
98 | u32 l; |
99 | ||
fa87931a | 100 | reg += bank->regs->direction; |
5e1c5ff4 TL |
101 | l = __raw_readl(reg); |
102 | if (is_input) | |
103 | l |= 1 << gpio; | |
104 | else | |
105 | l &= ~(1 << gpio); | |
106 | __raw_writel(l, reg); | |
41d87cbd | 107 | bank->context.oe = l; |
5e1c5ff4 TL |
108 | } |
109 | ||
fa87931a KH |
110 | |
111 | /* set data out value using dedicate set/clear register */ | |
112 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 113 | { |
92105bb7 | 114 | void __iomem *reg = bank->base; |
fa87931a | 115 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 116 | |
2c836f7e | 117 | if (enable) { |
fa87931a | 118 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
119 | bank->context.dataout |= l; |
120 | } else { | |
fa87931a | 121 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
122 | bank->context.dataout &= ~l; |
123 | } | |
5e1c5ff4 | 124 | |
5e1c5ff4 TL |
125 | __raw_writel(l, reg); |
126 | } | |
127 | ||
fa87931a KH |
128 | /* set data out value using mask register */ |
129 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 130 | { |
fa87931a KH |
131 | void __iomem *reg = bank->base + bank->regs->dataout; |
132 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
133 | u32 l; | |
5e1c5ff4 | 134 | |
fa87931a KH |
135 | l = __raw_readl(reg); |
136 | if (enable) | |
137 | l |= gpio_bit; | |
138 | else | |
139 | l &= ~gpio_bit; | |
5e1c5ff4 | 140 | __raw_writel(l, reg); |
41d87cbd | 141 | bank->context.dataout = l; |
5e1c5ff4 TL |
142 | } |
143 | ||
7fcca715 | 144 | static int _get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 145 | { |
fa87931a | 146 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 147 | |
7fcca715 | 148 | return (__raw_readl(reg) & (1 << offset)) != 0; |
5e1c5ff4 | 149 | } |
b37c45b8 | 150 | |
7fcca715 | 151 | static int _get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 152 | { |
fa87931a | 153 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 154 | |
7fcca715 | 155 | return (__raw_readl(reg) & (1 << offset)) != 0; |
b37c45b8 RQ |
156 | } |
157 | ||
ece9528e KH |
158 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
159 | { | |
160 | int l = __raw_readl(base + reg); | |
161 | ||
862ff640 | 162 | if (set) |
ece9528e KH |
163 | l |= mask; |
164 | else | |
165 | l &= ~mask; | |
166 | ||
167 | __raw_writel(l, base + reg); | |
168 | } | |
92105bb7 | 169 | |
72f83af9 TKD |
170 | static inline void _gpio_dbck_enable(struct gpio_bank *bank) |
171 | { | |
172 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
173 | clk_enable(bank->dbck); | |
174 | bank->dbck_enabled = true; | |
9e303f22 GI |
175 | |
176 | __raw_writel(bank->dbck_enable_mask, | |
177 | bank->base + bank->regs->debounce_en); | |
72f83af9 TKD |
178 | } |
179 | } | |
180 | ||
181 | static inline void _gpio_dbck_disable(struct gpio_bank *bank) | |
182 | { | |
183 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
184 | /* |
185 | * Disable debounce before cutting it's clock. If debounce is | |
186 | * enabled but the clock is not, GPIO module seems to be unable | |
187 | * to detect events and generate interrupts at least on OMAP3. | |
188 | */ | |
189 | __raw_writel(0, bank->base + bank->regs->debounce_en); | |
190 | ||
72f83af9 TKD |
191 | clk_disable(bank->dbck); |
192 | bank->dbck_enabled = false; | |
193 | } | |
194 | } | |
195 | ||
168ef3d9 FB |
196 | /** |
197 | * _set_gpio_debounce - low level gpio debounce time | |
198 | * @bank: the gpio bank we're acting upon | |
199 | * @gpio: the gpio number on this @gpio | |
200 | * @debounce: debounce time to use | |
201 | * | |
202 | * OMAP's debounce time is in 31us steps so we need | |
203 | * to convert and round up to the closest unit. | |
204 | */ | |
205 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
206 | unsigned debounce) | |
207 | { | |
9942da0e | 208 | void __iomem *reg; |
168ef3d9 FB |
209 | u32 val; |
210 | u32 l; | |
211 | ||
77640aab VC |
212 | if (!bank->dbck_flag) |
213 | return; | |
214 | ||
168ef3d9 FB |
215 | if (debounce < 32) |
216 | debounce = 0x01; | |
217 | else if (debounce > 7936) | |
218 | debounce = 0xff; | |
219 | else | |
220 | debounce = (debounce / 0x1f) - 1; | |
221 | ||
129fd223 | 222 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 223 | |
6fd9c421 | 224 | clk_enable(bank->dbck); |
9942da0e | 225 | reg = bank->base + bank->regs->debounce; |
168ef3d9 FB |
226 | __raw_writel(debounce, reg); |
227 | ||
9942da0e | 228 | reg = bank->base + bank->regs->debounce_en; |
168ef3d9 FB |
229 | val = __raw_readl(reg); |
230 | ||
6fd9c421 | 231 | if (debounce) |
168ef3d9 | 232 | val |= l; |
6fd9c421 | 233 | else |
168ef3d9 | 234 | val &= ~l; |
f7ec0b0b | 235 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
236 | |
237 | __raw_writel(val, reg); | |
6fd9c421 TKD |
238 | clk_disable(bank->dbck); |
239 | /* | |
240 | * Enable debounce clock per module. | |
241 | * This call is mandatory because in omap_gpio_request() when | |
242 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
243 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
244 | * used within _gpio_dbck_enable() is still not initialized at | |
245 | * that point. Therefore we have to enable dbck here. | |
246 | */ | |
247 | _gpio_dbck_enable(bank); | |
ae547354 NM |
248 | if (bank->dbck_enable_mask) { |
249 | bank->context.debounce = debounce; | |
250 | bank->context.debounce_en = val; | |
251 | } | |
168ef3d9 FB |
252 | } |
253 | ||
c9c55d92 JH |
254 | /** |
255 | * _clear_gpio_debounce - clear debounce settings for a gpio | |
256 | * @bank: the gpio bank we're acting upon | |
257 | * @gpio: the gpio number on this @gpio | |
258 | * | |
259 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
260 | * this is the only gpio in this bank using debounce, then clear the debounce | |
261 | * time too. The debounce clock will also be disabled when calling this function | |
262 | * if this is the only gpio in the bank using debounce. | |
263 | */ | |
264 | static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio) | |
265 | { | |
266 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
267 | ||
268 | if (!bank->dbck_flag) | |
269 | return; | |
270 | ||
271 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
272 | return; | |
273 | ||
274 | bank->dbck_enable_mask &= ~gpio_bit; | |
275 | bank->context.debounce_en &= ~gpio_bit; | |
276 | __raw_writel(bank->context.debounce_en, | |
277 | bank->base + bank->regs->debounce_en); | |
278 | ||
279 | if (!bank->dbck_enable_mask) { | |
280 | bank->context.debounce = 0; | |
281 | __raw_writel(bank->context.debounce, bank->base + | |
282 | bank->regs->debounce); | |
283 | clk_disable(bank->dbck); | |
284 | bank->dbck_enabled = false; | |
285 | } | |
286 | } | |
287 | ||
5e571f38 | 288 | static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 289 | unsigned trigger) |
5e1c5ff4 | 290 | { |
3ac4fa99 | 291 | void __iomem *base = bank->base; |
92105bb7 TL |
292 | u32 gpio_bit = 1 << gpio; |
293 | ||
5e571f38 TKD |
294 | _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
295 | trigger & IRQ_TYPE_LEVEL_LOW); | |
296 | _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
297 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
298 | _gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
299 | trigger & IRQ_TYPE_EDGE_RISING); | |
300 | _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
301 | trigger & IRQ_TYPE_EDGE_FALLING); | |
302 | ||
41d87cbd TKD |
303 | bank->context.leveldetect0 = |
304 | __raw_readl(bank->base + bank->regs->leveldetect0); | |
305 | bank->context.leveldetect1 = | |
306 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
307 | bank->context.risingdetect = | |
308 | __raw_readl(bank->base + bank->regs->risingdetect); | |
309 | bank->context.fallingdetect = | |
310 | __raw_readl(bank->base + bank->regs->fallingdetect); | |
311 | ||
312 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
5e571f38 | 313 | _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd TKD |
314 | bank->context.wake_en = |
315 | __raw_readl(bank->base + bank->regs->wkup_en); | |
316 | } | |
5e571f38 | 317 | |
55b220ca | 318 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
319 | if (!bank->regs->irqctrl) { |
320 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
321 | if (bank->non_wakeup_gpios) { | |
322 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
323 | goto exit; | |
324 | } | |
325 | ||
699117a6 CW |
326 | /* |
327 | * Log the edge gpio and manually trigger the IRQ | |
328 | * after resume if the input level changes | |
329 | * to avoid irq lost during PER RET/OFF mode | |
330 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
331 | */ | |
332 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
333 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
334 | else | |
335 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
336 | } | |
5eb3bb9c | 337 | |
5e571f38 | 338 | exit: |
9ea14d8c TKD |
339 | bank->level_mask = |
340 | __raw_readl(bank->base + bank->regs->leveldetect0) | | |
341 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
342 | } |
343 | ||
9198bcd3 | 344 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
345 | /* |
346 | * This only applies to chips that can't do both rising and falling edge | |
347 | * detection at once. For all other chips, this function is a noop. | |
348 | */ | |
349 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
350 | { | |
351 | void __iomem *reg = bank->base; | |
352 | u32 l = 0; | |
353 | ||
5e571f38 | 354 | if (!bank->regs->irqctrl) |
4318f36b | 355 | return; |
5e571f38 TKD |
356 | |
357 | reg += bank->regs->irqctrl; | |
4318f36b CM |
358 | |
359 | l = __raw_readl(reg); | |
360 | if ((l >> gpio) & 1) | |
361 | l &= ~(1 << gpio); | |
362 | else | |
363 | l |= 1 << gpio; | |
364 | ||
365 | __raw_writel(l, reg); | |
366 | } | |
5e571f38 TKD |
367 | #else |
368 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} | |
9198bcd3 | 369 | #endif |
4318f36b | 370 | |
00ece7e4 TKD |
371 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, |
372 | unsigned trigger) | |
92105bb7 TL |
373 | { |
374 | void __iomem *reg = bank->base; | |
5e571f38 | 375 | void __iomem *base = bank->base; |
92105bb7 | 376 | u32 l = 0; |
5e1c5ff4 | 377 | |
5e571f38 TKD |
378 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
379 | set_gpio_trigger(bank, gpio, trigger); | |
380 | } else if (bank->regs->irqctrl) { | |
381 | reg += bank->regs->irqctrl; | |
382 | ||
5e1c5ff4 | 383 | l = __raw_readl(reg); |
29501577 | 384 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 385 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 386 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 387 | l |= 1 << gpio; |
6cab4860 | 388 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 389 | l &= ~(1 << gpio); |
92105bb7 | 390 | else |
5e571f38 TKD |
391 | return -EINVAL; |
392 | ||
393 | __raw_writel(l, reg); | |
394 | } else if (bank->regs->edgectrl1) { | |
5e1c5ff4 | 395 | if (gpio & 0x08) |
5e571f38 | 396 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 397 | else |
5e571f38 TKD |
398 | reg += bank->regs->edgectrl1; |
399 | ||
5e1c5ff4 TL |
400 | gpio &= 0x07; |
401 | l = __raw_readl(reg); | |
402 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 403 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 404 | l |= 2 << (gpio << 1); |
6cab4860 | 405 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 406 | l |= 1 << (gpio << 1); |
5e571f38 TKD |
407 | |
408 | /* Enable wake-up during idle for dynamic tick */ | |
409 | _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger); | |
41d87cbd TKD |
410 | bank->context.wake_en = |
411 | __raw_readl(bank->base + bank->regs->wkup_en); | |
5e571f38 | 412 | __raw_writel(l, reg); |
5e1c5ff4 | 413 | } |
92105bb7 | 414 | return 0; |
5e1c5ff4 TL |
415 | } |
416 | ||
e9191028 | 417 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 418 | { |
25db711d | 419 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
4b25408f | 420 | unsigned gpio = 0; |
92105bb7 | 421 | int retval; |
a6472533 | 422 | unsigned long flags; |
92105bb7 | 423 | |
4b25408f TL |
424 | #ifdef CONFIG_ARCH_OMAP1 |
425 | if (d->irq > IH_MPUIO_BASE) | |
e9191028 | 426 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
4b25408f TL |
427 | #endif |
428 | ||
429 | if (!gpio) | |
25db711d | 430 | gpio = irq_to_gpio(bank, d->irq); |
5e1c5ff4 | 431 | |
e5c56ed3 | 432 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 433 | return -EINVAL; |
e5c56ed3 | 434 | |
9ea14d8c TKD |
435 | if (!bank->regs->leveldetect0 && |
436 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
437 | return -EINVAL; |
438 | ||
a6472533 | 439 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 440 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
a6472533 | 441 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
442 | |
443 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 444 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 445 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 446 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 447 | |
92105bb7 | 448 | return retval; |
5e1c5ff4 TL |
449 | } |
450 | ||
451 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
452 | { | |
92105bb7 | 453 | void __iomem *reg = bank->base; |
5e1c5ff4 | 454 | |
eef4bec7 | 455 | reg += bank->regs->irqstatus; |
5e1c5ff4 | 456 | __raw_writel(gpio_mask, reg); |
bee7930f HD |
457 | |
458 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
459 | if (bank->regs->irqstatus2) { |
460 | reg = bank->base + bank->regs->irqstatus2; | |
bedfd154 | 461 | __raw_writel(gpio_mask, reg); |
eef4bec7 | 462 | } |
bedfd154 RQ |
463 | |
464 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
465 | __raw_readl(reg); | |
5e1c5ff4 TL |
466 | } |
467 | ||
468 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
469 | { | |
129fd223 | 470 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
471 | } |
472 | ||
ea6dedd7 ID |
473 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
474 | { | |
475 | void __iomem *reg = bank->base; | |
99c47707 | 476 | u32 l; |
c390aad0 | 477 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 478 | |
28f3b5a0 | 479 | reg += bank->regs->irqenable; |
99c47707 | 480 | l = __raw_readl(reg); |
28f3b5a0 | 481 | if (bank->regs->irqenable_inv) |
99c47707 ID |
482 | l = ~l; |
483 | l &= mask; | |
484 | return l; | |
ea6dedd7 ID |
485 | } |
486 | ||
28f3b5a0 | 487 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 488 | { |
92105bb7 | 489 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
490 | u32 l; |
491 | ||
28f3b5a0 KH |
492 | if (bank->regs->set_irqenable) { |
493 | reg += bank->regs->set_irqenable; | |
494 | l = gpio_mask; | |
2a900eb7 | 495 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
496 | } else { |
497 | reg += bank->regs->irqenable; | |
5e1c5ff4 | 498 | l = __raw_readl(reg); |
28f3b5a0 KH |
499 | if (bank->regs->irqenable_inv) |
500 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
501 | else |
502 | l |= gpio_mask; | |
2a900eb7 | 503 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
504 | } |
505 | ||
506 | __raw_writel(l, reg); | |
507 | } | |
508 | ||
509 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
510 | { | |
511 | void __iomem *reg = bank->base; | |
512 | u32 l; | |
513 | ||
514 | if (bank->regs->clr_irqenable) { | |
515 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 516 | l = gpio_mask; |
2a900eb7 | 517 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
518 | } else { |
519 | reg += bank->regs->irqenable; | |
56739a69 | 520 | l = __raw_readl(reg); |
28f3b5a0 | 521 | if (bank->regs->irqenable_inv) |
56739a69 | 522 | l |= gpio_mask; |
92105bb7 | 523 | else |
28f3b5a0 | 524 | l &= ~gpio_mask; |
2a900eb7 | 525 | bank->context.irqenable1 = l; |
5e1c5ff4 | 526 | } |
28f3b5a0 | 527 | |
5e1c5ff4 TL |
528 | __raw_writel(l, reg); |
529 | } | |
530 | ||
531 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
532 | { | |
8276536c TKD |
533 | if (enable) |
534 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | |
535 | else | |
536 | _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); | |
5e1c5ff4 TL |
537 | } |
538 | ||
92105bb7 TL |
539 | /* |
540 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
541 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
542 | * to the target, system will wake up always on GPIO events. While | |
543 | * system is running all registered GPIO interrupts need to have wake-up | |
544 | * enabled. When system is suspended, only selected GPIO interrupts need | |
545 | * to have wake-up enabled. | |
546 | */ | |
547 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
548 | { | |
f64ad1a0 KH |
549 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
550 | unsigned long flags; | |
a6472533 | 551 | |
f64ad1a0 | 552 | if (bank->non_wakeup_gpios & gpio_bit) { |
862ff640 | 553 | dev_err(bank->dev, |
f64ad1a0 | 554 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); |
92105bb7 TL |
555 | return -EINVAL; |
556 | } | |
f64ad1a0 KH |
557 | |
558 | spin_lock_irqsave(&bank->lock, flags); | |
559 | if (enable) | |
0aa27273 | 560 | bank->context.wake_en |= gpio_bit; |
f64ad1a0 | 561 | else |
0aa27273 | 562 | bank->context.wake_en &= ~gpio_bit; |
f64ad1a0 | 563 | |
0aa27273 | 564 | __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en); |
f64ad1a0 KH |
565 | spin_unlock_irqrestore(&bank->lock, flags); |
566 | ||
567 | return 0; | |
92105bb7 TL |
568 | } |
569 | ||
4196dd6b TL |
570 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
571 | { | |
129fd223 | 572 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
573 | _set_gpio_irqenable(bank, gpio, 0); |
574 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 575 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
c9c55d92 | 576 | _clear_gpio_debounce(bank, gpio); |
4196dd6b TL |
577 | } |
578 | ||
92105bb7 | 579 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 580 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 581 | { |
25db711d BC |
582 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
583 | unsigned int gpio = irq_to_gpio(bank, d->irq); | |
92105bb7 | 584 | |
25db711d | 585 | return _set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
586 | } |
587 | ||
3ff164e1 | 588 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 589 | { |
3ff164e1 | 590 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 591 | unsigned long flags; |
52e31344 | 592 | |
55b93c32 TKD |
593 | /* |
594 | * If this is the first gpio_request for the bank, | |
595 | * enable the bank module. | |
596 | */ | |
597 | if (!bank->mod_usage) | |
598 | pm_runtime_get_sync(bank->dev); | |
92105bb7 | 599 | |
55b93c32 | 600 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b TL |
601 | /* Set trigger to none. You need to enable the desired trigger with |
602 | * request_irq() or set_irq_type(). | |
603 | */ | |
3ff164e1 | 604 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 605 | |
fad96ea8 C |
606 | if (bank->regs->pinctrl) { |
607 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
5e1c5ff4 | 608 | |
92105bb7 | 609 | /* Claim the pin for MPU */ |
3ff164e1 | 610 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 | 611 | } |
fad96ea8 | 612 | |
c8eef65a C |
613 | if (bank->regs->ctrl && !bank->mod_usage) { |
614 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
615 | u32 ctrl; | |
616 | ||
617 | ctrl = __raw_readl(reg); | |
618 | /* Module is enabled, clocks are not gated */ | |
619 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
620 | __raw_writel(ctrl, reg); | |
41d87cbd | 621 | bank->context.ctrl = ctrl; |
058af1ea | 622 | } |
c8eef65a C |
623 | |
624 | bank->mod_usage |= 1 << offset; | |
625 | ||
a6472533 | 626 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
627 | |
628 | return 0; | |
629 | } | |
630 | ||
3ff164e1 | 631 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 632 | { |
3ff164e1 | 633 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
6ed87c5b | 634 | void __iomem *base = bank->base; |
a6472533 | 635 | unsigned long flags; |
5e1c5ff4 | 636 | |
a6472533 | 637 | spin_lock_irqsave(&bank->lock, flags); |
6ed87c5b | 638 | |
41d87cbd | 639 | if (bank->regs->wkup_en) { |
9f096868 | 640 | /* Disable wake-up during idle for dynamic tick */ |
6ed87c5b | 641 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); |
41d87cbd TKD |
642 | bank->context.wake_en = |
643 | __raw_readl(bank->base + bank->regs->wkup_en); | |
644 | } | |
6ed87c5b | 645 | |
c8eef65a C |
646 | bank->mod_usage &= ~(1 << offset); |
647 | ||
648 | if (bank->regs->ctrl && !bank->mod_usage) { | |
649 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
650 | u32 ctrl; | |
651 | ||
652 | ctrl = __raw_readl(reg); | |
653 | /* Module is disabled, clocks are gated */ | |
654 | ctrl |= GPIO_MOD_CTRL_BIT; | |
655 | __raw_writel(ctrl, reg); | |
41d87cbd | 656 | bank->context.ctrl = ctrl; |
058af1ea | 657 | } |
c8eef65a | 658 | |
3ff164e1 | 659 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 660 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
661 | |
662 | /* | |
663 | * If this is the last gpio to be freed in the bank, | |
664 | * disable the bank module. | |
665 | */ | |
666 | if (!bank->mod_usage) | |
667 | pm_runtime_put(bank->dev); | |
5e1c5ff4 TL |
668 | } |
669 | ||
670 | /* | |
671 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
672 | * avoid missing GPIO interrupts for other lines in the bank. | |
673 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
674 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
675 | * If we wait to unmask individual GPIO lines in the bank after the | |
676 | * line's interrupt handler has been run, we may miss some nested | |
677 | * interrupts. | |
678 | */ | |
10dd5ce2 | 679 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 680 | { |
92105bb7 | 681 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 682 | u32 isr; |
4318f36b | 683 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 684 | struct gpio_bank *bank; |
ea6dedd7 | 685 | int unmasked = 0; |
ee144182 | 686 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 687 | |
ee144182 | 688 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 689 | |
6845664a | 690 | bank = irq_get_handler_data(irq); |
eef4bec7 | 691 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 692 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
693 | |
694 | if (WARN_ON(!isr_reg)) | |
695 | goto exit; | |
696 | ||
92105bb7 | 697 | while(1) { |
6e60e79a | 698 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 699 | u32 enabled; |
6e60e79a | 700 | |
ea6dedd7 ID |
701 | enabled = _get_gpio_irqbank_mask(bank); |
702 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a | 703 | |
9ea14d8c | 704 | if (bank->level_mask) |
b144ff6f | 705 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
706 | |
707 | /* clear edge sensitive interrupts before handler(s) are | |
708 | called so that we don't miss any interrupt occurred while | |
709 | executing them */ | |
28f3b5a0 | 710 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 711 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 712 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
713 | |
714 | /* if there is only edge sensitive GPIO pin interrupts | |
715 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
716 | if (!level_mask && !unmasked) { |
717 | unmasked = 1; | |
ee144182 | 718 | chained_irq_exit(chip, desc); |
ea6dedd7 | 719 | } |
92105bb7 TL |
720 | |
721 | if (!isr) | |
722 | break; | |
723 | ||
384ebe1c | 724 | gpio_irq = bank->irq_base; |
92105bb7 | 725 | for (; isr != 0; isr >>= 1, gpio_irq++) { |
25db711d | 726 | int gpio = irq_to_gpio(bank, gpio_irq); |
4318f36b | 727 | |
92105bb7 TL |
728 | if (!(isr & 1)) |
729 | continue; | |
29454dde | 730 | |
25db711d BC |
731 | gpio_index = GPIO_INDEX(bank, gpio); |
732 | ||
4318f36b CM |
733 | /* |
734 | * Some chips can't respond to both rising and falling | |
735 | * at the same time. If this irq was requested with | |
736 | * both flags, we need to flip the ICR data for the IRQ | |
737 | * to respond to the IRQ for the opposite direction. | |
738 | * This will be indicated in the bank toggle_mask. | |
739 | */ | |
740 | if (bank->toggle_mask & (1 << gpio_index)) | |
741 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
4318f36b | 742 | |
d8aa0251 | 743 | generic_handle_irq(gpio_irq); |
92105bb7 | 744 | } |
1a8bfa1e | 745 | } |
ea6dedd7 ID |
746 | /* if bank has any level sensitive GPIO pin interrupt |
747 | configured, we must unmask the bank interrupt only after | |
748 | handler(s) are executed in order to avoid spurious bank | |
749 | interrupt */ | |
b1cc4c55 | 750 | exit: |
ea6dedd7 | 751 | if (!unmasked) |
ee144182 | 752 | chained_irq_exit(chip, desc); |
55b93c32 | 753 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
754 | } |
755 | ||
e9191028 | 756 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 757 | { |
e9191028 | 758 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
25db711d | 759 | unsigned int gpio = irq_to_gpio(bank, d->irq); |
85ec7b97 | 760 | unsigned long flags; |
4196dd6b | 761 | |
85ec7b97 | 762 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 763 | _reset_gpio(bank, gpio); |
85ec7b97 | 764 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
765 | } |
766 | ||
e9191028 | 767 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 768 | { |
e9191028 | 769 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
25db711d | 770 | unsigned int gpio = irq_to_gpio(bank, d->irq); |
5e1c5ff4 TL |
771 | |
772 | _clear_gpio_irqstatus(bank, gpio); | |
773 | } | |
774 | ||
e9191028 | 775 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 776 | { |
e9191028 | 777 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
25db711d | 778 | unsigned int gpio = irq_to_gpio(bank, d->irq); |
85ec7b97 | 779 | unsigned long flags; |
5e1c5ff4 | 780 | |
85ec7b97 | 781 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 782 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 783 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 784 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
785 | } |
786 | ||
e9191028 | 787 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 788 | { |
e9191028 | 789 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
25db711d | 790 | unsigned int gpio = irq_to_gpio(bank, d->irq); |
129fd223 | 791 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 792 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 793 | unsigned long flags; |
55b6019a | 794 | |
85ec7b97 | 795 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 796 | if (trigger) |
129fd223 | 797 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
798 | |
799 | /* For level-triggered GPIOs, the clearing must be done after | |
800 | * the HW source is cleared, thus after the handler has run */ | |
801 | if (bank->level_mask & irq_mask) { | |
802 | _set_gpio_irqenable(bank, gpio, 0); | |
803 | _clear_gpio_irqstatus(bank, gpio); | |
804 | } | |
5e1c5ff4 | 805 | |
4de8c75b | 806 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 807 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
808 | } |
809 | ||
e5c56ed3 DB |
810 | static struct irq_chip gpio_irq_chip = { |
811 | .name = "GPIO", | |
e9191028 LB |
812 | .irq_shutdown = gpio_irq_shutdown, |
813 | .irq_ack = gpio_ack_irq, | |
814 | .irq_mask = gpio_mask_irq, | |
815 | .irq_unmask = gpio_unmask_irq, | |
816 | .irq_set_type = gpio_irq_type, | |
817 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
818 | }; |
819 | ||
820 | /*---------------------------------------------------------------------*/ | |
821 | ||
79ee031f | 822 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 823 | { |
79ee031f | 824 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 825 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
826 | void __iomem *mask_reg = bank->base + |
827 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 828 | unsigned long flags; |
11a78b79 | 829 | |
a6472533 | 830 | spin_lock_irqsave(&bank->lock, flags); |
0aa27273 | 831 | __raw_writel(0xffff & ~bank->context.wake_en, mask_reg); |
a6472533 | 832 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
833 | |
834 | return 0; | |
835 | } | |
836 | ||
79ee031f | 837 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 838 | { |
79ee031f | 839 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 840 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
841 | void __iomem *mask_reg = bank->base + |
842 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 843 | unsigned long flags; |
11a78b79 | 844 | |
a6472533 | 845 | spin_lock_irqsave(&bank->lock, flags); |
499fa287 | 846 | __raw_writel(bank->context.wake_en, mask_reg); |
a6472533 | 847 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
848 | |
849 | return 0; | |
850 | } | |
851 | ||
47145210 | 852 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
853 | .suspend_noirq = omap_mpuio_suspend_noirq, |
854 | .resume_noirq = omap_mpuio_resume_noirq, | |
855 | }; | |
856 | ||
3c437ffd | 857 | /* use platform_driver for this. */ |
11a78b79 | 858 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
859 | .driver = { |
860 | .name = "mpuio", | |
79ee031f | 861 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
862 | }, |
863 | }; | |
864 | ||
865 | static struct platform_device omap_mpuio_device = { | |
866 | .name = "mpuio", | |
867 | .id = -1, | |
868 | .dev = { | |
869 | .driver = &omap_mpuio_driver.driver, | |
870 | } | |
871 | /* could list the /proc/iomem resources */ | |
872 | }; | |
873 | ||
03e128ca | 874 | static inline void mpuio_init(struct gpio_bank *bank) |
11a78b79 | 875 | { |
77640aab | 876 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 877 | |
11a78b79 DB |
878 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
879 | (void) platform_device_register(&omap_mpuio_device); | |
880 | } | |
881 | ||
e5c56ed3 | 882 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 883 | |
52e31344 DB |
884 | static int gpio_input(struct gpio_chip *chip, unsigned offset) |
885 | { | |
886 | struct gpio_bank *bank; | |
887 | unsigned long flags; | |
888 | ||
889 | bank = container_of(chip, struct gpio_bank, chip); | |
890 | spin_lock_irqsave(&bank->lock, flags); | |
891 | _set_gpio_direction(bank, offset, 1); | |
892 | spin_unlock_irqrestore(&bank->lock, flags); | |
893 | return 0; | |
894 | } | |
895 | ||
b37c45b8 RQ |
896 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
897 | { | |
fa87931a | 898 | void __iomem *reg = bank->base + bank->regs->direction; |
b37c45b8 | 899 | |
b37c45b8 RQ |
900 | return __raw_readl(reg) & mask; |
901 | } | |
902 | ||
52e31344 DB |
903 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
904 | { | |
b37c45b8 | 905 | struct gpio_bank *bank; |
b37c45b8 RQ |
906 | u32 mask; |
907 | ||
a8be8daf | 908 | bank = container_of(chip, struct gpio_bank, chip); |
7fcca715 | 909 | mask = (1 << offset); |
b37c45b8 RQ |
910 | |
911 | if (gpio_is_input(bank, mask)) | |
7fcca715 | 912 | return _get_gpio_datain(bank, offset); |
b37c45b8 | 913 | else |
7fcca715 | 914 | return _get_gpio_dataout(bank, offset); |
52e31344 DB |
915 | } |
916 | ||
917 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
918 | { | |
919 | struct gpio_bank *bank; | |
920 | unsigned long flags; | |
921 | ||
922 | bank = container_of(chip, struct gpio_bank, chip); | |
923 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 924 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
925 | _set_gpio_direction(bank, offset, 0); |
926 | spin_unlock_irqrestore(&bank->lock, flags); | |
927 | return 0; | |
928 | } | |
929 | ||
168ef3d9 FB |
930 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
931 | unsigned debounce) | |
932 | { | |
933 | struct gpio_bank *bank; | |
934 | unsigned long flags; | |
935 | ||
936 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab | 937 | |
168ef3d9 FB |
938 | spin_lock_irqsave(&bank->lock, flags); |
939 | _set_gpio_debounce(bank, offset, debounce); | |
940 | spin_unlock_irqrestore(&bank->lock, flags); | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
52e31344 DB |
945 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
946 | { | |
947 | struct gpio_bank *bank; | |
948 | unsigned long flags; | |
949 | ||
950 | bank = container_of(chip, struct gpio_bank, chip); | |
951 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 952 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
953 | spin_unlock_irqrestore(&bank->lock, flags); |
954 | } | |
955 | ||
a007b709 DB |
956 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
957 | { | |
958 | struct gpio_bank *bank; | |
959 | ||
960 | bank = container_of(chip, struct gpio_bank, chip); | |
384ebe1c | 961 | return bank->irq_base + offset; |
a007b709 DB |
962 | } |
963 | ||
52e31344 DB |
964 | /*---------------------------------------------------------------------*/ |
965 | ||
9a748053 | 966 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 967 | { |
e5ff4440 | 968 | static bool called; |
9f7065da TL |
969 | u32 rev; |
970 | ||
e5ff4440 | 971 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
972 | return; |
973 | ||
e5ff4440 KH |
974 | rev = __raw_readw(bank->base + bank->regs->revision); |
975 | pr_info("OMAP GPIO hardware version %d.%d\n", | |
9f7065da | 976 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
977 | |
978 | called = true; | |
9f7065da TL |
979 | } |
980 | ||
8ba55c5c DB |
981 | /* This lock class tells lockdep that GPIO irqs are in a different |
982 | * category than their parents, so it won't report false recursion. | |
983 | */ | |
984 | static struct lock_class_key gpio_lock_class; | |
985 | ||
03e128ca | 986 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 987 | { |
ab985f0f TKD |
988 | void __iomem *base = bank->base; |
989 | u32 l = 0xffffffff; | |
2fae7fbe | 990 | |
ab985f0f TKD |
991 | if (bank->width == 16) |
992 | l = 0xffff; | |
993 | ||
d0d665a8 | 994 | if (bank->is_mpuio) { |
ab985f0f TKD |
995 | __raw_writel(l, bank->base + bank->regs->irqenable); |
996 | return; | |
2fae7fbe | 997 | } |
ab985f0f TKD |
998 | |
999 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv); | |
6edd94db | 1000 | _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv); |
ab985f0f | 1001 | if (bank->regs->debounce_en) |
6edd94db | 1002 | __raw_writel(0, base + bank->regs->debounce_en); |
ab985f0f | 1003 | |
2dc983c5 TKD |
1004 | /* Save OE default value (0xffffffff) in the context */ |
1005 | bank->context.oe = __raw_readl(bank->base + bank->regs->direction); | |
ab985f0f TKD |
1006 | /* Initialize interface clk ungated, module enabled */ |
1007 | if (bank->regs->ctrl) | |
6edd94db | 1008 | __raw_writel(0, base + bank->regs->ctrl); |
34672013 TKD |
1009 | |
1010 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1011 | if (IS_ERR(bank->dbck)) | |
1012 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
2fae7fbe VC |
1013 | } |
1014 | ||
3836309d | 1015 | static void |
f8b46b58 KH |
1016 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, |
1017 | unsigned int num) | |
1018 | { | |
1019 | struct irq_chip_generic *gc; | |
1020 | struct irq_chip_type *ct; | |
1021 | ||
1022 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
1023 | handle_simple_irq); | |
83233749 TP |
1024 | if (!gc) { |
1025 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
1026 | return; | |
1027 | } | |
1028 | ||
f8b46b58 KH |
1029 | ct = gc->chip_types; |
1030 | ||
1031 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
1032 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
1033 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
1034 | ct->chip.irq_set_type = gpio_irq_type; | |
6ed87c5b TKD |
1035 | |
1036 | if (bank->regs->wkup_en) | |
f8b46b58 KH |
1037 | ct->chip.irq_set_wake = gpio_wake_enable, |
1038 | ||
1039 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
1040 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
1041 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
1042 | } | |
1043 | ||
3836309d | 1044 | static void omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 1045 | { |
77640aab | 1046 | int j; |
2fae7fbe VC |
1047 | static int gpio; |
1048 | ||
2fae7fbe VC |
1049 | /* |
1050 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1051 | * over to the generic ones | |
1052 | */ | |
1053 | bank->chip.request = omap_gpio_request; | |
1054 | bank->chip.free = omap_gpio_free; | |
1055 | bank->chip.direction_input = gpio_input; | |
1056 | bank->chip.get = gpio_get; | |
1057 | bank->chip.direction_output = gpio_output; | |
1058 | bank->chip.set_debounce = gpio_debounce; | |
1059 | bank->chip.set = gpio_set; | |
1060 | bank->chip.to_irq = gpio_2irq; | |
d0d665a8 | 1061 | if (bank->is_mpuio) { |
2fae7fbe | 1062 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
1063 | if (bank->regs->wkup_en) |
1064 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
1065 | bank->chip.base = OMAP_MPUIO(0); |
1066 | } else { | |
1067 | bank->chip.label = "gpio"; | |
1068 | bank->chip.base = gpio; | |
d5f46247 | 1069 | gpio += bank->width; |
2fae7fbe | 1070 | } |
d5f46247 | 1071 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
1072 | |
1073 | gpiochip_add(&bank->chip); | |
1074 | ||
384ebe1c | 1075 | for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) { |
1475b85d | 1076 | irq_set_lockdep_class(j, &gpio_lock_class); |
6845664a | 1077 | irq_set_chip_data(j, bank); |
d0d665a8 | 1078 | if (bank->is_mpuio) { |
f8b46b58 KH |
1079 | omap_mpuio_alloc_gc(bank, j, bank->width); |
1080 | } else { | |
6845664a | 1081 | irq_set_chip(j, &gpio_irq_chip); |
f8b46b58 KH |
1082 | irq_set_handler(j, handle_simple_irq); |
1083 | set_irq_flags(j, IRQF_VALID); | |
1084 | } | |
2fae7fbe | 1085 | } |
6845664a TG |
1086 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1087 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
1088 | } |
1089 | ||
384ebe1c BC |
1090 | static const struct of_device_id omap_gpio_match[]; |
1091 | ||
3836309d | 1092 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1093 | { |
862ff640 | 1094 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1095 | struct device_node *node = dev->of_node; |
1096 | const struct of_device_id *match; | |
f6817a2c | 1097 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1098 | struct resource *res; |
5e1c5ff4 | 1099 | struct gpio_bank *bank; |
03e128ca | 1100 | int ret = 0; |
5e1c5ff4 | 1101 | |
384ebe1c BC |
1102 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1103 | ||
1104 | pdata = match ? match->data : dev->platform_data; | |
1105 | if (!pdata) | |
96751fcb | 1106 | return -EINVAL; |
5492fb1a | 1107 | |
086d585f | 1108 | bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL); |
03e128ca | 1109 | if (!bank) { |
862ff640 | 1110 | dev_err(dev, "Memory alloc failed\n"); |
96751fcb | 1111 | return -ENOMEM; |
03e128ca | 1112 | } |
92105bb7 | 1113 | |
77640aab VC |
1114 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1115 | if (unlikely(!res)) { | |
862ff640 | 1116 | dev_err(dev, "Invalid IRQ resource\n"); |
96751fcb | 1117 | return -ENODEV; |
44169075 | 1118 | } |
5e1c5ff4 | 1119 | |
77640aab | 1120 | bank->irq = res->start; |
862ff640 | 1121 | bank->dev = dev; |
77640aab | 1122 | bank->dbck_flag = pdata->dbck_flag; |
5de62b86 | 1123 | bank->stride = pdata->bank_stride; |
d5f46247 | 1124 | bank->width = pdata->bank_width; |
d0d665a8 | 1125 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1126 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
0cde8d03 | 1127 | bank->loses_context = pdata->loses_context; |
fa87931a | 1128 | bank->regs = pdata->regs; |
384ebe1c BC |
1129 | #ifdef CONFIG_OF_GPIO |
1130 | bank->chip.of_node = of_node_get(node); | |
1131 | #endif | |
1132 | ||
1133 | bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0); | |
1134 | if (bank->irq_base < 0) { | |
1135 | dev_err(dev, "Couldn't allocate IRQ numbers\n"); | |
1136 | return -ENODEV; | |
1137 | } | |
1138 | ||
1139 | bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base, | |
1140 | 0, &irq_domain_simple_ops, NULL); | |
fa87931a KH |
1141 | |
1142 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1143 | bank->set_dataout = _set_gpio_dataout_reg; | |
1144 | else | |
1145 | bank->set_dataout = _set_gpio_dataout_mask; | |
9f7065da | 1146 | |
77640aab | 1147 | spin_lock_init(&bank->lock); |
9f7065da | 1148 | |
77640aab VC |
1149 | /* Static mapping, never released */ |
1150 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1151 | if (unlikely(!res)) { | |
862ff640 | 1152 | dev_err(dev, "Invalid mem resource\n"); |
96751fcb BC |
1153 | return -ENODEV; |
1154 | } | |
1155 | ||
1156 | if (!devm_request_mem_region(dev, res->start, resource_size(res), | |
1157 | pdev->name)) { | |
1158 | dev_err(dev, "Region already claimed\n"); | |
1159 | return -EBUSY; | |
77640aab | 1160 | } |
89db9482 | 1161 | |
96751fcb | 1162 | bank->base = devm_ioremap(dev, res->start, resource_size(res)); |
77640aab | 1163 | if (!bank->base) { |
862ff640 | 1164 | dev_err(dev, "Could not ioremap\n"); |
96751fcb | 1165 | return -ENOMEM; |
5e1c5ff4 TL |
1166 | } |
1167 | ||
065cd795 TKD |
1168 | platform_set_drvdata(pdev, bank); |
1169 | ||
77640aab | 1170 | pm_runtime_enable(bank->dev); |
55b93c32 | 1171 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1172 | pm_runtime_get_sync(bank->dev); |
1173 | ||
d0d665a8 | 1174 | if (bank->is_mpuio) |
ab985f0f TKD |
1175 | mpuio_init(bank); |
1176 | ||
03e128ca | 1177 | omap_gpio_mod_init(bank); |
77640aab | 1178 | omap_gpio_chip_init(bank); |
9a748053 | 1179 | omap_gpio_show_rev(bank); |
9f7065da | 1180 | |
7b86cef3 JH |
1181 | if (bank->loses_context) |
1182 | bank->get_context_loss_count = pdata->get_context_loss_count; | |
1183 | ||
55b93c32 TKD |
1184 | pm_runtime_put(bank->dev); |
1185 | ||
03e128ca | 1186 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1187 | |
03e128ca | 1188 | return ret; |
5e1c5ff4 TL |
1189 | } |
1190 | ||
55b93c32 TKD |
1191 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1192 | ||
2dc983c5 | 1193 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1194 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1195 | |
2dc983c5 | 1196 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1197 | { |
2dc983c5 TKD |
1198 | struct platform_device *pdev = to_platform_device(dev); |
1199 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1200 | u32 l1 = 0, l2 = 0; | |
1201 | unsigned long flags; | |
68942edb | 1202 | u32 wake_low, wake_hi; |
8865b9b6 | 1203 | |
2dc983c5 | 1204 | spin_lock_irqsave(&bank->lock, flags); |
68942edb KH |
1205 | |
1206 | /* | |
1207 | * Only edges can generate a wakeup event to the PRCM. | |
1208 | * | |
1209 | * Therefore, ensure any wake-up capable GPIOs have | |
1210 | * edge-detection enabled before going idle to ensure a wakeup | |
1211 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
1212 | * NDA TRM 25.5.3.1) | |
1213 | * | |
1214 | * The normal values will be restored upon ->runtime_resume() | |
1215 | * by writing back the values saved in bank->context. | |
1216 | */ | |
1217 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
1218 | if (wake_low) | |
1219 | __raw_writel(wake_low | bank->context.fallingdetect, | |
1220 | bank->base + bank->regs->fallingdetect); | |
1221 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
1222 | if (wake_hi) | |
1223 | __raw_writel(wake_hi | bank->context.risingdetect, | |
1224 | bank->base + bank->regs->risingdetect); | |
1225 | ||
b3c64bc3 KH |
1226 | if (!bank->enabled_non_wakeup_gpios) |
1227 | goto update_gpio_context_count; | |
1228 | ||
2dc983c5 TKD |
1229 | if (bank->power_mode != OFF_MODE) { |
1230 | bank->power_mode = 0; | |
41d87cbd | 1231 | goto update_gpio_context_count; |
2dc983c5 TKD |
1232 | } |
1233 | /* | |
1234 | * If going to OFF, remove triggering for all | |
1235 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1236 | * generated. See OMAP2420 Errata item 1.101. | |
1237 | */ | |
2dc983c5 TKD |
1238 | bank->saved_datain = __raw_readl(bank->base + |
1239 | bank->regs->datain); | |
c6f31c9e TKD |
1240 | l1 = bank->context.fallingdetect; |
1241 | l2 = bank->context.risingdetect; | |
3f1686a9 | 1242 | |
2dc983c5 TKD |
1243 | l1 &= ~bank->enabled_non_wakeup_gpios; |
1244 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1245 | |
2dc983c5 TKD |
1246 | __raw_writel(l1, bank->base + bank->regs->fallingdetect); |
1247 | __raw_writel(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1248 | |
2dc983c5 | 1249 | bank->workaround_enabled = true; |
3f1686a9 | 1250 | |
41d87cbd | 1251 | update_gpio_context_count: |
2dc983c5 TKD |
1252 | if (bank->get_context_loss_count) |
1253 | bank->context_loss_count = | |
60a3437d TKD |
1254 | bank->get_context_loss_count(bank->dev); |
1255 | ||
72f83af9 | 1256 | _gpio_dbck_disable(bank); |
2dc983c5 | 1257 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1258 | |
2dc983c5 | 1259 | return 0; |
3ac4fa99 JY |
1260 | } |
1261 | ||
2dc983c5 | 1262 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1263 | { |
2dc983c5 TKD |
1264 | struct platform_device *pdev = to_platform_device(dev); |
1265 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1266 | int context_lost_cnt_after; | |
1267 | u32 l = 0, gen, gen0, gen1; | |
1268 | unsigned long flags; | |
8865b9b6 | 1269 | |
2dc983c5 | 1270 | spin_lock_irqsave(&bank->lock, flags); |
72f83af9 | 1271 | _gpio_dbck_enable(bank); |
68942edb KH |
1272 | |
1273 | /* | |
1274 | * In ->runtime_suspend(), level-triggered, wakeup-enabled | |
1275 | * GPIOs were set to edge trigger also in order to be able to | |
1276 | * generate a PRCM wakeup. Here we restore the | |
1277 | * pre-runtime_suspend() values for edge triggering. | |
1278 | */ | |
1279 | __raw_writel(bank->context.fallingdetect, | |
1280 | bank->base + bank->regs->fallingdetect); | |
1281 | __raw_writel(bank->context.risingdetect, | |
1282 | bank->base + bank->regs->risingdetect); | |
1283 | ||
2dc983c5 TKD |
1284 | if (bank->get_context_loss_count) { |
1285 | context_lost_cnt_after = | |
1286 | bank->get_context_loss_count(bank->dev); | |
22770de1 | 1287 | if (context_lost_cnt_after != bank->context_loss_count) { |
2dc983c5 TKD |
1288 | omap_gpio_restore_context(bank); |
1289 | } else { | |
1290 | spin_unlock_irqrestore(&bank->lock, flags); | |
1291 | return 0; | |
60a3437d | 1292 | } |
2dc983c5 | 1293 | } |
43ffcd9a | 1294 | |
1b128703 TKD |
1295 | if (!bank->workaround_enabled) { |
1296 | spin_unlock_irqrestore(&bank->lock, flags); | |
1297 | return 0; | |
1298 | } | |
1299 | ||
c6f31c9e | 1300 | __raw_writel(bank->context.fallingdetect, |
2dc983c5 | 1301 | bank->base + bank->regs->fallingdetect); |
c6f31c9e | 1302 | __raw_writel(bank->context.risingdetect, |
2dc983c5 TKD |
1303 | bank->base + bank->regs->risingdetect); |
1304 | l = __raw_readl(bank->base + bank->regs->datain); | |
3f1686a9 | 1305 | |
2dc983c5 TKD |
1306 | /* |
1307 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1308 | * state. If so, generate an IRQ by software. This is | |
1309 | * horribly racy, but it's the best we can do to work around | |
1310 | * this silicon bug. | |
1311 | */ | |
1312 | l ^= bank->saved_datain; | |
1313 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1314 | |
2dc983c5 TKD |
1315 | /* |
1316 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1317 | * configured with falling edge only; and vice versa. | |
1318 | */ | |
c6f31c9e | 1319 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1320 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1321 | |
c6f31c9e | 1322 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1323 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1324 | |
2dc983c5 | 1325 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1326 | gen = l & (~(bank->context.fallingdetect) & |
1327 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1328 | /* Consider all GPIO IRQs needed to be updated */ |
1329 | gen |= gen0 | gen1; | |
82dbb9d3 | 1330 | |
2dc983c5 TKD |
1331 | if (gen) { |
1332 | u32 old0, old1; | |
82dbb9d3 | 1333 | |
2dc983c5 TKD |
1334 | old0 = __raw_readl(bank->base + bank->regs->leveldetect0); |
1335 | old1 = __raw_readl(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1336 | |
4e962e89 | 1337 | if (!bank->regs->irqstatus_raw0) { |
2dc983c5 | 1338 | __raw_writel(old0 | gen, bank->base + |
9ea14d8c | 1339 | bank->regs->leveldetect0); |
2dc983c5 | 1340 | __raw_writel(old1 | gen, bank->base + |
9ea14d8c | 1341 | bank->regs->leveldetect1); |
2dc983c5 | 1342 | } |
9ea14d8c | 1343 | |
4e962e89 | 1344 | if (bank->regs->irqstatus_raw0) { |
2dc983c5 | 1345 | __raw_writel(old0 | l, bank->base + |
9ea14d8c | 1346 | bank->regs->leveldetect0); |
2dc983c5 | 1347 | __raw_writel(old1 | l, bank->base + |
9ea14d8c | 1348 | bank->regs->leveldetect1); |
3ac4fa99 | 1349 | } |
2dc983c5 TKD |
1350 | __raw_writel(old0, bank->base + bank->regs->leveldetect0); |
1351 | __raw_writel(old1, bank->base + bank->regs->leveldetect1); | |
1352 | } | |
1353 | ||
1354 | bank->workaround_enabled = false; | |
1355 | spin_unlock_irqrestore(&bank->lock, flags); | |
1356 | ||
1357 | return 0; | |
1358 | } | |
1359 | #endif /* CONFIG_PM_RUNTIME */ | |
1360 | ||
1361 | void omap2_gpio_prepare_for_idle(int pwr_mode) | |
1362 | { | |
1363 | struct gpio_bank *bank; | |
1364 | ||
1365 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
2dc983c5 TKD |
1366 | if (!bank->mod_usage || !bank->loses_context) |
1367 | continue; | |
1368 | ||
1369 | bank->power_mode = pwr_mode; | |
1370 | ||
2dc983c5 TKD |
1371 | pm_runtime_put_sync_suspend(bank->dev); |
1372 | } | |
1373 | } | |
1374 | ||
1375 | void omap2_gpio_resume_after_idle(void) | |
1376 | { | |
1377 | struct gpio_bank *bank; | |
1378 | ||
1379 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
2dc983c5 TKD |
1380 | if (!bank->mod_usage || !bank->loses_context) |
1381 | continue; | |
1382 | ||
2dc983c5 | 1383 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1384 | } |
3ac4fa99 JY |
1385 | } |
1386 | ||
2dc983c5 | 1387 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1388 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1389 | { |
60a3437d | 1390 | __raw_writel(bank->context.wake_en, |
ae10f233 TKD |
1391 | bank->base + bank->regs->wkup_en); |
1392 | __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
60a3437d | 1393 | __raw_writel(bank->context.leveldetect0, |
ae10f233 | 1394 | bank->base + bank->regs->leveldetect0); |
60a3437d | 1395 | __raw_writel(bank->context.leveldetect1, |
ae10f233 | 1396 | bank->base + bank->regs->leveldetect1); |
60a3437d | 1397 | __raw_writel(bank->context.risingdetect, |
ae10f233 | 1398 | bank->base + bank->regs->risingdetect); |
60a3437d | 1399 | __raw_writel(bank->context.fallingdetect, |
ae10f233 | 1400 | bank->base + bank->regs->fallingdetect); |
f86bcc30 NM |
1401 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
1402 | __raw_writel(bank->context.dataout, | |
1403 | bank->base + bank->regs->set_dataout); | |
1404 | else | |
1405 | __raw_writel(bank->context.dataout, | |
1406 | bank->base + bank->regs->dataout); | |
6d13eaaf NM |
1407 | __raw_writel(bank->context.oe, bank->base + bank->regs->direction); |
1408 | ||
ae547354 NM |
1409 | if (bank->dbck_enable_mask) { |
1410 | __raw_writel(bank->context.debounce, bank->base + | |
1411 | bank->regs->debounce); | |
1412 | __raw_writel(bank->context.debounce_en, | |
1413 | bank->base + bank->regs->debounce_en); | |
1414 | } | |
ba805be5 NM |
1415 | |
1416 | __raw_writel(bank->context.irqenable1, | |
1417 | bank->base + bank->regs->irqenable); | |
1418 | __raw_writel(bank->context.irqenable2, | |
1419 | bank->base + bank->regs->irqenable2); | |
40c670f0 | 1420 | } |
2dc983c5 | 1421 | #endif /* CONFIG_PM_RUNTIME */ |
55b93c32 | 1422 | #else |
2dc983c5 TKD |
1423 | #define omap_gpio_runtime_suspend NULL |
1424 | #define omap_gpio_runtime_resume NULL | |
40c670f0 RN |
1425 | #endif |
1426 | ||
55b93c32 | 1427 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1428 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1429 | NULL) | |
55b93c32 TKD |
1430 | }; |
1431 | ||
384ebe1c BC |
1432 | #if defined(CONFIG_OF) |
1433 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1434 | .revision = OMAP24XX_GPIO_REVISION, | |
1435 | .direction = OMAP24XX_GPIO_OE, | |
1436 | .datain = OMAP24XX_GPIO_DATAIN, | |
1437 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1438 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1439 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1440 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1441 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1442 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1443 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1444 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1445 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1446 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1447 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1448 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1449 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1450 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1451 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1452 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1453 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1454 | }; | |
1455 | ||
1456 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1457 | .revision = OMAP4_GPIO_REVISION, | |
1458 | .direction = OMAP4_GPIO_OE, | |
1459 | .datain = OMAP4_GPIO_DATAIN, | |
1460 | .dataout = OMAP4_GPIO_DATAOUT, | |
1461 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1462 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1463 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1464 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1465 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1466 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1467 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1468 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1469 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1470 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1471 | .ctrl = OMAP4_GPIO_CTRL, | |
1472 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1473 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1474 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1475 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1476 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1477 | }; | |
1478 | ||
c06e6769 | 1479 | const static struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1480 | .regs = &omap2_gpio_regs, |
1481 | .bank_width = 32, | |
1482 | .dbck_flag = false, | |
1483 | }; | |
1484 | ||
c06e6769 | 1485 | const static struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1486 | .regs = &omap2_gpio_regs, |
1487 | .bank_width = 32, | |
1488 | .dbck_flag = true, | |
1489 | }; | |
1490 | ||
c06e6769 | 1491 | const static struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1492 | .regs = &omap4_gpio_regs, |
1493 | .bank_width = 32, | |
1494 | .dbck_flag = true, | |
1495 | }; | |
1496 | ||
1497 | static const struct of_device_id omap_gpio_match[] = { | |
1498 | { | |
1499 | .compatible = "ti,omap4-gpio", | |
1500 | .data = &omap4_pdata, | |
1501 | }, | |
1502 | { | |
1503 | .compatible = "ti,omap3-gpio", | |
1504 | .data = &omap3_pdata, | |
1505 | }, | |
1506 | { | |
1507 | .compatible = "ti,omap2-gpio", | |
1508 | .data = &omap2_pdata, | |
1509 | }, | |
1510 | { }, | |
1511 | }; | |
1512 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1513 | #endif | |
1514 | ||
77640aab VC |
1515 | static struct platform_driver omap_gpio_driver = { |
1516 | .probe = omap_gpio_probe, | |
1517 | .driver = { | |
1518 | .name = "omap_gpio", | |
55b93c32 | 1519 | .pm = &gpio_pm_ops, |
384ebe1c | 1520 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1521 | }, |
1522 | }; | |
1523 | ||
5e1c5ff4 | 1524 | /* |
77640aab VC |
1525 | * gpio driver register needs to be done before |
1526 | * machine_init functions access gpio APIs. | |
1527 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1528 | */ |
77640aab | 1529 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1530 | { |
77640aab | 1531 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1532 | } |
77640aab | 1533 | postcore_initcall(omap_gpio_drv_reg); |