]>
Commit | Line | Data |
---|---|---|
5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
b764a586 | 22 | #include <linux/cpu_pm.h> |
96751fcb | 23 | #include <linux/device.h> |
77640aab | 24 | #include <linux/pm_runtime.h> |
55b93c32 | 25 | #include <linux/pm.h> |
384ebe1c BC |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
b7351b07 | 28 | #include <linux/gpio/driver.h> |
9370084e | 29 | #include <linux/bitops.h> |
4b25408f | 30 | #include <linux/platform_data/gpio-omap.h> |
5e1c5ff4 | 31 | |
e85ec6c3 | 32 | #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF |
2dc983c5 | 33 | |
b764a586 | 34 | #define OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER BIT(2) |
ec0daae6 | 35 | |
6d62e216 C |
36 | struct gpio_regs { |
37 | u32 irqenable1; | |
38 | u32 irqenable2; | |
39 | u32 wake_en; | |
40 | u32 ctrl; | |
41 | u32 oe; | |
42 | u32 leveldetect0; | |
43 | u32 leveldetect1; | |
44 | u32 risingdetect; | |
45 | u32 fallingdetect; | |
46 | u32 dataout; | |
ae547354 NM |
47 | u32 debounce; |
48 | u32 debounce_en; | |
6d62e216 C |
49 | }; |
50 | ||
ec0daae6 TL |
51 | struct gpio_bank; |
52 | ||
53 | struct gpio_omap_funcs { | |
54 | void (*idle_enable_level_quirk)(struct gpio_bank *bank); | |
55 | void (*idle_disable_level_quirk)(struct gpio_bank *bank); | |
56 | }; | |
57 | ||
5e1c5ff4 | 58 | struct gpio_bank { |
03e128ca | 59 | struct list_head node; |
92105bb7 | 60 | void __iomem *base; |
30cefeac | 61 | int irq; |
3ac4fa99 JY |
62 | u32 non_wakeup_gpios; |
63 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 64 | struct gpio_regs context; |
ec0daae6 | 65 | struct gpio_omap_funcs funcs; |
3ac4fa99 | 66 | u32 saved_datain; |
b144ff6f | 67 | u32 level_mask; |
4318f36b | 68 | u32 toggle_mask; |
4dbada2b | 69 | raw_spinlock_t lock; |
450fa54c | 70 | raw_spinlock_t wa_lock; |
52e31344 | 71 | struct gpio_chip chip; |
89db9482 | 72 | struct clk *dbck; |
b764a586 TL |
73 | struct notifier_block nb; |
74 | unsigned int is_suspended:1; | |
058af1ea | 75 | u32 mod_usage; |
fa365e4d | 76 | u32 irq_usage; |
8865b9b6 | 77 | u32 dbck_enable_mask; |
72f83af9 | 78 | bool dbck_enabled; |
d0d665a8 | 79 | bool is_mpuio; |
77640aab | 80 | bool dbck_flag; |
0cde8d03 | 81 | bool loses_context; |
352a2d5b | 82 | bool context_valid; |
5de62b86 | 83 | int stride; |
d5f46247 | 84 | u32 width; |
60a3437d | 85 | int context_loss_count; |
ec0daae6 | 86 | u32 quirks; |
fa87931a | 87 | |
04ebcbd8 | 88 | void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); |
442af140 JK |
89 | void (*set_dataout_multiple)(struct gpio_bank *bank, |
90 | unsigned long *mask, unsigned long *bits); | |
60a3437d | 91 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
92 | |
93 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
94 | }; |
95 | ||
c8eef65a | 96 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 | 97 | |
fa365e4d | 98 | #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) |
b1e9fec2 | 99 | #define LINE_USED(line, offset) (line & (BIT(offset))) |
fa365e4d | 100 | |
3d009c8c TL |
101 | static void omap_gpio_unmask_irq(struct irq_data *d); |
102 | ||
a0e827c6 | 103 | static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) |
ede4d7a5 | 104 | { |
fb655f57 | 105 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
d99f7aec | 106 | return gpiochip_get_data(chip); |
25db711d BC |
107 | } |
108 | ||
a0e827c6 JMC |
109 | static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, |
110 | int is_input) | |
5e1c5ff4 | 111 | { |
92105bb7 | 112 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
113 | u32 l; |
114 | ||
fa87931a | 115 | reg += bank->regs->direction; |
661553b9 | 116 | l = readl_relaxed(reg); |
5e1c5ff4 | 117 | if (is_input) |
b1e9fec2 | 118 | l |= BIT(gpio); |
5e1c5ff4 | 119 | else |
b1e9fec2 | 120 | l &= ~(BIT(gpio)); |
661553b9 | 121 | writel_relaxed(l, reg); |
41d87cbd | 122 | bank->context.oe = l; |
5e1c5ff4 TL |
123 | } |
124 | ||
fa87931a KH |
125 | |
126 | /* set data out value using dedicate set/clear register */ | |
04ebcbd8 | 127 | static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 128 | int enable) |
5e1c5ff4 | 129 | { |
92105bb7 | 130 | void __iomem *reg = bank->base; |
04ebcbd8 | 131 | u32 l = BIT(offset); |
5e1c5ff4 | 132 | |
2c836f7e | 133 | if (enable) { |
fa87931a | 134 | reg += bank->regs->set_dataout; |
2c836f7e TKD |
135 | bank->context.dataout |= l; |
136 | } else { | |
fa87931a | 137 | reg += bank->regs->clr_dataout; |
2c836f7e TKD |
138 | bank->context.dataout &= ~l; |
139 | } | |
5e1c5ff4 | 140 | |
661553b9 | 141 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
142 | } |
143 | ||
fa87931a | 144 | /* set data out value using mask register */ |
04ebcbd8 | 145 | static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, |
a0e827c6 | 146 | int enable) |
5e1c5ff4 | 147 | { |
fa87931a | 148 | void __iomem *reg = bank->base + bank->regs->dataout; |
04ebcbd8 | 149 | u32 gpio_bit = BIT(offset); |
fa87931a | 150 | u32 l; |
5e1c5ff4 | 151 | |
661553b9 | 152 | l = readl_relaxed(reg); |
fa87931a KH |
153 | if (enable) |
154 | l |= gpio_bit; | |
155 | else | |
156 | l &= ~gpio_bit; | |
661553b9 | 157 | writel_relaxed(l, reg); |
41d87cbd | 158 | bank->context.dataout = l; |
5e1c5ff4 TL |
159 | } |
160 | ||
a0e827c6 | 161 | static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) |
b37c45b8 | 162 | { |
fa87931a | 163 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 164 | |
b1e9fec2 | 165 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
5e1c5ff4 | 166 | } |
b37c45b8 | 167 | |
a0e827c6 | 168 | static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) |
b37c45b8 | 169 | { |
fa87931a | 170 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 171 | |
b1e9fec2 | 172 | return (readl_relaxed(reg) & (BIT(offset))) != 0; |
b37c45b8 RQ |
173 | } |
174 | ||
442af140 JK |
175 | /* set multiple data out values using dedicate set/clear register */ |
176 | static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank, | |
177 | unsigned long *mask, | |
178 | unsigned long *bits) | |
179 | { | |
180 | void __iomem *reg = bank->base; | |
181 | u32 l; | |
182 | ||
183 | l = *bits & *mask; | |
184 | writel_relaxed(l, reg + bank->regs->set_dataout); | |
185 | bank->context.dataout |= l; | |
186 | ||
187 | l = ~*bits & *mask; | |
188 | writel_relaxed(l, reg + bank->regs->clr_dataout); | |
189 | bank->context.dataout &= ~l; | |
190 | } | |
191 | ||
192 | /* set multiple data out values using mask register */ | |
193 | static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank, | |
194 | unsigned long *mask, | |
195 | unsigned long *bits) | |
196 | { | |
197 | void __iomem *reg = bank->base + bank->regs->dataout; | |
198 | u32 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); | |
199 | ||
200 | writel_relaxed(l, reg); | |
201 | bank->context.dataout = l; | |
202 | } | |
203 | ||
204 | static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank *bank, | |
205 | unsigned long *mask) | |
206 | { | |
207 | void __iomem *reg = bank->base + bank->regs->datain; | |
208 | ||
209 | return readl_relaxed(reg) & *mask; | |
210 | } | |
211 | ||
212 | static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank *bank, | |
213 | unsigned long *mask) | |
214 | { | |
215 | void __iomem *reg = bank->base + bank->regs->dataout; | |
216 | ||
217 | return readl_relaxed(reg) & *mask; | |
218 | } | |
219 | ||
a0e827c6 | 220 | static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
ece9528e | 221 | { |
661553b9 | 222 | int l = readl_relaxed(base + reg); |
ece9528e | 223 | |
862ff640 | 224 | if (set) |
ece9528e KH |
225 | l |= mask; |
226 | else | |
227 | l &= ~mask; | |
228 | ||
661553b9 | 229 | writel_relaxed(l, base + reg); |
ece9528e | 230 | } |
92105bb7 | 231 | |
a0e827c6 | 232 | static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) |
72f83af9 TKD |
233 | { |
234 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
5d9452e7 | 235 | clk_enable(bank->dbck); |
72f83af9 | 236 | bank->dbck_enabled = true; |
9e303f22 | 237 | |
661553b9 | 238 | writel_relaxed(bank->dbck_enable_mask, |
9e303f22 | 239 | bank->base + bank->regs->debounce_en); |
72f83af9 TKD |
240 | } |
241 | } | |
242 | ||
a0e827c6 | 243 | static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) |
72f83af9 TKD |
244 | { |
245 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
9e303f22 GI |
246 | /* |
247 | * Disable debounce before cutting it's clock. If debounce is | |
248 | * enabled but the clock is not, GPIO module seems to be unable | |
249 | * to detect events and generate interrupts at least on OMAP3. | |
250 | */ | |
661553b9 | 251 | writel_relaxed(0, bank->base + bank->regs->debounce_en); |
9e303f22 | 252 | |
5d9452e7 | 253 | clk_disable(bank->dbck); |
72f83af9 TKD |
254 | bank->dbck_enabled = false; |
255 | } | |
256 | } | |
257 | ||
168ef3d9 | 258 | /** |
a0e827c6 | 259 | * omap2_set_gpio_debounce - low level gpio debounce time |
168ef3d9 | 260 | * @bank: the gpio bank we're acting upon |
4a58d229 | 261 | * @offset: the gpio number on this @bank |
168ef3d9 FB |
262 | * @debounce: debounce time to use |
263 | * | |
e85ec6c3 GS |
264 | * OMAP's debounce time is in 31us steps |
265 | * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 | |
266 | * so we need to convert and round up to the closest unit. | |
83977443 DR |
267 | * |
268 | * Return: 0 on success, negative error otherwise. | |
168ef3d9 | 269 | */ |
83977443 DR |
270 | static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, |
271 | unsigned debounce) | |
168ef3d9 | 272 | { |
9942da0e | 273 | void __iomem *reg; |
168ef3d9 FB |
274 | u32 val; |
275 | u32 l; | |
e85ec6c3 | 276 | bool enable = !!debounce; |
168ef3d9 | 277 | |
77640aab | 278 | if (!bank->dbck_flag) |
83977443 | 279 | return -ENOTSUPP; |
77640aab | 280 | |
e85ec6c3 GS |
281 | if (enable) { |
282 | debounce = DIV_ROUND_UP(debounce, 31) - 1; | |
83977443 DR |
283 | if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) |
284 | return -EINVAL; | |
e85ec6c3 | 285 | } |
168ef3d9 | 286 | |
4a58d229 | 287 | l = BIT(offset); |
168ef3d9 | 288 | |
5d9452e7 | 289 | clk_enable(bank->dbck); |
9942da0e | 290 | reg = bank->base + bank->regs->debounce; |
661553b9 | 291 | writel_relaxed(debounce, reg); |
168ef3d9 | 292 | |
9942da0e | 293 | reg = bank->base + bank->regs->debounce_en; |
661553b9 | 294 | val = readl_relaxed(reg); |
168ef3d9 | 295 | |
e85ec6c3 | 296 | if (enable) |
168ef3d9 | 297 | val |= l; |
6fd9c421 | 298 | else |
168ef3d9 | 299 | val &= ~l; |
f7ec0b0b | 300 | bank->dbck_enable_mask = val; |
168ef3d9 | 301 | |
661553b9 | 302 | writel_relaxed(val, reg); |
5d9452e7 | 303 | clk_disable(bank->dbck); |
6fd9c421 TKD |
304 | /* |
305 | * Enable debounce clock per module. | |
306 | * This call is mandatory because in omap_gpio_request() when | |
307 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
308 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
309 | * used within _gpio_dbck_enable() is still not initialized at | |
310 | * that point. Therefore we have to enable dbck here. | |
311 | */ | |
a0e827c6 | 312 | omap_gpio_dbck_enable(bank); |
ae547354 NM |
313 | if (bank->dbck_enable_mask) { |
314 | bank->context.debounce = debounce; | |
315 | bank->context.debounce_en = val; | |
316 | } | |
83977443 DR |
317 | |
318 | return 0; | |
168ef3d9 FB |
319 | } |
320 | ||
c9c55d92 | 321 | /** |
a0e827c6 | 322 | * omap_clear_gpio_debounce - clear debounce settings for a gpio |
c9c55d92 | 323 | * @bank: the gpio bank we're acting upon |
4a58d229 | 324 | * @offset: the gpio number on this @bank |
c9c55d92 JH |
325 | * |
326 | * If a gpio is using debounce, then clear the debounce enable bit and if | |
327 | * this is the only gpio in this bank using debounce, then clear the debounce | |
328 | * time too. The debounce clock will also be disabled when calling this function | |
329 | * if this is the only gpio in the bank using debounce. | |
330 | */ | |
4a58d229 | 331 | static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) |
c9c55d92 | 332 | { |
4a58d229 | 333 | u32 gpio_bit = BIT(offset); |
c9c55d92 JH |
334 | |
335 | if (!bank->dbck_flag) | |
336 | return; | |
337 | ||
338 | if (!(bank->dbck_enable_mask & gpio_bit)) | |
339 | return; | |
340 | ||
341 | bank->dbck_enable_mask &= ~gpio_bit; | |
342 | bank->context.debounce_en &= ~gpio_bit; | |
661553b9 | 343 | writel_relaxed(bank->context.debounce_en, |
c9c55d92 JH |
344 | bank->base + bank->regs->debounce_en); |
345 | ||
346 | if (!bank->dbck_enable_mask) { | |
347 | bank->context.debounce = 0; | |
661553b9 | 348 | writel_relaxed(bank->context.debounce, bank->base + |
c9c55d92 | 349 | bank->regs->debounce); |
5d9452e7 | 350 | clk_disable(bank->dbck); |
c9c55d92 JH |
351 | bank->dbck_enabled = false; |
352 | } | |
353 | } | |
354 | ||
da38ef3e TL |
355 | /* |
356 | * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain. | |
357 | * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs | |
358 | * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none | |
359 | * are capable waking up the system from off mode. | |
360 | */ | |
361 | static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask) | |
362 | { | |
363 | u32 no_wake = bank->non_wakeup_gpios; | |
364 | ||
365 | if (no_wake) | |
366 | return !!(~no_wake & gpio_mask); | |
367 | ||
368 | return false; | |
369 | } | |
370 | ||
a0e827c6 | 371 | static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, |
00ece7e4 | 372 | unsigned trigger) |
5e1c5ff4 | 373 | { |
3ac4fa99 | 374 | void __iomem *base = bank->base; |
b1e9fec2 | 375 | u32 gpio_bit = BIT(gpio); |
92105bb7 | 376 | |
a0e827c6 JMC |
377 | omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
378 | trigger & IRQ_TYPE_LEVEL_LOW); | |
379 | omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
380 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
381 | omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
382 | trigger & IRQ_TYPE_EDGE_RISING); | |
383 | omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
384 | trigger & IRQ_TYPE_EDGE_FALLING); | |
5e571f38 | 385 | |
41d87cbd | 386 | bank->context.leveldetect0 = |
661553b9 | 387 | readl_relaxed(bank->base + bank->regs->leveldetect0); |
41d87cbd | 388 | bank->context.leveldetect1 = |
661553b9 | 389 | readl_relaxed(bank->base + bank->regs->leveldetect1); |
41d87cbd | 390 | bank->context.risingdetect = |
661553b9 | 391 | readl_relaxed(bank->base + bank->regs->risingdetect); |
41d87cbd | 392 | bank->context.fallingdetect = |
661553b9 | 393 | readl_relaxed(bank->base + bank->regs->fallingdetect); |
41d87cbd TKD |
394 | |
395 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
00ded24c TL |
396 | omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
397 | bank->context.wake_en = | |
398 | readl_relaxed(bank->base + bank->regs->wkup_en); | |
41d87cbd | 399 | } |
5e571f38 | 400 | |
55b220ca | 401 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
da38ef3e | 402 | if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { |
699117a6 CW |
403 | /* |
404 | * Log the edge gpio and manually trigger the IRQ | |
405 | * after resume if the input level changes | |
406 | * to avoid irq lost during PER RET/OFF mode | |
407 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
408 | */ | |
409 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
410 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
411 | else | |
412 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
413 | } | |
5eb3bb9c | 414 | |
9ea14d8c | 415 | bank->level_mask = |
661553b9 VK |
416 | readl_relaxed(bank->base + bank->regs->leveldetect0) | |
417 | readl_relaxed(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
418 | } |
419 | ||
9198bcd3 | 420 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
421 | /* |
422 | * This only applies to chips that can't do both rising and falling edge | |
423 | * detection at once. For all other chips, this function is a noop. | |
424 | */ | |
a0e827c6 | 425 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) |
4318f36b CM |
426 | { |
427 | void __iomem *reg = bank->base; | |
428 | u32 l = 0; | |
429 | ||
5e571f38 | 430 | if (!bank->regs->irqctrl) |
4318f36b | 431 | return; |
5e571f38 TKD |
432 | |
433 | reg += bank->regs->irqctrl; | |
4318f36b | 434 | |
661553b9 | 435 | l = readl_relaxed(reg); |
4318f36b | 436 | if ((l >> gpio) & 1) |
b1e9fec2 | 437 | l &= ~(BIT(gpio)); |
4318f36b | 438 | else |
b1e9fec2 | 439 | l |= BIT(gpio); |
4318f36b | 440 | |
661553b9 | 441 | writel_relaxed(l, reg); |
4318f36b | 442 | } |
5e571f38 | 443 | #else |
a0e827c6 | 444 | static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} |
9198bcd3 | 445 | #endif |
4318f36b | 446 | |
a0e827c6 JMC |
447 | static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, |
448 | unsigned trigger) | |
92105bb7 TL |
449 | { |
450 | void __iomem *reg = bank->base; | |
5e571f38 | 451 | void __iomem *base = bank->base; |
92105bb7 | 452 | u32 l = 0; |
5e1c5ff4 | 453 | |
5e571f38 | 454 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
a0e827c6 | 455 | omap_set_gpio_trigger(bank, gpio, trigger); |
5e571f38 TKD |
456 | } else if (bank->regs->irqctrl) { |
457 | reg += bank->regs->irqctrl; | |
458 | ||
661553b9 | 459 | l = readl_relaxed(reg); |
29501577 | 460 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
b1e9fec2 | 461 | bank->toggle_mask |= BIT(gpio); |
6cab4860 | 462 | if (trigger & IRQ_TYPE_EDGE_RISING) |
b1e9fec2 | 463 | l |= BIT(gpio); |
6cab4860 | 464 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 465 | l &= ~(BIT(gpio)); |
92105bb7 | 466 | else |
5e571f38 TKD |
467 | return -EINVAL; |
468 | ||
661553b9 | 469 | writel_relaxed(l, reg); |
5e571f38 | 470 | } else if (bank->regs->edgectrl1) { |
5e1c5ff4 | 471 | if (gpio & 0x08) |
5e571f38 | 472 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 473 | else |
5e571f38 TKD |
474 | reg += bank->regs->edgectrl1; |
475 | ||
5e1c5ff4 | 476 | gpio &= 0x07; |
661553b9 | 477 | l = readl_relaxed(reg); |
5e1c5ff4 | 478 | l &= ~(3 << (gpio << 1)); |
6cab4860 | 479 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 480 | l |= 2 << (gpio << 1); |
6cab4860 | 481 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
b1e9fec2 | 482 | l |= BIT(gpio << 1); |
5e571f38 TKD |
483 | |
484 | /* Enable wake-up during idle for dynamic tick */ | |
a0e827c6 | 485 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); |
41d87cbd | 486 | bank->context.wake_en = |
661553b9 VK |
487 | readl_relaxed(bank->base + bank->regs->wkup_en); |
488 | writel_relaxed(l, reg); | |
5e1c5ff4 | 489 | } |
92105bb7 | 490 | return 0; |
5e1c5ff4 TL |
491 | } |
492 | ||
a0e827c6 | 493 | static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
494 | { |
495 | if (bank->regs->pinctrl) { | |
496 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
497 | ||
498 | /* Claim the pin for MPU */ | |
b1e9fec2 | 499 | writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); |
fac7fa16 JMC |
500 | } |
501 | ||
502 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
503 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
504 | u32 ctrl; | |
505 | ||
661553b9 | 506 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
507 | /* Module is enabled, clocks are not gated */ |
508 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
661553b9 | 509 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
510 | bank->context.ctrl = ctrl; |
511 | } | |
512 | } | |
513 | ||
a0e827c6 | 514 | static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) |
fac7fa16 JMC |
515 | { |
516 | void __iomem *base = bank->base; | |
517 | ||
518 | if (bank->regs->wkup_en && | |
519 | !LINE_USED(bank->mod_usage, offset) && | |
520 | !LINE_USED(bank->irq_usage, offset)) { | |
521 | /* Disable wake-up during idle for dynamic tick */ | |
a0e827c6 | 522 | omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); |
fac7fa16 | 523 | bank->context.wake_en = |
661553b9 | 524 | readl_relaxed(bank->base + bank->regs->wkup_en); |
fac7fa16 JMC |
525 | } |
526 | ||
527 | if (bank->regs->ctrl && !BANK_USED(bank)) { | |
528 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
529 | u32 ctrl; | |
530 | ||
661553b9 | 531 | ctrl = readl_relaxed(reg); |
fac7fa16 JMC |
532 | /* Module is disabled, clocks are gated */ |
533 | ctrl |= GPIO_MOD_CTRL_BIT; | |
661553b9 | 534 | writel_relaxed(ctrl, reg); |
fac7fa16 JMC |
535 | bank->context.ctrl = ctrl; |
536 | } | |
537 | } | |
538 | ||
b2b20045 | 539 | static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) |
fa365e4d JMC |
540 | { |
541 | void __iomem *reg = bank->base + bank->regs->direction; | |
542 | ||
b2b20045 | 543 | return readl_relaxed(reg) & BIT(offset); |
fa365e4d JMC |
544 | } |
545 | ||
37e14ecf | 546 | static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) |
3d009c8c TL |
547 | { |
548 | if (!LINE_USED(bank->mod_usage, offset)) { | |
549 | omap_enable_gpio_module(bank, offset); | |
550 | omap_set_gpio_direction(bank, offset, 1); | |
551 | } | |
37e14ecf | 552 | bank->irq_usage |= BIT(offset); |
3d009c8c TL |
553 | } |
554 | ||
a0e827c6 | 555 | static int omap_gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 | 556 | { |
a0e827c6 | 557 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
92105bb7 | 558 | int retval; |
a6472533 | 559 | unsigned long flags; |
ea5fbe8d | 560 | unsigned offset = d->hwirq; |
92105bb7 | 561 | |
e5c56ed3 | 562 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 563 | return -EINVAL; |
e5c56ed3 | 564 | |
9ea14d8c TKD |
565 | if (!bank->regs->leveldetect0 && |
566 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
567 | return -EINVAL; |
568 | ||
4dbada2b | 569 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 570 | retval = omap_set_gpio_triggering(bank, offset, type); |
977bd8a9 | 571 | if (retval) { |
627c89b4 | 572 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 | 573 | goto error; |
977bd8a9 | 574 | } |
37e14ecf | 575 | omap_gpio_init_irq(bank, offset); |
b2b20045 | 576 | if (!omap_gpio_is_input(bank, offset)) { |
4dbada2b | 577 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
1562e461 GS |
578 | retval = -EINVAL; |
579 | goto error; | |
fac7fa16 | 580 | } |
4dbada2b | 581 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
582 | |
583 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
43ec2e43 | 584 | irq_set_handler_locked(d, handle_level_irq); |
672e302e | 585 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
80ac93c2 GS |
586 | /* |
587 | * Edge IRQs are already cleared/acked in irq_handler and | |
588 | * not need to be masked, as result handle_edge_irq() | |
589 | * logic is excessed here and may cause lose of interrupts. | |
590 | * So just use handle_simple_irq. | |
591 | */ | |
592 | irq_set_handler_locked(d, handle_simple_irq); | |
672e302e | 593 | |
1562e461 GS |
594 | return 0; |
595 | ||
596 | error: | |
92105bb7 | 597 | return retval; |
5e1c5ff4 TL |
598 | } |
599 | ||
a0e827c6 | 600 | static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 601 | { |
92105bb7 | 602 | void __iomem *reg = bank->base; |
5e1c5ff4 | 603 | |
eef4bec7 | 604 | reg += bank->regs->irqstatus; |
661553b9 | 605 | writel_relaxed(gpio_mask, reg); |
bee7930f HD |
606 | |
607 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
608 | if (bank->regs->irqstatus2) { |
609 | reg = bank->base + bank->regs->irqstatus2; | |
661553b9 | 610 | writel_relaxed(gpio_mask, reg); |
eef4bec7 | 611 | } |
bedfd154 RQ |
612 | |
613 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
661553b9 | 614 | readl_relaxed(reg); |
5e1c5ff4 TL |
615 | } |
616 | ||
9943f261 GS |
617 | static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, |
618 | unsigned offset) | |
5e1c5ff4 | 619 | { |
9943f261 | 620 | omap_clear_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
621 | } |
622 | ||
a0e827c6 | 623 | static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) |
ea6dedd7 ID |
624 | { |
625 | void __iomem *reg = bank->base; | |
99c47707 | 626 | u32 l; |
b1e9fec2 | 627 | u32 mask = (BIT(bank->width)) - 1; |
ea6dedd7 | 628 | |
28f3b5a0 | 629 | reg += bank->regs->irqenable; |
661553b9 | 630 | l = readl_relaxed(reg); |
28f3b5a0 | 631 | if (bank->regs->irqenable_inv) |
99c47707 ID |
632 | l = ~l; |
633 | l &= mask; | |
634 | return l; | |
ea6dedd7 ID |
635 | } |
636 | ||
a0e827c6 | 637 | static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 638 | { |
92105bb7 | 639 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
640 | u32 l; |
641 | ||
28f3b5a0 KH |
642 | if (bank->regs->set_irqenable) { |
643 | reg += bank->regs->set_irqenable; | |
644 | l = gpio_mask; | |
2a900eb7 | 645 | bank->context.irqenable1 |= gpio_mask; |
28f3b5a0 KH |
646 | } else { |
647 | reg += bank->regs->irqenable; | |
661553b9 | 648 | l = readl_relaxed(reg); |
28f3b5a0 KH |
649 | if (bank->regs->irqenable_inv) |
650 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
651 | else |
652 | l |= gpio_mask; | |
2a900eb7 | 653 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
654 | } |
655 | ||
661553b9 | 656 | writel_relaxed(l, reg); |
28f3b5a0 KH |
657 | } |
658 | ||
a0e827c6 | 659 | static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
28f3b5a0 KH |
660 | { |
661 | void __iomem *reg = bank->base; | |
662 | u32 l; | |
663 | ||
664 | if (bank->regs->clr_irqenable) { | |
665 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 666 | l = gpio_mask; |
2a900eb7 | 667 | bank->context.irqenable1 &= ~gpio_mask; |
28f3b5a0 KH |
668 | } else { |
669 | reg += bank->regs->irqenable; | |
661553b9 | 670 | l = readl_relaxed(reg); |
28f3b5a0 | 671 | if (bank->regs->irqenable_inv) |
56739a69 | 672 | l |= gpio_mask; |
92105bb7 | 673 | else |
28f3b5a0 | 674 | l &= ~gpio_mask; |
2a900eb7 | 675 | bank->context.irqenable1 = l; |
5e1c5ff4 | 676 | } |
28f3b5a0 | 677 | |
661553b9 | 678 | writel_relaxed(l, reg); |
5e1c5ff4 TL |
679 | } |
680 | ||
9943f261 GS |
681 | static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, |
682 | unsigned offset, int enable) | |
5e1c5ff4 | 683 | { |
8276536c | 684 | if (enable) |
9943f261 | 685 | omap_enable_gpio_irqbank(bank, BIT(offset)); |
8276536c | 686 | else |
9943f261 | 687 | omap_disable_gpio_irqbank(bank, BIT(offset)); |
5e1c5ff4 TL |
688 | } |
689 | ||
92105bb7 | 690 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
a0e827c6 | 691 | static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 692 | { |
a0e827c6 | 693 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
450fa54c | 694 | |
0c0451e7 | 695 | return irq_set_irq_wake(bank->irq, enable); |
92105bb7 TL |
696 | } |
697 | ||
3ff164e1 | 698 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 699 | { |
d99f7aec | 700 | struct gpio_bank *bank = gpiochip_get_data(chip); |
a6472533 | 701 | unsigned long flags; |
52e31344 | 702 | |
46748073 | 703 | pm_runtime_get_sync(chip->parent); |
92105bb7 | 704 | |
4dbada2b | 705 | raw_spin_lock_irqsave(&bank->lock, flags); |
c3518172 | 706 | omap_enable_gpio_module(bank, offset); |
b1e9fec2 | 707 | bank->mod_usage |= BIT(offset); |
4dbada2b | 708 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
709 | |
710 | return 0; | |
711 | } | |
712 | ||
3ff164e1 | 713 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 714 | { |
d99f7aec | 715 | struct gpio_bank *bank = gpiochip_get_data(chip); |
a6472533 | 716 | unsigned long flags; |
5e1c5ff4 | 717 | |
4dbada2b | 718 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 719 | bank->mod_usage &= ~(BIT(offset)); |
5f982c70 GS |
720 | if (!LINE_USED(bank->irq_usage, offset)) { |
721 | omap_set_gpio_direction(bank, offset, 1); | |
722 | omap_clear_gpio_debounce(bank, offset); | |
723 | } | |
a0e827c6 | 724 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 725 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 726 | |
46748073 | 727 | pm_runtime_put(chip->parent); |
5e1c5ff4 TL |
728 | } |
729 | ||
730 | /* | |
731 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
732 | * avoid missing GPIO interrupts for other lines in the bank. | |
733 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
734 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
735 | * If we wait to unmask individual GPIO lines in the bank after the | |
736 | * line's interrupt handler has been run, we may miss some nested | |
737 | * interrupts. | |
738 | */ | |
450fa54c | 739 | static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) |
5e1c5ff4 | 740 | { |
92105bb7 | 741 | void __iomem *isr_reg = NULL; |
80ac93c2 | 742 | u32 enabled, isr, level_mask; |
3513cdec | 743 | unsigned int bit; |
450fa54c GS |
744 | struct gpio_bank *bank = gpiobank; |
745 | unsigned long wa_lock_flags; | |
235f1eb1 | 746 | unsigned long lock_flags; |
5e1c5ff4 | 747 | |
eef4bec7 | 748 | isr_reg = bank->base + bank->regs->irqstatus; |
b1cc4c55 EK |
749 | if (WARN_ON(!isr_reg)) |
750 | goto exit; | |
751 | ||
5284521a TL |
752 | if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), |
753 | "gpio irq%i while runtime suspended?\n", irq)) | |
754 | return IRQ_NONE; | |
450fa54c | 755 | |
e83507b7 | 756 | while (1) { |
235f1eb1 GS |
757 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
758 | ||
a0e827c6 | 759 | enabled = omap_get_gpio_irqbank_mask(bank); |
80ac93c2 | 760 | isr = readl_relaxed(isr_reg) & enabled; |
6e60e79a | 761 | |
9ea14d8c | 762 | if (bank->level_mask) |
b144ff6f | 763 | level_mask = bank->level_mask & enabled; |
80ac93c2 GS |
764 | else |
765 | level_mask = 0; | |
6e60e79a TL |
766 | |
767 | /* clear edge sensitive interrupts before handler(s) are | |
768 | called so that we don't miss any interrupt occurred while | |
769 | executing them */ | |
80ac93c2 GS |
770 | if (isr & ~level_mask) |
771 | omap_clear_gpio_irqbank(bank, isr & ~level_mask); | |
6e60e79a | 772 | |
235f1eb1 GS |
773 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
774 | ||
92105bb7 TL |
775 | if (!isr) |
776 | break; | |
777 | ||
3513cdec JH |
778 | while (isr) { |
779 | bit = __ffs(isr); | |
b1e9fec2 | 780 | isr &= ~(BIT(bit)); |
25db711d | 781 | |
235f1eb1 | 782 | raw_spin_lock_irqsave(&bank->lock, lock_flags); |
4318f36b CM |
783 | /* |
784 | * Some chips can't respond to both rising and falling | |
785 | * at the same time. If this irq was requested with | |
786 | * both flags, we need to flip the ICR data for the IRQ | |
787 | * to respond to the IRQ for the opposite direction. | |
788 | * This will be indicated in the bank toggle_mask. | |
789 | */ | |
b1e9fec2 | 790 | if (bank->toggle_mask & (BIT(bit))) |
a0e827c6 | 791 | omap_toggle_gpio_edge_triggering(bank, bit); |
4318f36b | 792 | |
235f1eb1 GS |
793 | raw_spin_unlock_irqrestore(&bank->lock, lock_flags); |
794 | ||
450fa54c GS |
795 | raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); |
796 | ||
f0fbe7bc | 797 | generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, |
fb655f57 | 798 | bit)); |
450fa54c GS |
799 | |
800 | raw_spin_unlock_irqrestore(&bank->wa_lock, | |
801 | wa_lock_flags); | |
92105bb7 | 802 | } |
1a8bfa1e | 803 | } |
b1cc4c55 | 804 | exit: |
450fa54c | 805 | return IRQ_HANDLED; |
5e1c5ff4 TL |
806 | } |
807 | ||
3d009c8c TL |
808 | static unsigned int omap_gpio_irq_startup(struct irq_data *d) |
809 | { | |
810 | struct gpio_bank *bank = omap_irq_data_get_bank(d); | |
3d009c8c | 811 | unsigned long flags; |
37e14ecf | 812 | unsigned offset = d->hwirq; |
3d009c8c | 813 | |
4dbada2b | 814 | raw_spin_lock_irqsave(&bank->lock, flags); |
121dcb76 GS |
815 | |
816 | if (!LINE_USED(bank->mod_usage, offset)) | |
817 | omap_set_gpio_direction(bank, offset, 1); | |
818 | else if (!omap_gpio_is_input(bank, offset)) | |
819 | goto err; | |
820 | omap_enable_gpio_module(bank, offset); | |
821 | bank->irq_usage |= BIT(offset); | |
822 | ||
4dbada2b | 823 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
3d009c8c TL |
824 | omap_gpio_unmask_irq(d); |
825 | ||
826 | return 0; | |
121dcb76 | 827 | err: |
4dbada2b | 828 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
121dcb76 | 829 | return -EINVAL; |
3d009c8c TL |
830 | } |
831 | ||
a0e827c6 | 832 | static void omap_gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 833 | { |
a0e827c6 | 834 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
85ec7b97 | 835 | unsigned long flags; |
9943f261 | 836 | unsigned offset = d->hwirq; |
4196dd6b | 837 | |
4dbada2b | 838 | raw_spin_lock_irqsave(&bank->lock, flags); |
b1e9fec2 | 839 | bank->irq_usage &= ~(BIT(offset)); |
6e96c1b5 GS |
840 | omap_set_gpio_irqenable(bank, offset, 0); |
841 | omap_clear_gpio_irqstatus(bank, offset); | |
842 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
843 | if (!LINE_USED(bank->mod_usage, offset)) | |
844 | omap_clear_gpio_debounce(bank, offset); | |
a0e827c6 | 845 | omap_disable_gpio_module(bank, offset); |
4dbada2b | 846 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
aca82d1c GS |
847 | } |
848 | ||
849 | static void omap_gpio_irq_bus_lock(struct irq_data *data) | |
850 | { | |
851 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
852 | ||
46748073 | 853 | pm_runtime_get_sync(bank->chip.parent); |
aca82d1c GS |
854 | } |
855 | ||
856 | static void gpio_irq_bus_sync_unlock(struct irq_data *data) | |
857 | { | |
858 | struct gpio_bank *bank = omap_irq_data_get_bank(data); | |
fac7fa16 | 859 | |
46748073 | 860 | pm_runtime_put(bank->chip.parent); |
4196dd6b TL |
861 | } |
862 | ||
a0e827c6 | 863 | static void omap_gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 864 | { |
a0e827c6 | 865 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 866 | unsigned offset = d->hwirq; |
5e1c5ff4 | 867 | |
9943f261 | 868 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 TL |
869 | } |
870 | ||
a0e827c6 | 871 | static void omap_gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 872 | { |
a0e827c6 | 873 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 874 | unsigned offset = d->hwirq; |
85ec7b97 | 875 | unsigned long flags; |
5e1c5ff4 | 876 | |
4dbada2b | 877 | raw_spin_lock_irqsave(&bank->lock, flags); |
9943f261 GS |
878 | omap_set_gpio_irqenable(bank, offset, 0); |
879 | omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); | |
4dbada2b | 880 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
881 | } |
882 | ||
a0e827c6 | 883 | static void omap_gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 884 | { |
a0e827c6 | 885 | struct gpio_bank *bank = omap_irq_data_get_bank(d); |
9943f261 | 886 | unsigned offset = d->hwirq; |
8c04a176 | 887 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 888 | unsigned long flags; |
55b6019a | 889 | |
4dbada2b | 890 | raw_spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 891 | if (trigger) |
9943f261 | 892 | omap_set_gpio_triggering(bank, offset, trigger); |
b144ff6f | 893 | |
d01849f7 RK |
894 | omap_set_gpio_irqenable(bank, offset, 1); |
895 | ||
896 | /* | |
897 | * For level-triggered GPIOs, clearing must be done after the source | |
898 | * is cleared, thus after the handler has run. OMAP4 needs this done | |
899 | * after enabing the interrupt to clear the wakeup status. | |
900 | */ | |
901 | if (bank->level_mask & BIT(offset)) | |
9943f261 | 902 | omap_clear_gpio_irqstatus(bank, offset); |
5e1c5ff4 | 903 | |
4dbada2b | 904 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
905 | } |
906 | ||
ec0daae6 TL |
907 | /* |
908 | * Only edges can generate a wakeup event to the PRCM. | |
909 | * | |
910 | * Therefore, ensure any wake-up capable GPIOs have | |
911 | * edge-detection enabled before going idle to ensure a wakeup | |
912 | * to the PRCM is generated on a GPIO transition. (c.f. 34xx | |
913 | * NDA TRM 25.5.3.1) | |
914 | * | |
915 | * The normal values will be restored upon ->runtime_resume() | |
916 | * by writing back the values saved in bank->context. | |
917 | */ | |
918 | static void __maybe_unused | |
919 | omap2_gpio_enable_level_quirk(struct gpio_bank *bank) | |
920 | { | |
921 | u32 wake_low, wake_hi; | |
922 | ||
923 | /* Enable additional edge detection for level gpios for idle */ | |
924 | wake_low = bank->context.leveldetect0 & bank->context.wake_en; | |
925 | if (wake_low) | |
926 | writel_relaxed(wake_low | bank->context.fallingdetect, | |
927 | bank->base + bank->regs->fallingdetect); | |
928 | ||
929 | wake_hi = bank->context.leveldetect1 & bank->context.wake_en; | |
930 | if (wake_hi) | |
931 | writel_relaxed(wake_hi | bank->context.risingdetect, | |
932 | bank->base + bank->regs->risingdetect); | |
933 | } | |
934 | ||
935 | static void __maybe_unused | |
936 | omap2_gpio_disable_level_quirk(struct gpio_bank *bank) | |
937 | { | |
938 | /* Disable edge detection for level gpios after idle */ | |
939 | writel_relaxed(bank->context.fallingdetect, | |
940 | bank->base + bank->regs->fallingdetect); | |
941 | writel_relaxed(bank->context.risingdetect, | |
942 | bank->base + bank->regs->risingdetect); | |
943 | } | |
944 | ||
e5c56ed3 DB |
945 | /*---------------------------------------------------------------------*/ |
946 | ||
79ee031f | 947 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 948 | { |
a3f4f728 | 949 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
950 | void __iomem *mask_reg = bank->base + |
951 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 952 | unsigned long flags; |
11a78b79 | 953 | |
4dbada2b | 954 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 955 | writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); |
4dbada2b | 956 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
957 | |
958 | return 0; | |
959 | } | |
960 | ||
79ee031f | 961 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 962 | { |
a3f4f728 | 963 | struct gpio_bank *bank = dev_get_drvdata(dev); |
5de62b86 TL |
964 | void __iomem *mask_reg = bank->base + |
965 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 966 | unsigned long flags; |
11a78b79 | 967 | |
4dbada2b | 968 | raw_spin_lock_irqsave(&bank->lock, flags); |
661553b9 | 969 | writel_relaxed(bank->context.wake_en, mask_reg); |
4dbada2b | 970 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
971 | |
972 | return 0; | |
973 | } | |
974 | ||
47145210 | 975 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
976 | .suspend_noirq = omap_mpuio_suspend_noirq, |
977 | .resume_noirq = omap_mpuio_resume_noirq, | |
978 | }; | |
979 | ||
3c437ffd | 980 | /* use platform_driver for this. */ |
11a78b79 | 981 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
982 | .driver = { |
983 | .name = "mpuio", | |
79ee031f | 984 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
985 | }, |
986 | }; | |
987 | ||
988 | static struct platform_device omap_mpuio_device = { | |
989 | .name = "mpuio", | |
990 | .id = -1, | |
991 | .dev = { | |
992 | .driver = &omap_mpuio_driver.driver, | |
993 | } | |
994 | /* could list the /proc/iomem resources */ | |
995 | }; | |
996 | ||
a0e827c6 | 997 | static inline void omap_mpuio_init(struct gpio_bank *bank) |
11a78b79 | 998 | { |
77640aab | 999 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 1000 | |
11a78b79 DB |
1001 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1002 | (void) platform_device_register(&omap_mpuio_device); | |
1003 | } | |
1004 | ||
e5c56ed3 | 1005 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 1006 | |
a0e827c6 | 1007 | static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
9370084e YY |
1008 | { |
1009 | struct gpio_bank *bank; | |
1010 | unsigned long flags; | |
1011 | void __iomem *reg; | |
1012 | int dir; | |
1013 | ||
d99f7aec | 1014 | bank = gpiochip_get_data(chip); |
9370084e | 1015 | reg = bank->base + bank->regs->direction; |
4dbada2b | 1016 | raw_spin_lock_irqsave(&bank->lock, flags); |
9370084e | 1017 | dir = !!(readl_relaxed(reg) & BIT(offset)); |
4dbada2b | 1018 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
9370084e YY |
1019 | return dir; |
1020 | } | |
1021 | ||
a0e827c6 | 1022 | static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) |
52e31344 DB |
1023 | { |
1024 | struct gpio_bank *bank; | |
1025 | unsigned long flags; | |
1026 | ||
d99f7aec | 1027 | bank = gpiochip_get_data(chip); |
4dbada2b | 1028 | raw_spin_lock_irqsave(&bank->lock, flags); |
a0e827c6 | 1029 | omap_set_gpio_direction(bank, offset, 1); |
4dbada2b | 1030 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
1031 | return 0; |
1032 | } | |
1033 | ||
a0e827c6 | 1034 | static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) |
52e31344 | 1035 | { |
b37c45b8 | 1036 | struct gpio_bank *bank; |
b37c45b8 | 1037 | |
d99f7aec | 1038 | bank = gpiochip_get_data(chip); |
b37c45b8 | 1039 | |
b2b20045 | 1040 | if (omap_gpio_is_input(bank, offset)) |
a0e827c6 | 1041 | return omap_get_gpio_datain(bank, offset); |
b37c45b8 | 1042 | else |
a0e827c6 | 1043 | return omap_get_gpio_dataout(bank, offset); |
52e31344 DB |
1044 | } |
1045 | ||
a0e827c6 | 1046 | static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
1047 | { |
1048 | struct gpio_bank *bank; | |
1049 | unsigned long flags; | |
1050 | ||
d99f7aec | 1051 | bank = gpiochip_get_data(chip); |
4dbada2b | 1052 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 1053 | bank->set_dataout(bank, offset, value); |
a0e827c6 | 1054 | omap_set_gpio_direction(bank, offset, 0); |
4dbada2b | 1055 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
2f56e0a5 | 1056 | return 0; |
52e31344 DB |
1057 | } |
1058 | ||
442af140 JK |
1059 | static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
1060 | unsigned long *bits) | |
1061 | { | |
1062 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
1063 | void __iomem *reg = bank->base + bank->regs->direction; | |
1064 | unsigned long in = readl_relaxed(reg), l; | |
1065 | ||
1066 | *bits = 0; | |
1067 | ||
1068 | l = in & *mask; | |
1069 | if (l) | |
1070 | *bits |= omap_get_gpio_datain_multiple(bank, &l); | |
1071 | ||
1072 | l = ~in & *mask; | |
1073 | if (l) | |
1074 | *bits |= omap_get_gpio_dataout_multiple(bank, &l); | |
1075 | ||
1076 | return 0; | |
1077 | } | |
1078 | ||
a0e827c6 JMC |
1079 | static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1080 | unsigned debounce) | |
168ef3d9 FB |
1081 | { |
1082 | struct gpio_bank *bank; | |
1083 | unsigned long flags; | |
83977443 | 1084 | int ret; |
168ef3d9 | 1085 | |
d99f7aec | 1086 | bank = gpiochip_get_data(chip); |
77640aab | 1087 | |
4dbada2b | 1088 | raw_spin_lock_irqsave(&bank->lock, flags); |
83977443 | 1089 | ret = omap2_set_gpio_debounce(bank, offset, debounce); |
4dbada2b | 1090 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
168ef3d9 | 1091 | |
83977443 DR |
1092 | if (ret) |
1093 | dev_info(chip->parent, | |
1094 | "Could not set line %u debounce to %u microseconds (%d)", | |
1095 | offset, debounce, ret); | |
1096 | ||
1097 | return ret; | |
168ef3d9 FB |
1098 | } |
1099 | ||
2956b5d9 MW |
1100 | static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
1101 | unsigned long config) | |
1102 | { | |
1103 | u32 debounce; | |
1104 | ||
1105 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
1106 | return -ENOTSUPP; | |
1107 | ||
1108 | debounce = pinconf_to_config_argument(config); | |
1109 | return omap_gpio_debounce(chip, offset, debounce); | |
1110 | } | |
1111 | ||
a0e827c6 | 1112 | static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
52e31344 DB |
1113 | { |
1114 | struct gpio_bank *bank; | |
1115 | unsigned long flags; | |
1116 | ||
d99f7aec | 1117 | bank = gpiochip_get_data(chip); |
4dbada2b | 1118 | raw_spin_lock_irqsave(&bank->lock, flags); |
fa87931a | 1119 | bank->set_dataout(bank, offset, value); |
4dbada2b | 1120 | raw_spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 DB |
1121 | } |
1122 | ||
442af140 JK |
1123 | static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, |
1124 | unsigned long *bits) | |
1125 | { | |
1126 | struct gpio_bank *bank = gpiochip_get_data(chip); | |
1127 | unsigned long flags; | |
1128 | ||
1129 | raw_spin_lock_irqsave(&bank->lock, flags); | |
1130 | bank->set_dataout_multiple(bank, mask, bits); | |
1131 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
1132 | } | |
1133 | ||
52e31344 DB |
1134 | /*---------------------------------------------------------------------*/ |
1135 | ||
e4b2ae7a | 1136 | static void omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 1137 | { |
e5ff4440 | 1138 | static bool called; |
9f7065da TL |
1139 | u32 rev; |
1140 | ||
e5ff4440 | 1141 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
1142 | return; |
1143 | ||
661553b9 | 1144 | rev = readw_relaxed(bank->base + bank->regs->revision); |
e5ff4440 | 1145 | pr_info("OMAP GPIO hardware version %d.%d\n", |
9f7065da | 1146 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
1147 | |
1148 | called = true; | |
9f7065da TL |
1149 | } |
1150 | ||
03e128ca | 1151 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 1152 | { |
ab985f0f TKD |
1153 | void __iomem *base = bank->base; |
1154 | u32 l = 0xffffffff; | |
2fae7fbe | 1155 | |
ab985f0f TKD |
1156 | if (bank->width == 16) |
1157 | l = 0xffff; | |
1158 | ||
d0d665a8 | 1159 | if (bank->is_mpuio) { |
661553b9 | 1160 | writel_relaxed(l, bank->base + bank->regs->irqenable); |
ab985f0f | 1161 | return; |
2fae7fbe | 1162 | } |
ab985f0f | 1163 | |
a0e827c6 JMC |
1164 | omap_gpio_rmw(base, bank->regs->irqenable, l, |
1165 | bank->regs->irqenable_inv); | |
1166 | omap_gpio_rmw(base, bank->regs->irqstatus, l, | |
1167 | !bank->regs->irqenable_inv); | |
ab985f0f | 1168 | if (bank->regs->debounce_en) |
661553b9 | 1169 | writel_relaxed(0, base + bank->regs->debounce_en); |
ab985f0f | 1170 | |
2dc983c5 | 1171 | /* Save OE default value (0xffffffff) in the context */ |
661553b9 | 1172 | bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); |
ab985f0f TKD |
1173 | /* Initialize interface clk ungated, module enabled */ |
1174 | if (bank->regs->ctrl) | |
661553b9 | 1175 | writel_relaxed(0, base + bank->regs->ctrl); |
2fae7fbe VC |
1176 | } |
1177 | ||
46824e22 | 1178 | static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) |
2fae7fbe | 1179 | { |
81930328 | 1180 | struct gpio_irq_chip *irq; |
2fae7fbe | 1181 | static int gpio; |
088413bc | 1182 | const char *label; |
fb655f57 | 1183 | int irq_base = 0; |
6ef7f385 | 1184 | int ret; |
2fae7fbe | 1185 | |
2fae7fbe VC |
1186 | /* |
1187 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1188 | * over to the generic ones | |
1189 | */ | |
1190 | bank->chip.request = omap_gpio_request; | |
1191 | bank->chip.free = omap_gpio_free; | |
a0e827c6 JMC |
1192 | bank->chip.get_direction = omap_gpio_get_direction; |
1193 | bank->chip.direction_input = omap_gpio_input; | |
1194 | bank->chip.get = omap_gpio_get; | |
442af140 | 1195 | bank->chip.get_multiple = omap_gpio_get_multiple; |
a0e827c6 | 1196 | bank->chip.direction_output = omap_gpio_output; |
2956b5d9 | 1197 | bank->chip.set_config = omap_gpio_set_config; |
a0e827c6 | 1198 | bank->chip.set = omap_gpio_set; |
442af140 | 1199 | bank->chip.set_multiple = omap_gpio_set_multiple; |
d0d665a8 | 1200 | if (bank->is_mpuio) { |
2fae7fbe | 1201 | bank->chip.label = "mpuio"; |
6ed87c5b | 1202 | if (bank->regs->wkup_en) |
58383c78 | 1203 | bank->chip.parent = &omap_mpuio_device.dev; |
2fae7fbe VC |
1204 | bank->chip.base = OMAP_MPUIO(0); |
1205 | } else { | |
088413bc LW |
1206 | label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", |
1207 | gpio, gpio + bank->width - 1); | |
1208 | if (!label) | |
1209 | return -ENOMEM; | |
1210 | bank->chip.label = label; | |
2fae7fbe | 1211 | bank->chip.base = gpio; |
2fae7fbe | 1212 | } |
d5f46247 | 1213 | bank->chip.ngpio = bank->width; |
2fae7fbe | 1214 | |
fb655f57 JMC |
1215 | #ifdef CONFIG_ARCH_OMAP1 |
1216 | /* | |
1217 | * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop | |
1218 | * irq_alloc_descs() since a base IRQ offset will no longer be needed. | |
1219 | */ | |
2ed36f30 BG |
1220 | irq_base = devm_irq_alloc_descs(bank->chip.parent, |
1221 | -1, 0, bank->width, 0); | |
fb655f57 | 1222 | if (irq_base < 0) { |
7b1e5dc8 | 1223 | dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); |
fb655f57 JMC |
1224 | return -ENODEV; |
1225 | } | |
1226 | #endif | |
1227 | ||
d2d05c65 TL |
1228 | /* MPUIO is a bit different, reading IRQ status clears it */ |
1229 | if (bank->is_mpuio) { | |
1230 | irqc->irq_ack = dummy_irq_chip.irq_ack; | |
d2d05c65 TL |
1231 | if (!bank->regs->wkup_en) |
1232 | irqc->irq_set_wake = NULL; | |
1233 | } | |
1234 | ||
81930328 GS |
1235 | irq = &bank->chip.irq; |
1236 | irq->chip = irqc; | |
1237 | irq->handler = handle_bad_irq; | |
1238 | irq->default_type = IRQ_TYPE_NONE; | |
1239 | irq->num_parents = 1; | |
1240 | irq->parents = &bank->irq; | |
1241 | irq->first = irq_base; | |
fb655f57 | 1242 | |
81930328 | 1243 | ret = gpiochip_add_data(&bank->chip, bank); |
fb655f57 | 1244 | if (ret) { |
7b1e5dc8 | 1245 | dev_err(bank->chip.parent, |
81930328 GS |
1246 | "Could not register gpio chip %d\n", ret); |
1247 | return ret; | |
fb655f57 JMC |
1248 | } |
1249 | ||
7b1e5dc8 GS |
1250 | ret = devm_request_irq(bank->chip.parent, bank->irq, |
1251 | omap_gpio_irq_handler, | |
1252 | 0, dev_name(bank->chip.parent), bank); | |
450fa54c GS |
1253 | if (ret) |
1254 | gpiochip_remove(&bank->chip); | |
1255 | ||
81930328 GS |
1256 | if (!bank->is_mpuio) |
1257 | gpio += bank->width; | |
1258 | ||
450fa54c | 1259 | return ret; |
2fae7fbe VC |
1260 | } |
1261 | ||
b764a586 TL |
1262 | static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context); |
1263 | static void omap_gpio_unidle(struct gpio_bank *bank); | |
1264 | ||
1265 | static int gpio_omap_cpu_notifier(struct notifier_block *nb, | |
1266 | unsigned long cmd, void *v) | |
1267 | { | |
1268 | struct gpio_bank *bank; | |
b764a586 TL |
1269 | unsigned long flags; |
1270 | ||
1271 | bank = container_of(nb, struct gpio_bank, nb); | |
b764a586 TL |
1272 | |
1273 | raw_spin_lock_irqsave(&bank->lock, flags); | |
1274 | switch (cmd) { | |
1275 | case CPU_CLUSTER_PM_ENTER: | |
1276 | if (bank->is_suspended) | |
1277 | break; | |
1278 | omap_gpio_idle(bank, true); | |
1279 | break; | |
1280 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
1281 | case CPU_CLUSTER_PM_EXIT: | |
1282 | if (bank->is_suspended) | |
1283 | break; | |
1284 | omap_gpio_unidle(bank); | |
1285 | break; | |
1286 | } | |
1287 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
1288 | ||
1289 | return NOTIFY_OK; | |
1290 | } | |
1291 | ||
384ebe1c BC |
1292 | static const struct of_device_id omap_gpio_match[]; |
1293 | ||
3836309d | 1294 | static int omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1295 | { |
862ff640 | 1296 | struct device *dev = &pdev->dev; |
384ebe1c BC |
1297 | struct device_node *node = dev->of_node; |
1298 | const struct of_device_id *match; | |
f6817a2c | 1299 | const struct omap_gpio_platform_data *pdata; |
77640aab | 1300 | struct resource *res; |
5e1c5ff4 | 1301 | struct gpio_bank *bank; |
46824e22 | 1302 | struct irq_chip *irqc; |
6ef7f385 | 1303 | int ret; |
5e1c5ff4 | 1304 | |
384ebe1c BC |
1305 | match = of_match_device(of_match_ptr(omap_gpio_match), dev); |
1306 | ||
e56aee18 | 1307 | pdata = match ? match->data : dev_get_platdata(dev); |
384ebe1c | 1308 | if (!pdata) |
96751fcb | 1309 | return -EINVAL; |
5492fb1a | 1310 | |
f97364c9 | 1311 | bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); |
9117d40b | 1312 | if (!bank) |
96751fcb | 1313 | return -ENOMEM; |
92105bb7 | 1314 | |
46824e22 NM |
1315 | irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); |
1316 | if (!irqc) | |
1317 | return -ENOMEM; | |
1318 | ||
3d009c8c | 1319 | irqc->irq_startup = omap_gpio_irq_startup, |
46824e22 NM |
1320 | irqc->irq_shutdown = omap_gpio_irq_shutdown, |
1321 | irqc->irq_ack = omap_gpio_ack_irq, | |
1322 | irqc->irq_mask = omap_gpio_mask_irq, | |
1323 | irqc->irq_unmask = omap_gpio_unmask_irq, | |
1324 | irqc->irq_set_type = omap_gpio_irq_type, | |
1325 | irqc->irq_set_wake = omap_gpio_wake_enable, | |
aca82d1c GS |
1326 | irqc->irq_bus_lock = omap_gpio_irq_bus_lock, |
1327 | irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, | |
46824e22 | 1328 | irqc->name = dev_name(&pdev->dev); |
0c0451e7 | 1329 | irqc->flags = IRQCHIP_MASK_ON_SUSPEND; |
46748073 | 1330 | irqc->parent_device = dev; |
46824e22 | 1331 | |
89d18e3a GS |
1332 | bank->irq = platform_get_irq(pdev, 0); |
1333 | if (bank->irq <= 0) { | |
1334 | if (!bank->irq) | |
1335 | bank->irq = -ENXIO; | |
1336 | if (bank->irq != -EPROBE_DEFER) | |
1337 | dev_err(dev, | |
1338 | "can't get irq resource ret=%d\n", bank->irq); | |
1339 | return bank->irq; | |
44169075 | 1340 | } |
5e1c5ff4 | 1341 | |
58383c78 | 1342 | bank->chip.parent = dev; |
c23837ce | 1343 | bank->chip.owner = THIS_MODULE; |
77640aab | 1344 | bank->dbck_flag = pdata->dbck_flag; |
ec0daae6 | 1345 | bank->quirks = pdata->quirks; |
5de62b86 | 1346 | bank->stride = pdata->bank_stride; |
d5f46247 | 1347 | bank->width = pdata->bank_width; |
d0d665a8 | 1348 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1349 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
fa87931a | 1350 | bank->regs = pdata->regs; |
384ebe1c BC |
1351 | #ifdef CONFIG_OF_GPIO |
1352 | bank->chip.of_node = of_node_get(node); | |
1353 | #endif | |
ec0daae6 | 1354 | |
a2797bea JH |
1355 | if (node) { |
1356 | if (!of_property_read_bool(node, "ti,gpio-always-on")) | |
1357 | bank->loses_context = true; | |
1358 | } else { | |
1359 | bank->loses_context = pdata->loses_context; | |
352a2d5b JH |
1360 | |
1361 | if (bank->loses_context) | |
1362 | bank->get_context_loss_count = | |
1363 | pdata->get_context_loss_count; | |
384ebe1c BC |
1364 | } |
1365 | ||
442af140 | 1366 | if (bank->regs->set_dataout && bank->regs->clr_dataout) { |
a0e827c6 | 1367 | bank->set_dataout = omap_set_gpio_dataout_reg; |
442af140 JK |
1368 | bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple; |
1369 | } else { | |
a0e827c6 | 1370 | bank->set_dataout = omap_set_gpio_dataout_mask; |
442af140 JK |
1371 | bank->set_dataout_multiple = |
1372 | omap_set_gpio_dataout_mask_multiple; | |
1373 | } | |
9f7065da | 1374 | |
00ded24c | 1375 | if (bank->quirks & OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER) { |
ec0daae6 TL |
1376 | bank->funcs.idle_enable_level_quirk = |
1377 | omap2_gpio_enable_level_quirk; | |
1378 | bank->funcs.idle_disable_level_quirk = | |
1379 | omap2_gpio_disable_level_quirk; | |
1380 | } | |
1381 | ||
4dbada2b | 1382 | raw_spin_lock_init(&bank->lock); |
450fa54c | 1383 | raw_spin_lock_init(&bank->wa_lock); |
9f7065da | 1384 | |
77640aab VC |
1385 | /* Static mapping, never released */ |
1386 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
717f70e3 JH |
1387 | bank->base = devm_ioremap_resource(dev, res); |
1388 | if (IS_ERR(bank->base)) { | |
717f70e3 | 1389 | return PTR_ERR(bank->base); |
5e1c5ff4 TL |
1390 | } |
1391 | ||
5d9452e7 | 1392 | if (bank->dbck_flag) { |
7b1e5dc8 | 1393 | bank->dbck = devm_clk_get(dev, "dbclk"); |
5d9452e7 | 1394 | if (IS_ERR(bank->dbck)) { |
7b1e5dc8 | 1395 | dev_err(dev, |
5d9452e7 GS |
1396 | "Could not get gpio dbck. Disable debounce\n"); |
1397 | bank->dbck_flag = false; | |
1398 | } else { | |
1399 | clk_prepare(bank->dbck); | |
1400 | } | |
1401 | } | |
1402 | ||
065cd795 TKD |
1403 | platform_set_drvdata(pdev, bank); |
1404 | ||
7b1e5dc8 | 1405 | pm_runtime_enable(dev); |
7b1e5dc8 | 1406 | pm_runtime_get_sync(dev); |
77640aab | 1407 | |
d0d665a8 | 1408 | if (bank->is_mpuio) |
a0e827c6 | 1409 | omap_mpuio_init(bank); |
ab985f0f | 1410 | |
03e128ca | 1411 | omap_gpio_mod_init(bank); |
6ef7f385 | 1412 | |
46824e22 | 1413 | ret = omap_gpio_chip_init(bank, irqc); |
5e606abe | 1414 | if (ret) { |
7b1e5dc8 GS |
1415 | pm_runtime_put_sync(dev); |
1416 | pm_runtime_disable(dev); | |
e2c3c196 AY |
1417 | if (bank->dbck_flag) |
1418 | clk_unprepare(bank->dbck); | |
6ef7f385 | 1419 | return ret; |
5e606abe | 1420 | } |
6ef7f385 | 1421 | |
9a748053 | 1422 | omap_gpio_show_rev(bank); |
9f7065da | 1423 | |
b764a586 TL |
1424 | if (bank->funcs.idle_enable_level_quirk && |
1425 | bank->funcs.idle_disable_level_quirk) { | |
1426 | bank->nb.notifier_call = gpio_omap_cpu_notifier; | |
1427 | cpu_pm_register_notifier(&bank->nb); | |
1428 | } | |
1429 | ||
7b1e5dc8 | 1430 | pm_runtime_put(dev); |
55b93c32 | 1431 | |
879fe324 | 1432 | return 0; |
5e1c5ff4 TL |
1433 | } |
1434 | ||
cac089f9 TL |
1435 | static int omap_gpio_remove(struct platform_device *pdev) |
1436 | { | |
1437 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1438 | ||
b764a586 TL |
1439 | if (bank->nb.notifier_call) |
1440 | cpu_pm_unregister_notifier(&bank->nb); | |
cac089f9 TL |
1441 | list_del(&bank->node); |
1442 | gpiochip_remove(&bank->chip); | |
7b1e5dc8 | 1443 | pm_runtime_disable(&pdev->dev); |
5d9452e7 GS |
1444 | if (bank->dbck_flag) |
1445 | clk_unprepare(bank->dbck); | |
cac089f9 TL |
1446 | |
1447 | return 0; | |
1448 | } | |
1449 | ||
60a3437d | 1450 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1451 | |
b764a586 | 1452 | static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) |
3ac4fa99 | 1453 | { |
b764a586 | 1454 | struct device *dev = bank->chip.parent; |
21e2118f TL |
1455 | void __iomem *base = bank->base; |
1456 | u32 nowake; | |
1457 | ||
1458 | bank->saved_datain = readl_relaxed(base + bank->regs->datain); | |
68942edb | 1459 | |
ec0daae6 TL |
1460 | if (bank->funcs.idle_enable_level_quirk) |
1461 | bank->funcs.idle_enable_level_quirk(bank); | |
68942edb | 1462 | |
b3c64bc3 KH |
1463 | if (!bank->enabled_non_wakeup_gpios) |
1464 | goto update_gpio_context_count; | |
1465 | ||
b764a586 | 1466 | if (!may_lose_context) |
41d87cbd | 1467 | goto update_gpio_context_count; |
b764a586 | 1468 | |
2dc983c5 | 1469 | /* |
21e2118f | 1470 | * If going to OFF, remove triggering for all wkup domain |
2dc983c5 TKD |
1471 | * non-wakeup GPIOs. Otherwise spurious IRQs will be |
1472 | * generated. See OMAP2420 Errata item 1.101. | |
1473 | */ | |
21e2118f TL |
1474 | if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { |
1475 | nowake = bank->enabled_non_wakeup_gpios; | |
1476 | omap_gpio_rmw(base, bank->regs->fallingdetect, nowake, ~nowake); | |
1477 | omap_gpio_rmw(base, bank->regs->risingdetect, nowake, ~nowake); | |
1478 | } | |
3f1686a9 | 1479 | |
41d87cbd | 1480 | update_gpio_context_count: |
2dc983c5 TKD |
1481 | if (bank->get_context_loss_count) |
1482 | bank->context_loss_count = | |
7b1e5dc8 | 1483 | bank->get_context_loss_count(dev); |
60a3437d | 1484 | |
a0e827c6 | 1485 | omap_gpio_dbck_disable(bank); |
3ac4fa99 JY |
1486 | } |
1487 | ||
352a2d5b JH |
1488 | static void omap_gpio_init_context(struct gpio_bank *p); |
1489 | ||
b764a586 | 1490 | static void omap_gpio_unidle(struct gpio_bank *bank) |
3ac4fa99 | 1491 | { |
b764a586 | 1492 | struct device *dev = bank->chip.parent; |
2dc983c5 | 1493 | u32 l = 0, gen, gen0, gen1; |
a2797bea | 1494 | int c; |
8865b9b6 | 1495 | |
352a2d5b JH |
1496 | /* |
1497 | * On the first resume during the probe, the context has not | |
1498 | * been initialised and so initialise it now. Also initialise | |
1499 | * the context loss count. | |
1500 | */ | |
1501 | if (bank->loses_context && !bank->context_valid) { | |
1502 | omap_gpio_init_context(bank); | |
1503 | ||
1504 | if (bank->get_context_loss_count) | |
1505 | bank->context_loss_count = | |
7b1e5dc8 | 1506 | bank->get_context_loss_count(dev); |
352a2d5b JH |
1507 | } |
1508 | ||
a0e827c6 | 1509 | omap_gpio_dbck_enable(bank); |
68942edb | 1510 | |
ec0daae6 TL |
1511 | if (bank->funcs.idle_disable_level_quirk) |
1512 | bank->funcs.idle_disable_level_quirk(bank); | |
68942edb | 1513 | |
a2797bea JH |
1514 | if (bank->loses_context) { |
1515 | if (!bank->get_context_loss_count) { | |
2dc983c5 TKD |
1516 | omap_gpio_restore_context(bank); |
1517 | } else { | |
7b1e5dc8 | 1518 | c = bank->get_context_loss_count(dev); |
a2797bea JH |
1519 | if (c != bank->context_loss_count) { |
1520 | omap_gpio_restore_context(bank); | |
1521 | } else { | |
b764a586 | 1522 | return; |
a2797bea | 1523 | } |
60a3437d | 1524 | } |
21e2118f TL |
1525 | } else { |
1526 | /* Restore changes done for OMAP2420 errata 1.101 */ | |
1527 | writel_relaxed(bank->context.fallingdetect, | |
1528 | bank->base + bank->regs->fallingdetect); | |
1529 | writel_relaxed(bank->context.risingdetect, | |
1530 | bank->base + bank->regs->risingdetect); | |
2dc983c5 | 1531 | } |
43ffcd9a | 1532 | |
661553b9 | 1533 | l = readl_relaxed(bank->base + bank->regs->datain); |
3f1686a9 | 1534 | |
2dc983c5 TKD |
1535 | /* |
1536 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1537 | * state. If so, generate an IRQ by software. This is | |
1538 | * horribly racy, but it's the best we can do to work around | |
1539 | * this silicon bug. | |
1540 | */ | |
1541 | l ^= bank->saved_datain; | |
1542 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1543 | |
2dc983c5 TKD |
1544 | /* |
1545 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1546 | * configured with falling edge only; and vice versa. | |
1547 | */ | |
c6f31c9e | 1548 | gen0 = l & bank->context.fallingdetect; |
2dc983c5 | 1549 | gen0 &= bank->saved_datain; |
82dbb9d3 | 1550 | |
c6f31c9e | 1551 | gen1 = l & bank->context.risingdetect; |
2dc983c5 | 1552 | gen1 &= ~(bank->saved_datain); |
82dbb9d3 | 1553 | |
2dc983c5 | 1554 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
c6f31c9e TKD |
1555 | gen = l & (~(bank->context.fallingdetect) & |
1556 | ~(bank->context.risingdetect)); | |
2dc983c5 TKD |
1557 | /* Consider all GPIO IRQs needed to be updated */ |
1558 | gen |= gen0 | gen1; | |
82dbb9d3 | 1559 | |
2dc983c5 TKD |
1560 | if (gen) { |
1561 | u32 old0, old1; | |
82dbb9d3 | 1562 | |
661553b9 VK |
1563 | old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); |
1564 | old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1565 | |
4e962e89 | 1566 | if (!bank->regs->irqstatus_raw0) { |
661553b9 | 1567 | writel_relaxed(old0 | gen, bank->base + |
9ea14d8c | 1568 | bank->regs->leveldetect0); |
661553b9 | 1569 | writel_relaxed(old1 | gen, bank->base + |
9ea14d8c | 1570 | bank->regs->leveldetect1); |
2dc983c5 | 1571 | } |
9ea14d8c | 1572 | |
4e962e89 | 1573 | if (bank->regs->irqstatus_raw0) { |
661553b9 | 1574 | writel_relaxed(old0 | l, bank->base + |
9ea14d8c | 1575 | bank->regs->leveldetect0); |
661553b9 | 1576 | writel_relaxed(old1 | l, bank->base + |
9ea14d8c | 1577 | bank->regs->leveldetect1); |
3ac4fa99 | 1578 | } |
661553b9 VK |
1579 | writel_relaxed(old0, bank->base + bank->regs->leveldetect0); |
1580 | writel_relaxed(old1, bank->base + bank->regs->leveldetect1); | |
2dc983c5 | 1581 | } |
2dc983c5 | 1582 | } |
2dc983c5 | 1583 | |
352a2d5b JH |
1584 | static void omap_gpio_init_context(struct gpio_bank *p) |
1585 | { | |
1586 | struct omap_gpio_reg_offs *regs = p->regs; | |
1587 | void __iomem *base = p->base; | |
1588 | ||
661553b9 VK |
1589 | p->context.ctrl = readl_relaxed(base + regs->ctrl); |
1590 | p->context.oe = readl_relaxed(base + regs->direction); | |
1591 | p->context.wake_en = readl_relaxed(base + regs->wkup_en); | |
1592 | p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); | |
1593 | p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); | |
1594 | p->context.risingdetect = readl_relaxed(base + regs->risingdetect); | |
1595 | p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); | |
1596 | p->context.irqenable1 = readl_relaxed(base + regs->irqenable); | |
1597 | p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); | |
352a2d5b JH |
1598 | |
1599 | if (regs->set_dataout && p->regs->clr_dataout) | |
661553b9 | 1600 | p->context.dataout = readl_relaxed(base + regs->set_dataout); |
352a2d5b | 1601 | else |
661553b9 | 1602 | p->context.dataout = readl_relaxed(base + regs->dataout); |
352a2d5b JH |
1603 | |
1604 | p->context_valid = true; | |
1605 | } | |
1606 | ||
60a3437d | 1607 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1608 | { |
661553b9 | 1609 | writel_relaxed(bank->context.wake_en, |
ae10f233 | 1610 | bank->base + bank->regs->wkup_en); |
661553b9 VK |
1611 | writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); |
1612 | writel_relaxed(bank->context.leveldetect0, | |
ae10f233 | 1613 | bank->base + bank->regs->leveldetect0); |
661553b9 | 1614 | writel_relaxed(bank->context.leveldetect1, |
ae10f233 | 1615 | bank->base + bank->regs->leveldetect1); |
661553b9 | 1616 | writel_relaxed(bank->context.risingdetect, |
ae10f233 | 1617 | bank->base + bank->regs->risingdetect); |
661553b9 | 1618 | writel_relaxed(bank->context.fallingdetect, |
ae10f233 | 1619 | bank->base + bank->regs->fallingdetect); |
f86bcc30 | 1620 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
661553b9 | 1621 | writel_relaxed(bank->context.dataout, |
f86bcc30 NM |
1622 | bank->base + bank->regs->set_dataout); |
1623 | else | |
661553b9 | 1624 | writel_relaxed(bank->context.dataout, |
f86bcc30 | 1625 | bank->base + bank->regs->dataout); |
661553b9 | 1626 | writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); |
6d13eaaf | 1627 | |
ae547354 | 1628 | if (bank->dbck_enable_mask) { |
661553b9 | 1629 | writel_relaxed(bank->context.debounce, bank->base + |
ae547354 | 1630 | bank->regs->debounce); |
661553b9 | 1631 | writel_relaxed(bank->context.debounce_en, |
ae547354 NM |
1632 | bank->base + bank->regs->debounce_en); |
1633 | } | |
ba805be5 | 1634 | |
661553b9 | 1635 | writel_relaxed(bank->context.irqenable1, |
ba805be5 | 1636 | bank->base + bank->regs->irqenable); |
661553b9 | 1637 | writel_relaxed(bank->context.irqenable2, |
ba805be5 | 1638 | bank->base + bank->regs->irqenable2); |
40c670f0 | 1639 | } |
40c670f0 | 1640 | |
b764a586 TL |
1641 | static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev) |
1642 | { | |
a3f4f728 | 1643 | struct gpio_bank *bank = dev_get_drvdata(dev); |
b764a586 TL |
1644 | unsigned long flags; |
1645 | int error = 0; | |
1646 | ||
1647 | raw_spin_lock_irqsave(&bank->lock, flags); | |
1648 | /* Must be idled only by CPU_CLUSTER_PM_ENTER? */ | |
1649 | if (bank->irq_usage) { | |
1650 | error = -EBUSY; | |
1651 | goto unlock; | |
1652 | } | |
1653 | omap_gpio_idle(bank, true); | |
1654 | bank->is_suspended = true; | |
1655 | unlock: | |
1656 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
1657 | ||
1658 | return error; | |
1659 | } | |
1660 | ||
1661 | static int __maybe_unused omap_gpio_runtime_resume(struct device *dev) | |
1662 | { | |
a3f4f728 | 1663 | struct gpio_bank *bank = dev_get_drvdata(dev); |
b764a586 TL |
1664 | unsigned long flags; |
1665 | int error = 0; | |
1666 | ||
1667 | raw_spin_lock_irqsave(&bank->lock, flags); | |
1668 | /* Must be unidled only by CPU_CLUSTER_PM_ENTER? */ | |
1669 | if (bank->irq_usage) { | |
1670 | error = -EBUSY; | |
1671 | goto unlock; | |
1672 | } | |
1673 | omap_gpio_unidle(bank); | |
1674 | bank->is_suspended = false; | |
1675 | unlock: | |
1676 | raw_spin_unlock_irqrestore(&bank->lock, flags); | |
1677 | ||
1678 | return error; | |
1679 | } | |
1680 | ||
1681 | #ifdef CONFIG_ARCH_OMAP2PLUS | |
55b93c32 | 1682 | static const struct dev_pm_ops gpio_pm_ops = { |
2dc983c5 TKD |
1683 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1684 | NULL) | |
55b93c32 | 1685 | }; |
b764a586 TL |
1686 | #else |
1687 | static const struct dev_pm_ops gpio_pm_ops; | |
1688 | #endif /* CONFIG_ARCH_OMAP2PLUS */ | |
55b93c32 | 1689 | |
384ebe1c BC |
1690 | #if defined(CONFIG_OF) |
1691 | static struct omap_gpio_reg_offs omap2_gpio_regs = { | |
1692 | .revision = OMAP24XX_GPIO_REVISION, | |
1693 | .direction = OMAP24XX_GPIO_OE, | |
1694 | .datain = OMAP24XX_GPIO_DATAIN, | |
1695 | .dataout = OMAP24XX_GPIO_DATAOUT, | |
1696 | .set_dataout = OMAP24XX_GPIO_SETDATAOUT, | |
1697 | .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, | |
1698 | .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, | |
1699 | .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, | |
1700 | .irqenable = OMAP24XX_GPIO_IRQENABLE1, | |
1701 | .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, | |
1702 | .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, | |
1703 | .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, | |
1704 | .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, | |
1705 | .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, | |
1706 | .ctrl = OMAP24XX_GPIO_CTRL, | |
1707 | .wkup_en = OMAP24XX_GPIO_WAKE_EN, | |
1708 | .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, | |
1709 | .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, | |
1710 | .risingdetect = OMAP24XX_GPIO_RISINGDETECT, | |
1711 | .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, | |
1712 | }; | |
1713 | ||
1714 | static struct omap_gpio_reg_offs omap4_gpio_regs = { | |
1715 | .revision = OMAP4_GPIO_REVISION, | |
1716 | .direction = OMAP4_GPIO_OE, | |
1717 | .datain = OMAP4_GPIO_DATAIN, | |
1718 | .dataout = OMAP4_GPIO_DATAOUT, | |
1719 | .set_dataout = OMAP4_GPIO_SETDATAOUT, | |
1720 | .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, | |
1721 | .irqstatus = OMAP4_GPIO_IRQSTATUS0, | |
1722 | .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, | |
1723 | .irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1724 | .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, | |
1725 | .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, | |
1726 | .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, | |
1727 | .debounce = OMAP4_GPIO_DEBOUNCINGTIME, | |
1728 | .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, | |
1729 | .ctrl = OMAP4_GPIO_CTRL, | |
1730 | .wkup_en = OMAP4_GPIO_IRQWAKEN0, | |
1731 | .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, | |
1732 | .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, | |
1733 | .risingdetect = OMAP4_GPIO_RISINGDETECT, | |
1734 | .fallingdetect = OMAP4_GPIO_FALLINGDETECT, | |
1735 | }; | |
1736 | ||
b764a586 TL |
1737 | /* |
1738 | * Note that omap2 does not currently support idle modes with context loss so | |
1739 | * no need to add OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER quirk flag to save | |
1740 | * and restore context. | |
1741 | */ | |
e9a65bb6 | 1742 | static const struct omap_gpio_platform_data omap2_pdata = { |
384ebe1c BC |
1743 | .regs = &omap2_gpio_regs, |
1744 | .bank_width = 32, | |
1745 | .dbck_flag = false, | |
1746 | }; | |
1747 | ||
e9a65bb6 | 1748 | static const struct omap_gpio_platform_data omap3_pdata = { |
384ebe1c BC |
1749 | .regs = &omap2_gpio_regs, |
1750 | .bank_width = 32, | |
1751 | .dbck_flag = true, | |
b764a586 | 1752 | .quirks = OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER, |
384ebe1c BC |
1753 | }; |
1754 | ||
e9a65bb6 | 1755 | static const struct omap_gpio_platform_data omap4_pdata = { |
384ebe1c BC |
1756 | .regs = &omap4_gpio_regs, |
1757 | .bank_width = 32, | |
1758 | .dbck_flag = true, | |
00ded24c | 1759 | .quirks = OMAP_GPIO_QUIRK_IDLE_REMOVE_TRIGGER, |
384ebe1c BC |
1760 | }; |
1761 | ||
1762 | static const struct of_device_id omap_gpio_match[] = { | |
1763 | { | |
1764 | .compatible = "ti,omap4-gpio", | |
1765 | .data = &omap4_pdata, | |
1766 | }, | |
1767 | { | |
1768 | .compatible = "ti,omap3-gpio", | |
1769 | .data = &omap3_pdata, | |
1770 | }, | |
1771 | { | |
1772 | .compatible = "ti,omap2-gpio", | |
1773 | .data = &omap2_pdata, | |
1774 | }, | |
1775 | { }, | |
1776 | }; | |
1777 | MODULE_DEVICE_TABLE(of, omap_gpio_match); | |
1778 | #endif | |
1779 | ||
77640aab VC |
1780 | static struct platform_driver omap_gpio_driver = { |
1781 | .probe = omap_gpio_probe, | |
cac089f9 | 1782 | .remove = omap_gpio_remove, |
77640aab VC |
1783 | .driver = { |
1784 | .name = "omap_gpio", | |
55b93c32 | 1785 | .pm = &gpio_pm_ops, |
384ebe1c | 1786 | .of_match_table = of_match_ptr(omap_gpio_match), |
77640aab VC |
1787 | }, |
1788 | }; | |
1789 | ||
5e1c5ff4 | 1790 | /* |
77640aab VC |
1791 | * gpio driver register needs to be done before |
1792 | * machine_init functions access gpio APIs. | |
1793 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1794 | */ |
77640aab | 1795 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1796 | { |
77640aab | 1797 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1798 | } |
77640aab | 1799 | postcore_initcall(omap_gpio_drv_reg); |
cac089f9 TL |
1800 | |
1801 | static void __exit omap_gpio_exit(void) | |
1802 | { | |
1803 | platform_driver_unregister(&omap_gpio_driver); | |
1804 | } | |
1805 | module_exit(omap_gpio_exit); | |
1806 | ||
1807 | MODULE_DESCRIPTION("omap gpio driver"); | |
1808 | MODULE_ALIAS("platform:gpio-omap"); | |
1809 | MODULE_LICENSE("GPL v2"); |