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Commit | Line | Data |
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5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
77640aab VC |
22 | #include <linux/slab.h> |
23 | #include <linux/pm_runtime.h> | |
55b93c32 | 24 | #include <linux/pm.h> |
5e1c5ff4 | 25 | |
a09e64fb | 26 | #include <mach/hardware.h> |
5e1c5ff4 | 27 | #include <asm/irq.h> |
a09e64fb | 28 | #include <mach/irqs.h> |
1bc857f7 | 29 | #include <asm/gpio.h> |
5e1c5ff4 TL |
30 | #include <asm/mach/irq.h> |
31 | ||
2dc983c5 TKD |
32 | #define OFF_MODE 1 |
33 | ||
03e128ca C |
34 | static LIST_HEAD(omap_gpio_list); |
35 | ||
6d62e216 C |
36 | struct gpio_regs { |
37 | u32 irqenable1; | |
38 | u32 irqenable2; | |
39 | u32 wake_en; | |
40 | u32 ctrl; | |
41 | u32 oe; | |
42 | u32 leveldetect0; | |
43 | u32 leveldetect1; | |
44 | u32 risingdetect; | |
45 | u32 fallingdetect; | |
46 | u32 dataout; | |
ae547354 NM |
47 | u32 debounce; |
48 | u32 debounce_en; | |
6d62e216 C |
49 | }; |
50 | ||
5e1c5ff4 | 51 | struct gpio_bank { |
03e128ca | 52 | struct list_head node; |
9f7065da | 53 | unsigned long pbase; |
92105bb7 | 54 | void __iomem *base; |
5e1c5ff4 TL |
55 | u16 irq; |
56 | u16 virtual_irq_start; | |
92105bb7 TL |
57 | u32 suspend_wakeup; |
58 | u32 saved_wakeup; | |
3ac4fa99 JY |
59 | u32 non_wakeup_gpios; |
60 | u32 enabled_non_wakeup_gpios; | |
6d62e216 | 61 | struct gpio_regs context; |
3ac4fa99 JY |
62 | u32 saved_datain; |
63 | u32 saved_fallingdetect; | |
64 | u32 saved_risingdetect; | |
b144ff6f | 65 | u32 level_mask; |
4318f36b | 66 | u32 toggle_mask; |
5e1c5ff4 | 67 | spinlock_t lock; |
52e31344 | 68 | struct gpio_chip chip; |
89db9482 | 69 | struct clk *dbck; |
058af1ea | 70 | u32 mod_usage; |
8865b9b6 | 71 | u32 dbck_enable_mask; |
72f83af9 | 72 | bool dbck_enabled; |
77640aab | 73 | struct device *dev; |
d0d665a8 | 74 | bool is_mpuio; |
77640aab | 75 | bool dbck_flag; |
0cde8d03 | 76 | bool loses_context; |
5de62b86 | 77 | int stride; |
d5f46247 | 78 | u32 width; |
60a3437d | 79 | int context_loss_count; |
03e128ca | 80 | u16 id; |
2dc983c5 TKD |
81 | int power_mode; |
82 | bool workaround_enabled; | |
fa87931a KH |
83 | |
84 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60a3437d | 85 | int (*get_context_loss_count)(struct device *dev); |
fa87931a KH |
86 | |
87 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
88 | }; |
89 | ||
129fd223 KH |
90 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
91 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
c8eef65a | 92 | #define GPIO_MOD_CTRL_BIT BIT(0) |
5e1c5ff4 TL |
93 | |
94 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
95 | { | |
92105bb7 | 96 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
97 | u32 l; |
98 | ||
fa87931a | 99 | reg += bank->regs->direction; |
5e1c5ff4 TL |
100 | l = __raw_readl(reg); |
101 | if (is_input) | |
102 | l |= 1 << gpio; | |
103 | else | |
104 | l &= ~(1 << gpio); | |
105 | __raw_writel(l, reg); | |
41d87cbd | 106 | bank->context.oe = l; |
5e1c5ff4 TL |
107 | } |
108 | ||
fa87931a KH |
109 | |
110 | /* set data out value using dedicate set/clear register */ | |
111 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 112 | { |
92105bb7 | 113 | void __iomem *reg = bank->base; |
fa87931a | 114 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 115 | |
fa87931a KH |
116 | if (enable) |
117 | reg += bank->regs->set_dataout; | |
118 | else | |
119 | reg += bank->regs->clr_dataout; | |
5e1c5ff4 | 120 | |
5e1c5ff4 TL |
121 | __raw_writel(l, reg); |
122 | } | |
123 | ||
fa87931a KH |
124 | /* set data out value using mask register */ |
125 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 126 | { |
fa87931a KH |
127 | void __iomem *reg = bank->base + bank->regs->dataout; |
128 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
129 | u32 l; | |
5e1c5ff4 | 130 | |
fa87931a KH |
131 | l = __raw_readl(reg); |
132 | if (enable) | |
133 | l |= gpio_bit; | |
134 | else | |
135 | l &= ~gpio_bit; | |
5e1c5ff4 | 136 | __raw_writel(l, reg); |
41d87cbd | 137 | bank->context.dataout = l; |
5e1c5ff4 TL |
138 | } |
139 | ||
b37c45b8 | 140 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
b37c45b8 | 141 | { |
fa87931a | 142 | void __iomem *reg = bank->base + bank->regs->datain; |
b37c45b8 | 143 | |
fa87931a | 144 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
5e1c5ff4 | 145 | } |
b37c45b8 | 146 | |
b37c45b8 RQ |
147 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
148 | { | |
fa87931a | 149 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 | 150 | |
129fd223 | 151 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
b37c45b8 RQ |
152 | } |
153 | ||
ece9528e KH |
154 | static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) |
155 | { | |
156 | int l = __raw_readl(base + reg); | |
157 | ||
158 | if (set) | |
159 | l |= mask; | |
160 | else | |
161 | l &= ~mask; | |
162 | ||
163 | __raw_writel(l, base + reg); | |
164 | } | |
92105bb7 | 165 | |
72f83af9 TKD |
166 | static inline void _gpio_dbck_enable(struct gpio_bank *bank) |
167 | { | |
168 | if (bank->dbck_enable_mask && !bank->dbck_enabled) { | |
169 | clk_enable(bank->dbck); | |
170 | bank->dbck_enabled = true; | |
171 | } | |
172 | } | |
173 | ||
174 | static inline void _gpio_dbck_disable(struct gpio_bank *bank) | |
175 | { | |
176 | if (bank->dbck_enable_mask && bank->dbck_enabled) { | |
177 | clk_disable(bank->dbck); | |
178 | bank->dbck_enabled = false; | |
179 | } | |
180 | } | |
181 | ||
168ef3d9 FB |
182 | /** |
183 | * _set_gpio_debounce - low level gpio debounce time | |
184 | * @bank: the gpio bank we're acting upon | |
185 | * @gpio: the gpio number on this @gpio | |
186 | * @debounce: debounce time to use | |
187 | * | |
188 | * OMAP's debounce time is in 31us steps so we need | |
189 | * to convert and round up to the closest unit. | |
190 | */ | |
191 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
192 | unsigned debounce) | |
193 | { | |
9942da0e | 194 | void __iomem *reg; |
168ef3d9 FB |
195 | u32 val; |
196 | u32 l; | |
197 | ||
77640aab VC |
198 | if (!bank->dbck_flag) |
199 | return; | |
200 | ||
168ef3d9 FB |
201 | if (debounce < 32) |
202 | debounce = 0x01; | |
203 | else if (debounce > 7936) | |
204 | debounce = 0xff; | |
205 | else | |
206 | debounce = (debounce / 0x1f) - 1; | |
207 | ||
129fd223 | 208 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 209 | |
6fd9c421 | 210 | clk_enable(bank->dbck); |
9942da0e | 211 | reg = bank->base + bank->regs->debounce; |
168ef3d9 FB |
212 | __raw_writel(debounce, reg); |
213 | ||
9942da0e | 214 | reg = bank->base + bank->regs->debounce_en; |
168ef3d9 FB |
215 | val = __raw_readl(reg); |
216 | ||
6fd9c421 | 217 | if (debounce) |
168ef3d9 | 218 | val |= l; |
6fd9c421 | 219 | else |
168ef3d9 | 220 | val &= ~l; |
f7ec0b0b | 221 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
222 | |
223 | __raw_writel(val, reg); | |
6fd9c421 TKD |
224 | clk_disable(bank->dbck); |
225 | /* | |
226 | * Enable debounce clock per module. | |
227 | * This call is mandatory because in omap_gpio_request() when | |
228 | * *_runtime_get_sync() is called, _gpio_dbck_enable() within | |
229 | * runtime callbck fails to turn on dbck because dbck_enable_mask | |
230 | * used within _gpio_dbck_enable() is still not initialized at | |
231 | * that point. Therefore we have to enable dbck here. | |
232 | */ | |
233 | _gpio_dbck_enable(bank); | |
ae547354 NM |
234 | if (bank->dbck_enable_mask) { |
235 | bank->context.debounce = debounce; | |
236 | bank->context.debounce_en = val; | |
237 | } | |
168ef3d9 FB |
238 | } |
239 | ||
5e571f38 | 240 | static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, |
5eb3bb9c | 241 | int trigger) |
5e1c5ff4 | 242 | { |
3ac4fa99 | 243 | void __iomem *base = bank->base; |
92105bb7 TL |
244 | u32 gpio_bit = 1 << gpio; |
245 | ||
5e571f38 TKD |
246 | _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, |
247 | trigger & IRQ_TYPE_LEVEL_LOW); | |
248 | _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, | |
249 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
250 | _gpio_rmw(base, bank->regs->risingdetect, gpio_bit, | |
251 | trigger & IRQ_TYPE_EDGE_RISING); | |
252 | _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, | |
253 | trigger & IRQ_TYPE_EDGE_FALLING); | |
254 | ||
41d87cbd TKD |
255 | bank->context.leveldetect0 = |
256 | __raw_readl(bank->base + bank->regs->leveldetect0); | |
257 | bank->context.leveldetect1 = | |
258 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
259 | bank->context.risingdetect = | |
260 | __raw_readl(bank->base + bank->regs->risingdetect); | |
261 | bank->context.fallingdetect = | |
262 | __raw_readl(bank->base + bank->regs->fallingdetect); | |
263 | ||
264 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | |
5e571f38 | 265 | _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); |
41d87cbd TKD |
266 | bank->context.wake_en = |
267 | __raw_readl(bank->base + bank->regs->wkup_en); | |
268 | } | |
5e571f38 | 269 | |
55b220ca | 270 | /* This part needs to be executed always for OMAP{34xx, 44xx} */ |
5e571f38 TKD |
271 | if (!bank->regs->irqctrl) { |
272 | /* On omap24xx proceed only when valid GPIO bit is set */ | |
273 | if (bank->non_wakeup_gpios) { | |
274 | if (!(bank->non_wakeup_gpios & gpio_bit)) | |
275 | goto exit; | |
276 | } | |
277 | ||
699117a6 CW |
278 | /* |
279 | * Log the edge gpio and manually trigger the IRQ | |
280 | * after resume if the input level changes | |
281 | * to avoid irq lost during PER RET/OFF mode | |
282 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
283 | */ | |
284 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
285 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
286 | else | |
287 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
288 | } | |
5eb3bb9c | 289 | |
5e571f38 | 290 | exit: |
9ea14d8c TKD |
291 | bank->level_mask = |
292 | __raw_readl(bank->base + bank->regs->leveldetect0) | | |
293 | __raw_readl(bank->base + bank->regs->leveldetect1); | |
92105bb7 TL |
294 | } |
295 | ||
9198bcd3 | 296 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
297 | /* |
298 | * This only applies to chips that can't do both rising and falling edge | |
299 | * detection at once. For all other chips, this function is a noop. | |
300 | */ | |
301 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
302 | { | |
303 | void __iomem *reg = bank->base; | |
304 | u32 l = 0; | |
305 | ||
5e571f38 | 306 | if (!bank->regs->irqctrl) |
4318f36b | 307 | return; |
5e571f38 TKD |
308 | |
309 | reg += bank->regs->irqctrl; | |
4318f36b CM |
310 | |
311 | l = __raw_readl(reg); | |
312 | if ((l >> gpio) & 1) | |
313 | l &= ~(1 << gpio); | |
314 | else | |
315 | l |= 1 << gpio; | |
316 | ||
317 | __raw_writel(l, reg); | |
318 | } | |
5e571f38 TKD |
319 | #else |
320 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} | |
9198bcd3 | 321 | #endif |
4318f36b | 322 | |
92105bb7 TL |
323 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
324 | { | |
325 | void __iomem *reg = bank->base; | |
5e571f38 | 326 | void __iomem *base = bank->base; |
92105bb7 | 327 | u32 l = 0; |
5e1c5ff4 | 328 | |
5e571f38 TKD |
329 | if (bank->regs->leveldetect0 && bank->regs->wkup_en) { |
330 | set_gpio_trigger(bank, gpio, trigger); | |
331 | } else if (bank->regs->irqctrl) { | |
332 | reg += bank->regs->irqctrl; | |
333 | ||
5e1c5ff4 | 334 | l = __raw_readl(reg); |
29501577 | 335 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 336 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 337 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 338 | l |= 1 << gpio; |
6cab4860 | 339 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 340 | l &= ~(1 << gpio); |
92105bb7 | 341 | else |
5e571f38 TKD |
342 | return -EINVAL; |
343 | ||
344 | __raw_writel(l, reg); | |
345 | } else if (bank->regs->edgectrl1) { | |
5e1c5ff4 | 346 | if (gpio & 0x08) |
5e571f38 | 347 | reg += bank->regs->edgectrl2; |
5e1c5ff4 | 348 | else |
5e571f38 TKD |
349 | reg += bank->regs->edgectrl1; |
350 | ||
5e1c5ff4 TL |
351 | gpio &= 0x07; |
352 | l = __raw_readl(reg); | |
353 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 354 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 355 | l |= 2 << (gpio << 1); |
6cab4860 | 356 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 357 | l |= 1 << (gpio << 1); |
5e571f38 TKD |
358 | |
359 | /* Enable wake-up during idle for dynamic tick */ | |
360 | _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger); | |
41d87cbd TKD |
361 | bank->context.wake_en = |
362 | __raw_readl(bank->base + bank->regs->wkup_en); | |
5e571f38 | 363 | __raw_writel(l, reg); |
5e1c5ff4 | 364 | } |
92105bb7 | 365 | return 0; |
5e1c5ff4 TL |
366 | } |
367 | ||
e9191028 | 368 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 TL |
369 | { |
370 | struct gpio_bank *bank; | |
92105bb7 TL |
371 | unsigned gpio; |
372 | int retval; | |
a6472533 | 373 | unsigned long flags; |
92105bb7 | 374 | |
e9191028 LB |
375 | if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) |
376 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | |
92105bb7 | 377 | else |
e9191028 | 378 | gpio = d->irq - IH_GPIO_BASE; |
5e1c5ff4 | 379 | |
e5c56ed3 | 380 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 381 | return -EINVAL; |
e5c56ed3 | 382 | |
9ea14d8c TKD |
383 | bank = irq_data_get_irq_chip_data(d); |
384 | ||
385 | if (!bank->regs->leveldetect0 && | |
386 | (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) | |
92105bb7 TL |
387 | return -EINVAL; |
388 | ||
a6472533 | 389 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 390 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
a6472533 | 391 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
392 | |
393 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 394 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 395 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 396 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 397 | |
92105bb7 | 398 | return retval; |
5e1c5ff4 TL |
399 | } |
400 | ||
401 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
402 | { | |
92105bb7 | 403 | void __iomem *reg = bank->base; |
5e1c5ff4 | 404 | |
eef4bec7 | 405 | reg += bank->regs->irqstatus; |
5e1c5ff4 | 406 | __raw_writel(gpio_mask, reg); |
bee7930f HD |
407 | |
408 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
eef4bec7 KH |
409 | if (bank->regs->irqstatus2) { |
410 | reg = bank->base + bank->regs->irqstatus2; | |
bedfd154 | 411 | __raw_writel(gpio_mask, reg); |
eef4bec7 | 412 | } |
bedfd154 RQ |
413 | |
414 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
415 | __raw_readl(reg); | |
5e1c5ff4 TL |
416 | } |
417 | ||
418 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
419 | { | |
129fd223 | 420 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
421 | } |
422 | ||
ea6dedd7 ID |
423 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
424 | { | |
425 | void __iomem *reg = bank->base; | |
99c47707 | 426 | u32 l; |
c390aad0 | 427 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 | 428 | |
28f3b5a0 | 429 | reg += bank->regs->irqenable; |
99c47707 | 430 | l = __raw_readl(reg); |
28f3b5a0 | 431 | if (bank->regs->irqenable_inv) |
99c47707 ID |
432 | l = ~l; |
433 | l &= mask; | |
434 | return l; | |
ea6dedd7 ID |
435 | } |
436 | ||
28f3b5a0 | 437 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) |
5e1c5ff4 | 438 | { |
92105bb7 | 439 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
440 | u32 l; |
441 | ||
28f3b5a0 KH |
442 | if (bank->regs->set_irqenable) { |
443 | reg += bank->regs->set_irqenable; | |
444 | l = gpio_mask; | |
445 | } else { | |
446 | reg += bank->regs->irqenable; | |
5e1c5ff4 | 447 | l = __raw_readl(reg); |
28f3b5a0 KH |
448 | if (bank->regs->irqenable_inv) |
449 | l &= ~gpio_mask; | |
5e1c5ff4 TL |
450 | else |
451 | l |= gpio_mask; | |
28f3b5a0 KH |
452 | } |
453 | ||
454 | __raw_writel(l, reg); | |
41d87cbd | 455 | bank->context.irqenable1 = l; |
28f3b5a0 KH |
456 | } |
457 | ||
458 | static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
459 | { | |
460 | void __iomem *reg = bank->base; | |
461 | u32 l; | |
462 | ||
463 | if (bank->regs->clr_irqenable) { | |
464 | reg += bank->regs->clr_irqenable; | |
5e1c5ff4 | 465 | l = gpio_mask; |
28f3b5a0 KH |
466 | } else { |
467 | reg += bank->regs->irqenable; | |
56739a69 | 468 | l = __raw_readl(reg); |
28f3b5a0 | 469 | if (bank->regs->irqenable_inv) |
56739a69 | 470 | l |= gpio_mask; |
92105bb7 | 471 | else |
28f3b5a0 | 472 | l &= ~gpio_mask; |
5e1c5ff4 | 473 | } |
28f3b5a0 | 474 | |
5e1c5ff4 | 475 | __raw_writel(l, reg); |
41d87cbd | 476 | bank->context.irqenable1 = l; |
5e1c5ff4 TL |
477 | } |
478 | ||
479 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
480 | { | |
28f3b5a0 | 481 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
482 | } |
483 | ||
92105bb7 TL |
484 | /* |
485 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
486 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
487 | * to the target, system will wake up always on GPIO events. While | |
488 | * system is running all registered GPIO interrupts need to have wake-up | |
489 | * enabled. When system is suspended, only selected GPIO interrupts need | |
490 | * to have wake-up enabled. | |
491 | */ | |
492 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
493 | { | |
f64ad1a0 KH |
494 | u32 gpio_bit = GPIO_BIT(bank, gpio); |
495 | unsigned long flags; | |
a6472533 | 496 | |
f64ad1a0 KH |
497 | if (bank->non_wakeup_gpios & gpio_bit) { |
498 | dev_err(bank->dev, | |
499 | "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); | |
92105bb7 TL |
500 | return -EINVAL; |
501 | } | |
f64ad1a0 KH |
502 | |
503 | spin_lock_irqsave(&bank->lock, flags); | |
504 | if (enable) | |
505 | bank->suspend_wakeup |= gpio_bit; | |
506 | else | |
507 | bank->suspend_wakeup &= ~gpio_bit; | |
508 | ||
509 | spin_unlock_irqrestore(&bank->lock, flags); | |
510 | ||
511 | return 0; | |
92105bb7 TL |
512 | } |
513 | ||
4196dd6b TL |
514 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
515 | { | |
129fd223 | 516 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
517 | _set_gpio_irqenable(bank, gpio, 0); |
518 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 519 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
520 | } |
521 | ||
92105bb7 | 522 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 523 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 524 | { |
e9191028 | 525 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
92105bb7 TL |
526 | struct gpio_bank *bank; |
527 | int retval; | |
528 | ||
e9191028 | 529 | bank = irq_data_get_irq_chip_data(d); |
f64ad1a0 | 530 | retval = _set_gpio_wakeup(bank, gpio, enable); |
92105bb7 TL |
531 | |
532 | return retval; | |
533 | } | |
534 | ||
3ff164e1 | 535 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 536 | { |
3ff164e1 | 537 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 538 | unsigned long flags; |
52e31344 | 539 | |
55b93c32 TKD |
540 | /* |
541 | * If this is the first gpio_request for the bank, | |
542 | * enable the bank module. | |
543 | */ | |
544 | if (!bank->mod_usage) | |
545 | pm_runtime_get_sync(bank->dev); | |
92105bb7 | 546 | |
55b93c32 | 547 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b TL |
548 | /* Set trigger to none. You need to enable the desired trigger with |
549 | * request_irq() or set_irq_type(). | |
550 | */ | |
3ff164e1 | 551 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 552 | |
fad96ea8 C |
553 | if (bank->regs->pinctrl) { |
554 | void __iomem *reg = bank->base + bank->regs->pinctrl; | |
5e1c5ff4 | 555 | |
92105bb7 | 556 | /* Claim the pin for MPU */ |
3ff164e1 | 557 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 | 558 | } |
fad96ea8 | 559 | |
c8eef65a C |
560 | if (bank->regs->ctrl && !bank->mod_usage) { |
561 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
562 | u32 ctrl; | |
563 | ||
564 | ctrl = __raw_readl(reg); | |
565 | /* Module is enabled, clocks are not gated */ | |
566 | ctrl &= ~GPIO_MOD_CTRL_BIT; | |
567 | __raw_writel(ctrl, reg); | |
41d87cbd | 568 | bank->context.ctrl = ctrl; |
058af1ea | 569 | } |
c8eef65a C |
570 | |
571 | bank->mod_usage |= 1 << offset; | |
572 | ||
a6472533 | 573 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
574 | |
575 | return 0; | |
576 | } | |
577 | ||
3ff164e1 | 578 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 579 | { |
3ff164e1 | 580 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
6ed87c5b | 581 | void __iomem *base = bank->base; |
a6472533 | 582 | unsigned long flags; |
5e1c5ff4 | 583 | |
a6472533 | 584 | spin_lock_irqsave(&bank->lock, flags); |
6ed87c5b | 585 | |
41d87cbd | 586 | if (bank->regs->wkup_en) { |
9f096868 | 587 | /* Disable wake-up during idle for dynamic tick */ |
6ed87c5b | 588 | _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0); |
41d87cbd TKD |
589 | bank->context.wake_en = |
590 | __raw_readl(bank->base + bank->regs->wkup_en); | |
591 | } | |
6ed87c5b | 592 | |
c8eef65a C |
593 | bank->mod_usage &= ~(1 << offset); |
594 | ||
595 | if (bank->regs->ctrl && !bank->mod_usage) { | |
596 | void __iomem *reg = bank->base + bank->regs->ctrl; | |
597 | u32 ctrl; | |
598 | ||
599 | ctrl = __raw_readl(reg); | |
600 | /* Module is disabled, clocks are gated */ | |
601 | ctrl |= GPIO_MOD_CTRL_BIT; | |
602 | __raw_writel(ctrl, reg); | |
41d87cbd | 603 | bank->context.ctrl = ctrl; |
058af1ea | 604 | } |
c8eef65a | 605 | |
3ff164e1 | 606 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 607 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 TKD |
608 | |
609 | /* | |
610 | * If this is the last gpio to be freed in the bank, | |
611 | * disable the bank module. | |
612 | */ | |
613 | if (!bank->mod_usage) | |
614 | pm_runtime_put(bank->dev); | |
5e1c5ff4 TL |
615 | } |
616 | ||
617 | /* | |
618 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
619 | * avoid missing GPIO interrupts for other lines in the bank. | |
620 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
621 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
622 | * If we wait to unmask individual GPIO lines in the bank after the | |
623 | * line's interrupt handler has been run, we may miss some nested | |
624 | * interrupts. | |
625 | */ | |
10dd5ce2 | 626 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 627 | { |
92105bb7 | 628 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 629 | u32 isr; |
4318f36b | 630 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 631 | struct gpio_bank *bank; |
ea6dedd7 ID |
632 | u32 retrigger = 0; |
633 | int unmasked = 0; | |
ee144182 | 634 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 635 | |
ee144182 | 636 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 637 | |
6845664a | 638 | bank = irq_get_handler_data(irq); |
eef4bec7 | 639 | isr_reg = bank->base + bank->regs->irqstatus; |
55b93c32 | 640 | pm_runtime_get_sync(bank->dev); |
b1cc4c55 EK |
641 | |
642 | if (WARN_ON(!isr_reg)) | |
643 | goto exit; | |
644 | ||
92105bb7 | 645 | while(1) { |
6e60e79a | 646 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 647 | u32 enabled; |
6e60e79a | 648 | |
ea6dedd7 ID |
649 | enabled = _get_gpio_irqbank_mask(bank); |
650 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a | 651 | |
9ea14d8c | 652 | if (bank->level_mask) |
b144ff6f | 653 | level_mask = bank->level_mask & enabled; |
6e60e79a TL |
654 | |
655 | /* clear edge sensitive interrupts before handler(s) are | |
656 | called so that we don't miss any interrupt occurred while | |
657 | executing them */ | |
28f3b5a0 | 658 | _disable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a | 659 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); |
28f3b5a0 | 660 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask); |
6e60e79a TL |
661 | |
662 | /* if there is only edge sensitive GPIO pin interrupts | |
663 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
664 | if (!level_mask && !unmasked) { |
665 | unmasked = 1; | |
ee144182 | 666 | chained_irq_exit(chip, desc); |
ea6dedd7 | 667 | } |
92105bb7 | 668 | |
ea6dedd7 ID |
669 | isr |= retrigger; |
670 | retrigger = 0; | |
92105bb7 TL |
671 | if (!isr) |
672 | break; | |
673 | ||
674 | gpio_irq = bank->virtual_irq_start; | |
675 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
129fd223 | 676 | gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq)); |
4318f36b | 677 | |
92105bb7 TL |
678 | if (!(isr & 1)) |
679 | continue; | |
29454dde | 680 | |
4318f36b CM |
681 | /* |
682 | * Some chips can't respond to both rising and falling | |
683 | * at the same time. If this irq was requested with | |
684 | * both flags, we need to flip the ICR data for the IRQ | |
685 | * to respond to the IRQ for the opposite direction. | |
686 | * This will be indicated in the bank toggle_mask. | |
687 | */ | |
688 | if (bank->toggle_mask & (1 << gpio_index)) | |
689 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
4318f36b | 690 | |
d8aa0251 | 691 | generic_handle_irq(gpio_irq); |
92105bb7 | 692 | } |
1a8bfa1e | 693 | } |
ea6dedd7 ID |
694 | /* if bank has any level sensitive GPIO pin interrupt |
695 | configured, we must unmask the bank interrupt only after | |
696 | handler(s) are executed in order to avoid spurious bank | |
697 | interrupt */ | |
b1cc4c55 | 698 | exit: |
ea6dedd7 | 699 | if (!unmasked) |
ee144182 | 700 | chained_irq_exit(chip, desc); |
55b93c32 | 701 | pm_runtime_put(bank->dev); |
5e1c5ff4 TL |
702 | } |
703 | ||
e9191028 | 704 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 705 | { |
e9191028 LB |
706 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
707 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 708 | unsigned long flags; |
4196dd6b | 709 | |
85ec7b97 | 710 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 711 | _reset_gpio(bank, gpio); |
85ec7b97 | 712 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
713 | } |
714 | ||
e9191028 | 715 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 716 | { |
e9191028 LB |
717 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
718 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
719 | |
720 | _clear_gpio_irqstatus(bank, gpio); | |
721 | } | |
722 | ||
e9191028 | 723 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 724 | { |
e9191028 LB |
725 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
726 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 727 | unsigned long flags; |
5e1c5ff4 | 728 | |
85ec7b97 | 729 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 730 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 731 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 732 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
733 | } |
734 | ||
e9191028 | 735 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 736 | { |
e9191028 LB |
737 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
738 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
129fd223 | 739 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 740 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 741 | unsigned long flags; |
55b6019a | 742 | |
85ec7b97 | 743 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 744 | if (trigger) |
129fd223 | 745 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
746 | |
747 | /* For level-triggered GPIOs, the clearing must be done after | |
748 | * the HW source is cleared, thus after the handler has run */ | |
749 | if (bank->level_mask & irq_mask) { | |
750 | _set_gpio_irqenable(bank, gpio, 0); | |
751 | _clear_gpio_irqstatus(bank, gpio); | |
752 | } | |
5e1c5ff4 | 753 | |
4de8c75b | 754 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 755 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
756 | } |
757 | ||
e5c56ed3 DB |
758 | static struct irq_chip gpio_irq_chip = { |
759 | .name = "GPIO", | |
e9191028 LB |
760 | .irq_shutdown = gpio_irq_shutdown, |
761 | .irq_ack = gpio_ack_irq, | |
762 | .irq_mask = gpio_mask_irq, | |
763 | .irq_unmask = gpio_unmask_irq, | |
764 | .irq_set_type = gpio_irq_type, | |
765 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
766 | }; |
767 | ||
768 | /*---------------------------------------------------------------------*/ | |
769 | ||
79ee031f | 770 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 771 | { |
79ee031f | 772 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 773 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
774 | void __iomem *mask_reg = bank->base + |
775 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 776 | unsigned long flags; |
11a78b79 | 777 | |
a6472533 | 778 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
779 | bank->saved_wakeup = __raw_readl(mask_reg); |
780 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 781 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
782 | |
783 | return 0; | |
784 | } | |
785 | ||
79ee031f | 786 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 787 | { |
79ee031f | 788 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 789 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
790 | void __iomem *mask_reg = bank->base + |
791 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 792 | unsigned long flags; |
11a78b79 | 793 | |
a6472533 | 794 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 795 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 796 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
797 | |
798 | return 0; | |
799 | } | |
800 | ||
47145210 | 801 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
802 | .suspend_noirq = omap_mpuio_suspend_noirq, |
803 | .resume_noirq = omap_mpuio_resume_noirq, | |
804 | }; | |
805 | ||
3c437ffd | 806 | /* use platform_driver for this. */ |
11a78b79 | 807 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
808 | .driver = { |
809 | .name = "mpuio", | |
79ee031f | 810 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
811 | }, |
812 | }; | |
813 | ||
814 | static struct platform_device omap_mpuio_device = { | |
815 | .name = "mpuio", | |
816 | .id = -1, | |
817 | .dev = { | |
818 | .driver = &omap_mpuio_driver.driver, | |
819 | } | |
820 | /* could list the /proc/iomem resources */ | |
821 | }; | |
822 | ||
03e128ca | 823 | static inline void mpuio_init(struct gpio_bank *bank) |
11a78b79 | 824 | { |
77640aab | 825 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 826 | |
11a78b79 DB |
827 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
828 | (void) platform_device_register(&omap_mpuio_device); | |
829 | } | |
830 | ||
e5c56ed3 | 831 | /*---------------------------------------------------------------------*/ |
5e1c5ff4 | 832 | |
52e31344 DB |
833 | static int gpio_input(struct gpio_chip *chip, unsigned offset) |
834 | { | |
835 | struct gpio_bank *bank; | |
836 | unsigned long flags; | |
837 | ||
838 | bank = container_of(chip, struct gpio_bank, chip); | |
839 | spin_lock_irqsave(&bank->lock, flags); | |
840 | _set_gpio_direction(bank, offset, 1); | |
841 | spin_unlock_irqrestore(&bank->lock, flags); | |
842 | return 0; | |
843 | } | |
844 | ||
b37c45b8 RQ |
845 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
846 | { | |
fa87931a | 847 | void __iomem *reg = bank->base + bank->regs->direction; |
b37c45b8 | 848 | |
b37c45b8 RQ |
849 | return __raw_readl(reg) & mask; |
850 | } | |
851 | ||
52e31344 DB |
852 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
853 | { | |
b37c45b8 RQ |
854 | struct gpio_bank *bank; |
855 | void __iomem *reg; | |
856 | int gpio; | |
857 | u32 mask; | |
858 | ||
859 | gpio = chip->base + offset; | |
a8be8daf | 860 | bank = container_of(chip, struct gpio_bank, chip); |
b37c45b8 | 861 | reg = bank->base; |
129fd223 | 862 | mask = GPIO_BIT(bank, gpio); |
b37c45b8 RQ |
863 | |
864 | if (gpio_is_input(bank, mask)) | |
865 | return _get_gpio_datain(bank, gpio); | |
866 | else | |
867 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
868 | } |
869 | ||
870 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
871 | { | |
872 | struct gpio_bank *bank; | |
873 | unsigned long flags; | |
874 | ||
875 | bank = container_of(chip, struct gpio_bank, chip); | |
876 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 877 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
878 | _set_gpio_direction(bank, offset, 0); |
879 | spin_unlock_irqrestore(&bank->lock, flags); | |
880 | return 0; | |
881 | } | |
882 | ||
168ef3d9 FB |
883 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
884 | unsigned debounce) | |
885 | { | |
886 | struct gpio_bank *bank; | |
887 | unsigned long flags; | |
888 | ||
889 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab VC |
890 | |
891 | if (!bank->dbck) { | |
892 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
893 | if (IS_ERR(bank->dbck)) | |
894 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
895 | } | |
896 | ||
168ef3d9 FB |
897 | spin_lock_irqsave(&bank->lock, flags); |
898 | _set_gpio_debounce(bank, offset, debounce); | |
899 | spin_unlock_irqrestore(&bank->lock, flags); | |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
52e31344 DB |
904 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
905 | { | |
906 | struct gpio_bank *bank; | |
907 | unsigned long flags; | |
908 | ||
909 | bank = container_of(chip, struct gpio_bank, chip); | |
910 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 911 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
912 | spin_unlock_irqrestore(&bank->lock, flags); |
913 | } | |
914 | ||
a007b709 DB |
915 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
916 | { | |
917 | struct gpio_bank *bank; | |
918 | ||
919 | bank = container_of(chip, struct gpio_bank, chip); | |
920 | return bank->virtual_irq_start + offset; | |
921 | } | |
922 | ||
52e31344 DB |
923 | /*---------------------------------------------------------------------*/ |
924 | ||
9a748053 | 925 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da | 926 | { |
e5ff4440 | 927 | static bool called; |
9f7065da TL |
928 | u32 rev; |
929 | ||
e5ff4440 | 930 | if (called || bank->regs->revision == USHRT_MAX) |
9f7065da TL |
931 | return; |
932 | ||
e5ff4440 KH |
933 | rev = __raw_readw(bank->base + bank->regs->revision); |
934 | pr_info("OMAP GPIO hardware version %d.%d\n", | |
9f7065da | 935 | (rev >> 4) & 0x0f, rev & 0x0f); |
e5ff4440 KH |
936 | |
937 | called = true; | |
9f7065da TL |
938 | } |
939 | ||
8ba55c5c DB |
940 | /* This lock class tells lockdep that GPIO irqs are in a different |
941 | * category than their parents, so it won't report false recursion. | |
942 | */ | |
943 | static struct lock_class_key gpio_lock_class; | |
944 | ||
03e128ca | 945 | static void omap_gpio_mod_init(struct gpio_bank *bank) |
2fae7fbe | 946 | { |
ab985f0f TKD |
947 | void __iomem *base = bank->base; |
948 | u32 l = 0xffffffff; | |
2fae7fbe | 949 | |
ab985f0f TKD |
950 | if (bank->width == 16) |
951 | l = 0xffff; | |
952 | ||
d0d665a8 | 953 | if (bank->is_mpuio) { |
ab985f0f TKD |
954 | __raw_writel(l, bank->base + bank->regs->irqenable); |
955 | return; | |
2fae7fbe | 956 | } |
ab985f0f TKD |
957 | |
958 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv); | |
959 | _gpio_rmw(base, bank->regs->irqstatus, l, | |
960 | bank->regs->irqenable_inv == false); | |
961 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0); | |
962 | _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0); | |
963 | if (bank->regs->debounce_en) | |
964 | _gpio_rmw(base, bank->regs->debounce_en, 0, 1); | |
965 | ||
2dc983c5 TKD |
966 | /* Save OE default value (0xffffffff) in the context */ |
967 | bank->context.oe = __raw_readl(bank->base + bank->regs->direction); | |
ab985f0f TKD |
968 | /* Initialize interface clk ungated, module enabled */ |
969 | if (bank->regs->ctrl) | |
970 | _gpio_rmw(base, bank->regs->ctrl, 0, 1); | |
2fae7fbe VC |
971 | } |
972 | ||
f8b46b58 KH |
973 | static __init void |
974 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, | |
975 | unsigned int num) | |
976 | { | |
977 | struct irq_chip_generic *gc; | |
978 | struct irq_chip_type *ct; | |
979 | ||
980 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | |
981 | handle_simple_irq); | |
83233749 TP |
982 | if (!gc) { |
983 | dev_err(bank->dev, "Memory alloc failed for gc\n"); | |
984 | return; | |
985 | } | |
986 | ||
f8b46b58 KH |
987 | ct = gc->chip_types; |
988 | ||
989 | /* NOTE: No ack required, reading IRQ status clears it. */ | |
990 | ct->chip.irq_mask = irq_gc_mask_set_bit; | |
991 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | |
992 | ct->chip.irq_set_type = gpio_irq_type; | |
6ed87c5b TKD |
993 | |
994 | if (bank->regs->wkup_en) | |
f8b46b58 KH |
995 | ct->chip.irq_set_wake = gpio_wake_enable, |
996 | ||
997 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | |
998 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | |
999 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
1000 | } | |
1001 | ||
d52b31de | 1002 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 1003 | { |
77640aab | 1004 | int j; |
2fae7fbe VC |
1005 | static int gpio; |
1006 | ||
2fae7fbe VC |
1007 | /* |
1008 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1009 | * over to the generic ones | |
1010 | */ | |
1011 | bank->chip.request = omap_gpio_request; | |
1012 | bank->chip.free = omap_gpio_free; | |
1013 | bank->chip.direction_input = gpio_input; | |
1014 | bank->chip.get = gpio_get; | |
1015 | bank->chip.direction_output = gpio_output; | |
1016 | bank->chip.set_debounce = gpio_debounce; | |
1017 | bank->chip.set = gpio_set; | |
1018 | bank->chip.to_irq = gpio_2irq; | |
d0d665a8 | 1019 | if (bank->is_mpuio) { |
2fae7fbe | 1020 | bank->chip.label = "mpuio"; |
6ed87c5b TKD |
1021 | if (bank->regs->wkup_en) |
1022 | bank->chip.dev = &omap_mpuio_device.dev; | |
2fae7fbe VC |
1023 | bank->chip.base = OMAP_MPUIO(0); |
1024 | } else { | |
1025 | bank->chip.label = "gpio"; | |
1026 | bank->chip.base = gpio; | |
d5f46247 | 1027 | gpio += bank->width; |
2fae7fbe | 1028 | } |
d5f46247 | 1029 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
1030 | |
1031 | gpiochip_add(&bank->chip); | |
1032 | ||
1033 | for (j = bank->virtual_irq_start; | |
d5f46247 | 1034 | j < bank->virtual_irq_start + bank->width; j++) { |
1475b85d | 1035 | irq_set_lockdep_class(j, &gpio_lock_class); |
6845664a | 1036 | irq_set_chip_data(j, bank); |
d0d665a8 | 1037 | if (bank->is_mpuio) { |
f8b46b58 KH |
1038 | omap_mpuio_alloc_gc(bank, j, bank->width); |
1039 | } else { | |
6845664a | 1040 | irq_set_chip(j, &gpio_irq_chip); |
f8b46b58 KH |
1041 | irq_set_handler(j, handle_simple_irq); |
1042 | set_irq_flags(j, IRQF_VALID); | |
1043 | } | |
2fae7fbe | 1044 | } |
6845664a TG |
1045 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1046 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
1047 | } |
1048 | ||
77640aab | 1049 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1050 | { |
77640aab VC |
1051 | struct omap_gpio_platform_data *pdata; |
1052 | struct resource *res; | |
5e1c5ff4 | 1053 | struct gpio_bank *bank; |
03e128ca | 1054 | int ret = 0; |
5e1c5ff4 | 1055 | |
03e128ca C |
1056 | if (!pdev->dev.platform_data) { |
1057 | ret = -EINVAL; | |
1058 | goto err_exit; | |
5492fb1a | 1059 | } |
5492fb1a | 1060 | |
03e128ca C |
1061 | bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL); |
1062 | if (!bank) { | |
1063 | dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); | |
1064 | ret = -ENOMEM; | |
1065 | goto err_exit; | |
1066 | } | |
92105bb7 | 1067 | |
77640aab VC |
1068 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1069 | if (unlikely(!res)) { | |
03e128ca C |
1070 | dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", |
1071 | pdev->id); | |
1072 | ret = -ENODEV; | |
1073 | goto err_free; | |
44169075 | 1074 | } |
5e1c5ff4 | 1075 | |
77640aab | 1076 | bank->irq = res->start; |
03e128ca C |
1077 | bank->id = pdev->id; |
1078 | ||
1079 | pdata = pdev->dev.platform_data; | |
77640aab | 1080 | bank->virtual_irq_start = pdata->virtual_irq_start; |
77640aab VC |
1081 | bank->dev = &pdev->dev; |
1082 | bank->dbck_flag = pdata->dbck_flag; | |
5de62b86 | 1083 | bank->stride = pdata->bank_stride; |
d5f46247 | 1084 | bank->width = pdata->bank_width; |
d0d665a8 | 1085 | bank->is_mpuio = pdata->is_mpuio; |
803a2434 | 1086 | bank->non_wakeup_gpios = pdata->non_wakeup_gpios; |
0cde8d03 | 1087 | bank->loses_context = pdata->loses_context; |
60a3437d | 1088 | bank->get_context_loss_count = pdata->get_context_loss_count; |
fa87931a KH |
1089 | bank->regs = pdata->regs; |
1090 | ||
1091 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1092 | bank->set_dataout = _set_gpio_dataout_reg; | |
1093 | else | |
1094 | bank->set_dataout = _set_gpio_dataout_mask; | |
9f7065da | 1095 | |
77640aab | 1096 | spin_lock_init(&bank->lock); |
9f7065da | 1097 | |
77640aab VC |
1098 | /* Static mapping, never released */ |
1099 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1100 | if (unlikely(!res)) { | |
03e128ca C |
1101 | dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", |
1102 | pdev->id); | |
1103 | ret = -ENODEV; | |
1104 | goto err_free; | |
77640aab | 1105 | } |
89db9482 | 1106 | |
77640aab VC |
1107 | bank->base = ioremap(res->start, resource_size(res)); |
1108 | if (!bank->base) { | |
03e128ca C |
1109 | dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", |
1110 | pdev->id); | |
1111 | ret = -ENOMEM; | |
1112 | goto err_free; | |
5e1c5ff4 TL |
1113 | } |
1114 | ||
065cd795 TKD |
1115 | platform_set_drvdata(pdev, bank); |
1116 | ||
77640aab | 1117 | pm_runtime_enable(bank->dev); |
55b93c32 | 1118 | pm_runtime_irq_safe(bank->dev); |
77640aab VC |
1119 | pm_runtime_get_sync(bank->dev); |
1120 | ||
d0d665a8 | 1121 | if (bank->is_mpuio) |
ab985f0f TKD |
1122 | mpuio_init(bank); |
1123 | ||
03e128ca | 1124 | omap_gpio_mod_init(bank); |
77640aab | 1125 | omap_gpio_chip_init(bank); |
9a748053 | 1126 | omap_gpio_show_rev(bank); |
9f7065da | 1127 | |
55b93c32 TKD |
1128 | pm_runtime_put(bank->dev); |
1129 | ||
03e128ca | 1130 | list_add_tail(&bank->node, &omap_gpio_list); |
77640aab | 1131 | |
03e128ca C |
1132 | return ret; |
1133 | ||
1134 | err_free: | |
1135 | kfree(bank); | |
1136 | err_exit: | |
1137 | return ret; | |
5e1c5ff4 TL |
1138 | } |
1139 | ||
55b93c32 TKD |
1140 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1141 | ||
1142 | #if defined(CONFIG_PM_SLEEP) | |
1143 | static int omap_gpio_suspend(struct device *dev) | |
92105bb7 | 1144 | { |
065cd795 TKD |
1145 | struct platform_device *pdev = to_platform_device(dev); |
1146 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1147 | void __iomem *base = bank->base; | |
1148 | void __iomem *wakeup_enable; | |
1149 | unsigned long flags; | |
92105bb7 | 1150 | |
065cd795 TKD |
1151 | if (!bank->mod_usage || !bank->loses_context) |
1152 | return 0; | |
92105bb7 | 1153 | |
065cd795 TKD |
1154 | if (!bank->regs->wkup_en || !bank->suspend_wakeup) |
1155 | return 0; | |
6ed87c5b | 1156 | |
065cd795 | 1157 | wakeup_enable = bank->base + bank->regs->wkup_en; |
92105bb7 | 1158 | |
065cd795 TKD |
1159 | spin_lock_irqsave(&bank->lock, flags); |
1160 | bank->saved_wakeup = __raw_readl(wakeup_enable); | |
1161 | _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0); | |
1162 | _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1); | |
1163 | spin_unlock_irqrestore(&bank->lock, flags); | |
92105bb7 TL |
1164 | |
1165 | return 0; | |
1166 | } | |
1167 | ||
55b93c32 | 1168 | static int omap_gpio_resume(struct device *dev) |
92105bb7 | 1169 | { |
065cd795 TKD |
1170 | struct platform_device *pdev = to_platform_device(dev); |
1171 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1172 | void __iomem *base = bank->base; | |
1173 | unsigned long flags; | |
92105bb7 | 1174 | |
065cd795 TKD |
1175 | if (!bank->mod_usage || !bank->loses_context) |
1176 | return 0; | |
92105bb7 | 1177 | |
065cd795 TKD |
1178 | if (!bank->regs->wkup_en || !bank->saved_wakeup) |
1179 | return 0; | |
92105bb7 | 1180 | |
065cd795 TKD |
1181 | spin_lock_irqsave(&bank->lock, flags); |
1182 | _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0); | |
1183 | _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1); | |
1184 | spin_unlock_irqrestore(&bank->lock, flags); | |
92105bb7 | 1185 | |
55b93c32 TKD |
1186 | return 0; |
1187 | } | |
1188 | #endif /* CONFIG_PM_SLEEP */ | |
3ac4fa99 | 1189 | |
2dc983c5 | 1190 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1191 | static void omap_gpio_restore_context(struct gpio_bank *bank); |
3ac4fa99 | 1192 | |
2dc983c5 | 1193 | static int omap_gpio_runtime_suspend(struct device *dev) |
3ac4fa99 | 1194 | { |
2dc983c5 TKD |
1195 | struct platform_device *pdev = to_platform_device(dev); |
1196 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1197 | u32 l1 = 0, l2 = 0; | |
1198 | unsigned long flags; | |
8865b9b6 | 1199 | |
2dc983c5 TKD |
1200 | spin_lock_irqsave(&bank->lock, flags); |
1201 | if (bank->power_mode != OFF_MODE) { | |
1202 | bank->power_mode = 0; | |
41d87cbd | 1203 | goto update_gpio_context_count; |
2dc983c5 TKD |
1204 | } |
1205 | /* | |
1206 | * If going to OFF, remove triggering for all | |
1207 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1208 | * generated. See OMAP2420 Errata item 1.101. | |
1209 | */ | |
1210 | if (!(bank->enabled_non_wakeup_gpios)) | |
41d87cbd | 1211 | goto update_gpio_context_count; |
43ffcd9a | 1212 | |
2dc983c5 TKD |
1213 | bank->saved_datain = __raw_readl(bank->base + |
1214 | bank->regs->datain); | |
1215 | l1 = __raw_readl(bank->base + bank->regs->fallingdetect); | |
1216 | l2 = __raw_readl(bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1217 | |
2dc983c5 TKD |
1218 | bank->saved_fallingdetect = l1; |
1219 | bank->saved_risingdetect = l2; | |
1220 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1221 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1222 | |
2dc983c5 TKD |
1223 | __raw_writel(l1, bank->base + bank->regs->fallingdetect); |
1224 | __raw_writel(l2, bank->base + bank->regs->risingdetect); | |
3f1686a9 | 1225 | |
2dc983c5 | 1226 | bank->workaround_enabled = true; |
3f1686a9 | 1227 | |
41d87cbd | 1228 | update_gpio_context_count: |
2dc983c5 TKD |
1229 | if (bank->get_context_loss_count) |
1230 | bank->context_loss_count = | |
60a3437d TKD |
1231 | bank->get_context_loss_count(bank->dev); |
1232 | ||
72f83af9 | 1233 | _gpio_dbck_disable(bank); |
2dc983c5 | 1234 | spin_unlock_irqrestore(&bank->lock, flags); |
55b93c32 | 1235 | |
2dc983c5 | 1236 | return 0; |
3ac4fa99 JY |
1237 | } |
1238 | ||
2dc983c5 | 1239 | static int omap_gpio_runtime_resume(struct device *dev) |
3ac4fa99 | 1240 | { |
2dc983c5 TKD |
1241 | struct platform_device *pdev = to_platform_device(dev); |
1242 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1243 | int context_lost_cnt_after; | |
1244 | u32 l = 0, gen, gen0, gen1; | |
1245 | unsigned long flags; | |
8865b9b6 | 1246 | |
2dc983c5 | 1247 | spin_lock_irqsave(&bank->lock, flags); |
72f83af9 | 1248 | _gpio_dbck_enable(bank); |
2dc983c5 TKD |
1249 | if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) { |
1250 | spin_unlock_irqrestore(&bank->lock, flags); | |
1251 | return 0; | |
1252 | } | |
55b93c32 | 1253 | |
2dc983c5 TKD |
1254 | if (bank->get_context_loss_count) { |
1255 | context_lost_cnt_after = | |
1256 | bank->get_context_loss_count(bank->dev); | |
1257 | if (context_lost_cnt_after != bank->context_loss_count || | |
1258 | !context_lost_cnt_after) { | |
1259 | omap_gpio_restore_context(bank); | |
1260 | } else { | |
1261 | spin_unlock_irqrestore(&bank->lock, flags); | |
1262 | return 0; | |
60a3437d | 1263 | } |
2dc983c5 | 1264 | } |
43ffcd9a | 1265 | |
2dc983c5 TKD |
1266 | __raw_writel(bank->saved_fallingdetect, |
1267 | bank->base + bank->regs->fallingdetect); | |
1268 | __raw_writel(bank->saved_risingdetect, | |
1269 | bank->base + bank->regs->risingdetect); | |
1270 | l = __raw_readl(bank->base + bank->regs->datain); | |
3f1686a9 | 1271 | |
2dc983c5 TKD |
1272 | /* |
1273 | * Check if any of the non-wakeup interrupt GPIOs have changed | |
1274 | * state. If so, generate an IRQ by software. This is | |
1275 | * horribly racy, but it's the best we can do to work around | |
1276 | * this silicon bug. | |
1277 | */ | |
1278 | l ^= bank->saved_datain; | |
1279 | l &= bank->enabled_non_wakeup_gpios; | |
3f1686a9 | 1280 | |
2dc983c5 TKD |
1281 | /* |
1282 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1283 | * configured with falling edge only; and vice versa. | |
1284 | */ | |
1285 | gen0 = l & bank->saved_fallingdetect; | |
1286 | gen0 &= bank->saved_datain; | |
82dbb9d3 | 1287 | |
2dc983c5 TKD |
1288 | gen1 = l & bank->saved_risingdetect; |
1289 | gen1 &= ~(bank->saved_datain); | |
82dbb9d3 | 1290 | |
2dc983c5 TKD |
1291 | /* FIXME: Consider GPIO IRQs with level detections properly! */ |
1292 | gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect)); | |
1293 | /* Consider all GPIO IRQs needed to be updated */ | |
1294 | gen |= gen0 | gen1; | |
82dbb9d3 | 1295 | |
2dc983c5 TKD |
1296 | if (gen) { |
1297 | u32 old0, old1; | |
82dbb9d3 | 1298 | |
2dc983c5 TKD |
1299 | old0 = __raw_readl(bank->base + bank->regs->leveldetect0); |
1300 | old1 = __raw_readl(bank->base + bank->regs->leveldetect1); | |
3f1686a9 | 1301 | |
2dc983c5 TKD |
1302 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
1303 | __raw_writel(old0 | gen, bank->base + | |
9ea14d8c | 1304 | bank->regs->leveldetect0); |
2dc983c5 | 1305 | __raw_writel(old1 | gen, bank->base + |
9ea14d8c | 1306 | bank->regs->leveldetect1); |
2dc983c5 | 1307 | } |
9ea14d8c | 1308 | |
2dc983c5 TKD |
1309 | if (cpu_is_omap44xx()) { |
1310 | __raw_writel(old0 | l, bank->base + | |
9ea14d8c | 1311 | bank->regs->leveldetect0); |
2dc983c5 | 1312 | __raw_writel(old1 | l, bank->base + |
9ea14d8c | 1313 | bank->regs->leveldetect1); |
3ac4fa99 | 1314 | } |
2dc983c5 TKD |
1315 | __raw_writel(old0, bank->base + bank->regs->leveldetect0); |
1316 | __raw_writel(old1, bank->base + bank->regs->leveldetect1); | |
1317 | } | |
1318 | ||
1319 | bank->workaround_enabled = false; | |
1320 | spin_unlock_irqrestore(&bank->lock, flags); | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | #endif /* CONFIG_PM_RUNTIME */ | |
1325 | ||
1326 | void omap2_gpio_prepare_for_idle(int pwr_mode) | |
1327 | { | |
1328 | struct gpio_bank *bank; | |
1329 | ||
1330 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
2dc983c5 TKD |
1331 | if (!bank->mod_usage || !bank->loses_context) |
1332 | continue; | |
1333 | ||
1334 | bank->power_mode = pwr_mode; | |
1335 | ||
2dc983c5 TKD |
1336 | pm_runtime_put_sync_suspend(bank->dev); |
1337 | } | |
1338 | } | |
1339 | ||
1340 | void omap2_gpio_resume_after_idle(void) | |
1341 | { | |
1342 | struct gpio_bank *bank; | |
1343 | ||
1344 | list_for_each_entry(bank, &omap_gpio_list, node) { | |
2dc983c5 TKD |
1345 | if (!bank->mod_usage || !bank->loses_context) |
1346 | continue; | |
1347 | ||
2dc983c5 | 1348 | pm_runtime_get_sync(bank->dev); |
3ac4fa99 | 1349 | } |
3ac4fa99 JY |
1350 | } |
1351 | ||
2dc983c5 | 1352 | #if defined(CONFIG_PM_RUNTIME) |
60a3437d | 1353 | static void omap_gpio_restore_context(struct gpio_bank *bank) |
40c670f0 | 1354 | { |
60a3437d | 1355 | __raw_writel(bank->context.wake_en, |
ae10f233 TKD |
1356 | bank->base + bank->regs->wkup_en); |
1357 | __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl); | |
60a3437d | 1358 | __raw_writel(bank->context.leveldetect0, |
ae10f233 | 1359 | bank->base + bank->regs->leveldetect0); |
60a3437d | 1360 | __raw_writel(bank->context.leveldetect1, |
ae10f233 | 1361 | bank->base + bank->regs->leveldetect1); |
60a3437d | 1362 | __raw_writel(bank->context.risingdetect, |
ae10f233 | 1363 | bank->base + bank->regs->risingdetect); |
60a3437d | 1364 | __raw_writel(bank->context.fallingdetect, |
ae10f233 | 1365 | bank->base + bank->regs->fallingdetect); |
f86bcc30 NM |
1366 | if (bank->regs->set_dataout && bank->regs->clr_dataout) |
1367 | __raw_writel(bank->context.dataout, | |
1368 | bank->base + bank->regs->set_dataout); | |
1369 | else | |
1370 | __raw_writel(bank->context.dataout, | |
1371 | bank->base + bank->regs->dataout); | |
6d13eaaf NM |
1372 | __raw_writel(bank->context.oe, bank->base + bank->regs->direction); |
1373 | ||
ae547354 NM |
1374 | if (bank->dbck_enable_mask) { |
1375 | __raw_writel(bank->context.debounce, bank->base + | |
1376 | bank->regs->debounce); | |
1377 | __raw_writel(bank->context.debounce_en, | |
1378 | bank->base + bank->regs->debounce_en); | |
1379 | } | |
ba805be5 NM |
1380 | |
1381 | __raw_writel(bank->context.irqenable1, | |
1382 | bank->base + bank->regs->irqenable); | |
1383 | __raw_writel(bank->context.irqenable2, | |
1384 | bank->base + bank->regs->irqenable2); | |
40c670f0 | 1385 | } |
2dc983c5 | 1386 | #endif /* CONFIG_PM_RUNTIME */ |
55b93c32 TKD |
1387 | #else |
1388 | #define omap_gpio_suspend NULL | |
1389 | #define omap_gpio_resume NULL | |
2dc983c5 TKD |
1390 | #define omap_gpio_runtime_suspend NULL |
1391 | #define omap_gpio_runtime_resume NULL | |
40c670f0 RN |
1392 | #endif |
1393 | ||
55b93c32 TKD |
1394 | static const struct dev_pm_ops gpio_pm_ops = { |
1395 | SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume) | |
2dc983c5 TKD |
1396 | SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, |
1397 | NULL) | |
55b93c32 TKD |
1398 | }; |
1399 | ||
77640aab VC |
1400 | static struct platform_driver omap_gpio_driver = { |
1401 | .probe = omap_gpio_probe, | |
1402 | .driver = { | |
1403 | .name = "omap_gpio", | |
55b93c32 | 1404 | .pm = &gpio_pm_ops, |
77640aab VC |
1405 | }, |
1406 | }; | |
1407 | ||
5e1c5ff4 | 1408 | /* |
77640aab VC |
1409 | * gpio driver register needs to be done before |
1410 | * machine_init functions access gpio APIs. | |
1411 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1412 | */ |
77640aab | 1413 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1414 | { |
77640aab | 1415 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1416 | } |
77640aab | 1417 | postcore_initcall(omap_gpio_drv_reg); |