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Commit | Line | Data |
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5e1c5ff4 | 1 | /* |
5e1c5ff4 TL |
2 | * Support functions for OMAP GPIO |
3 | * | |
92105bb7 | 4 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 5 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 6 | * |
44169075 SS |
7 | * Copyright (C) 2009 Texas Instruments |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
5e1c5ff4 TL |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
5e1c5ff4 TL |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
5e1c5ff4 | 17 | #include <linux/interrupt.h> |
3c437ffd | 18 | #include <linux/syscore_ops.h> |
92105bb7 | 19 | #include <linux/err.h> |
f8ce2547 | 20 | #include <linux/clk.h> |
fced80c7 | 21 | #include <linux/io.h> |
77640aab VC |
22 | #include <linux/slab.h> |
23 | #include <linux/pm_runtime.h> | |
5e1c5ff4 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e1c5ff4 | 26 | #include <asm/irq.h> |
a09e64fb RK |
27 | #include <mach/irqs.h> |
28 | #include <mach/gpio.h> | |
5e1c5ff4 TL |
29 | #include <asm/mach/irq.h> |
30 | ||
5e1c5ff4 | 31 | struct gpio_bank { |
9f7065da | 32 | unsigned long pbase; |
92105bb7 | 33 | void __iomem *base; |
5e1c5ff4 TL |
34 | u16 irq; |
35 | u16 virtual_irq_start; | |
92105bb7 | 36 | int method; |
140455fa | 37 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
92105bb7 TL |
38 | u32 suspend_wakeup; |
39 | u32 saved_wakeup; | |
3ac4fa99 | 40 | #endif |
3ac4fa99 JY |
41 | u32 non_wakeup_gpios; |
42 | u32 enabled_non_wakeup_gpios; | |
43 | ||
44 | u32 saved_datain; | |
45 | u32 saved_fallingdetect; | |
46 | u32 saved_risingdetect; | |
b144ff6f | 47 | u32 level_mask; |
4318f36b | 48 | u32 toggle_mask; |
5e1c5ff4 | 49 | spinlock_t lock; |
52e31344 | 50 | struct gpio_chip chip; |
89db9482 | 51 | struct clk *dbck; |
058af1ea | 52 | u32 mod_usage; |
8865b9b6 | 53 | u32 dbck_enable_mask; |
77640aab VC |
54 | struct device *dev; |
55 | bool dbck_flag; | |
5de62b86 | 56 | int stride; |
d5f46247 | 57 | u32 width; |
fa87931a KH |
58 | |
59 | void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); | |
60 | ||
61 | struct omap_gpio_reg_offs *regs; | |
5e1c5ff4 TL |
62 | }; |
63 | ||
a8eb7ca0 | 64 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 | 65 | struct omap3_gpio_regs { |
40c670f0 RN |
66 | u32 irqenable1; |
67 | u32 irqenable2; | |
68 | u32 wake_en; | |
69 | u32 ctrl; | |
70 | u32 oe; | |
71 | u32 leveldetect0; | |
72 | u32 leveldetect1; | |
73 | u32 risingdetect; | |
74 | u32 fallingdetect; | |
75 | u32 dataout; | |
5492fb1a SMK |
76 | }; |
77 | ||
40c670f0 | 78 | static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; |
5492fb1a SMK |
79 | #endif |
80 | ||
77640aab VC |
81 | /* |
82 | * TODO: Cleanup gpio_bank usage as it is having information | |
83 | * related to all instances of the device | |
84 | */ | |
85 | static struct gpio_bank *gpio_bank; | |
44169075 | 86 | |
c95d10bc VC |
87 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ |
88 | int gpio_bank_count; | |
5e1c5ff4 | 89 | |
129fd223 KH |
90 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
91 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | |
92 | ||
5e1c5ff4 TL |
93 | static inline int gpio_valid(int gpio) |
94 | { | |
95 | if (gpio < 0) | |
96 | return -1; | |
d11ac979 | 97 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 98 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
99 | return -1; |
100 | return 0; | |
101 | } | |
6e60e79a | 102 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 103 | return 0; |
5e1c5ff4 TL |
104 | if ((cpu_is_omap16xx()) && gpio < 64) |
105 | return 0; | |
56739a69 | 106 | if (cpu_is_omap7xx() && gpio < 192) |
5e1c5ff4 | 107 | return 0; |
25d6f630 TL |
108 | if (cpu_is_omap2420() && gpio < 128) |
109 | return 0; | |
110 | if (cpu_is_omap2430() && gpio < 160) | |
92105bb7 | 111 | return 0; |
44169075 | 112 | if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) |
5492fb1a | 113 | return 0; |
5e1c5ff4 TL |
114 | return -1; |
115 | } | |
116 | ||
117 | static int check_gpio(int gpio) | |
118 | { | |
d32b20fc | 119 | if (unlikely(gpio_valid(gpio) < 0)) { |
5e1c5ff4 TL |
120 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); |
121 | dump_stack(); | |
122 | return -1; | |
123 | } | |
124 | return 0; | |
125 | } | |
126 | ||
127 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
128 | { | |
92105bb7 | 129 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
130 | u32 l; |
131 | ||
fa87931a | 132 | reg += bank->regs->direction; |
5e1c5ff4 TL |
133 | l = __raw_readl(reg); |
134 | if (is_input) | |
135 | l |= 1 << gpio; | |
136 | else | |
137 | l &= ~(1 << gpio); | |
138 | __raw_writel(l, reg); | |
139 | } | |
140 | ||
fa87931a KH |
141 | |
142 | /* set data out value using dedicate set/clear register */ | |
143 | static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) | |
5e1c5ff4 | 144 | { |
92105bb7 | 145 | void __iomem *reg = bank->base; |
fa87931a | 146 | u32 l = GPIO_BIT(bank, gpio); |
5e1c5ff4 | 147 | |
fa87931a KH |
148 | if (enable) |
149 | reg += bank->regs->set_dataout; | |
150 | else | |
151 | reg += bank->regs->clr_dataout; | |
152 | ||
153 | __raw_writel(l, reg); | |
154 | } | |
155 | ||
156 | /* set data out value using mask register */ | |
157 | static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) | |
158 | { | |
159 | void __iomem *reg = bank->base + bank->regs->dataout; | |
160 | u32 gpio_bit = GPIO_BIT(bank, gpio); | |
161 | u32 l; | |
162 | ||
163 | l = __raw_readl(reg); | |
164 | if (enable) | |
165 | l |= gpio_bit; | |
166 | else | |
167 | l &= ~gpio_bit; | |
5e1c5ff4 TL |
168 | __raw_writel(l, reg); |
169 | } | |
170 | ||
b37c45b8 | 171 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
5e1c5ff4 | 172 | { |
fa87931a | 173 | void __iomem *reg = bank->base + bank->regs->datain; |
5e1c5ff4 TL |
174 | |
175 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 176 | return -EINVAL; |
fa87931a KH |
177 | |
178 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; | |
5e1c5ff4 TL |
179 | } |
180 | ||
b37c45b8 RQ |
181 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
182 | { | |
fa87931a | 183 | void __iomem *reg = bank->base + bank->regs->dataout; |
b37c45b8 RQ |
184 | |
185 | if (check_gpio(gpio) < 0) | |
186 | return -EINVAL; | |
b37c45b8 | 187 | |
129fd223 | 188 | return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; |
b37c45b8 RQ |
189 | } |
190 | ||
92105bb7 TL |
191 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
192 | do { \ | |
193 | int l = __raw_readl(base + reg); \ | |
194 | if (set) l |= bit_mask; \ | |
195 | else l &= ~bit_mask; \ | |
196 | __raw_writel(l, base + reg); \ | |
197 | } while(0) | |
198 | ||
168ef3d9 FB |
199 | /** |
200 | * _set_gpio_debounce - low level gpio debounce time | |
201 | * @bank: the gpio bank we're acting upon | |
202 | * @gpio: the gpio number on this @gpio | |
203 | * @debounce: debounce time to use | |
204 | * | |
205 | * OMAP's debounce time is in 31us steps so we need | |
206 | * to convert and round up to the closest unit. | |
207 | */ | |
208 | static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, | |
209 | unsigned debounce) | |
210 | { | |
211 | void __iomem *reg = bank->base; | |
212 | u32 val; | |
213 | u32 l; | |
214 | ||
77640aab VC |
215 | if (!bank->dbck_flag) |
216 | return; | |
217 | ||
168ef3d9 FB |
218 | if (debounce < 32) |
219 | debounce = 0x01; | |
220 | else if (debounce > 7936) | |
221 | debounce = 0xff; | |
222 | else | |
223 | debounce = (debounce / 0x1f) - 1; | |
224 | ||
129fd223 | 225 | l = GPIO_BIT(bank, gpio); |
168ef3d9 | 226 | |
77640aab | 227 | if (bank->method == METHOD_GPIO_44XX) |
168ef3d9 FB |
228 | reg += OMAP4_GPIO_DEBOUNCINGTIME; |
229 | else | |
230 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
231 | ||
232 | __raw_writel(debounce, reg); | |
233 | ||
234 | reg = bank->base; | |
77640aab | 235 | if (bank->method == METHOD_GPIO_44XX) |
168ef3d9 FB |
236 | reg += OMAP4_GPIO_DEBOUNCENABLE; |
237 | else | |
238 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | |
239 | ||
240 | val = __raw_readl(reg); | |
241 | ||
242 | if (debounce) { | |
243 | val |= l; | |
77640aab | 244 | clk_enable(bank->dbck); |
168ef3d9 FB |
245 | } else { |
246 | val &= ~l; | |
77640aab | 247 | clk_disable(bank->dbck); |
168ef3d9 | 248 | } |
f7ec0b0b | 249 | bank->dbck_enable_mask = val; |
168ef3d9 FB |
250 | |
251 | __raw_writel(val, reg); | |
252 | } | |
253 | ||
140455fa | 254 | #ifdef CONFIG_ARCH_OMAP2PLUS |
5eb3bb9c KH |
255 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
256 | int trigger) | |
5e1c5ff4 | 257 | { |
3ac4fa99 | 258 | void __iomem *base = bank->base; |
92105bb7 TL |
259 | u32 gpio_bit = 1 << gpio; |
260 | ||
78a1a6d3 SR |
261 | if (cpu_is_omap44xx()) { |
262 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit, | |
263 | trigger & IRQ_TYPE_LEVEL_LOW); | |
264 | MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit, | |
265 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
266 | MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit, | |
267 | trigger & IRQ_TYPE_EDGE_RISING); | |
268 | MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit, | |
269 | trigger & IRQ_TYPE_EDGE_FALLING); | |
270 | } else { | |
271 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
272 | trigger & IRQ_TYPE_LEVEL_LOW); | |
273 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, | |
274 | trigger & IRQ_TYPE_LEVEL_HIGH); | |
275 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, | |
276 | trigger & IRQ_TYPE_EDGE_RISING); | |
277 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, | |
278 | trigger & IRQ_TYPE_EDGE_FALLING); | |
279 | } | |
3ac4fa99 | 280 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
78a1a6d3 | 281 | if (cpu_is_omap44xx()) { |
0622b25b CC |
282 | MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit, |
283 | trigger != 0); | |
78a1a6d3 | 284 | } else { |
699117a6 CW |
285 | /* |
286 | * GPIO wakeup request can only be generated on edge | |
287 | * transitions | |
288 | */ | |
289 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
78a1a6d3 | 290 | __raw_writel(1 << gpio, bank->base |
5eb3bb9c | 291 | + OMAP24XX_GPIO_SETWKUENA); |
78a1a6d3 SR |
292 | else |
293 | __raw_writel(1 << gpio, bank->base | |
5eb3bb9c | 294 | + OMAP24XX_GPIO_CLEARWKUENA); |
78a1a6d3 | 295 | } |
a118b5f3 TK |
296 | } |
297 | /* This part needs to be executed always for OMAP34xx */ | |
298 | if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) { | |
699117a6 CW |
299 | /* |
300 | * Log the edge gpio and manually trigger the IRQ | |
301 | * after resume if the input level changes | |
302 | * to avoid irq lost during PER RET/OFF mode | |
303 | * Applies for omap2 non-wakeup gpio and all omap3 gpios | |
304 | */ | |
305 | if (trigger & IRQ_TYPE_EDGE_BOTH) | |
3ac4fa99 JY |
306 | bank->enabled_non_wakeup_gpios |= gpio_bit; |
307 | else | |
308 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
309 | } | |
5eb3bb9c | 310 | |
78a1a6d3 SR |
311 | if (cpu_is_omap44xx()) { |
312 | bank->level_mask = | |
313 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | | |
314 | __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); | |
315 | } else { | |
316 | bank->level_mask = | |
317 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
318 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
319 | } | |
92105bb7 | 320 | } |
3ac4fa99 | 321 | #endif |
92105bb7 | 322 | |
9198bcd3 | 323 | #ifdef CONFIG_ARCH_OMAP1 |
4318f36b CM |
324 | /* |
325 | * This only applies to chips that can't do both rising and falling edge | |
326 | * detection at once. For all other chips, this function is a noop. | |
327 | */ | |
328 | static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) | |
329 | { | |
330 | void __iomem *reg = bank->base; | |
331 | u32 l = 0; | |
332 | ||
333 | switch (bank->method) { | |
4318f36b | 334 | case METHOD_MPUIO: |
5de62b86 | 335 | reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; |
4318f36b | 336 | break; |
4318f36b CM |
337 | #ifdef CONFIG_ARCH_OMAP15XX |
338 | case METHOD_GPIO_1510: | |
339 | reg += OMAP1510_GPIO_INT_CONTROL; | |
340 | break; | |
341 | #endif | |
342 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | |
343 | case METHOD_GPIO_7XX: | |
344 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
345 | break; | |
346 | #endif | |
347 | default: | |
348 | return; | |
349 | } | |
350 | ||
351 | l = __raw_readl(reg); | |
352 | if ((l >> gpio) & 1) | |
353 | l &= ~(1 << gpio); | |
354 | else | |
355 | l |= 1 << gpio; | |
356 | ||
357 | __raw_writel(l, reg); | |
358 | } | |
9198bcd3 | 359 | #endif |
4318f36b | 360 | |
92105bb7 TL |
361 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) |
362 | { | |
363 | void __iomem *reg = bank->base; | |
364 | u32 l = 0; | |
5e1c5ff4 TL |
365 | |
366 | switch (bank->method) { | |
e5c56ed3 | 367 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 368 | case METHOD_MPUIO: |
5de62b86 | 369 | reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; |
5e1c5ff4 | 370 | l = __raw_readl(reg); |
29501577 | 371 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 372 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 373 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 374 | l |= 1 << gpio; |
6cab4860 | 375 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 376 | l &= ~(1 << gpio); |
92105bb7 TL |
377 | else |
378 | goto bad; | |
5e1c5ff4 | 379 | break; |
e5c56ed3 DB |
380 | #endif |
381 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
382 | case METHOD_GPIO_1510: |
383 | reg += OMAP1510_GPIO_INT_CONTROL; | |
384 | l = __raw_readl(reg); | |
29501577 | 385 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 386 | bank->toggle_mask |= 1 << gpio; |
6cab4860 | 387 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 388 | l |= 1 << gpio; |
6cab4860 | 389 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 390 | l &= ~(1 << gpio); |
92105bb7 TL |
391 | else |
392 | goto bad; | |
5e1c5ff4 | 393 | break; |
e5c56ed3 | 394 | #endif |
3ac4fa99 | 395 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 396 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
397 | if (gpio & 0x08) |
398 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
399 | else | |
400 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
401 | gpio &= 0x07; | |
402 | l = __raw_readl(reg); | |
403 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 404 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 405 | l |= 2 << (gpio << 1); |
6cab4860 | 406 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 407 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
408 | if (trigger) |
409 | /* Enable wake-up during idle for dynamic tick */ | |
410 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
411 | else | |
412 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 413 | break; |
3ac4fa99 | 414 | #endif |
b718aa81 | 415 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
416 | case METHOD_GPIO_7XX: |
417 | reg += OMAP7XX_GPIO_INT_CONTROL; | |
56739a69 | 418 | l = __raw_readl(reg); |
29501577 | 419 | if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
4318f36b | 420 | bank->toggle_mask |= 1 << gpio; |
56739a69 ZM |
421 | if (trigger & IRQ_TYPE_EDGE_RISING) |
422 | l |= 1 << gpio; | |
423 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | |
424 | l &= ~(1 << gpio); | |
425 | else | |
426 | goto bad; | |
427 | break; | |
428 | #endif | |
140455fa | 429 | #ifdef CONFIG_ARCH_OMAP2PLUS |
92105bb7 | 430 | case METHOD_GPIO_24XX: |
3f1686a9 | 431 | case METHOD_GPIO_44XX: |
3ac4fa99 | 432 | set_24xx_gpio_triggering(bank, gpio, trigger); |
f7c5cc45 | 433 | return 0; |
3ac4fa99 | 434 | #endif |
5e1c5ff4 | 435 | default: |
92105bb7 | 436 | goto bad; |
5e1c5ff4 | 437 | } |
92105bb7 TL |
438 | __raw_writel(l, reg); |
439 | return 0; | |
440 | bad: | |
441 | return -EINVAL; | |
5e1c5ff4 TL |
442 | } |
443 | ||
e9191028 | 444 | static int gpio_irq_type(struct irq_data *d, unsigned type) |
5e1c5ff4 TL |
445 | { |
446 | struct gpio_bank *bank; | |
92105bb7 TL |
447 | unsigned gpio; |
448 | int retval; | |
a6472533 | 449 | unsigned long flags; |
92105bb7 | 450 | |
e9191028 LB |
451 | if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) |
452 | gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | |
92105bb7 | 453 | else |
e9191028 | 454 | gpio = d->irq - IH_GPIO_BASE; |
5e1c5ff4 TL |
455 | |
456 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
457 | return -EINVAL; |
458 | ||
e5c56ed3 | 459 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 460 | return -EINVAL; |
e5c56ed3 DB |
461 | |
462 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 463 | if (!cpu_class_is_omap2() |
e5c56ed3 | 464 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
465 | return -EINVAL; |
466 | ||
e9191028 | 467 | bank = irq_data_get_irq_chip_data(d); |
a6472533 | 468 | spin_lock_irqsave(&bank->lock, flags); |
129fd223 | 469 | retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); |
a6472533 | 470 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
471 | |
472 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 473 | __irq_set_handler_locked(d->irq, handle_level_irq); |
672e302e | 474 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 475 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
672e302e | 476 | |
92105bb7 | 477 | return retval; |
5e1c5ff4 TL |
478 | } |
479 | ||
480 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
481 | { | |
92105bb7 | 482 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
483 | |
484 | switch (bank->method) { | |
e5c56ed3 | 485 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
486 | case METHOD_GPIO_1510: |
487 | reg += OMAP1510_GPIO_INT_STATUS; | |
488 | break; | |
e5c56ed3 DB |
489 | #endif |
490 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
491 | case METHOD_GPIO_1610: |
492 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
493 | break; | |
e5c56ed3 | 494 | #endif |
b718aa81 | 495 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
496 | case METHOD_GPIO_7XX: |
497 | reg += OMAP7XX_GPIO_INT_STATUS; | |
56739a69 ZM |
498 | break; |
499 | #endif | |
a8eb7ca0 | 500 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
501 | case METHOD_GPIO_24XX: |
502 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
503 | break; | |
78a1a6d3 SR |
504 | #endif |
505 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 506 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
507 | reg += OMAP4_GPIO_IRQSTATUS0; |
508 | break; | |
e5c56ed3 | 509 | #endif |
5e1c5ff4 | 510 | default: |
e5c56ed3 | 511 | WARN_ON(1); |
5e1c5ff4 TL |
512 | return; |
513 | } | |
514 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
515 | |
516 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
3f1686a9 TL |
517 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
518 | reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; | |
519 | else if (cpu_is_omap44xx()) | |
520 | reg = bank->base + OMAP4_GPIO_IRQSTATUS1; | |
521 | ||
df3c8517 | 522 | if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) |
bedfd154 RQ |
523 | __raw_writel(gpio_mask, reg); |
524 | ||
525 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
526 | __raw_readl(reg); | |
5e1c5ff4 TL |
527 | } |
528 | ||
529 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
530 | { | |
129fd223 | 531 | _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); |
5e1c5ff4 TL |
532 | } |
533 | ||
ea6dedd7 ID |
534 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
535 | { | |
536 | void __iomem *reg = bank->base; | |
99c47707 ID |
537 | int inv = 0; |
538 | u32 l; | |
c390aad0 | 539 | u32 mask = (1 << bank->width) - 1; |
ea6dedd7 ID |
540 | |
541 | switch (bank->method) { | |
e5c56ed3 | 542 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 | 543 | case METHOD_MPUIO: |
5de62b86 | 544 | reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; |
99c47707 | 545 | inv = 1; |
ea6dedd7 | 546 | break; |
e5c56ed3 DB |
547 | #endif |
548 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
549 | case METHOD_GPIO_1510: |
550 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 | 551 | inv = 1; |
ea6dedd7 | 552 | break; |
e5c56ed3 DB |
553 | #endif |
554 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
555 | case METHOD_GPIO_1610: |
556 | reg += OMAP1610_GPIO_IRQENABLE1; | |
557 | break; | |
e5c56ed3 | 558 | #endif |
b718aa81 | 559 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
560 | case METHOD_GPIO_7XX: |
561 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
562 | inv = 1; |
563 | break; | |
564 | #endif | |
a8eb7ca0 | 565 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
ea6dedd7 ID |
566 | case METHOD_GPIO_24XX: |
567 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
568 | break; | |
78a1a6d3 SR |
569 | #endif |
570 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 571 | case METHOD_GPIO_44XX: |
78a1a6d3 | 572 | reg += OMAP4_GPIO_IRQSTATUSSET0; |
78a1a6d3 | 573 | break; |
e5c56ed3 | 574 | #endif |
ea6dedd7 | 575 | default: |
e5c56ed3 | 576 | WARN_ON(1); |
ea6dedd7 ID |
577 | return 0; |
578 | } | |
579 | ||
99c47707 ID |
580 | l = __raw_readl(reg); |
581 | if (inv) | |
582 | l = ~l; | |
583 | l &= mask; | |
584 | return l; | |
ea6dedd7 ID |
585 | } |
586 | ||
5e1c5ff4 TL |
587 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
588 | { | |
92105bb7 | 589 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
590 | u32 l; |
591 | ||
592 | switch (bank->method) { | |
e5c56ed3 | 593 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 594 | case METHOD_MPUIO: |
5de62b86 | 595 | reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride; |
5e1c5ff4 TL |
596 | l = __raw_readl(reg); |
597 | if (enable) | |
598 | l &= ~(gpio_mask); | |
599 | else | |
600 | l |= gpio_mask; | |
601 | break; | |
e5c56ed3 DB |
602 | #endif |
603 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
604 | case METHOD_GPIO_1510: |
605 | reg += OMAP1510_GPIO_INT_MASK; | |
606 | l = __raw_readl(reg); | |
607 | if (enable) | |
608 | l &= ~(gpio_mask); | |
609 | else | |
610 | l |= gpio_mask; | |
611 | break; | |
e5c56ed3 DB |
612 | #endif |
613 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
614 | case METHOD_GPIO_1610: |
615 | if (enable) | |
616 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
617 | else | |
618 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
619 | l = gpio_mask; | |
620 | break; | |
e5c56ed3 | 621 | #endif |
b718aa81 | 622 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
623 | case METHOD_GPIO_7XX: |
624 | reg += OMAP7XX_GPIO_INT_MASK; | |
56739a69 ZM |
625 | l = __raw_readl(reg); |
626 | if (enable) | |
627 | l &= ~(gpio_mask); | |
628 | else | |
629 | l |= gpio_mask; | |
630 | break; | |
631 | #endif | |
a8eb7ca0 | 632 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
633 | case METHOD_GPIO_24XX: |
634 | if (enable) | |
635 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
636 | else | |
637 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
638 | l = gpio_mask; | |
639 | break; | |
78a1a6d3 SR |
640 | #endif |
641 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 642 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
643 | if (enable) |
644 | reg += OMAP4_GPIO_IRQSTATUSSET0; | |
645 | else | |
646 | reg += OMAP4_GPIO_IRQSTATUSCLR0; | |
647 | l = gpio_mask; | |
648 | break; | |
e5c56ed3 | 649 | #endif |
5e1c5ff4 | 650 | default: |
e5c56ed3 | 651 | WARN_ON(1); |
5e1c5ff4 TL |
652 | return; |
653 | } | |
654 | __raw_writel(l, reg); | |
655 | } | |
656 | ||
657 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
658 | { | |
129fd223 | 659 | _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio), enable); |
5e1c5ff4 TL |
660 | } |
661 | ||
92105bb7 TL |
662 | /* |
663 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
664 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
665 | * to the target, system will wake up always on GPIO events. While | |
666 | * system is running all registered GPIO interrupts need to have wake-up | |
667 | * enabled. When system is suspended, only selected GPIO interrupts need | |
668 | * to have wake-up enabled. | |
669 | */ | |
670 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
671 | { | |
4cc6420c | 672 | unsigned long uninitialized_var(flags); |
a6472533 | 673 | |
92105bb7 | 674 | switch (bank->method) { |
3ac4fa99 | 675 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 676 | case METHOD_MPUIO: |
92105bb7 | 677 | case METHOD_GPIO_1610: |
a6472533 | 678 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 679 | if (enable) |
92105bb7 | 680 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 681 | else |
92105bb7 | 682 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 683 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 684 | return 0; |
3ac4fa99 | 685 | #endif |
140455fa | 686 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 | 687 | case METHOD_GPIO_24XX: |
3f1686a9 | 688 | case METHOD_GPIO_44XX: |
11a78b79 DB |
689 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
690 | printk(KERN_ERR "Unable to modify wakeup on " | |
691 | "non-wakeup GPIO%d\n", | |
d5f46247 | 692 | (bank - gpio_bank) * bank->width + gpio); |
11a78b79 DB |
693 | return -EINVAL; |
694 | } | |
a6472533 | 695 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 696 | if (enable) |
3ac4fa99 | 697 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 698 | else |
3ac4fa99 | 699 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 700 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
701 | return 0; |
702 | #endif | |
92105bb7 TL |
703 | default: |
704 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
705 | bank->method); | |
706 | return -EINVAL; | |
707 | } | |
708 | } | |
709 | ||
4196dd6b TL |
710 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
711 | { | |
129fd223 | 712 | _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); |
4196dd6b TL |
713 | _set_gpio_irqenable(bank, gpio, 0); |
714 | _clear_gpio_irqstatus(bank, gpio); | |
129fd223 | 715 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
716 | } |
717 | ||
92105bb7 | 718 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
e9191028 | 719 | static int gpio_wake_enable(struct irq_data *d, unsigned int enable) |
92105bb7 | 720 | { |
e9191028 | 721 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
92105bb7 TL |
722 | struct gpio_bank *bank; |
723 | int retval; | |
724 | ||
725 | if (check_gpio(gpio) < 0) | |
726 | return -ENODEV; | |
e9191028 | 727 | bank = irq_data_get_irq_chip_data(d); |
129fd223 | 728 | retval = _set_gpio_wakeup(bank, GPIO_INDEX(bank, gpio), enable); |
92105bb7 TL |
729 | |
730 | return retval; | |
731 | } | |
732 | ||
3ff164e1 | 733 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 734 | { |
3ff164e1 | 735 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 736 | unsigned long flags; |
52e31344 | 737 | |
a6472533 | 738 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 739 | |
4196dd6b TL |
740 | /* Set trigger to none. You need to enable the desired trigger with |
741 | * request_irq() or set_irq_type(). | |
742 | */ | |
3ff164e1 | 743 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 744 | |
1a8bfa1e | 745 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 746 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 747 | void __iomem *reg; |
5e1c5ff4 | 748 | |
92105bb7 | 749 | /* Claim the pin for MPU */ |
5e1c5ff4 | 750 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 751 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
752 | } |
753 | #endif | |
058af1ea C |
754 | if (!cpu_class_is_omap1()) { |
755 | if (!bank->mod_usage) { | |
9f096868 | 756 | void __iomem *reg = bank->base; |
058af1ea | 757 | u32 ctrl; |
9f096868 C |
758 | |
759 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
760 | reg += OMAP24XX_GPIO_CTRL; | |
761 | else if (cpu_is_omap44xx()) | |
762 | reg += OMAP4_GPIO_CTRL; | |
763 | ctrl = __raw_readl(reg); | |
058af1ea | 764 | /* Module is enabled, clocks are not gated */ |
9f096868 C |
765 | ctrl &= 0xFFFFFFFE; |
766 | __raw_writel(ctrl, reg); | |
058af1ea C |
767 | } |
768 | bank->mod_usage |= 1 << offset; | |
769 | } | |
a6472533 | 770 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
771 | |
772 | return 0; | |
773 | } | |
774 | ||
3ff164e1 | 775 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 776 | { |
3ff164e1 | 777 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 778 | unsigned long flags; |
5e1c5ff4 | 779 | |
a6472533 | 780 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
781 | #ifdef CONFIG_ARCH_OMAP16XX |
782 | if (bank->method == METHOD_GPIO_1610) { | |
783 | /* Disable wake-up during idle for dynamic tick */ | |
784 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 785 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
786 | } |
787 | #endif | |
9f096868 C |
788 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
789 | if (bank->method == METHOD_GPIO_24XX) { | |
92105bb7 TL |
790 | /* Disable wake-up during idle for dynamic tick */ |
791 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 792 | __raw_writel(1 << offset, reg); |
92105bb7 | 793 | } |
9f096868 C |
794 | #endif |
795 | #ifdef CONFIG_ARCH_OMAP4 | |
796 | if (bank->method == METHOD_GPIO_44XX) { | |
797 | /* Disable wake-up during idle for dynamic tick */ | |
798 | void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
799 | __raw_writel(1 << offset, reg); | |
800 | } | |
92105bb7 | 801 | #endif |
058af1ea C |
802 | if (!cpu_class_is_omap1()) { |
803 | bank->mod_usage &= ~(1 << offset); | |
804 | if (!bank->mod_usage) { | |
9f096868 | 805 | void __iomem *reg = bank->base; |
058af1ea | 806 | u32 ctrl; |
9f096868 C |
807 | |
808 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
809 | reg += OMAP24XX_GPIO_CTRL; | |
810 | else if (cpu_is_omap44xx()) | |
811 | reg += OMAP4_GPIO_CTRL; | |
812 | ctrl = __raw_readl(reg); | |
058af1ea C |
813 | /* Module is disabled, clocks are gated */ |
814 | ctrl |= 1; | |
9f096868 | 815 | __raw_writel(ctrl, reg); |
058af1ea C |
816 | } |
817 | } | |
3ff164e1 | 818 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 819 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
820 | } |
821 | ||
822 | /* | |
823 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
824 | * avoid missing GPIO interrupts for other lines in the bank. | |
825 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
826 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
827 | * If we wait to unmask individual GPIO lines in the bank after the | |
828 | * line's interrupt handler has been run, we may miss some nested | |
829 | * interrupts. | |
830 | */ | |
10dd5ce2 | 831 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 832 | { |
92105bb7 | 833 | void __iomem *isr_reg = NULL; |
5e1c5ff4 | 834 | u32 isr; |
4318f36b | 835 | unsigned int gpio_irq, gpio_index; |
5e1c5ff4 | 836 | struct gpio_bank *bank; |
ea6dedd7 ID |
837 | u32 retrigger = 0; |
838 | int unmasked = 0; | |
ee144182 | 839 | struct irq_chip *chip = irq_desc_get_chip(desc); |
5e1c5ff4 | 840 | |
ee144182 | 841 | chained_irq_enter(chip, desc); |
5e1c5ff4 | 842 | |
6845664a | 843 | bank = irq_get_handler_data(irq); |
e5c56ed3 | 844 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 | 845 | if (bank->method == METHOD_MPUIO) |
5de62b86 TL |
846 | isr_reg = bank->base + |
847 | OMAP_MPUIO_GPIO_INT / bank->stride; | |
e5c56ed3 | 848 | #endif |
1a8bfa1e | 849 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
850 | if (bank->method == METHOD_GPIO_1510) |
851 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
852 | #endif | |
853 | #if defined(CONFIG_ARCH_OMAP16XX) | |
854 | if (bank->method == METHOD_GPIO_1610) | |
855 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
856 | #endif | |
b718aa81 | 857 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
7c006926 AB |
858 | if (bank->method == METHOD_GPIO_7XX) |
859 | isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; | |
56739a69 | 860 | #endif |
a8eb7ca0 | 861 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 TL |
862 | if (bank->method == METHOD_GPIO_24XX) |
863 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
78a1a6d3 SR |
864 | #endif |
865 | #if defined(CONFIG_ARCH_OMAP4) | |
3f1686a9 | 866 | if (bank->method == METHOD_GPIO_44XX) |
78a1a6d3 | 867 | isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; |
92105bb7 | 868 | #endif |
b1cc4c55 EK |
869 | |
870 | if (WARN_ON(!isr_reg)) | |
871 | goto exit; | |
872 | ||
92105bb7 | 873 | while(1) { |
6e60e79a | 874 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 875 | u32 enabled; |
6e60e79a | 876 | |
ea6dedd7 ID |
877 | enabled = _get_gpio_irqbank_mask(bank); |
878 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
879 | |
880 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
881 | isr &= 0x0000ffff; | |
882 | ||
5492fb1a | 883 | if (cpu_class_is_omap2()) { |
b144ff6f | 884 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 885 | } |
6e60e79a TL |
886 | |
887 | /* clear edge sensitive interrupts before handler(s) are | |
888 | called so that we don't miss any interrupt occurred while | |
889 | executing them */ | |
890 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
891 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
892 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
893 | ||
894 | /* if there is only edge sensitive GPIO pin interrupts | |
895 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
896 | if (!level_mask && !unmasked) { |
897 | unmasked = 1; | |
ee144182 | 898 | chained_irq_exit(chip, desc); |
ea6dedd7 | 899 | } |
92105bb7 | 900 | |
ea6dedd7 ID |
901 | isr |= retrigger; |
902 | retrigger = 0; | |
92105bb7 TL |
903 | if (!isr) |
904 | break; | |
905 | ||
906 | gpio_irq = bank->virtual_irq_start; | |
907 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
129fd223 | 908 | gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq)); |
4318f36b | 909 | |
92105bb7 TL |
910 | if (!(isr & 1)) |
911 | continue; | |
29454dde | 912 | |
4318f36b CM |
913 | #ifdef CONFIG_ARCH_OMAP1 |
914 | /* | |
915 | * Some chips can't respond to both rising and falling | |
916 | * at the same time. If this irq was requested with | |
917 | * both flags, we need to flip the ICR data for the IRQ | |
918 | * to respond to the IRQ for the opposite direction. | |
919 | * This will be indicated in the bank toggle_mask. | |
920 | */ | |
921 | if (bank->toggle_mask & (1 << gpio_index)) | |
922 | _toggle_gpio_edge_triggering(bank, gpio_index); | |
923 | #endif | |
924 | ||
d8aa0251 | 925 | generic_handle_irq(gpio_irq); |
92105bb7 | 926 | } |
1a8bfa1e | 927 | } |
ea6dedd7 ID |
928 | /* if bank has any level sensitive GPIO pin interrupt |
929 | configured, we must unmask the bank interrupt only after | |
930 | handler(s) are executed in order to avoid spurious bank | |
931 | interrupt */ | |
b1cc4c55 | 932 | exit: |
ea6dedd7 | 933 | if (!unmasked) |
ee144182 | 934 | chained_irq_exit(chip, desc); |
5e1c5ff4 TL |
935 | } |
936 | ||
e9191028 | 937 | static void gpio_irq_shutdown(struct irq_data *d) |
4196dd6b | 938 | { |
e9191028 LB |
939 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
940 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 941 | unsigned long flags; |
4196dd6b | 942 | |
85ec7b97 | 943 | spin_lock_irqsave(&bank->lock, flags); |
4196dd6b | 944 | _reset_gpio(bank, gpio); |
85ec7b97 | 945 | spin_unlock_irqrestore(&bank->lock, flags); |
4196dd6b TL |
946 | } |
947 | ||
e9191028 | 948 | static void gpio_ack_irq(struct irq_data *d) |
5e1c5ff4 | 949 | { |
e9191028 LB |
950 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
951 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
952 | |
953 | _clear_gpio_irqstatus(bank, gpio); | |
954 | } | |
955 | ||
e9191028 | 956 | static void gpio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 957 | { |
e9191028 LB |
958 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
959 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
85ec7b97 | 960 | unsigned long flags; |
5e1c5ff4 | 961 | |
85ec7b97 | 962 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 963 | _set_gpio_irqenable(bank, gpio, 0); |
129fd223 | 964 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); |
85ec7b97 | 965 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
966 | } |
967 | ||
e9191028 | 968 | static void gpio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 969 | { |
e9191028 LB |
970 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
971 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
129fd223 | 972 | unsigned int irq_mask = GPIO_BIT(bank, gpio); |
8c04a176 | 973 | u32 trigger = irqd_get_trigger_type(d); |
85ec7b97 | 974 | unsigned long flags; |
55b6019a | 975 | |
85ec7b97 | 976 | spin_lock_irqsave(&bank->lock, flags); |
55b6019a | 977 | if (trigger) |
129fd223 | 978 | _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); |
b144ff6f KH |
979 | |
980 | /* For level-triggered GPIOs, the clearing must be done after | |
981 | * the HW source is cleared, thus after the handler has run */ | |
982 | if (bank->level_mask & irq_mask) { | |
983 | _set_gpio_irqenable(bank, gpio, 0); | |
984 | _clear_gpio_irqstatus(bank, gpio); | |
985 | } | |
5e1c5ff4 | 986 | |
4de8c75b | 987 | _set_gpio_irqenable(bank, gpio, 1); |
85ec7b97 | 988 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
989 | } |
990 | ||
e5c56ed3 DB |
991 | static struct irq_chip gpio_irq_chip = { |
992 | .name = "GPIO", | |
e9191028 LB |
993 | .irq_shutdown = gpio_irq_shutdown, |
994 | .irq_ack = gpio_ack_irq, | |
995 | .irq_mask = gpio_mask_irq, | |
996 | .irq_unmask = gpio_unmask_irq, | |
997 | .irq_set_type = gpio_irq_type, | |
998 | .irq_set_wake = gpio_wake_enable, | |
e5c56ed3 DB |
999 | }; |
1000 | ||
1001 | /*---------------------------------------------------------------------*/ | |
1002 | ||
1003 | #ifdef CONFIG_ARCH_OMAP1 | |
1004 | ||
1005 | /* MPUIO uses the always-on 32k clock */ | |
1006 | ||
e9191028 | 1007 | static void mpuio_ack_irq(struct irq_data *d) |
5e1c5ff4 TL |
1008 | { |
1009 | /* The ISR is reset automatically, so do nothing here. */ | |
1010 | } | |
1011 | ||
e9191028 | 1012 | static void mpuio_mask_irq(struct irq_data *d) |
5e1c5ff4 | 1013 | { |
e9191028 LB |
1014 | unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
1015 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
1016 | |
1017 | _set_gpio_irqenable(bank, gpio, 0); | |
1018 | } | |
1019 | ||
e9191028 | 1020 | static void mpuio_unmask_irq(struct irq_data *d) |
5e1c5ff4 | 1021 | { |
e9191028 LB |
1022 | unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); |
1023 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | |
5e1c5ff4 TL |
1024 | |
1025 | _set_gpio_irqenable(bank, gpio, 1); | |
1026 | } | |
1027 | ||
e5c56ed3 DB |
1028 | static struct irq_chip mpuio_irq_chip = { |
1029 | .name = "MPUIO", | |
e9191028 LB |
1030 | .irq_ack = mpuio_ack_irq, |
1031 | .irq_mask = mpuio_mask_irq, | |
1032 | .irq_unmask = mpuio_unmask_irq, | |
1033 | .irq_set_type = gpio_irq_type, | |
11a78b79 DB |
1034 | #ifdef CONFIG_ARCH_OMAP16XX |
1035 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
e9191028 | 1036 | .irq_set_wake = gpio_wake_enable, |
11a78b79 | 1037 | #endif |
5e1c5ff4 TL |
1038 | }; |
1039 | ||
e5c56ed3 DB |
1040 | |
1041 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1042 | ||
11a78b79 DB |
1043 | |
1044 | #ifdef CONFIG_ARCH_OMAP16XX | |
1045 | ||
1046 | #include <linux/platform_device.h> | |
1047 | ||
79ee031f | 1048 | static int omap_mpuio_suspend_noirq(struct device *dev) |
11a78b79 | 1049 | { |
79ee031f | 1050 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 1051 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
1052 | void __iomem *mask_reg = bank->base + |
1053 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 1054 | unsigned long flags; |
11a78b79 | 1055 | |
a6472533 | 1056 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1057 | bank->saved_wakeup = __raw_readl(mask_reg); |
1058 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1059 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1060 | |
1061 | return 0; | |
1062 | } | |
1063 | ||
79ee031f | 1064 | static int omap_mpuio_resume_noirq(struct device *dev) |
11a78b79 | 1065 | { |
79ee031f | 1066 | struct platform_device *pdev = to_platform_device(dev); |
11a78b79 | 1067 | struct gpio_bank *bank = platform_get_drvdata(pdev); |
5de62b86 TL |
1068 | void __iomem *mask_reg = bank->base + |
1069 | OMAP_MPUIO_GPIO_MASKIT / bank->stride; | |
a6472533 | 1070 | unsigned long flags; |
11a78b79 | 1071 | |
a6472533 | 1072 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1073 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1074 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1075 | |
1076 | return 0; | |
1077 | } | |
1078 | ||
47145210 | 1079 | static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { |
79ee031f MD |
1080 | .suspend_noirq = omap_mpuio_suspend_noirq, |
1081 | .resume_noirq = omap_mpuio_resume_noirq, | |
1082 | }; | |
1083 | ||
3c437ffd | 1084 | /* use platform_driver for this. */ |
11a78b79 | 1085 | static struct platform_driver omap_mpuio_driver = { |
11a78b79 DB |
1086 | .driver = { |
1087 | .name = "mpuio", | |
79ee031f | 1088 | .pm = &omap_mpuio_dev_pm_ops, |
11a78b79 DB |
1089 | }, |
1090 | }; | |
1091 | ||
1092 | static struct platform_device omap_mpuio_device = { | |
1093 | .name = "mpuio", | |
1094 | .id = -1, | |
1095 | .dev = { | |
1096 | .driver = &omap_mpuio_driver.driver, | |
1097 | } | |
1098 | /* could list the /proc/iomem resources */ | |
1099 | }; | |
1100 | ||
1101 | static inline void mpuio_init(void) | |
1102 | { | |
a8be8daf | 1103 | struct gpio_bank *bank = &gpio_bank[0]; |
77640aab | 1104 | platform_set_drvdata(&omap_mpuio_device, bank); |
fcf126d8 | 1105 | |
11a78b79 DB |
1106 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1107 | (void) platform_device_register(&omap_mpuio_device); | |
1108 | } | |
1109 | ||
1110 | #else | |
1111 | static inline void mpuio_init(void) {} | |
1112 | #endif /* 16xx */ | |
1113 | ||
e5c56ed3 DB |
1114 | #else |
1115 | ||
1116 | extern struct irq_chip mpuio_irq_chip; | |
1117 | ||
1118 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1119 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1120 | |
1121 | #endif | |
1122 | ||
1123 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1124 | |
52e31344 DB |
1125 | /* REVISIT these are stupid implementations! replace by ones that |
1126 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1127 | */ | |
1128 | ||
1129 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1130 | { | |
1131 | struct gpio_bank *bank; | |
1132 | unsigned long flags; | |
1133 | ||
1134 | bank = container_of(chip, struct gpio_bank, chip); | |
1135 | spin_lock_irqsave(&bank->lock, flags); | |
1136 | _set_gpio_direction(bank, offset, 1); | |
1137 | spin_unlock_irqrestore(&bank->lock, flags); | |
1138 | return 0; | |
1139 | } | |
1140 | ||
b37c45b8 RQ |
1141 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
1142 | { | |
fa87931a | 1143 | void __iomem *reg = bank->base + bank->regs->direction; |
b37c45b8 | 1144 | |
b37c45b8 RQ |
1145 | return __raw_readl(reg) & mask; |
1146 | } | |
1147 | ||
52e31344 DB |
1148 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
1149 | { | |
b37c45b8 RQ |
1150 | struct gpio_bank *bank; |
1151 | void __iomem *reg; | |
1152 | int gpio; | |
1153 | u32 mask; | |
1154 | ||
1155 | gpio = chip->base + offset; | |
a8be8daf | 1156 | bank = container_of(chip, struct gpio_bank, chip); |
b37c45b8 | 1157 | reg = bank->base; |
129fd223 | 1158 | mask = GPIO_BIT(bank, gpio); |
b37c45b8 RQ |
1159 | |
1160 | if (gpio_is_input(bank, mask)) | |
1161 | return _get_gpio_datain(bank, gpio); | |
1162 | else | |
1163 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
1164 | } |
1165 | ||
1166 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1167 | { | |
1168 | struct gpio_bank *bank; | |
1169 | unsigned long flags; | |
1170 | ||
1171 | bank = container_of(chip, struct gpio_bank, chip); | |
1172 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 1173 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
1174 | _set_gpio_direction(bank, offset, 0); |
1175 | spin_unlock_irqrestore(&bank->lock, flags); | |
1176 | return 0; | |
1177 | } | |
1178 | ||
168ef3d9 FB |
1179 | static int gpio_debounce(struct gpio_chip *chip, unsigned offset, |
1180 | unsigned debounce) | |
1181 | { | |
1182 | struct gpio_bank *bank; | |
1183 | unsigned long flags; | |
1184 | ||
1185 | bank = container_of(chip, struct gpio_bank, chip); | |
77640aab VC |
1186 | |
1187 | if (!bank->dbck) { | |
1188 | bank->dbck = clk_get(bank->dev, "dbclk"); | |
1189 | if (IS_ERR(bank->dbck)) | |
1190 | dev_err(bank->dev, "Could not get gpio dbck\n"); | |
1191 | } | |
1192 | ||
168ef3d9 FB |
1193 | spin_lock_irqsave(&bank->lock, flags); |
1194 | _set_gpio_debounce(bank, offset, debounce); | |
1195 | spin_unlock_irqrestore(&bank->lock, flags); | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
52e31344 DB |
1200 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
1201 | { | |
1202 | struct gpio_bank *bank; | |
1203 | unsigned long flags; | |
1204 | ||
1205 | bank = container_of(chip, struct gpio_bank, chip); | |
1206 | spin_lock_irqsave(&bank->lock, flags); | |
fa87931a | 1207 | bank->set_dataout(bank, offset, value); |
52e31344 DB |
1208 | spin_unlock_irqrestore(&bank->lock, flags); |
1209 | } | |
1210 | ||
a007b709 DB |
1211 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
1212 | { | |
1213 | struct gpio_bank *bank; | |
1214 | ||
1215 | bank = container_of(chip, struct gpio_bank, chip); | |
1216 | return bank->virtual_irq_start + offset; | |
1217 | } | |
1218 | ||
52e31344 DB |
1219 | /*---------------------------------------------------------------------*/ |
1220 | ||
9a748053 | 1221 | static void __init omap_gpio_show_rev(struct gpio_bank *bank) |
9f7065da TL |
1222 | { |
1223 | u32 rev; | |
1224 | ||
9a748053 TL |
1225 | if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO)) |
1226 | rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION); | |
9f7065da | 1227 | else if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
9a748053 | 1228 | rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION); |
9f7065da | 1229 | else if (cpu_is_omap44xx()) |
9a748053 | 1230 | rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION); |
9f7065da TL |
1231 | else |
1232 | return; | |
1233 | ||
1234 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | |
1235 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1236 | } | |
1237 | ||
8ba55c5c DB |
1238 | /* This lock class tells lockdep that GPIO irqs are in a different |
1239 | * category than their parents, so it won't report false recursion. | |
1240 | */ | |
1241 | static struct lock_class_key gpio_lock_class; | |
1242 | ||
77640aab VC |
1243 | static inline int init_gpio_info(struct platform_device *pdev) |
1244 | { | |
1245 | /* TODO: Analyze removing gpio_bank_count usage from driver code */ | |
1246 | gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank), | |
1247 | GFP_KERNEL); | |
1248 | if (!gpio_bank) { | |
1249 | dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); | |
1250 | return -ENOMEM; | |
1251 | } | |
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | /* TODO: Cleanup cpu_is_* checks */ | |
2fae7fbe VC |
1256 | static void omap_gpio_mod_init(struct gpio_bank *bank, int id) |
1257 | { | |
1258 | if (cpu_class_is_omap2()) { | |
1259 | if (cpu_is_omap44xx()) { | |
1260 | __raw_writel(0xffffffff, bank->base + | |
1261 | OMAP4_GPIO_IRQSTATUSCLR0); | |
1262 | __raw_writel(0x00000000, bank->base + | |
1263 | OMAP4_GPIO_DEBOUNCENABLE); | |
1264 | /* Initialize interface clk ungated, module enabled */ | |
1265 | __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); | |
1266 | } else if (cpu_is_omap34xx()) { | |
1267 | __raw_writel(0x00000000, bank->base + | |
1268 | OMAP24XX_GPIO_IRQENABLE1); | |
1269 | __raw_writel(0xffffffff, bank->base + | |
1270 | OMAP24XX_GPIO_IRQSTATUS1); | |
1271 | __raw_writel(0x00000000, bank->base + | |
1272 | OMAP24XX_GPIO_DEBOUNCE_EN); | |
1273 | ||
1274 | /* Initialize interface clk ungated, module enabled */ | |
1275 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
1276 | } else if (cpu_is_omap24xx()) { | |
1277 | static const u32 non_wakeup_gpios[] = { | |
1278 | 0xe203ffc0, 0x08700040 | |
1279 | }; | |
1280 | if (id < ARRAY_SIZE(non_wakeup_gpios)) | |
1281 | bank->non_wakeup_gpios = non_wakeup_gpios[id]; | |
1282 | } | |
1283 | } else if (cpu_class_is_omap1()) { | |
1284 | if (bank_is_mpuio(bank)) | |
5de62b86 TL |
1285 | __raw_writew(0xffff, bank->base + |
1286 | OMAP_MPUIO_GPIO_MASKIT / bank->stride); | |
2fae7fbe VC |
1287 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
1288 | __raw_writew(0xffff, bank->base | |
1289 | + OMAP1510_GPIO_INT_MASK); | |
1290 | __raw_writew(0x0000, bank->base | |
1291 | + OMAP1510_GPIO_INT_STATUS); | |
1292 | } | |
1293 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { | |
1294 | __raw_writew(0x0000, bank->base | |
1295 | + OMAP1610_GPIO_IRQENABLE1); | |
1296 | __raw_writew(0xffff, bank->base | |
1297 | + OMAP1610_GPIO_IRQSTATUS1); | |
1298 | __raw_writew(0x0014, bank->base | |
1299 | + OMAP1610_GPIO_SYSCONFIG); | |
1300 | ||
1301 | /* | |
1302 | * Enable system clock for GPIO module. | |
1303 | * The CAM_CLK_CTRL *is* really the right place. | |
1304 | */ | |
1305 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, | |
1306 | ULPD_CAM_CLK_CTRL); | |
1307 | } | |
1308 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { | |
1309 | __raw_writel(0xffffffff, bank->base | |
1310 | + OMAP7XX_GPIO_INT_MASK); | |
1311 | __raw_writel(0x00000000, bank->base | |
1312 | + OMAP7XX_GPIO_INT_STATUS); | |
1313 | } | |
1314 | } | |
1315 | } | |
1316 | ||
d52b31de | 1317 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) |
2fae7fbe | 1318 | { |
77640aab | 1319 | int j; |
2fae7fbe VC |
1320 | static int gpio; |
1321 | ||
2fae7fbe VC |
1322 | bank->mod_usage = 0; |
1323 | /* | |
1324 | * REVISIT eventually switch from OMAP-specific gpio structs | |
1325 | * over to the generic ones | |
1326 | */ | |
1327 | bank->chip.request = omap_gpio_request; | |
1328 | bank->chip.free = omap_gpio_free; | |
1329 | bank->chip.direction_input = gpio_input; | |
1330 | bank->chip.get = gpio_get; | |
1331 | bank->chip.direction_output = gpio_output; | |
1332 | bank->chip.set_debounce = gpio_debounce; | |
1333 | bank->chip.set = gpio_set; | |
1334 | bank->chip.to_irq = gpio_2irq; | |
1335 | if (bank_is_mpuio(bank)) { | |
1336 | bank->chip.label = "mpuio"; | |
1337 | #ifdef CONFIG_ARCH_OMAP16XX | |
1338 | bank->chip.dev = &omap_mpuio_device.dev; | |
1339 | #endif | |
1340 | bank->chip.base = OMAP_MPUIO(0); | |
1341 | } else { | |
1342 | bank->chip.label = "gpio"; | |
1343 | bank->chip.base = gpio; | |
d5f46247 | 1344 | gpio += bank->width; |
2fae7fbe | 1345 | } |
d5f46247 | 1346 | bank->chip.ngpio = bank->width; |
2fae7fbe VC |
1347 | |
1348 | gpiochip_add(&bank->chip); | |
1349 | ||
1350 | for (j = bank->virtual_irq_start; | |
d5f46247 | 1351 | j < bank->virtual_irq_start + bank->width; j++) { |
1475b85d | 1352 | irq_set_lockdep_class(j, &gpio_lock_class); |
6845664a | 1353 | irq_set_chip_data(j, bank); |
2fae7fbe | 1354 | if (bank_is_mpuio(bank)) |
6845664a | 1355 | irq_set_chip(j, &mpuio_irq_chip); |
2fae7fbe | 1356 | else |
6845664a TG |
1357 | irq_set_chip(j, &gpio_irq_chip); |
1358 | irq_set_handler(j, handle_simple_irq); | |
2fae7fbe VC |
1359 | set_irq_flags(j, IRQF_VALID); |
1360 | } | |
6845664a TG |
1361 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1362 | irq_set_handler_data(bank->irq, bank); | |
2fae7fbe VC |
1363 | } |
1364 | ||
77640aab | 1365 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
5e1c5ff4 | 1366 | { |
77640aab VC |
1367 | static int gpio_init_done; |
1368 | struct omap_gpio_platform_data *pdata; | |
1369 | struct resource *res; | |
1370 | int id; | |
5e1c5ff4 TL |
1371 | struct gpio_bank *bank; |
1372 | ||
77640aab VC |
1373 | if (!pdev->dev.platform_data) |
1374 | return -EINVAL; | |
5e1c5ff4 | 1375 | |
77640aab | 1376 | pdata = pdev->dev.platform_data; |
56a25641 | 1377 | |
77640aab VC |
1378 | if (!gpio_init_done) { |
1379 | int ret; | |
5492fb1a | 1380 | |
77640aab VC |
1381 | ret = init_gpio_info(pdev); |
1382 | if (ret) | |
1383 | return ret; | |
5492fb1a | 1384 | } |
5492fb1a | 1385 | |
77640aab VC |
1386 | id = pdev->id; |
1387 | bank = &gpio_bank[id]; | |
92105bb7 | 1388 | |
77640aab VC |
1389 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
1390 | if (unlikely(!res)) { | |
1391 | dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id); | |
1392 | return -ENODEV; | |
44169075 | 1393 | } |
5e1c5ff4 | 1394 | |
77640aab VC |
1395 | bank->irq = res->start; |
1396 | bank->virtual_irq_start = pdata->virtual_irq_start; | |
1397 | bank->method = pdata->bank_type; | |
1398 | bank->dev = &pdev->dev; | |
1399 | bank->dbck_flag = pdata->dbck_flag; | |
5de62b86 | 1400 | bank->stride = pdata->bank_stride; |
d5f46247 | 1401 | bank->width = pdata->bank_width; |
9f7065da | 1402 | |
fa87931a KH |
1403 | bank->regs = pdata->regs; |
1404 | ||
1405 | if (bank->regs->set_dataout && bank->regs->clr_dataout) | |
1406 | bank->set_dataout = _set_gpio_dataout_reg; | |
1407 | else | |
1408 | bank->set_dataout = _set_gpio_dataout_mask; | |
1409 | ||
77640aab | 1410 | spin_lock_init(&bank->lock); |
9f7065da | 1411 | |
77640aab VC |
1412 | /* Static mapping, never released */ |
1413 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1414 | if (unlikely(!res)) { | |
1415 | dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id); | |
1416 | return -ENODEV; | |
1417 | } | |
89db9482 | 1418 | |
77640aab VC |
1419 | bank->base = ioremap(res->start, resource_size(res)); |
1420 | if (!bank->base) { | |
1421 | dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id); | |
1422 | return -ENOMEM; | |
5e1c5ff4 TL |
1423 | } |
1424 | ||
77640aab VC |
1425 | pm_runtime_enable(bank->dev); |
1426 | pm_runtime_get_sync(bank->dev); | |
1427 | ||
1428 | omap_gpio_mod_init(bank, id); | |
1429 | omap_gpio_chip_init(bank); | |
9a748053 | 1430 | omap_gpio_show_rev(bank); |
9f7065da | 1431 | |
77640aab VC |
1432 | if (!gpio_init_done) |
1433 | gpio_init_done = 1; | |
1434 | ||
5e1c5ff4 TL |
1435 | return 0; |
1436 | } | |
1437 | ||
140455fa | 1438 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
3c437ffd | 1439 | static int omap_gpio_suspend(void) |
92105bb7 TL |
1440 | { |
1441 | int i; | |
1442 | ||
5492fb1a | 1443 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1444 | return 0; |
1445 | ||
1446 | for (i = 0; i < gpio_bank_count; i++) { | |
1447 | struct gpio_bank *bank = &gpio_bank[i]; | |
1448 | void __iomem *wake_status; | |
1449 | void __iomem *wake_clear; | |
1450 | void __iomem *wake_set; | |
a6472533 | 1451 | unsigned long flags; |
92105bb7 TL |
1452 | |
1453 | switch (bank->method) { | |
e5c56ed3 | 1454 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1455 | case METHOD_GPIO_1610: |
1456 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1457 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1458 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1459 | break; | |
e5c56ed3 | 1460 | #endif |
a8eb7ca0 | 1461 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1462 | case METHOD_GPIO_24XX: |
723fdb78 | 1463 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1464 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1465 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1466 | break; | |
78a1a6d3 SR |
1467 | #endif |
1468 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1469 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1470 | wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1471 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1472 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1473 | break; | |
e5c56ed3 | 1474 | #endif |
92105bb7 TL |
1475 | default: |
1476 | continue; | |
1477 | } | |
1478 | ||
a6472533 | 1479 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1480 | bank->saved_wakeup = __raw_readl(wake_status); |
1481 | __raw_writel(0xffffffff, wake_clear); | |
1482 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1483 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1484 | } |
1485 | ||
1486 | return 0; | |
1487 | } | |
1488 | ||
3c437ffd | 1489 | static void omap_gpio_resume(void) |
92105bb7 TL |
1490 | { |
1491 | int i; | |
1492 | ||
723fdb78 | 1493 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
3c437ffd | 1494 | return; |
92105bb7 TL |
1495 | |
1496 | for (i = 0; i < gpio_bank_count; i++) { | |
1497 | struct gpio_bank *bank = &gpio_bank[i]; | |
1498 | void __iomem *wake_clear; | |
1499 | void __iomem *wake_set; | |
a6472533 | 1500 | unsigned long flags; |
92105bb7 TL |
1501 | |
1502 | switch (bank->method) { | |
e5c56ed3 | 1503 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1504 | case METHOD_GPIO_1610: |
1505 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1506 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1507 | break; | |
e5c56ed3 | 1508 | #endif |
a8eb7ca0 | 1509 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
92105bb7 | 1510 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1511 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1512 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1513 | break; |
78a1a6d3 SR |
1514 | #endif |
1515 | #ifdef CONFIG_ARCH_OMAP4 | |
3f1686a9 | 1516 | case METHOD_GPIO_44XX: |
78a1a6d3 SR |
1517 | wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; |
1518 | wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; | |
1519 | break; | |
e5c56ed3 | 1520 | #endif |
92105bb7 TL |
1521 | default: |
1522 | continue; | |
1523 | } | |
1524 | ||
a6472533 | 1525 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1526 | __raw_writel(0xffffffff, wake_clear); |
1527 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 1528 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1529 | } |
92105bb7 TL |
1530 | } |
1531 | ||
3c437ffd | 1532 | static struct syscore_ops omap_gpio_syscore_ops = { |
92105bb7 TL |
1533 | .suspend = omap_gpio_suspend, |
1534 | .resume = omap_gpio_resume, | |
1535 | }; | |
1536 | ||
3ac4fa99 JY |
1537 | #endif |
1538 | ||
140455fa | 1539 | #ifdef CONFIG_ARCH_OMAP2PLUS |
3ac4fa99 JY |
1540 | |
1541 | static int workaround_enabled; | |
1542 | ||
72e06d08 | 1543 | void omap2_gpio_prepare_for_idle(int off_mode) |
3ac4fa99 JY |
1544 | { |
1545 | int i, c = 0; | |
a118b5f3 | 1546 | int min = 0; |
3ac4fa99 | 1547 | |
a118b5f3 TK |
1548 | if (cpu_is_omap34xx()) |
1549 | min = 1; | |
43ffcd9a | 1550 | |
a118b5f3 | 1551 | for (i = min; i < gpio_bank_count; i++) { |
3ac4fa99 | 1552 | struct gpio_bank *bank = &gpio_bank[i]; |
ca828760 | 1553 | u32 l1 = 0, l2 = 0; |
0aed0435 | 1554 | int j; |
3ac4fa99 | 1555 | |
0aed0435 | 1556 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1557 | clk_disable(bank->dbck); |
1558 | ||
72e06d08 | 1559 | if (!off_mode) |
43ffcd9a KH |
1560 | continue; |
1561 | ||
1562 | /* If going to OFF, remove triggering for all | |
1563 | * non-wakeup GPIOs. Otherwise spurious IRQs will be | |
1564 | * generated. See OMAP2420 Errata item 1.101. */ | |
3ac4fa99 JY |
1565 | if (!(bank->enabled_non_wakeup_gpios)) |
1566 | continue; | |
3f1686a9 TL |
1567 | |
1568 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1569 | bank->saved_datain = __raw_readl(bank->base + | |
1570 | OMAP24XX_GPIO_DATAIN); | |
1571 | l1 = __raw_readl(bank->base + | |
1572 | OMAP24XX_GPIO_FALLINGDETECT); | |
1573 | l2 = __raw_readl(bank->base + | |
1574 | OMAP24XX_GPIO_RISINGDETECT); | |
1575 | } | |
1576 | ||
1577 | if (cpu_is_omap44xx()) { | |
1578 | bank->saved_datain = __raw_readl(bank->base + | |
1579 | OMAP4_GPIO_DATAIN); | |
1580 | l1 = __raw_readl(bank->base + | |
1581 | OMAP4_GPIO_FALLINGDETECT); | |
1582 | l2 = __raw_readl(bank->base + | |
1583 | OMAP4_GPIO_RISINGDETECT); | |
1584 | } | |
1585 | ||
3ac4fa99 JY |
1586 | bank->saved_fallingdetect = l1; |
1587 | bank->saved_risingdetect = l2; | |
1588 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1589 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
3f1686a9 TL |
1590 | |
1591 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1592 | __raw_writel(l1, bank->base + | |
1593 | OMAP24XX_GPIO_FALLINGDETECT); | |
1594 | __raw_writel(l2, bank->base + | |
1595 | OMAP24XX_GPIO_RISINGDETECT); | |
1596 | } | |
1597 | ||
1598 | if (cpu_is_omap44xx()) { | |
1599 | __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); | |
1600 | __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); | |
1601 | } | |
1602 | ||
3ac4fa99 JY |
1603 | c++; |
1604 | } | |
1605 | if (!c) { | |
1606 | workaround_enabled = 0; | |
1607 | return; | |
1608 | } | |
1609 | workaround_enabled = 1; | |
1610 | } | |
1611 | ||
43ffcd9a | 1612 | void omap2_gpio_resume_after_idle(void) |
3ac4fa99 JY |
1613 | { |
1614 | int i; | |
a118b5f3 | 1615 | int min = 0; |
3ac4fa99 | 1616 | |
a118b5f3 TK |
1617 | if (cpu_is_omap34xx()) |
1618 | min = 1; | |
1619 | for (i = min; i < gpio_bank_count; i++) { | |
3ac4fa99 | 1620 | struct gpio_bank *bank = &gpio_bank[i]; |
ca828760 | 1621 | u32 l = 0, gen, gen0, gen1; |
0aed0435 | 1622 | int j; |
3ac4fa99 | 1623 | |
0aed0435 | 1624 | for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) |
8865b9b6 KH |
1625 | clk_enable(bank->dbck); |
1626 | ||
43ffcd9a KH |
1627 | if (!workaround_enabled) |
1628 | continue; | |
1629 | ||
3ac4fa99 JY |
1630 | if (!(bank->enabled_non_wakeup_gpios)) |
1631 | continue; | |
3f1686a9 TL |
1632 | |
1633 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1634 | __raw_writel(bank->saved_fallingdetect, | |
3ac4fa99 | 1635 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
3f1686a9 | 1636 | __raw_writel(bank->saved_risingdetect, |
3ac4fa99 | 1637 | bank->base + OMAP24XX_GPIO_RISINGDETECT); |
3f1686a9 TL |
1638 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
1639 | } | |
1640 | ||
1641 | if (cpu_is_omap44xx()) { | |
1642 | __raw_writel(bank->saved_fallingdetect, | |
78a1a6d3 | 1643 | bank->base + OMAP4_GPIO_FALLINGDETECT); |
3f1686a9 | 1644 | __raw_writel(bank->saved_risingdetect, |
78a1a6d3 | 1645 | bank->base + OMAP4_GPIO_RISINGDETECT); |
3f1686a9 TL |
1646 | l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); |
1647 | } | |
1648 | ||
3ac4fa99 JY |
1649 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1650 | * state. If so, generate an IRQ by software. This is | |
1651 | * horribly racy, but it's the best we can do to work around | |
1652 | * this silicon bug. */ | |
3ac4fa99 | 1653 | l ^= bank->saved_datain; |
a118b5f3 | 1654 | l &= bank->enabled_non_wakeup_gpios; |
82dbb9d3 EN |
1655 | |
1656 | /* | |
1657 | * No need to generate IRQs for the rising edge for gpio IRQs | |
1658 | * configured with falling edge only; and vice versa. | |
1659 | */ | |
1660 | gen0 = l & bank->saved_fallingdetect; | |
1661 | gen0 &= bank->saved_datain; | |
1662 | ||
1663 | gen1 = l & bank->saved_risingdetect; | |
1664 | gen1 &= ~(bank->saved_datain); | |
1665 | ||
1666 | /* FIXME: Consider GPIO IRQs with level detections properly! */ | |
1667 | gen = l & (~(bank->saved_fallingdetect) & | |
1668 | ~(bank->saved_risingdetect)); | |
1669 | /* Consider all GPIO IRQs needed to be updated */ | |
1670 | gen |= gen0 | gen1; | |
1671 | ||
1672 | if (gen) { | |
3ac4fa99 | 1673 | u32 old0, old1; |
3f1686a9 | 1674 | |
f00d6497 | 1675 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
3f1686a9 TL |
1676 | old0 = __raw_readl(bank->base + |
1677 | OMAP24XX_GPIO_LEVELDETECT0); | |
1678 | old1 = __raw_readl(bank->base + | |
1679 | OMAP24XX_GPIO_LEVELDETECT1); | |
f00d6497 | 1680 | __raw_writel(old0 | gen, bank->base + |
82dbb9d3 | 1681 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 1682 | __raw_writel(old1 | gen, bank->base + |
82dbb9d3 | 1683 | OMAP24XX_GPIO_LEVELDETECT1); |
f00d6497 | 1684 | __raw_writel(old0, bank->base + |
3f1686a9 | 1685 | OMAP24XX_GPIO_LEVELDETECT0); |
f00d6497 | 1686 | __raw_writel(old1, bank->base + |
3f1686a9 TL |
1687 | OMAP24XX_GPIO_LEVELDETECT1); |
1688 | } | |
1689 | ||
1690 | if (cpu_is_omap44xx()) { | |
1691 | old0 = __raw_readl(bank->base + | |
78a1a6d3 | 1692 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1693 | old1 = __raw_readl(bank->base + |
78a1a6d3 | 1694 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1695 | __raw_writel(old0 | l, bank->base + |
78a1a6d3 | 1696 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1697 | __raw_writel(old1 | l, bank->base + |
78a1a6d3 | 1698 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1699 | __raw_writel(old0, bank->base + |
78a1a6d3 | 1700 | OMAP4_GPIO_LEVELDETECT0); |
3f1686a9 | 1701 | __raw_writel(old1, bank->base + |
78a1a6d3 | 1702 | OMAP4_GPIO_LEVELDETECT1); |
3f1686a9 | 1703 | } |
3ac4fa99 JY |
1704 | } |
1705 | } | |
1706 | ||
1707 | } | |
1708 | ||
92105bb7 TL |
1709 | #endif |
1710 | ||
a8eb7ca0 | 1711 | #ifdef CONFIG_ARCH_OMAP3 |
40c670f0 RN |
1712 | /* save the registers of bank 2-6 */ |
1713 | void omap_gpio_save_context(void) | |
1714 | { | |
1715 | int i; | |
1716 | ||
1717 | /* saving banks from 2-6 only since GPIO1 is in WKUP */ | |
1718 | for (i = 1; i < gpio_bank_count; i++) { | |
1719 | struct gpio_bank *bank = &gpio_bank[i]; | |
40c670f0 RN |
1720 | gpio_context[i].irqenable1 = |
1721 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
1722 | gpio_context[i].irqenable2 = | |
1723 | __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
1724 | gpio_context[i].wake_en = | |
1725 | __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); | |
1726 | gpio_context[i].ctrl = | |
1727 | __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); | |
1728 | gpio_context[i].oe = | |
1729 | __raw_readl(bank->base + OMAP24XX_GPIO_OE); | |
1730 | gpio_context[i].leveldetect0 = | |
1731 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1732 | gpio_context[i].leveldetect1 = | |
1733 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1734 | gpio_context[i].risingdetect = | |
1735 | __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
1736 | gpio_context[i].fallingdetect = | |
1737 | __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1738 | gpio_context[i].dataout = | |
1739 | __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
1740 | } |
1741 | } | |
1742 | ||
1743 | /* restore the required registers of bank 2-6 */ | |
1744 | void omap_gpio_restore_context(void) | |
1745 | { | |
1746 | int i; | |
1747 | ||
1748 | for (i = 1; i < gpio_bank_count; i++) { | |
1749 | struct gpio_bank *bank = &gpio_bank[i]; | |
40c670f0 RN |
1750 | __raw_writel(gpio_context[i].irqenable1, |
1751 | bank->base + OMAP24XX_GPIO_IRQENABLE1); | |
1752 | __raw_writel(gpio_context[i].irqenable2, | |
1753 | bank->base + OMAP24XX_GPIO_IRQENABLE2); | |
1754 | __raw_writel(gpio_context[i].wake_en, | |
1755 | bank->base + OMAP24XX_GPIO_WAKE_EN); | |
1756 | __raw_writel(gpio_context[i].ctrl, | |
1757 | bank->base + OMAP24XX_GPIO_CTRL); | |
1758 | __raw_writel(gpio_context[i].oe, | |
1759 | bank->base + OMAP24XX_GPIO_OE); | |
1760 | __raw_writel(gpio_context[i].leveldetect0, | |
1761 | bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1762 | __raw_writel(gpio_context[i].leveldetect1, | |
1763 | bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1764 | __raw_writel(gpio_context[i].risingdetect, | |
1765 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
1766 | __raw_writel(gpio_context[i].fallingdetect, | |
1767 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1768 | __raw_writel(gpio_context[i].dataout, | |
1769 | bank->base + OMAP24XX_GPIO_DATAOUT); | |
40c670f0 RN |
1770 | } |
1771 | } | |
1772 | #endif | |
1773 | ||
77640aab VC |
1774 | static struct platform_driver omap_gpio_driver = { |
1775 | .probe = omap_gpio_probe, | |
1776 | .driver = { | |
1777 | .name = "omap_gpio", | |
1778 | }, | |
1779 | }; | |
1780 | ||
5e1c5ff4 | 1781 | /* |
77640aab VC |
1782 | * gpio driver register needs to be done before |
1783 | * machine_init functions access gpio APIs. | |
1784 | * Hence omap_gpio_drv_reg() is a postcore_initcall. | |
5e1c5ff4 | 1785 | */ |
77640aab | 1786 | static int __init omap_gpio_drv_reg(void) |
5e1c5ff4 | 1787 | { |
77640aab | 1788 | return platform_driver_register(&omap_gpio_driver); |
5e1c5ff4 | 1789 | } |
77640aab | 1790 | postcore_initcall(omap_gpio_drv_reg); |
5e1c5ff4 | 1791 | |
92105bb7 TL |
1792 | static int __init omap_gpio_sysinit(void) |
1793 | { | |
11a78b79 DB |
1794 | mpuio_init(); |
1795 | ||
140455fa | 1796 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) |
3c437ffd RW |
1797 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) |
1798 | register_syscore_ops(&omap_gpio_syscore_ops); | |
92105bb7 TL |
1799 | #endif |
1800 | ||
3c437ffd | 1801 | return 0; |
92105bb7 TL |
1802 | } |
1803 | ||
92105bb7 | 1804 | arch_initcall(omap_gpio_sysinit); |