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9e60fdcf 1/*
1e191695 2 * PCA953x 4/8/16/24/40 bit I/O ports
9e60fdcf 3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd.
6 *
7 * Derived from drivers/i2c/chips/pca9539.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */
13
b413d7a0 14#include <linux/acpi.h>
d120c17f 15#include <linux/gpio.h>
054ccdef 16#include <linux/gpio/consumer.h>
9e60fdcf 17#include <linux/i2c.h>
b413d7a0
AS
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/of_platform.h>
5877457a 22#include <linux/platform_data/pca953x.h>
b413d7a0 23#include <linux/regulator/consumer.h>
5a0e3ad6 24#include <linux/slab.h>
b413d7a0 25
9b8e3ec3 26#include <asm/unaligned.h>
9e60fdcf 27
33226ffd
HZ
28#define PCA953X_INPUT 0
29#define PCA953X_OUTPUT 1
30#define PCA953X_INVERT 2
31#define PCA953X_DIRECTION 3
32
ae79c190
AS
33#define REG_ADDR_AI 0x80
34
33226ffd
HZ
35#define PCA957X_IN 0
36#define PCA957X_INVRT 1
37#define PCA957X_BKEN 2
38#define PCA957X_PUPD 3
39#define PCA957X_CFG 4
40#define PCA957X_OUT 5
41#define PCA957X_MSK 6
42#define PCA957X_INTS 7
43
44896bea
YL
44#define PCAL953X_IN_LATCH 34
45#define PCAL953X_INT_MASK 37
46#define PCAL953X_INT_STAT 38
47
33226ffd
HZ
48#define PCA_GPIO_MASK 0x00FF
49#define PCA_INT 0x0100
8c7a92da 50#define PCA_PCAL 0x0200
33226ffd
HZ
51#define PCA953X_TYPE 0x1000
52#define PCA957X_TYPE 0x2000
c6664149
AS
53#define PCA_TYPE_MASK 0xF000
54
55#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
89ea8bbe 56
3760f736 57static const struct i2c_device_id pca953x_id[] = {
89f5df01 58 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
33226ffd
HZ
59 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
60 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
61 { "pca9536", 4 | PCA953X_TYPE, },
62 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
63 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
64 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
65 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
66 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
67 { "pca9556", 8 | PCA953X_TYPE, },
68 { "pca9557", 8 | PCA953X_TYPE, },
69 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
70 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
eb32b5aa 71 { "pca9698", 40 | PCA953X_TYPE, },
33226ffd 72
747e42a1
AS
73 { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
74
33226ffd
HZ
75 { "max7310", 8 | PCA953X_TYPE, },
76 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
77 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
78 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
1208c935 79 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
33226ffd
HZ
80 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
81 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
82 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
ae79c190 83 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
2db8aba8 84 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
1b9a0c25 85 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
e73760a6 86 { "xra1202", 8 | PCA953X_TYPE },
3760f736 87 { }
f5e8ff48 88};
3760f736 89MODULE_DEVICE_TABLE(i2c, pca953x_id);
9e60fdcf 90
f32517bf 91static const struct acpi_device_id pca953x_acpi_ids[] = {
44896bea 92 { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
f32517bf
AS
93 { }
94};
95MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
96
f5f0b7aa
GC
97#define MAX_BANK 5
98#define BANK_SZ 8
99
a246b819 100#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
f5f0b7aa 101
53661f3b
BG
102struct pca953x_reg_config {
103 int direction;
104 int output;
105 int input;
106};
107
108static const struct pca953x_reg_config pca953x_regs = {
109 .direction = PCA953X_DIRECTION,
110 .output = PCA953X_OUTPUT,
111 .input = PCA953X_INPUT,
112};
113
114static const struct pca953x_reg_config pca957x_regs = {
115 .direction = PCA957X_CFG,
116 .output = PCA957X_OUT,
117 .input = PCA957X_IN,
118};
119
f3dc3630 120struct pca953x_chip {
9e60fdcf 121 unsigned gpio_start;
f5f0b7aa
GC
122 u8 reg_output[MAX_BANK];
123 u8 reg_direction[MAX_BANK];
6e20fb18 124 struct mutex i2c_lock;
9e60fdcf 125
89ea8bbe
MZ
126#ifdef CONFIG_GPIO_PCA953X_IRQ
127 struct mutex irq_lock;
f5f0b7aa
GC
128 u8 irq_mask[MAX_BANK];
129 u8 irq_stat[MAX_BANK];
130 u8 irq_trig_raise[MAX_BANK];
131 u8 irq_trig_fall[MAX_BANK];
89ea8bbe
MZ
132#endif
133
9e60fdcf 134 struct i2c_client *client;
135 struct gpio_chip gpio_chip;
62154991 136 const char *const *names;
c6664149 137 unsigned long driver_data;
e23efa31 138 struct regulator *regulator;
53661f3b
BG
139
140 const struct pca953x_reg_config *regs;
7acc66e3
BG
141
142 int (*write_regs)(struct pca953x_chip *, int, u8 *);
c6e3cf01 143 int (*read_regs)(struct pca953x_chip *, int, u8 *);
9e60fdcf 144};
145
f5f0b7aa
GC
146static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
147 int off)
148{
149 int ret;
150 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
151 int offset = off / BANK_SZ;
152
153 ret = i2c_smbus_read_byte_data(chip->client,
154 (reg << bank_shift) + offset);
155 *val = ret;
156
157 if (ret < 0) {
158 dev_err(&chip->client->dev, "failed reading register\n");
159 return ret;
160 }
161
162 return 0;
163}
164
165static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
166 int off)
167{
8c7a92da 168 int ret;
f5f0b7aa
GC
169 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
170 int offset = off / BANK_SZ;
171
172 ret = i2c_smbus_write_byte_data(chip->client,
173 (reg << bank_shift) + offset, val);
174
175 if (ret < 0) {
176 dev_err(&chip->client->dev, "failed writing register\n");
177 return ret;
178 }
179
180 return 0;
181}
182
7acc66e3 183static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 184{
7acc66e3
BG
185 return i2c_smbus_write_byte_data(chip->client, reg, *val);
186}
f5e8ff48 187
7acc66e3
BG
188static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
189{
190 __le16 word = cpu_to_le16(get_unaligned((u16 *)val));
c4d1cbd7 191
7acc66e3
BG
192 return i2c_smbus_write_word_data(chip->client,
193 reg << 1, (__force u16)word);
194}
195
196static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
197{
198 int ret;
199
200 ret = i2c_smbus_write_byte_data(chip->client, reg << 1, val[0]);
201 if (ret < 0)
202 return ret;
203
204 return i2c_smbus_write_byte_data(chip->client, (reg << 1) + 1, val[1]);
205}
f5e8ff48 206
7acc66e3
BG
207static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
208{
209 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
210
211 return i2c_smbus_write_i2c_block_data(chip->client,
212 (reg << bank_shift) | REG_ADDR_AI,
213 NBANK(chip), val);
214}
215
216static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
217{
218 int ret = 0;
219
220 ret = chip->write_regs(chip, reg, val);
f5e8ff48
GL
221 if (ret < 0) {
222 dev_err(&chip->client->dev, "failed writing register\n");
ab5dc372 223 return ret;
f5e8ff48
GL
224 }
225
226 return 0;
9e60fdcf 227}
228
c6e3cf01 229static int pca953x_read_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 230{
231 int ret;
232
c6e3cf01
BG
233 ret = i2c_smbus_read_byte_data(chip->client, reg);
234 *val = ret;
f5f0b7aa 235
c6e3cf01
BG
236 return ret;
237}
238
239static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
240{
241 int ret;
242
243 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
244 val[0] = (u16)ret & 0xFF;
245 val[1] = (u16)ret >> 8;
246
247 return ret;
248}
249
250static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
251{
252 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
253
254 return i2c_smbus_read_i2c_block_data(chip->client,
255 (reg << bank_shift) | REG_ADDR_AI,
256 NBANK(chip), val);
257}
258
259static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
260{
261 int ret;
262
263 ret = chip->read_regs(chip, reg, val);
9e60fdcf 264 if (ret < 0) {
265 dev_err(&chip->client->dev, "failed reading register\n");
ab5dc372 266 return ret;
9e60fdcf 267 }
268
9e60fdcf 269 return 0;
270}
271
f3dc3630 272static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
9e60fdcf 273{
468e67f6 274 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 275 u8 reg_val;
53661f3b 276 int ret;
9e60fdcf 277
6e20fb18 278 mutex_lock(&chip->i2c_lock);
f5f0b7aa 279 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
33226ffd 280
53661f3b 281 ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off);
9e60fdcf 282 if (ret)
6e20fb18 283 goto exit;
9e60fdcf 284
f5f0b7aa 285 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
286exit:
287 mutex_unlock(&chip->i2c_lock);
288 return ret;
9e60fdcf 289}
290
f3dc3630 291static int pca953x_gpio_direction_output(struct gpio_chip *gc,
9e60fdcf 292 unsigned off, int val)
293{
468e67f6 294 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 295 u8 reg_val;
53661f3b 296 int ret;
9e60fdcf 297
6e20fb18 298 mutex_lock(&chip->i2c_lock);
9e60fdcf 299 /* set output level */
300 if (val)
f5f0b7aa
GC
301 reg_val = chip->reg_output[off / BANK_SZ]
302 | (1u << (off % BANK_SZ));
9e60fdcf 303 else
f5f0b7aa
GC
304 reg_val = chip->reg_output[off / BANK_SZ]
305 & ~(1u << (off % BANK_SZ));
9e60fdcf 306
53661f3b 307 ret = pca953x_write_single(chip, chip->regs->output, reg_val, off);
9e60fdcf 308 if (ret)
6e20fb18 309 goto exit;
9e60fdcf 310
f5f0b7aa 311 chip->reg_output[off / BANK_SZ] = reg_val;
9e60fdcf 312
313 /* then direction */
f5f0b7aa 314 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
53661f3b 315 ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off);
9e60fdcf 316 if (ret)
6e20fb18 317 goto exit;
9e60fdcf 318
f5f0b7aa 319 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
320exit:
321 mutex_unlock(&chip->i2c_lock);
322 return ret;
9e60fdcf 323}
324
f3dc3630 325static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
9e60fdcf 326{
468e67f6 327 struct pca953x_chip *chip = gpiochip_get_data(gc);
ae79c190 328 u32 reg_val;
53661f3b 329 int ret;
9e60fdcf 330
6e20fb18 331 mutex_lock(&chip->i2c_lock);
53661f3b 332 ret = pca953x_read_single(chip, chip->regs->input, &reg_val, off);
6e20fb18 333 mutex_unlock(&chip->i2c_lock);
9e60fdcf 334 if (ret < 0) {
335 /* NOTE: diagnostic already emitted; that's all we should
336 * do unless gpio_*_value_cansleep() calls become different
337 * from their nonsleeping siblings (and report faults).
338 */
339 return 0;
340 }
341
40a625da 342 return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
9e60fdcf 343}
344
f3dc3630 345static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
9e60fdcf 346{
468e67f6 347 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 348 u8 reg_val;
53661f3b 349 int ret;
9e60fdcf 350
6e20fb18 351 mutex_lock(&chip->i2c_lock);
9e60fdcf 352 if (val)
f5f0b7aa
GC
353 reg_val = chip->reg_output[off / BANK_SZ]
354 | (1u << (off % BANK_SZ));
9e60fdcf 355 else
f5f0b7aa
GC
356 reg_val = chip->reg_output[off / BANK_SZ]
357 & ~(1u << (off % BANK_SZ));
9e60fdcf 358
53661f3b 359 ret = pca953x_write_single(chip, chip->regs->output, reg_val, off);
9e60fdcf 360 if (ret)
6e20fb18 361 goto exit;
9e60fdcf 362
f5f0b7aa 363 chip->reg_output[off / BANK_SZ] = reg_val;
6e20fb18
RS
364exit:
365 mutex_unlock(&chip->i2c_lock);
9e60fdcf 366}
367
66e57192
AS
368static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
369{
370 struct pca953x_chip *chip = gpiochip_get_data(gc);
371 u32 reg_val;
372 int ret;
373
374 mutex_lock(&chip->i2c_lock);
375 ret = pca953x_read_single(chip, chip->regs->direction, &reg_val, off);
376 mutex_unlock(&chip->i2c_lock);
377 if (ret < 0)
378 return ret;
379
380 return !!(reg_val & (1u << (off % BANK_SZ)));
381}
382
b4818afe 383static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
ea3d579d 384 unsigned long *mask, unsigned long *bits)
b4818afe 385{
468e67f6 386 struct pca953x_chip *chip = gpiochip_get_data(gc);
ea3d579d
BG
387 unsigned int bank_mask, bank_val;
388 int bank_shift, bank;
b4818afe 389 u8 reg_val[MAX_BANK];
53661f3b 390 int ret;
ea3d579d
BG
391
392 bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
b4818afe 393
b4818afe 394 mutex_lock(&chip->i2c_lock);
386377b5 395 memcpy(reg_val, chip->reg_output, NBANK(chip));
ea3d579d
BG
396 for (bank = 0; bank < NBANK(chip); bank++) {
397 bank_mask = mask[bank / sizeof(*mask)] >>
398 ((bank % sizeof(*mask)) * 8);
399 if (bank_mask) {
400 bank_val = bits[bank / sizeof(*bits)] >>
401 ((bank % sizeof(*bits)) * 8);
53f8d322 402 bank_val &= bank_mask;
ea3d579d 403 reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val;
b4818afe
PR
404 }
405 }
ea3d579d 406
53661f3b
BG
407 ret = i2c_smbus_write_i2c_block_data(chip->client,
408 chip->regs->output << bank_shift,
409 NBANK(chip), reg_val);
b4818afe
PR
410 if (ret)
411 goto exit;
412
413 memcpy(chip->reg_output, reg_val, NBANK(chip));
414exit:
415 mutex_unlock(&chip->i2c_lock);
416}
417
f5e8ff48 418static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
9e60fdcf 419{
420 struct gpio_chip *gc;
421
422 gc = &chip->gpio_chip;
423
f3dc3630
GL
424 gc->direction_input = pca953x_gpio_direction_input;
425 gc->direction_output = pca953x_gpio_direction_output;
426 gc->get = pca953x_gpio_get_value;
427 gc->set = pca953x_gpio_set_value;
66e57192 428 gc->get_direction = pca953x_gpio_get_direction;
b4818afe 429 gc->set_multiple = pca953x_gpio_set_multiple;
9fb1f39e 430 gc->can_sleep = true;
9e60fdcf 431
432 gc->base = chip->gpio_start;
f5e8ff48
GL
433 gc->ngpio = gpios;
434 gc->label = chip->client->name;
58383c78 435 gc->parent = &chip->client->dev;
d72cbed0 436 gc->owner = THIS_MODULE;
77906a54 437 gc->names = chip->names;
9e60fdcf 438}
439
89ea8bbe 440#ifdef CONFIG_GPIO_PCA953X_IRQ
6f5cfc0e 441static void pca953x_irq_mask(struct irq_data *d)
89ea8bbe 442{
7bcbce55 443 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 444 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe 445
f5f0b7aa 446 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
89ea8bbe
MZ
447}
448
6f5cfc0e 449static void pca953x_irq_unmask(struct irq_data *d)
89ea8bbe 450{
7bcbce55 451 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 452 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe 453
f5f0b7aa 454 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
455}
456
6f5cfc0e 457static void pca953x_irq_bus_lock(struct irq_data *d)
89ea8bbe 458{
7bcbce55 459 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 460 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe
MZ
461
462 mutex_lock(&chip->irq_lock);
463}
464
6f5cfc0e 465static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
89ea8bbe 466{
7bcbce55 467 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 468 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa
GC
469 u8 new_irqs;
470 int level, i;
44896bea
YL
471 u8 invert_irq_mask[MAX_BANK];
472
473 if (chip->driver_data & PCA_PCAL) {
474 /* Enable latch on interrupt-enabled inputs */
475 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
476
477 for (i = 0; i < NBANK(chip); i++)
478 invert_irq_mask[i] = ~chip->irq_mask[i];
479
480 /* Unmask enabled interrupts */
481 pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
482 }
a2cb9aeb
MZ
483
484 /* Look for any newly setup interrupt */
f5f0b7aa
GC
485 for (i = 0; i < NBANK(chip); i++) {
486 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
487 new_irqs &= ~chip->reg_direction[i];
488
489 while (new_irqs) {
490 level = __ffs(new_irqs);
491 pca953x_gpio_direction_input(&chip->gpio_chip,
492 level + (BANK_SZ * i));
493 new_irqs &= ~(1 << level);
494 }
a2cb9aeb 495 }
89ea8bbe
MZ
496
497 mutex_unlock(&chip->irq_lock);
498}
499
6f5cfc0e 500static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
89ea8bbe 501{
7bcbce55 502 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 503 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa
GC
504 int bank_nb = d->hwirq / BANK_SZ;
505 u8 mask = 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
506
507 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
508 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
6f5cfc0e 509 d->irq, type);
89ea8bbe
MZ
510 return -EINVAL;
511 }
512
513 if (type & IRQ_TYPE_EDGE_FALLING)
f5f0b7aa 514 chip->irq_trig_fall[bank_nb] |= mask;
89ea8bbe 515 else
f5f0b7aa 516 chip->irq_trig_fall[bank_nb] &= ~mask;
89ea8bbe
MZ
517
518 if (type & IRQ_TYPE_EDGE_RISING)
f5f0b7aa 519 chip->irq_trig_raise[bank_nb] |= mask;
89ea8bbe 520 else
f5f0b7aa 521 chip->irq_trig_raise[bank_nb] &= ~mask;
89ea8bbe 522
a2cb9aeb 523 return 0;
89ea8bbe
MZ
524}
525
526static struct irq_chip pca953x_irq_chip = {
527 .name = "pca953x",
6f5cfc0e
LB
528 .irq_mask = pca953x_irq_mask,
529 .irq_unmask = pca953x_irq_unmask,
530 .irq_bus_lock = pca953x_irq_bus_lock,
531 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
532 .irq_set_type = pca953x_irq_set_type,
89ea8bbe
MZ
533};
534
b6ac1280 535static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
89ea8bbe 536{
f5f0b7aa
GC
537 u8 cur_stat[MAX_BANK];
538 u8 old_stat[MAX_BANK];
b6ac1280
JS
539 bool pending_seen = false;
540 bool trigger_seen = false;
541 u8 trigger[MAX_BANK];
53661f3b 542 int ret, i;
33226ffd 543
44896bea
YL
544 if (chip->driver_data & PCA_PCAL) {
545 /* Read the current interrupt status from the device */
546 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
547 if (ret)
548 return false;
549
550 /* Check latched inputs and clear interrupt status */
551 ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
552 if (ret)
553 return false;
554
555 for (i = 0; i < NBANK(chip); i++) {
556 /* Apply filter for rising/falling edge selection */
557 pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
558 (cur_stat[i] & chip->irq_trig_raise[i]);
559 pending[i] &= trigger[i];
560 if (pending[i])
561 pending_seen = true;
562 }
563
564 return pending_seen;
565 }
566
53661f3b 567 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
89ea8bbe 568 if (ret)
b6ac1280 569 return false;
89ea8bbe
MZ
570
571 /* Remove output pins from the equation */
f5f0b7aa
GC
572 for (i = 0; i < NBANK(chip); i++)
573 cur_stat[i] &= chip->reg_direction[i];
89ea8bbe 574
f5f0b7aa 575 memcpy(old_stat, chip->irq_stat, NBANK(chip));
89ea8bbe 576
f5f0b7aa
GC
577 for (i = 0; i < NBANK(chip); i++) {
578 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
b6ac1280
JS
579 if (trigger[i])
580 trigger_seen = true;
f5f0b7aa
GC
581 }
582
b6ac1280
JS
583 if (!trigger_seen)
584 return false;
89ea8bbe 585
f5f0b7aa 586 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
89ea8bbe 587
f5f0b7aa
GC
588 for (i = 0; i < NBANK(chip); i++) {
589 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
590 (cur_stat[i] & chip->irq_trig_raise[i]);
591 pending[i] &= trigger[i];
b6ac1280
JS
592 if (pending[i])
593 pending_seen = true;
f5f0b7aa 594 }
89ea8bbe 595
b6ac1280 596 return pending_seen;
89ea8bbe
MZ
597}
598
599static irqreturn_t pca953x_irq_handler(int irq, void *devid)
600{
601 struct pca953x_chip *chip = devid;
f5f0b7aa
GC
602 u8 pending[MAX_BANK];
603 u8 level;
3275d072 604 unsigned nhandled = 0;
f5f0b7aa 605 int i;
89ea8bbe 606
f5f0b7aa 607 if (!pca953x_irq_pending(chip, pending))
3275d072 608 return IRQ_NONE;
89ea8bbe 609
f5f0b7aa
GC
610 for (i = 0; i < NBANK(chip); i++) {
611 while (pending[i]) {
612 level = __ffs(pending[i]);
7bcbce55 613 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
f5f0b7aa
GC
614 level + (BANK_SZ * i)));
615 pending[i] &= ~(1 << level);
3275d072 616 nhandled++;
f5f0b7aa
GC
617 }
618 }
89ea8bbe 619
3275d072 620 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
89ea8bbe
MZ
621}
622
623static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592 624 int irq_base)
89ea8bbe
MZ
625{
626 struct i2c_client *client = chip->client;
53661f3b 627 int ret, i;
89ea8bbe 628
4bb93349 629 if (client->irq && irq_base != -1
c6664149 630 && (chip->driver_data & PCA_INT)) {
53661f3b
BG
631 ret = pca953x_read_regs(chip,
632 chip->regs->input, chip->irq_stat);
89ea8bbe 633 if (ret)
b42748c9 634 return ret;
89ea8bbe
MZ
635
636 /*
637 * There is no way to know which GPIO line generated the
638 * interrupt. We have to rely on the previous read for
639 * this purpose.
640 */
f5f0b7aa
GC
641 for (i = 0; i < NBANK(chip); i++)
642 chip->irq_stat[i] &= chip->reg_direction[i];
89ea8bbe
MZ
643 mutex_init(&chip->irq_lock);
644
b42748c9
LW
645 ret = devm_request_threaded_irq(&client->dev,
646 client->irq,
89ea8bbe
MZ
647 NULL,
648 pca953x_irq_handler,
91329132
TS
649 IRQF_TRIGGER_LOW | IRQF_ONESHOT |
650 IRQF_SHARED,
89ea8bbe
MZ
651 dev_name(&client->dev), chip);
652 if (ret) {
653 dev_err(&client->dev, "failed to request irq %d\n",
654 client->irq);
0e8f2fda 655 return ret;
89ea8bbe
MZ
656 }
657
d245b3f9
LW
658 ret = gpiochip_irqchip_add_nested(&chip->gpio_chip,
659 &pca953x_irq_chip,
660 irq_base,
661 handle_simple_irq,
662 IRQ_TYPE_NONE);
7bcbce55
LW
663 if (ret) {
664 dev_err(&client->dev,
665 "could not connect irqchip to gpiochip\n");
666 return ret;
667 }
fdd50409 668
d245b3f9
LW
669 gpiochip_set_nested_irqchip(&chip->gpio_chip,
670 &pca953x_irq_chip,
671 client->irq);
89ea8bbe
MZ
672 }
673
674 return 0;
89ea8bbe
MZ
675}
676
89ea8bbe
MZ
677#else /* CONFIG_GPIO_PCA953X_IRQ */
678static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592 679 int irq_base)
89ea8bbe
MZ
680{
681 struct i2c_client *client = chip->client;
89ea8bbe 682
c6664149 683 if (irq_base != -1 && (chip->driver_data & PCA_INT))
89ea8bbe
MZ
684 dev_warn(&client->dev, "interrupt support not compiled in\n");
685
686 return 0;
687}
89ea8bbe
MZ
688#endif
689
3836309d 690static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
691{
692 int ret;
f5f0b7aa 693 u8 val[MAX_BANK];
33226ffd 694
53661f3b
BG
695 chip->regs = &pca953x_regs;
696
697 ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output);
33226ffd
HZ
698 if (ret)
699 goto out;
700
53661f3b
BG
701 ret = pca953x_read_regs(chip, chip->regs->direction,
702 chip->reg_direction);
33226ffd
HZ
703 if (ret)
704 goto out;
705
706 /* set platform specific polarity inversion */
f5f0b7aa
GC
707 if (invert)
708 memset(val, 0xFF, NBANK(chip));
709 else
710 memset(val, 0, NBANK(chip));
711
712 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
33226ffd
HZ
713out:
714 return ret;
715}
716
3836309d 717static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
718{
719 int ret;
f5f0b7aa 720 u8 val[MAX_BANK];
33226ffd 721
53661f3b
BG
722 chip->regs = &pca957x_regs;
723
724 ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output);
33226ffd
HZ
725 if (ret)
726 goto out;
53661f3b
BG
727 ret = pca953x_read_regs(chip, chip->regs->direction,
728 chip->reg_direction);
33226ffd
HZ
729 if (ret)
730 goto out;
731
732 /* set platform specific polarity inversion */
f5f0b7aa
GC
733 if (invert)
734 memset(val, 0xFF, NBANK(chip));
735 else
736 memset(val, 0, NBANK(chip));
c75a3772
NK
737 ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
738 if (ret)
739 goto out;
33226ffd 740
20a8a968 741 /* To enable register 6, 7 to control pull up and pull down */
f5f0b7aa 742 memset(val, 0x02, NBANK(chip));
c75a3772
NK
743 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
744 if (ret)
745 goto out;
33226ffd
HZ
746
747 return 0;
748out:
749 return ret;
750}
751
6f29c9af
BD
752static const struct of_device_id pca953x_dt_ids[];
753
3836309d 754static int pca953x_probe(struct i2c_client *client,
6212e1d6 755 const struct i2c_device_id *i2c_id)
9e60fdcf 756{
f3dc3630
GL
757 struct pca953x_platform_data *pdata;
758 struct pca953x_chip *chip;
6a7b36aa 759 int irq_base = 0;
7ea2aa20 760 int ret;
6a7b36aa 761 u32 invert = 0;
e23efa31 762 struct regulator *reg;
9e60fdcf 763
b42748c9
LW
764 chip = devm_kzalloc(&client->dev,
765 sizeof(struct pca953x_chip), GFP_KERNEL);
1965d303
NC
766 if (chip == NULL)
767 return -ENOMEM;
768
e56aee18 769 pdata = dev_get_platdata(&client->dev);
c6dcf592
DJ
770 if (pdata) {
771 irq_base = pdata->irq_base;
772 chip->gpio_start = pdata->gpio_base;
773 invert = pdata->invert;
774 chip->names = pdata->names;
775 } else {
054ccdef
SL
776 struct gpio_desc *reset_gpio;
777
4bb93349
MP
778 chip->gpio_start = -1;
779 irq_base = 0;
054ccdef 780
96530b37
AS
781 /*
782 * See if we need to de-assert a reset pin.
783 *
784 * There is no known ACPI-enabled platforms that are
785 * using "reset" GPIO. Otherwise any of those platform
786 * must use _DSD method with corresponding property.
787 */
054ccdef
SL
788 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
789 GPIOD_OUT_LOW);
790 if (IS_ERR(reset_gpio))
791 return PTR_ERR(reset_gpio);
1965d303 792 }
9e60fdcf 793
794 chip->client = client;
795
e23efa31
PR
796 reg = devm_regulator_get(&client->dev, "vcc");
797 if (IS_ERR(reg)) {
798 ret = PTR_ERR(reg);
799 if (ret != -EPROBE_DEFER)
800 dev_err(&client->dev, "reg get err: %d\n", ret);
801 return ret;
802 }
803 ret = regulator_enable(reg);
804 if (ret) {
805 dev_err(&client->dev, "reg en err: %d\n", ret);
806 return ret;
807 }
808 chip->regulator = reg;
809
6212e1d6
WS
810 if (i2c_id) {
811 chip->driver_data = i2c_id->driver_data;
f32517bf 812 } else {
6212e1d6 813 const struct acpi_device_id *acpi_id;
6f29c9af 814 const struct of_device_id *match;
f32517bf 815
6f29c9af
BD
816 match = of_match_device(pca953x_dt_ids, &client->dev);
817 if (match) {
818 chip->driver_data = (int)(uintptr_t)match->data;
819 } else {
6212e1d6 820 acpi_id = acpi_match_device(pca953x_acpi_ids, &client->dev);
87840a2b 821 if (!acpi_id) {
e23efa31
PR
822 ret = -ENODEV;
823 goto err_exit;
824 }
f32517bf 825
6212e1d6 826 chip->driver_data = acpi_id->driver_data;
6f29c9af 827 }
f32517bf
AS
828 }
829
6e20fb18 830 mutex_init(&chip->i2c_lock);
74f47f07
BG
831 /*
832 * In case we have an i2c-mux controlled by a GPIO provided by an
833 * expander using the same driver higher on the device tree, read the
834 * i2c adapter nesting depth and use the retrieved value as lockdep
835 * subclass for chip->i2c_lock.
836 *
837 * REVISIT: This solution is not complete. It protects us from lockdep
838 * false positives when the expander controlling the i2c-mux is on
839 * a different level on the device tree, but not when it's on the same
840 * level on a different branch (in which case the subclass number
841 * would be the same).
842 *
843 * TODO: Once a correct solution is developed, a similar fix should be
844 * applied to all other i2c-controlled GPIO expanders (and potentially
845 * regmap-i2c).
846 */
559b4699
BG
847 lockdep_set_subclass(&chip->i2c_lock,
848 i2c_adapter_depth(client->adapter));
6e20fb18 849
9e60fdcf 850 /* initialize cached registers from their original values.
851 * we can't share this chip with another i2c master.
852 */
c6664149 853 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
f5e8ff48 854
7acc66e3
BG
855 if (chip->gpio_chip.ngpio <= 8) {
856 chip->write_regs = pca953x_write_regs_8;
c6e3cf01 857 chip->read_regs = pca953x_read_regs_8;
7acc66e3
BG
858 } else if (chip->gpio_chip.ngpio >= 24) {
859 chip->write_regs = pca953x_write_regs_24;
c6e3cf01 860 chip->read_regs = pca953x_read_regs_24;
7acc66e3
BG
861 } else {
862 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
863 chip->write_regs = pca953x_write_regs_16;
864 else
865 chip->write_regs = pca957x_write_regs_16;
c6e3cf01 866 chip->read_regs = pca953x_read_regs_16;
7acc66e3
BG
867 }
868
60f547be 869 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
7ea2aa20 870 ret = device_pca953x_init(chip, invert);
33226ffd 871 else
7ea2aa20
WS
872 ret = device_pca957x_init(chip, invert);
873 if (ret)
e23efa31 874 goto err_exit;
9e60fdcf 875
0ece84f5 876 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
89ea8bbe 877 if (ret)
e23efa31 878 goto err_exit;
f5e8ff48 879
c6664149 880 ret = pca953x_irq_setup(chip, irq_base);
9e60fdcf 881 if (ret)
e23efa31 882 goto err_exit;
9e60fdcf 883
c6dcf592 884 if (pdata && pdata->setup) {
9e60fdcf 885 ret = pdata->setup(client, chip->gpio_chip.base,
886 chip->gpio_chip.ngpio, pdata->context);
887 if (ret < 0)
888 dev_warn(&client->dev, "setup failed, %d\n", ret);
889 }
890
891 i2c_set_clientdata(client, chip);
892 return 0;
e23efa31
PR
893
894err_exit:
895 regulator_disable(chip->regulator);
896 return ret;
9e60fdcf 897}
898
f3dc3630 899static int pca953x_remove(struct i2c_client *client)
9e60fdcf 900{
e56aee18 901 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
f3dc3630 902 struct pca953x_chip *chip = i2c_get_clientdata(client);
d147d548 903 int ret;
9e60fdcf 904
c6dcf592 905 if (pdata && pdata->teardown) {
9e60fdcf 906 ret = pdata->teardown(client, chip->gpio_chip.base,
907 chip->gpio_chip.ngpio, pdata->context);
e23efa31 908 if (ret < 0)
9e60fdcf 909 dev_err(&client->dev, "%s failed, %d\n",
910 "teardown", ret);
bf62efeb
AB
911 } else {
912 ret = 0;
9e60fdcf 913 }
914
e23efa31
PR
915 regulator_disable(chip->regulator);
916
917 return ret;
9e60fdcf 918}
919
6f29c9af
BD
920/* convenience to stop overlong match-table lines */
921#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
922#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
923
ed32620e 924static const struct of_device_id pca953x_dt_ids[] = {
6f29c9af
BD
925 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
926 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
927 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
928 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
929 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
930 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
931 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
932 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
933 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
934 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
935 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
936 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
937 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
938 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
939
940 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
941 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
942 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
943 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
1208c935 944 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
6f29c9af
BD
945
946 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
353661df 947 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
6f29c9af
BD
948 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
949 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
950 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
951
952 { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), },
953
954 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
ed32620e
MR
955 { }
956};
957
958MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
959
f3dc3630 960static struct i2c_driver pca953x_driver = {
9e60fdcf 961 .driver = {
f3dc3630 962 .name = "pca953x",
ed32620e 963 .of_match_table = pca953x_dt_ids,
f32517bf 964 .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
9e60fdcf 965 },
f3dc3630
GL
966 .probe = pca953x_probe,
967 .remove = pca953x_remove,
3760f736 968 .id_table = pca953x_id,
9e60fdcf 969};
970
f3dc3630 971static int __init pca953x_init(void)
9e60fdcf 972{
f3dc3630 973 return i2c_add_driver(&pca953x_driver);
9e60fdcf 974}
2f8d1197
DB
975/* register after i2c postcore initcall and before
976 * subsys initcalls that may rely on these GPIOs
977 */
978subsys_initcall(pca953x_init);
9e60fdcf 979
f3dc3630 980static void __exit pca953x_exit(void)
9e60fdcf 981{
f3dc3630 982 i2c_del_driver(&pca953x_driver);
9e60fdcf 983}
f3dc3630 984module_exit(pca953x_exit);
9e60fdcf 985
986MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
f3dc3630 987MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
9e60fdcf 988MODULE_LICENSE("GPL");