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9e60fdcf 1/*
1e191695 2 * PCA953x 4/8/16/24/40 bit I/O ports
9e60fdcf 3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd.
6 *
7 * Derived from drivers/i2c/chips/pca9539.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */
13
b413d7a0 14#include <linux/acpi.h>
d120c17f 15#include <linux/gpio.h>
054ccdef 16#include <linux/gpio/consumer.h>
9e60fdcf 17#include <linux/i2c.h>
b413d7a0
AS
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/of_platform.h>
5877457a 22#include <linux/platform_data/pca953x.h>
b413d7a0 23#include <linux/regulator/consumer.h>
5a0e3ad6 24#include <linux/slab.h>
b413d7a0 25
9b8e3ec3 26#include <asm/unaligned.h>
9e60fdcf 27
33226ffd
HZ
28#define PCA953X_INPUT 0
29#define PCA953X_OUTPUT 1
30#define PCA953X_INVERT 2
31#define PCA953X_DIRECTION 3
32
ae79c190
AS
33#define REG_ADDR_AI 0x80
34
33226ffd
HZ
35#define PCA957X_IN 0
36#define PCA957X_INVRT 1
37#define PCA957X_BKEN 2
38#define PCA957X_PUPD 3
39#define PCA957X_CFG 4
40#define PCA957X_OUT 5
41#define PCA957X_MSK 6
42#define PCA957X_INTS 7
43
44896bea
YL
44#define PCAL953X_IN_LATCH 34
45#define PCAL953X_INT_MASK 37
46#define PCAL953X_INT_STAT 38
47
33226ffd
HZ
48#define PCA_GPIO_MASK 0x00FF
49#define PCA_INT 0x0100
8c7a92da 50#define PCA_PCAL 0x0200
33226ffd
HZ
51#define PCA953X_TYPE 0x1000
52#define PCA957X_TYPE 0x2000
c6664149
AS
53#define PCA_TYPE_MASK 0xF000
54
55#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
89ea8bbe 56
3760f736 57static const struct i2c_device_id pca953x_id[] = {
89f5df01 58 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
33226ffd
HZ
59 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
60 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
61 { "pca9536", 4 | PCA953X_TYPE, },
62 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
63 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
64 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
65 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
66 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
67 { "pca9556", 8 | PCA953X_TYPE, },
68 { "pca9557", 8 | PCA953X_TYPE, },
69 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
70 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
eb32b5aa 71 { "pca9698", 40 | PCA953X_TYPE, },
33226ffd 72
747e42a1
AS
73 { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
74
33226ffd
HZ
75 { "max7310", 8 | PCA953X_TYPE, },
76 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
77 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
78 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
1208c935 79 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
33226ffd
HZ
80 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
81 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
82 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
ae79c190 83 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
2db8aba8 84 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
1b9a0c25 85 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
e73760a6 86 { "xra1202", 8 | PCA953X_TYPE },
3760f736 87 { }
f5e8ff48 88};
3760f736 89MODULE_DEVICE_TABLE(i2c, pca953x_id);
9e60fdcf 90
f32517bf 91static const struct acpi_device_id pca953x_acpi_ids[] = {
44896bea 92 { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
f32517bf
AS
93 { }
94};
95MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
96
f5f0b7aa
GC
97#define MAX_BANK 5
98#define BANK_SZ 8
99
a246b819 100#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
f5f0b7aa 101
53661f3b
BG
102struct pca953x_reg_config {
103 int direction;
104 int output;
105 int input;
106};
107
108static const struct pca953x_reg_config pca953x_regs = {
109 .direction = PCA953X_DIRECTION,
110 .output = PCA953X_OUTPUT,
111 .input = PCA953X_INPUT,
112};
113
114static const struct pca953x_reg_config pca957x_regs = {
115 .direction = PCA957X_CFG,
116 .output = PCA957X_OUT,
117 .input = PCA957X_IN,
118};
119
f3dc3630 120struct pca953x_chip {
9e60fdcf 121 unsigned gpio_start;
f5f0b7aa
GC
122 u8 reg_output[MAX_BANK];
123 u8 reg_direction[MAX_BANK];
6e20fb18 124 struct mutex i2c_lock;
9e60fdcf 125
89ea8bbe
MZ
126#ifdef CONFIG_GPIO_PCA953X_IRQ
127 struct mutex irq_lock;
f5f0b7aa
GC
128 u8 irq_mask[MAX_BANK];
129 u8 irq_stat[MAX_BANK];
130 u8 irq_trig_raise[MAX_BANK];
131 u8 irq_trig_fall[MAX_BANK];
89ea8bbe
MZ
132#endif
133
9e60fdcf 134 struct i2c_client *client;
135 struct gpio_chip gpio_chip;
62154991 136 const char *const *names;
c6664149 137 unsigned long driver_data;
e23efa31 138 struct regulator *regulator;
53661f3b
BG
139
140 const struct pca953x_reg_config *regs;
7acc66e3
BG
141
142 int (*write_regs)(struct pca953x_chip *, int, u8 *);
c6e3cf01 143 int (*read_regs)(struct pca953x_chip *, int, u8 *);
9e60fdcf 144};
145
f5f0b7aa
GC
146static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
147 int off)
148{
149 int ret;
150 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
151 int offset = off / BANK_SZ;
152
153 ret = i2c_smbus_read_byte_data(chip->client,
154 (reg << bank_shift) + offset);
155 *val = ret;
156
157 if (ret < 0) {
158 dev_err(&chip->client->dev, "failed reading register\n");
159 return ret;
160 }
161
162 return 0;
163}
164
165static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
166 int off)
167{
8c7a92da 168 int ret;
f5f0b7aa
GC
169 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
170 int offset = off / BANK_SZ;
171
172 ret = i2c_smbus_write_byte_data(chip->client,
173 (reg << bank_shift) + offset, val);
174
175 if (ret < 0) {
176 dev_err(&chip->client->dev, "failed writing register\n");
177 return ret;
178 }
179
180 return 0;
181}
182
7acc66e3 183static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 184{
7acc66e3
BG
185 return i2c_smbus_write_byte_data(chip->client, reg, *val);
186}
f5e8ff48 187
7acc66e3
BG
188static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
189{
b2dc4110 190 u16 word = get_unaligned((u16 *)val);
c4d1cbd7 191
b2dc4110 192 return i2c_smbus_write_word_data(chip->client, reg << 1, word);
7acc66e3
BG
193}
194
195static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
196{
197 int ret;
198
199 ret = i2c_smbus_write_byte_data(chip->client, reg << 1, val[0]);
200 if (ret < 0)
201 return ret;
202
203 return i2c_smbus_write_byte_data(chip->client, (reg << 1) + 1, val[1]);
204}
f5e8ff48 205
7acc66e3
BG
206static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
207{
208 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
209
210 return i2c_smbus_write_i2c_block_data(chip->client,
211 (reg << bank_shift) | REG_ADDR_AI,
212 NBANK(chip), val);
213}
214
215static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
216{
217 int ret = 0;
218
219 ret = chip->write_regs(chip, reg, val);
f5e8ff48
GL
220 if (ret < 0) {
221 dev_err(&chip->client->dev, "failed writing register\n");
ab5dc372 222 return ret;
f5e8ff48
GL
223 }
224
225 return 0;
9e60fdcf 226}
227
c6e3cf01 228static int pca953x_read_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 229{
230 int ret;
231
c6e3cf01
BG
232 ret = i2c_smbus_read_byte_data(chip->client, reg);
233 *val = ret;
f5f0b7aa 234
c6e3cf01
BG
235 return ret;
236}
237
238static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
239{
240 int ret;
241
242 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
b2dc4110 243 put_unaligned(ret, (u16 *)val);
c6e3cf01
BG
244
245 return ret;
246}
247
248static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
249{
250 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
251
252 return i2c_smbus_read_i2c_block_data(chip->client,
253 (reg << bank_shift) | REG_ADDR_AI,
254 NBANK(chip), val);
255}
256
257static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
258{
259 int ret;
260
261 ret = chip->read_regs(chip, reg, val);
9e60fdcf 262 if (ret < 0) {
263 dev_err(&chip->client->dev, "failed reading register\n");
ab5dc372 264 return ret;
9e60fdcf 265 }
266
9e60fdcf 267 return 0;
268}
269
f3dc3630 270static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
9e60fdcf 271{
468e67f6 272 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 273 u8 reg_val;
53661f3b 274 int ret;
9e60fdcf 275
6e20fb18 276 mutex_lock(&chip->i2c_lock);
f5f0b7aa 277 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
33226ffd 278
53661f3b 279 ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off);
9e60fdcf 280 if (ret)
6e20fb18 281 goto exit;
9e60fdcf 282
f5f0b7aa 283 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
284exit:
285 mutex_unlock(&chip->i2c_lock);
286 return ret;
9e60fdcf 287}
288
f3dc3630 289static int pca953x_gpio_direction_output(struct gpio_chip *gc,
9e60fdcf 290 unsigned off, int val)
291{
468e67f6 292 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 293 u8 reg_val;
53661f3b 294 int ret;
9e60fdcf 295
6e20fb18 296 mutex_lock(&chip->i2c_lock);
9e60fdcf 297 /* set output level */
298 if (val)
f5f0b7aa
GC
299 reg_val = chip->reg_output[off / BANK_SZ]
300 | (1u << (off % BANK_SZ));
9e60fdcf 301 else
f5f0b7aa
GC
302 reg_val = chip->reg_output[off / BANK_SZ]
303 & ~(1u << (off % BANK_SZ));
9e60fdcf 304
53661f3b 305 ret = pca953x_write_single(chip, chip->regs->output, reg_val, off);
9e60fdcf 306 if (ret)
6e20fb18 307 goto exit;
9e60fdcf 308
f5f0b7aa 309 chip->reg_output[off / BANK_SZ] = reg_val;
9e60fdcf 310
311 /* then direction */
f5f0b7aa 312 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
53661f3b 313 ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off);
9e60fdcf 314 if (ret)
6e20fb18 315 goto exit;
9e60fdcf 316
f5f0b7aa 317 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
318exit:
319 mutex_unlock(&chip->i2c_lock);
320 return ret;
9e60fdcf 321}
322
f3dc3630 323static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
9e60fdcf 324{
468e67f6 325 struct pca953x_chip *chip = gpiochip_get_data(gc);
ae79c190 326 u32 reg_val;
53661f3b 327 int ret;
9e60fdcf 328
6e20fb18 329 mutex_lock(&chip->i2c_lock);
53661f3b 330 ret = pca953x_read_single(chip, chip->regs->input, &reg_val, off);
6e20fb18 331 mutex_unlock(&chip->i2c_lock);
9e60fdcf 332 if (ret < 0) {
333 /* NOTE: diagnostic already emitted; that's all we should
334 * do unless gpio_*_value_cansleep() calls become different
335 * from their nonsleeping siblings (and report faults).
336 */
337 return 0;
338 }
339
40a625da 340 return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
9e60fdcf 341}
342
f3dc3630 343static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
9e60fdcf 344{
468e67f6 345 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 346 u8 reg_val;
53661f3b 347 int ret;
9e60fdcf 348
6e20fb18 349 mutex_lock(&chip->i2c_lock);
9e60fdcf 350 if (val)
f5f0b7aa
GC
351 reg_val = chip->reg_output[off / BANK_SZ]
352 | (1u << (off % BANK_SZ));
9e60fdcf 353 else
f5f0b7aa
GC
354 reg_val = chip->reg_output[off / BANK_SZ]
355 & ~(1u << (off % BANK_SZ));
9e60fdcf 356
53661f3b 357 ret = pca953x_write_single(chip, chip->regs->output, reg_val, off);
9e60fdcf 358 if (ret)
6e20fb18 359 goto exit;
9e60fdcf 360
f5f0b7aa 361 chip->reg_output[off / BANK_SZ] = reg_val;
6e20fb18
RS
362exit:
363 mutex_unlock(&chip->i2c_lock);
9e60fdcf 364}
365
66e57192
AS
366static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
367{
368 struct pca953x_chip *chip = gpiochip_get_data(gc);
369 u32 reg_val;
370 int ret;
371
372 mutex_lock(&chip->i2c_lock);
373 ret = pca953x_read_single(chip, chip->regs->direction, &reg_val, off);
374 mutex_unlock(&chip->i2c_lock);
375 if (ret < 0)
376 return ret;
377
378 return !!(reg_val & (1u << (off % BANK_SZ)));
379}
380
b4818afe 381static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
ea3d579d 382 unsigned long *mask, unsigned long *bits)
b4818afe 383{
468e67f6 384 struct pca953x_chip *chip = gpiochip_get_data(gc);
ea3d579d
BG
385 unsigned int bank_mask, bank_val;
386 int bank_shift, bank;
b4818afe 387 u8 reg_val[MAX_BANK];
53661f3b 388 int ret;
ea3d579d
BG
389
390 bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
b4818afe 391
b4818afe 392 mutex_lock(&chip->i2c_lock);
386377b5 393 memcpy(reg_val, chip->reg_output, NBANK(chip));
ea3d579d
BG
394 for (bank = 0; bank < NBANK(chip); bank++) {
395 bank_mask = mask[bank / sizeof(*mask)] >>
396 ((bank % sizeof(*mask)) * 8);
397 if (bank_mask) {
398 bank_val = bits[bank / sizeof(*bits)] >>
399 ((bank % sizeof(*bits)) * 8);
53f8d322 400 bank_val &= bank_mask;
ea3d579d 401 reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val;
b4818afe
PR
402 }
403 }
ea3d579d 404
53661f3b
BG
405 ret = i2c_smbus_write_i2c_block_data(chip->client,
406 chip->regs->output << bank_shift,
407 NBANK(chip), reg_val);
b4818afe
PR
408 if (ret)
409 goto exit;
410
411 memcpy(chip->reg_output, reg_val, NBANK(chip));
412exit:
413 mutex_unlock(&chip->i2c_lock);
414}
415
f5e8ff48 416static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
9e60fdcf 417{
418 struct gpio_chip *gc;
419
420 gc = &chip->gpio_chip;
421
f3dc3630
GL
422 gc->direction_input = pca953x_gpio_direction_input;
423 gc->direction_output = pca953x_gpio_direction_output;
424 gc->get = pca953x_gpio_get_value;
425 gc->set = pca953x_gpio_set_value;
66e57192 426 gc->get_direction = pca953x_gpio_get_direction;
b4818afe 427 gc->set_multiple = pca953x_gpio_set_multiple;
9fb1f39e 428 gc->can_sleep = true;
9e60fdcf 429
430 gc->base = chip->gpio_start;
f5e8ff48
GL
431 gc->ngpio = gpios;
432 gc->label = chip->client->name;
58383c78 433 gc->parent = &chip->client->dev;
d72cbed0 434 gc->owner = THIS_MODULE;
77906a54 435 gc->names = chip->names;
9e60fdcf 436}
437
89ea8bbe 438#ifdef CONFIG_GPIO_PCA953X_IRQ
6f5cfc0e 439static void pca953x_irq_mask(struct irq_data *d)
89ea8bbe 440{
7bcbce55 441 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 442 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe 443
f5f0b7aa 444 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
89ea8bbe
MZ
445}
446
6f5cfc0e 447static void pca953x_irq_unmask(struct irq_data *d)
89ea8bbe 448{
7bcbce55 449 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 450 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe 451
f5f0b7aa 452 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
453}
454
6f5cfc0e 455static void pca953x_irq_bus_lock(struct irq_data *d)
89ea8bbe 456{
7bcbce55 457 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 458 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe
MZ
459
460 mutex_lock(&chip->irq_lock);
461}
462
6f5cfc0e 463static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
89ea8bbe 464{
7bcbce55 465 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 466 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa
GC
467 u8 new_irqs;
468 int level, i;
44896bea
YL
469 u8 invert_irq_mask[MAX_BANK];
470
471 if (chip->driver_data & PCA_PCAL) {
472 /* Enable latch on interrupt-enabled inputs */
473 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
474
475 for (i = 0; i < NBANK(chip); i++)
476 invert_irq_mask[i] = ~chip->irq_mask[i];
477
478 /* Unmask enabled interrupts */
479 pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
480 }
a2cb9aeb
MZ
481
482 /* Look for any newly setup interrupt */
f5f0b7aa
GC
483 for (i = 0; i < NBANK(chip); i++) {
484 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
485 new_irqs &= ~chip->reg_direction[i];
486
487 while (new_irqs) {
488 level = __ffs(new_irqs);
489 pca953x_gpio_direction_input(&chip->gpio_chip,
490 level + (BANK_SZ * i));
491 new_irqs &= ~(1 << level);
492 }
a2cb9aeb 493 }
89ea8bbe
MZ
494
495 mutex_unlock(&chip->irq_lock);
496}
497
6f5cfc0e 498static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
89ea8bbe 499{
7bcbce55 500 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 501 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa
GC
502 int bank_nb = d->hwirq / BANK_SZ;
503 u8 mask = 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
504
505 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
506 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
6f5cfc0e 507 d->irq, type);
89ea8bbe
MZ
508 return -EINVAL;
509 }
510
511 if (type & IRQ_TYPE_EDGE_FALLING)
f5f0b7aa 512 chip->irq_trig_fall[bank_nb] |= mask;
89ea8bbe 513 else
f5f0b7aa 514 chip->irq_trig_fall[bank_nb] &= ~mask;
89ea8bbe
MZ
515
516 if (type & IRQ_TYPE_EDGE_RISING)
f5f0b7aa 517 chip->irq_trig_raise[bank_nb] |= mask;
89ea8bbe 518 else
f5f0b7aa 519 chip->irq_trig_raise[bank_nb] &= ~mask;
89ea8bbe 520
a2cb9aeb 521 return 0;
89ea8bbe
MZ
522}
523
524static struct irq_chip pca953x_irq_chip = {
525 .name = "pca953x",
6f5cfc0e
LB
526 .irq_mask = pca953x_irq_mask,
527 .irq_unmask = pca953x_irq_unmask,
528 .irq_bus_lock = pca953x_irq_bus_lock,
529 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
530 .irq_set_type = pca953x_irq_set_type,
89ea8bbe
MZ
531};
532
b6ac1280 533static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
89ea8bbe 534{
f5f0b7aa
GC
535 u8 cur_stat[MAX_BANK];
536 u8 old_stat[MAX_BANK];
b6ac1280
JS
537 bool pending_seen = false;
538 bool trigger_seen = false;
539 u8 trigger[MAX_BANK];
53661f3b 540 int ret, i;
33226ffd 541
44896bea
YL
542 if (chip->driver_data & PCA_PCAL) {
543 /* Read the current interrupt status from the device */
544 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
545 if (ret)
546 return false;
547
548 /* Check latched inputs and clear interrupt status */
549 ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
550 if (ret)
551 return false;
552
553 for (i = 0; i < NBANK(chip); i++) {
554 /* Apply filter for rising/falling edge selection */
555 pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
556 (cur_stat[i] & chip->irq_trig_raise[i]);
557 pending[i] &= trigger[i];
558 if (pending[i])
559 pending_seen = true;
560 }
561
562 return pending_seen;
563 }
564
53661f3b 565 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
89ea8bbe 566 if (ret)
b6ac1280 567 return false;
89ea8bbe
MZ
568
569 /* Remove output pins from the equation */
f5f0b7aa
GC
570 for (i = 0; i < NBANK(chip); i++)
571 cur_stat[i] &= chip->reg_direction[i];
89ea8bbe 572
f5f0b7aa 573 memcpy(old_stat, chip->irq_stat, NBANK(chip));
89ea8bbe 574
f5f0b7aa
GC
575 for (i = 0; i < NBANK(chip); i++) {
576 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
b6ac1280
JS
577 if (trigger[i])
578 trigger_seen = true;
f5f0b7aa
GC
579 }
580
b6ac1280
JS
581 if (!trigger_seen)
582 return false;
89ea8bbe 583
f5f0b7aa 584 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
89ea8bbe 585
f5f0b7aa
GC
586 for (i = 0; i < NBANK(chip); i++) {
587 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
588 (cur_stat[i] & chip->irq_trig_raise[i]);
589 pending[i] &= trigger[i];
b6ac1280
JS
590 if (pending[i])
591 pending_seen = true;
f5f0b7aa 592 }
89ea8bbe 593
b6ac1280 594 return pending_seen;
89ea8bbe
MZ
595}
596
597static irqreturn_t pca953x_irq_handler(int irq, void *devid)
598{
599 struct pca953x_chip *chip = devid;
f5f0b7aa
GC
600 u8 pending[MAX_BANK];
601 u8 level;
3275d072 602 unsigned nhandled = 0;
f5f0b7aa 603 int i;
89ea8bbe 604
f5f0b7aa 605 if (!pca953x_irq_pending(chip, pending))
3275d072 606 return IRQ_NONE;
89ea8bbe 607
f5f0b7aa
GC
608 for (i = 0; i < NBANK(chip); i++) {
609 while (pending[i]) {
610 level = __ffs(pending[i]);
f0fbe7bc 611 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
f5f0b7aa
GC
612 level + (BANK_SZ * i)));
613 pending[i] &= ~(1 << level);
3275d072 614 nhandled++;
f5f0b7aa
GC
615 }
616 }
89ea8bbe 617
3275d072 618 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
89ea8bbe
MZ
619}
620
621static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592 622 int irq_base)
89ea8bbe
MZ
623{
624 struct i2c_client *client = chip->client;
53661f3b 625 int ret, i;
89ea8bbe 626
4bb93349 627 if (client->irq && irq_base != -1
c6664149 628 && (chip->driver_data & PCA_INT)) {
53661f3b
BG
629 ret = pca953x_read_regs(chip,
630 chip->regs->input, chip->irq_stat);
89ea8bbe 631 if (ret)
b42748c9 632 return ret;
89ea8bbe
MZ
633
634 /*
635 * There is no way to know which GPIO line generated the
636 * interrupt. We have to rely on the previous read for
637 * this purpose.
638 */
f5f0b7aa
GC
639 for (i = 0; i < NBANK(chip); i++)
640 chip->irq_stat[i] &= chip->reg_direction[i];
89ea8bbe
MZ
641 mutex_init(&chip->irq_lock);
642
b42748c9
LW
643 ret = devm_request_threaded_irq(&client->dev,
644 client->irq,
89ea8bbe
MZ
645 NULL,
646 pca953x_irq_handler,
91329132
TS
647 IRQF_TRIGGER_LOW | IRQF_ONESHOT |
648 IRQF_SHARED,
89ea8bbe
MZ
649 dev_name(&client->dev), chip);
650 if (ret) {
651 dev_err(&client->dev, "failed to request irq %d\n",
652 client->irq);
0e8f2fda 653 return ret;
89ea8bbe
MZ
654 }
655
d245b3f9
LW
656 ret = gpiochip_irqchip_add_nested(&chip->gpio_chip,
657 &pca953x_irq_chip,
658 irq_base,
659 handle_simple_irq,
660 IRQ_TYPE_NONE);
7bcbce55
LW
661 if (ret) {
662 dev_err(&client->dev,
663 "could not connect irqchip to gpiochip\n");
664 return ret;
665 }
fdd50409 666
d245b3f9
LW
667 gpiochip_set_nested_irqchip(&chip->gpio_chip,
668 &pca953x_irq_chip,
669 client->irq);
89ea8bbe
MZ
670 }
671
672 return 0;
89ea8bbe
MZ
673}
674
89ea8bbe
MZ
675#else /* CONFIG_GPIO_PCA953X_IRQ */
676static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592 677 int irq_base)
89ea8bbe
MZ
678{
679 struct i2c_client *client = chip->client;
89ea8bbe 680
c6664149 681 if (irq_base != -1 && (chip->driver_data & PCA_INT))
89ea8bbe
MZ
682 dev_warn(&client->dev, "interrupt support not compiled in\n");
683
684 return 0;
685}
89ea8bbe
MZ
686#endif
687
3836309d 688static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
689{
690 int ret;
f5f0b7aa 691 u8 val[MAX_BANK];
33226ffd 692
53661f3b
BG
693 chip->regs = &pca953x_regs;
694
695 ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output);
33226ffd
HZ
696 if (ret)
697 goto out;
698
53661f3b
BG
699 ret = pca953x_read_regs(chip, chip->regs->direction,
700 chip->reg_direction);
33226ffd
HZ
701 if (ret)
702 goto out;
703
704 /* set platform specific polarity inversion */
f5f0b7aa
GC
705 if (invert)
706 memset(val, 0xFF, NBANK(chip));
707 else
708 memset(val, 0, NBANK(chip));
709
710 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
33226ffd
HZ
711out:
712 return ret;
713}
714
3836309d 715static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
716{
717 int ret;
f5f0b7aa 718 u8 val[MAX_BANK];
33226ffd 719
53661f3b
BG
720 chip->regs = &pca957x_regs;
721
722 ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output);
33226ffd
HZ
723 if (ret)
724 goto out;
53661f3b
BG
725 ret = pca953x_read_regs(chip, chip->regs->direction,
726 chip->reg_direction);
33226ffd
HZ
727 if (ret)
728 goto out;
729
730 /* set platform specific polarity inversion */
f5f0b7aa
GC
731 if (invert)
732 memset(val, 0xFF, NBANK(chip));
733 else
734 memset(val, 0, NBANK(chip));
c75a3772
NK
735 ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
736 if (ret)
737 goto out;
33226ffd 738
20a8a968 739 /* To enable register 6, 7 to control pull up and pull down */
f5f0b7aa 740 memset(val, 0x02, NBANK(chip));
c75a3772
NK
741 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
742 if (ret)
743 goto out;
33226ffd
HZ
744
745 return 0;
746out:
747 return ret;
748}
749
6f29c9af
BD
750static const struct of_device_id pca953x_dt_ids[];
751
3836309d 752static int pca953x_probe(struct i2c_client *client,
6212e1d6 753 const struct i2c_device_id *i2c_id)
9e60fdcf 754{
f3dc3630
GL
755 struct pca953x_platform_data *pdata;
756 struct pca953x_chip *chip;
6a7b36aa 757 int irq_base = 0;
7ea2aa20 758 int ret;
6a7b36aa 759 u32 invert = 0;
e23efa31 760 struct regulator *reg;
9e60fdcf 761
b42748c9
LW
762 chip = devm_kzalloc(&client->dev,
763 sizeof(struct pca953x_chip), GFP_KERNEL);
1965d303
NC
764 if (chip == NULL)
765 return -ENOMEM;
766
e56aee18 767 pdata = dev_get_platdata(&client->dev);
c6dcf592
DJ
768 if (pdata) {
769 irq_base = pdata->irq_base;
770 chip->gpio_start = pdata->gpio_base;
771 invert = pdata->invert;
772 chip->names = pdata->names;
773 } else {
054ccdef
SL
774 struct gpio_desc *reset_gpio;
775
4bb93349
MP
776 chip->gpio_start = -1;
777 irq_base = 0;
054ccdef 778
96530b37
AS
779 /*
780 * See if we need to de-assert a reset pin.
781 *
782 * There is no known ACPI-enabled platforms that are
783 * using "reset" GPIO. Otherwise any of those platform
784 * must use _DSD method with corresponding property.
785 */
054ccdef
SL
786 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
787 GPIOD_OUT_LOW);
788 if (IS_ERR(reset_gpio))
789 return PTR_ERR(reset_gpio);
1965d303 790 }
9e60fdcf 791
792 chip->client = client;
793
e23efa31
PR
794 reg = devm_regulator_get(&client->dev, "vcc");
795 if (IS_ERR(reg)) {
796 ret = PTR_ERR(reg);
797 if (ret != -EPROBE_DEFER)
798 dev_err(&client->dev, "reg get err: %d\n", ret);
799 return ret;
800 }
801 ret = regulator_enable(reg);
802 if (ret) {
803 dev_err(&client->dev, "reg en err: %d\n", ret);
804 return ret;
805 }
806 chip->regulator = reg;
807
6212e1d6
WS
808 if (i2c_id) {
809 chip->driver_data = i2c_id->driver_data;
f32517bf 810 } else {
6212e1d6 811 const struct acpi_device_id *acpi_id;
6f29c9af 812 const struct of_device_id *match;
f32517bf 813
6f29c9af
BD
814 match = of_match_device(pca953x_dt_ids, &client->dev);
815 if (match) {
816 chip->driver_data = (int)(uintptr_t)match->data;
817 } else {
6212e1d6 818 acpi_id = acpi_match_device(pca953x_acpi_ids, &client->dev);
87840a2b 819 if (!acpi_id) {
e23efa31
PR
820 ret = -ENODEV;
821 goto err_exit;
822 }
f32517bf 823
6212e1d6 824 chip->driver_data = acpi_id->driver_data;
6f29c9af 825 }
f32517bf
AS
826 }
827
6e20fb18 828 mutex_init(&chip->i2c_lock);
74f47f07
BG
829 /*
830 * In case we have an i2c-mux controlled by a GPIO provided by an
831 * expander using the same driver higher on the device tree, read the
832 * i2c adapter nesting depth and use the retrieved value as lockdep
833 * subclass for chip->i2c_lock.
834 *
835 * REVISIT: This solution is not complete. It protects us from lockdep
836 * false positives when the expander controlling the i2c-mux is on
837 * a different level on the device tree, but not when it's on the same
838 * level on a different branch (in which case the subclass number
839 * would be the same).
840 *
841 * TODO: Once a correct solution is developed, a similar fix should be
842 * applied to all other i2c-controlled GPIO expanders (and potentially
843 * regmap-i2c).
844 */
559b4699
BG
845 lockdep_set_subclass(&chip->i2c_lock,
846 i2c_adapter_depth(client->adapter));
6e20fb18 847
9e60fdcf 848 /* initialize cached registers from their original values.
849 * we can't share this chip with another i2c master.
850 */
c6664149 851 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
f5e8ff48 852
7acc66e3
BG
853 if (chip->gpio_chip.ngpio <= 8) {
854 chip->write_regs = pca953x_write_regs_8;
c6e3cf01 855 chip->read_regs = pca953x_read_regs_8;
7acc66e3
BG
856 } else if (chip->gpio_chip.ngpio >= 24) {
857 chip->write_regs = pca953x_write_regs_24;
c6e3cf01 858 chip->read_regs = pca953x_read_regs_24;
7acc66e3
BG
859 } else {
860 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
861 chip->write_regs = pca953x_write_regs_16;
862 else
863 chip->write_regs = pca957x_write_regs_16;
c6e3cf01 864 chip->read_regs = pca953x_read_regs_16;
7acc66e3
BG
865 }
866
60f547be 867 if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
7ea2aa20 868 ret = device_pca953x_init(chip, invert);
33226ffd 869 else
7ea2aa20
WS
870 ret = device_pca957x_init(chip, invert);
871 if (ret)
e23efa31 872 goto err_exit;
9e60fdcf 873
0ece84f5 874 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
89ea8bbe 875 if (ret)
e23efa31 876 goto err_exit;
f5e8ff48 877
c6664149 878 ret = pca953x_irq_setup(chip, irq_base);
9e60fdcf 879 if (ret)
e23efa31 880 goto err_exit;
9e60fdcf 881
c6dcf592 882 if (pdata && pdata->setup) {
9e60fdcf 883 ret = pdata->setup(client, chip->gpio_chip.base,
884 chip->gpio_chip.ngpio, pdata->context);
885 if (ret < 0)
886 dev_warn(&client->dev, "setup failed, %d\n", ret);
887 }
888
889 i2c_set_clientdata(client, chip);
890 return 0;
e23efa31
PR
891
892err_exit:
893 regulator_disable(chip->regulator);
894 return ret;
9e60fdcf 895}
896
f3dc3630 897static int pca953x_remove(struct i2c_client *client)
9e60fdcf 898{
e56aee18 899 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
f3dc3630 900 struct pca953x_chip *chip = i2c_get_clientdata(client);
d147d548 901 int ret;
9e60fdcf 902
c6dcf592 903 if (pdata && pdata->teardown) {
9e60fdcf 904 ret = pdata->teardown(client, chip->gpio_chip.base,
905 chip->gpio_chip.ngpio, pdata->context);
e23efa31 906 if (ret < 0)
9e60fdcf 907 dev_err(&client->dev, "%s failed, %d\n",
908 "teardown", ret);
bf62efeb
AB
909 } else {
910 ret = 0;
9e60fdcf 911 }
912
e23efa31
PR
913 regulator_disable(chip->regulator);
914
915 return ret;
9e60fdcf 916}
917
6f29c9af
BD
918/* convenience to stop overlong match-table lines */
919#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
920#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
921
ed32620e 922static const struct of_device_id pca953x_dt_ids[] = {
6f29c9af
BD
923 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
924 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
925 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
926 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
927 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
928 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
929 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
930 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
931 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
932 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
933 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
934 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
935 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
936 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
937
938 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
939 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
940 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
941 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
1208c935 942 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
6f29c9af
BD
943
944 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
353661df 945 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
6f29c9af
BD
946 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
947 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
948 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
949
8a64e557 950 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
6f29c9af
BD
951
952 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
ed32620e
MR
953 { }
954};
955
956MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
957
f3dc3630 958static struct i2c_driver pca953x_driver = {
9e60fdcf 959 .driver = {
f3dc3630 960 .name = "pca953x",
ed32620e 961 .of_match_table = pca953x_dt_ids,
f32517bf 962 .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
9e60fdcf 963 },
f3dc3630
GL
964 .probe = pca953x_probe,
965 .remove = pca953x_remove,
3760f736 966 .id_table = pca953x_id,
9e60fdcf 967};
968
f3dc3630 969static int __init pca953x_init(void)
9e60fdcf 970{
f3dc3630 971 return i2c_add_driver(&pca953x_driver);
9e60fdcf 972}
2f8d1197
DB
973/* register after i2c postcore initcall and before
974 * subsys initcalls that may rely on these GPIOs
975 */
976subsys_initcall(pca953x_init);
9e60fdcf 977
f3dc3630 978static void __exit pca953x_exit(void)
9e60fdcf 979{
f3dc3630 980 i2c_del_driver(&pca953x_driver);
9e60fdcf 981}
f3dc3630 982module_exit(pca953x_exit);
9e60fdcf 983
984MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
f3dc3630 985MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
9e60fdcf 986MODULE_LICENSE("GPL");