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gpio: omap: rework omap_gpio_irq_startup to handle current pin state properly
[mirror_ubuntu-zesty-kernel.git] / drivers / gpio / gpio-pca953x.c
CommitLineData
9e60fdcf 1/*
1e191695 2 * PCA953x 4/8/16/24/40 bit I/O ports
9e60fdcf 3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd.
6 *
7 * Derived from drivers/i2c/chips/pca9539.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
d120c17f 16#include <linux/gpio.h>
89ea8bbe 17#include <linux/interrupt.h>
9e60fdcf 18#include <linux/i2c.h>
5877457a 19#include <linux/platform_data/pca953x.h>
5a0e3ad6 20#include <linux/slab.h>
1965d303
NC
21#ifdef CONFIG_OF_GPIO
22#include <linux/of_platform.h>
1965d303 23#endif
9e60fdcf 24
33226ffd
HZ
25#define PCA953X_INPUT 0
26#define PCA953X_OUTPUT 1
27#define PCA953X_INVERT 2
28#define PCA953X_DIRECTION 3
29
ae79c190
AS
30#define REG_ADDR_AI 0x80
31
33226ffd
HZ
32#define PCA957X_IN 0
33#define PCA957X_INVRT 1
34#define PCA957X_BKEN 2
35#define PCA957X_PUPD 3
36#define PCA957X_CFG 4
37#define PCA957X_OUT 5
38#define PCA957X_MSK 6
39#define PCA957X_INTS 7
40
41#define PCA_GPIO_MASK 0x00FF
42#define PCA_INT 0x0100
43#define PCA953X_TYPE 0x1000
44#define PCA957X_TYPE 0x2000
89ea8bbe 45
3760f736 46static const struct i2c_device_id pca953x_id[] = {
89f5df01 47 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
33226ffd
HZ
48 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
49 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
50 { "pca9536", 4 | PCA953X_TYPE, },
51 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
52 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
53 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
54 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
55 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
56 { "pca9556", 8 | PCA953X_TYPE, },
57 { "pca9557", 8 | PCA953X_TYPE, },
58 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
59 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
eb32b5aa 60 { "pca9698", 40 | PCA953X_TYPE, },
33226ffd
HZ
61
62 { "max7310", 8 | PCA953X_TYPE, },
63 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
64 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
65 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
66 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
67 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
68 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
ae79c190 69 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
e73760a6 70 { "xra1202", 8 | PCA953X_TYPE },
3760f736 71 { }
f5e8ff48 72};
3760f736 73MODULE_DEVICE_TABLE(i2c, pca953x_id);
9e60fdcf 74
f5f0b7aa
GC
75#define MAX_BANK 5
76#define BANK_SZ 8
77
78#define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
79
f3dc3630 80struct pca953x_chip {
9e60fdcf 81 unsigned gpio_start;
f5f0b7aa
GC
82 u8 reg_output[MAX_BANK];
83 u8 reg_direction[MAX_BANK];
6e20fb18 84 struct mutex i2c_lock;
9e60fdcf 85
89ea8bbe
MZ
86#ifdef CONFIG_GPIO_PCA953X_IRQ
87 struct mutex irq_lock;
f5f0b7aa
GC
88 u8 irq_mask[MAX_BANK];
89 u8 irq_stat[MAX_BANK];
90 u8 irq_trig_raise[MAX_BANK];
91 u8 irq_trig_fall[MAX_BANK];
89ea8bbe
MZ
92#endif
93
9e60fdcf 94 struct i2c_client *client;
95 struct gpio_chip gpio_chip;
62154991 96 const char *const *names;
33226ffd 97 int chip_type;
9e60fdcf 98};
99
7bcbce55
LW
100static inline struct pca953x_chip *to_pca(struct gpio_chip *gc)
101{
102 return container_of(gc, struct pca953x_chip, gpio_chip);
103}
104
f5f0b7aa
GC
105static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
106 int off)
107{
108 int ret;
109 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
110 int offset = off / BANK_SZ;
111
112 ret = i2c_smbus_read_byte_data(chip->client,
113 (reg << bank_shift) + offset);
114 *val = ret;
115
116 if (ret < 0) {
117 dev_err(&chip->client->dev, "failed reading register\n");
118 return ret;
119 }
120
121 return 0;
122}
123
124static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
125 int off)
126{
127 int ret = 0;
128 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
129 int offset = off / BANK_SZ;
130
131 ret = i2c_smbus_write_byte_data(chip->client,
132 (reg << bank_shift) + offset, val);
133
134 if (ret < 0) {
135 dev_err(&chip->client->dev, "failed writing register\n");
136 return ret;
137 }
138
139 return 0;
140}
141
142static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 143{
33226ffd 144 int ret = 0;
f5e8ff48
GL
145
146 if (chip->gpio_chip.ngpio <= 8)
f5f0b7aa
GC
147 ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
148 else if (chip->gpio_chip.ngpio >= 24) {
149 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
96b70641 150 ret = i2c_smbus_write_i2c_block_data(chip->client,
f5f0b7aa
GC
151 (reg << bank_shift) | REG_ADDR_AI,
152 NBANK(chip), val);
50e44430 153 } else {
33226ffd
HZ
154 switch (chip->chip_type) {
155 case PCA953X_TYPE:
156 ret = i2c_smbus_write_word_data(chip->client,
f5f0b7aa 157 reg << 1, (u16) *val);
33226ffd
HZ
158 break;
159 case PCA957X_TYPE:
160 ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
f5f0b7aa 161 val[0]);
33226ffd
HZ
162 if (ret < 0)
163 break;
164 ret = i2c_smbus_write_byte_data(chip->client,
165 (reg << 1) + 1,
f5f0b7aa 166 val[1]);
33226ffd
HZ
167 break;
168 }
169 }
f5e8ff48
GL
170
171 if (ret < 0) {
172 dev_err(&chip->client->dev, "failed writing register\n");
ab5dc372 173 return ret;
f5e8ff48
GL
174 }
175
176 return 0;
9e60fdcf 177}
178
f5f0b7aa 179static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 180{
181 int ret;
182
96b70641 183 if (chip->gpio_chip.ngpio <= 8) {
f5e8ff48 184 ret = i2c_smbus_read_byte_data(chip->client, reg);
96b70641 185 *val = ret;
f5f0b7aa
GC
186 } else if (chip->gpio_chip.ngpio >= 24) {
187 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
188
96b70641 189 ret = i2c_smbus_read_i2c_block_data(chip->client,
f5f0b7aa
GC
190 (reg << bank_shift) | REG_ADDR_AI,
191 NBANK(chip), val);
96b70641 192 } else {
f5e8ff48 193 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
f5f0b7aa
GC
194 val[0] = (u16)ret & 0xFF;
195 val[1] = (u16)ret >> 8;
96b70641 196 }
9e60fdcf 197 if (ret < 0) {
198 dev_err(&chip->client->dev, "failed reading register\n");
ab5dc372 199 return ret;
9e60fdcf 200 }
201
9e60fdcf 202 return 0;
203}
204
f3dc3630 205static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
9e60fdcf 206{
7bcbce55 207 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa 208 u8 reg_val;
33226ffd 209 int ret, offset = 0;
9e60fdcf 210
6e20fb18 211 mutex_lock(&chip->i2c_lock);
f5f0b7aa 212 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
33226ffd
HZ
213
214 switch (chip->chip_type) {
215 case PCA953X_TYPE:
216 offset = PCA953X_DIRECTION;
217 break;
218 case PCA957X_TYPE:
219 offset = PCA957X_CFG;
220 break;
221 }
f5f0b7aa 222 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 223 if (ret)
6e20fb18 224 goto exit;
9e60fdcf 225
f5f0b7aa 226 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
227 ret = 0;
228exit:
229 mutex_unlock(&chip->i2c_lock);
230 return ret;
9e60fdcf 231}
232
f3dc3630 233static int pca953x_gpio_direction_output(struct gpio_chip *gc,
9e60fdcf 234 unsigned off, int val)
235{
7bcbce55 236 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa 237 u8 reg_val;
33226ffd 238 int ret, offset = 0;
9e60fdcf 239
6e20fb18 240 mutex_lock(&chip->i2c_lock);
9e60fdcf 241 /* set output level */
242 if (val)
f5f0b7aa
GC
243 reg_val = chip->reg_output[off / BANK_SZ]
244 | (1u << (off % BANK_SZ));
9e60fdcf 245 else
f5f0b7aa
GC
246 reg_val = chip->reg_output[off / BANK_SZ]
247 & ~(1u << (off % BANK_SZ));
9e60fdcf 248
33226ffd
HZ
249 switch (chip->chip_type) {
250 case PCA953X_TYPE:
251 offset = PCA953X_OUTPUT;
252 break;
253 case PCA957X_TYPE:
254 offset = PCA957X_OUT;
255 break;
256 }
f5f0b7aa 257 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 258 if (ret)
6e20fb18 259 goto exit;
9e60fdcf 260
f5f0b7aa 261 chip->reg_output[off / BANK_SZ] = reg_val;
9e60fdcf 262
263 /* then direction */
f5f0b7aa 264 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
33226ffd
HZ
265 switch (chip->chip_type) {
266 case PCA953X_TYPE:
267 offset = PCA953X_DIRECTION;
268 break;
269 case PCA957X_TYPE:
270 offset = PCA957X_CFG;
271 break;
272 }
f5f0b7aa 273 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 274 if (ret)
6e20fb18 275 goto exit;
9e60fdcf 276
f5f0b7aa 277 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
278 ret = 0;
279exit:
280 mutex_unlock(&chip->i2c_lock);
281 return ret;
9e60fdcf 282}
283
f3dc3630 284static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
9e60fdcf 285{
7bcbce55 286 struct pca953x_chip *chip = to_pca(gc);
ae79c190 287 u32 reg_val;
33226ffd 288 int ret, offset = 0;
9e60fdcf 289
6e20fb18 290 mutex_lock(&chip->i2c_lock);
33226ffd
HZ
291 switch (chip->chip_type) {
292 case PCA953X_TYPE:
293 offset = PCA953X_INPUT;
294 break;
295 case PCA957X_TYPE:
296 offset = PCA957X_IN;
297 break;
298 }
f5f0b7aa 299 ret = pca953x_read_single(chip, offset, &reg_val, off);
6e20fb18 300 mutex_unlock(&chip->i2c_lock);
9e60fdcf 301 if (ret < 0) {
302 /* NOTE: diagnostic already emitted; that's all we should
303 * do unless gpio_*_value_cansleep() calls become different
304 * from their nonsleeping siblings (and report faults).
305 */
306 return 0;
307 }
308
40a625da 309 return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
9e60fdcf 310}
311
f3dc3630 312static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
9e60fdcf 313{
7bcbce55 314 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa 315 u8 reg_val;
33226ffd 316 int ret, offset = 0;
9e60fdcf 317
6e20fb18 318 mutex_lock(&chip->i2c_lock);
9e60fdcf 319 if (val)
f5f0b7aa
GC
320 reg_val = chip->reg_output[off / BANK_SZ]
321 | (1u << (off % BANK_SZ));
9e60fdcf 322 else
f5f0b7aa
GC
323 reg_val = chip->reg_output[off / BANK_SZ]
324 & ~(1u << (off % BANK_SZ));
9e60fdcf 325
33226ffd
HZ
326 switch (chip->chip_type) {
327 case PCA953X_TYPE:
328 offset = PCA953X_OUTPUT;
329 break;
330 case PCA957X_TYPE:
331 offset = PCA957X_OUT;
332 break;
333 }
f5f0b7aa 334 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 335 if (ret)
6e20fb18 336 goto exit;
9e60fdcf 337
f5f0b7aa 338 chip->reg_output[off / BANK_SZ] = reg_val;
6e20fb18
RS
339exit:
340 mutex_unlock(&chip->i2c_lock);
9e60fdcf 341}
342
f5e8ff48 343static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
9e60fdcf 344{
345 struct gpio_chip *gc;
346
347 gc = &chip->gpio_chip;
348
f3dc3630
GL
349 gc->direction_input = pca953x_gpio_direction_input;
350 gc->direction_output = pca953x_gpio_direction_output;
351 gc->get = pca953x_gpio_get_value;
352 gc->set = pca953x_gpio_set_value;
9fb1f39e 353 gc->can_sleep = true;
9e60fdcf 354
355 gc->base = chip->gpio_start;
f5e8ff48
GL
356 gc->ngpio = gpios;
357 gc->label = chip->client->name;
d8f388d8 358 gc->dev = &chip->client->dev;
d72cbed0 359 gc->owner = THIS_MODULE;
77906a54 360 gc->names = chip->names;
9e60fdcf 361}
362
89ea8bbe 363#ifdef CONFIG_GPIO_PCA953X_IRQ
6f5cfc0e 364static void pca953x_irq_mask(struct irq_data *d)
89ea8bbe 365{
7bcbce55
LW
366 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
367 struct pca953x_chip *chip = to_pca(gc);
89ea8bbe 368
f5f0b7aa 369 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
89ea8bbe
MZ
370}
371
6f5cfc0e 372static void pca953x_irq_unmask(struct irq_data *d)
89ea8bbe 373{
7bcbce55
LW
374 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
375 struct pca953x_chip *chip = to_pca(gc);
89ea8bbe 376
f5f0b7aa 377 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
378}
379
6f5cfc0e 380static void pca953x_irq_bus_lock(struct irq_data *d)
89ea8bbe 381{
7bcbce55
LW
382 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
383 struct pca953x_chip *chip = to_pca(gc);
89ea8bbe
MZ
384
385 mutex_lock(&chip->irq_lock);
386}
387
6f5cfc0e 388static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
89ea8bbe 389{
7bcbce55
LW
390 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
391 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa
GC
392 u8 new_irqs;
393 int level, i;
a2cb9aeb
MZ
394
395 /* Look for any newly setup interrupt */
f5f0b7aa
GC
396 for (i = 0; i < NBANK(chip); i++) {
397 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
398 new_irqs &= ~chip->reg_direction[i];
399
400 while (new_irqs) {
401 level = __ffs(new_irqs);
402 pca953x_gpio_direction_input(&chip->gpio_chip,
403 level + (BANK_SZ * i));
404 new_irqs &= ~(1 << level);
405 }
a2cb9aeb 406 }
89ea8bbe
MZ
407
408 mutex_unlock(&chip->irq_lock);
409}
410
6f5cfc0e 411static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
89ea8bbe 412{
7bcbce55
LW
413 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
414 struct pca953x_chip *chip = to_pca(gc);
f5f0b7aa
GC
415 int bank_nb = d->hwirq / BANK_SZ;
416 u8 mask = 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
417
418 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
419 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
6f5cfc0e 420 d->irq, type);
89ea8bbe
MZ
421 return -EINVAL;
422 }
423
424 if (type & IRQ_TYPE_EDGE_FALLING)
f5f0b7aa 425 chip->irq_trig_fall[bank_nb] |= mask;
89ea8bbe 426 else
f5f0b7aa 427 chip->irq_trig_fall[bank_nb] &= ~mask;
89ea8bbe
MZ
428
429 if (type & IRQ_TYPE_EDGE_RISING)
f5f0b7aa 430 chip->irq_trig_raise[bank_nb] |= mask;
89ea8bbe 431 else
f5f0b7aa 432 chip->irq_trig_raise[bank_nb] &= ~mask;
89ea8bbe 433
a2cb9aeb 434 return 0;
89ea8bbe
MZ
435}
436
437static struct irq_chip pca953x_irq_chip = {
438 .name = "pca953x",
6f5cfc0e
LB
439 .irq_mask = pca953x_irq_mask,
440 .irq_unmask = pca953x_irq_unmask,
441 .irq_bus_lock = pca953x_irq_bus_lock,
442 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
443 .irq_set_type = pca953x_irq_set_type,
89ea8bbe
MZ
444};
445
f5f0b7aa 446static u8 pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
89ea8bbe 447{
f5f0b7aa
GC
448 u8 cur_stat[MAX_BANK];
449 u8 old_stat[MAX_BANK];
450 u8 pendings = 0;
451 u8 trigger[MAX_BANK], triggers = 0;
452 int ret, i, offset = 0;
33226ffd
HZ
453
454 switch (chip->chip_type) {
455 case PCA953X_TYPE:
456 offset = PCA953X_INPUT;
457 break;
458 case PCA957X_TYPE:
459 offset = PCA957X_IN;
460 break;
461 }
f5f0b7aa 462 ret = pca953x_read_regs(chip, offset, cur_stat);
89ea8bbe
MZ
463 if (ret)
464 return 0;
465
466 /* Remove output pins from the equation */
f5f0b7aa
GC
467 for (i = 0; i < NBANK(chip); i++)
468 cur_stat[i] &= chip->reg_direction[i];
89ea8bbe 469
f5f0b7aa 470 memcpy(old_stat, chip->irq_stat, NBANK(chip));
89ea8bbe 471
f5f0b7aa
GC
472 for (i = 0; i < NBANK(chip); i++) {
473 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
474 triggers += trigger[i];
475 }
476
477 if (!triggers)
89ea8bbe
MZ
478 return 0;
479
f5f0b7aa 480 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
89ea8bbe 481
f5f0b7aa
GC
482 for (i = 0; i < NBANK(chip); i++) {
483 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
484 (cur_stat[i] & chip->irq_trig_raise[i]);
485 pending[i] &= trigger[i];
486 pendings += pending[i];
487 }
89ea8bbe 488
f5f0b7aa 489 return pendings;
89ea8bbe
MZ
490}
491
492static irqreturn_t pca953x_irq_handler(int irq, void *devid)
493{
494 struct pca953x_chip *chip = devid;
f5f0b7aa
GC
495 u8 pending[MAX_BANK];
496 u8 level;
3275d072 497 unsigned nhandled = 0;
f5f0b7aa 498 int i;
89ea8bbe 499
f5f0b7aa 500 if (!pca953x_irq_pending(chip, pending))
3275d072 501 return IRQ_NONE;
89ea8bbe 502
f5f0b7aa
GC
503 for (i = 0; i < NBANK(chip); i++) {
504 while (pending[i]) {
505 level = __ffs(pending[i]);
7bcbce55 506 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
f5f0b7aa
GC
507 level + (BANK_SZ * i)));
508 pending[i] &= ~(1 << level);
3275d072 509 nhandled++;
f5f0b7aa
GC
510 }
511 }
89ea8bbe 512
3275d072 513 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
89ea8bbe
MZ
514}
515
516static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592
DJ
517 const struct i2c_device_id *id,
518 int irq_base)
89ea8bbe
MZ
519{
520 struct i2c_client *client = chip->client;
f5f0b7aa 521 int ret, i, offset = 0;
89ea8bbe 522
4bb93349 523 if (client->irq && irq_base != -1
33226ffd 524 && (id->driver_data & PCA_INT)) {
89ea8bbe 525
33226ffd
HZ
526 switch (chip->chip_type) {
527 case PCA953X_TYPE:
528 offset = PCA953X_INPUT;
529 break;
530 case PCA957X_TYPE:
531 offset = PCA957X_IN;
532 break;
533 }
f5f0b7aa 534 ret = pca953x_read_regs(chip, offset, chip->irq_stat);
89ea8bbe 535 if (ret)
b42748c9 536 return ret;
89ea8bbe
MZ
537
538 /*
539 * There is no way to know which GPIO line generated the
540 * interrupt. We have to rely on the previous read for
541 * this purpose.
542 */
f5f0b7aa
GC
543 for (i = 0; i < NBANK(chip); i++)
544 chip->irq_stat[i] &= chip->reg_direction[i];
89ea8bbe
MZ
545 mutex_init(&chip->irq_lock);
546
b42748c9
LW
547 ret = devm_request_threaded_irq(&client->dev,
548 client->irq,
89ea8bbe
MZ
549 NULL,
550 pca953x_irq_handler,
91329132
TS
551 IRQF_TRIGGER_LOW | IRQF_ONESHOT |
552 IRQF_SHARED,
89ea8bbe
MZ
553 dev_name(&client->dev), chip);
554 if (ret) {
555 dev_err(&client->dev, "failed to request irq %d\n",
556 client->irq);
0e8f2fda 557 return ret;
89ea8bbe
MZ
558 }
559
7bcbce55
LW
560 ret = gpiochip_irqchip_add(&chip->gpio_chip,
561 &pca953x_irq_chip,
562 irq_base,
563 handle_simple_irq,
564 IRQ_TYPE_NONE);
565 if (ret) {
566 dev_err(&client->dev,
567 "could not connect irqchip to gpiochip\n");
568 return ret;
569 }
89ea8bbe
MZ
570 }
571
572 return 0;
89ea8bbe
MZ
573}
574
89ea8bbe
MZ
575#else /* CONFIG_GPIO_PCA953X_IRQ */
576static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592
DJ
577 const struct i2c_device_id *id,
578 int irq_base)
89ea8bbe
MZ
579{
580 struct i2c_client *client = chip->client;
89ea8bbe 581
c6dcf592 582 if (irq_base != -1 && (id->driver_data & PCA_INT))
89ea8bbe
MZ
583 dev_warn(&client->dev, "interrupt support not compiled in\n");
584
585 return 0;
586}
89ea8bbe
MZ
587#endif
588
3836309d 589static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
590{
591 int ret;
f5f0b7aa 592 u8 val[MAX_BANK];
33226ffd 593
f5f0b7aa 594 ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
33226ffd
HZ
595 if (ret)
596 goto out;
597
f5f0b7aa
GC
598 ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
599 chip->reg_direction);
33226ffd
HZ
600 if (ret)
601 goto out;
602
603 /* set platform specific polarity inversion */
f5f0b7aa
GC
604 if (invert)
605 memset(val, 0xFF, NBANK(chip));
606 else
607 memset(val, 0, NBANK(chip));
608
609 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
33226ffd
HZ
610out:
611 return ret;
612}
613
3836309d 614static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
615{
616 int ret;
f5f0b7aa 617 u8 val[MAX_BANK];
33226ffd 618
f5f0b7aa 619 ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
33226ffd
HZ
620 if (ret)
621 goto out;
f5f0b7aa 622 ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
33226ffd
HZ
623 if (ret)
624 goto out;
625
626 /* set platform specific polarity inversion */
f5f0b7aa
GC
627 if (invert)
628 memset(val, 0xFF, NBANK(chip));
629 else
630 memset(val, 0, NBANK(chip));
631 pca953x_write_regs(chip, PCA957X_INVRT, val);
33226ffd 632
20a8a968 633 /* To enable register 6, 7 to control pull up and pull down */
f5f0b7aa
GC
634 memset(val, 0x02, NBANK(chip));
635 pca953x_write_regs(chip, PCA957X_BKEN, val);
33226ffd
HZ
636
637 return 0;
638out:
639 return ret;
640}
641
3836309d 642static int pca953x_probe(struct i2c_client *client,
3760f736 643 const struct i2c_device_id *id)
9e60fdcf 644{
f3dc3630
GL
645 struct pca953x_platform_data *pdata;
646 struct pca953x_chip *chip;
6a7b36aa 647 int irq_base = 0;
7ea2aa20 648 int ret;
6a7b36aa 649 u32 invert = 0;
9e60fdcf 650
b42748c9
LW
651 chip = devm_kzalloc(&client->dev,
652 sizeof(struct pca953x_chip), GFP_KERNEL);
1965d303
NC
653 if (chip == NULL)
654 return -ENOMEM;
655
e56aee18 656 pdata = dev_get_platdata(&client->dev);
c6dcf592
DJ
657 if (pdata) {
658 irq_base = pdata->irq_base;
659 chip->gpio_start = pdata->gpio_base;
660 invert = pdata->invert;
661 chip->names = pdata->names;
662 } else {
4bb93349
MP
663 chip->gpio_start = -1;
664 irq_base = 0;
1965d303 665 }
9e60fdcf 666
667 chip->client = client;
668
33226ffd 669 chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE);
77906a54 670
6e20fb18
RS
671 mutex_init(&chip->i2c_lock);
672
9e60fdcf 673 /* initialize cached registers from their original values.
674 * we can't share this chip with another i2c master.
675 */
33226ffd 676 pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK);
f5e8ff48 677
33226ffd 678 if (chip->chip_type == PCA953X_TYPE)
7ea2aa20 679 ret = device_pca953x_init(chip, invert);
33226ffd 680 else
7ea2aa20
WS
681 ret = device_pca957x_init(chip, invert);
682 if (ret)
b42748c9 683 return ret;
9e60fdcf 684
7bcbce55 685 ret = gpiochip_add(&chip->gpio_chip);
89ea8bbe 686 if (ret)
b42748c9 687 return ret;
f5e8ff48 688
7bcbce55 689 ret = pca953x_irq_setup(chip, id, irq_base);
9e60fdcf 690 if (ret)
b42748c9 691 return ret;
9e60fdcf 692
c6dcf592 693 if (pdata && pdata->setup) {
9e60fdcf 694 ret = pdata->setup(client, chip->gpio_chip.base,
695 chip->gpio_chip.ngpio, pdata->context);
696 if (ret < 0)
697 dev_warn(&client->dev, "setup failed, %d\n", ret);
698 }
699
700 i2c_set_clientdata(client, chip);
701 return 0;
9e60fdcf 702}
703
f3dc3630 704static int pca953x_remove(struct i2c_client *client)
9e60fdcf 705{
e56aee18 706 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
f3dc3630 707 struct pca953x_chip *chip = i2c_get_clientdata(client);
9e60fdcf 708 int ret = 0;
709
c6dcf592 710 if (pdata && pdata->teardown) {
9e60fdcf 711 ret = pdata->teardown(client, chip->gpio_chip.base,
712 chip->gpio_chip.ngpio, pdata->context);
713 if (ret < 0) {
714 dev_err(&client->dev, "%s failed, %d\n",
715 "teardown", ret);
716 return ret;
717 }
718 }
719
9f5132ae 720 gpiochip_remove(&chip->gpio_chip);
9e60fdcf 721
9e60fdcf 722 return 0;
723}
724
ed32620e 725static const struct of_device_id pca953x_dt_ids[] = {
89f5df01 726 { .compatible = "nxp,pca9505", },
ed32620e
MR
727 { .compatible = "nxp,pca9534", },
728 { .compatible = "nxp,pca9535", },
729 { .compatible = "nxp,pca9536", },
730 { .compatible = "nxp,pca9537", },
731 { .compatible = "nxp,pca9538", },
732 { .compatible = "nxp,pca9539", },
733 { .compatible = "nxp,pca9554", },
734 { .compatible = "nxp,pca9555", },
735 { .compatible = "nxp,pca9556", },
736 { .compatible = "nxp,pca9557", },
737 { .compatible = "nxp,pca9574", },
738 { .compatible = "nxp,pca9575", },
eb32b5aa 739 { .compatible = "nxp,pca9698", },
ed32620e
MR
740
741 { .compatible = "maxim,max7310", },
742 { .compatible = "maxim,max7312", },
743 { .compatible = "maxim,max7313", },
744 { .compatible = "maxim,max7315", },
745
746 { .compatible = "ti,pca6107", },
747 { .compatible = "ti,tca6408", },
748 { .compatible = "ti,tca6416", },
749 { .compatible = "ti,tca6424", },
e73760a6
AS
750
751 { .compatible = "exar,xra1202", },
ed32620e
MR
752 { }
753};
754
755MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
756
f3dc3630 757static struct i2c_driver pca953x_driver = {
9e60fdcf 758 .driver = {
f3dc3630 759 .name = "pca953x",
ed32620e 760 .of_match_table = pca953x_dt_ids,
9e60fdcf 761 },
f3dc3630
GL
762 .probe = pca953x_probe,
763 .remove = pca953x_remove,
3760f736 764 .id_table = pca953x_id,
9e60fdcf 765};
766
f3dc3630 767static int __init pca953x_init(void)
9e60fdcf 768{
f3dc3630 769 return i2c_add_driver(&pca953x_driver);
9e60fdcf 770}
2f8d1197
DB
771/* register after i2c postcore initcall and before
772 * subsys initcalls that may rely on these GPIOs
773 */
774subsys_initcall(pca953x_init);
9e60fdcf 775
f3dc3630 776static void __exit pca953x_exit(void)
9e60fdcf 777{
f3dc3630 778 i2c_del_driver(&pca953x_driver);
9e60fdcf 779}
f3dc3630 780module_exit(pca953x_exit);
9e60fdcf 781
782MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
f3dc3630 783MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
9e60fdcf 784MODULE_LICENSE("GPL");