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9e60fdcf 1/*
1e191695 2 * PCA953x 4/8/16/24/40 bit I/O ports
9e60fdcf 3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd.
6 *
7 * Derived from drivers/i2c/chips/pca9539.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
d120c17f 16#include <linux/gpio.h>
89ea8bbe 17#include <linux/interrupt.h>
9e60fdcf 18#include <linux/i2c.h>
5877457a 19#include <linux/platform_data/pca953x.h>
5a0e3ad6 20#include <linux/slab.h>
9b8e3ec3 21#include <asm/unaligned.h>
1965d303 22#include <linux/of_platform.h>
f32517bf 23#include <linux/acpi.h>
e23efa31 24#include <linux/regulator/consumer.h>
9e60fdcf 25
33226ffd
HZ
26#define PCA953X_INPUT 0
27#define PCA953X_OUTPUT 1
28#define PCA953X_INVERT 2
29#define PCA953X_DIRECTION 3
30
ae79c190
AS
31#define REG_ADDR_AI 0x80
32
33226ffd
HZ
33#define PCA957X_IN 0
34#define PCA957X_INVRT 1
35#define PCA957X_BKEN 2
36#define PCA957X_PUPD 3
37#define PCA957X_CFG 4
38#define PCA957X_OUT 5
39#define PCA957X_MSK 6
40#define PCA957X_INTS 7
41
44896bea
YL
42#define PCAL953X_IN_LATCH 34
43#define PCAL953X_INT_MASK 37
44#define PCAL953X_INT_STAT 38
45
33226ffd
HZ
46#define PCA_GPIO_MASK 0x00FF
47#define PCA_INT 0x0100
8c7a92da 48#define PCA_PCAL 0x0200
33226ffd
HZ
49#define PCA953X_TYPE 0x1000
50#define PCA957X_TYPE 0x2000
c6664149
AS
51#define PCA_TYPE_MASK 0xF000
52
53#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
89ea8bbe 54
3760f736 55static const struct i2c_device_id pca953x_id[] = {
89f5df01 56 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
33226ffd
HZ
57 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
58 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
59 { "pca9536", 4 | PCA953X_TYPE, },
60 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
61 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
62 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
63 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
64 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
65 { "pca9556", 8 | PCA953X_TYPE, },
66 { "pca9557", 8 | PCA953X_TYPE, },
67 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
68 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
eb32b5aa 69 { "pca9698", 40 | PCA953X_TYPE, },
33226ffd 70
747e42a1
AS
71 { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
72
33226ffd
HZ
73 { "max7310", 8 | PCA953X_TYPE, },
74 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
75 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
76 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
77 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
78 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
79 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
ae79c190 80 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
2db8aba8 81 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
e73760a6 82 { "xra1202", 8 | PCA953X_TYPE },
3760f736 83 { }
f5e8ff48 84};
3760f736 85MODULE_DEVICE_TABLE(i2c, pca953x_id);
9e60fdcf 86
f32517bf 87static const struct acpi_device_id pca953x_acpi_ids[] = {
44896bea 88 { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
f32517bf
AS
89 { }
90};
91MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
92
f5f0b7aa
GC
93#define MAX_BANK 5
94#define BANK_SZ 8
95
a246b819 96#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
f5f0b7aa 97
f3dc3630 98struct pca953x_chip {
9e60fdcf 99 unsigned gpio_start;
f5f0b7aa
GC
100 u8 reg_output[MAX_BANK];
101 u8 reg_direction[MAX_BANK];
6e20fb18 102 struct mutex i2c_lock;
9e60fdcf 103
89ea8bbe
MZ
104#ifdef CONFIG_GPIO_PCA953X_IRQ
105 struct mutex irq_lock;
f5f0b7aa
GC
106 u8 irq_mask[MAX_BANK];
107 u8 irq_stat[MAX_BANK];
108 u8 irq_trig_raise[MAX_BANK];
109 u8 irq_trig_fall[MAX_BANK];
89ea8bbe
MZ
110#endif
111
9e60fdcf 112 struct i2c_client *client;
113 struct gpio_chip gpio_chip;
62154991 114 const char *const *names;
33226ffd 115 int chip_type;
c6664149 116 unsigned long driver_data;
e23efa31 117 struct regulator *regulator;
9e60fdcf 118};
119
f5f0b7aa
GC
120static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
121 int off)
122{
123 int ret;
124 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
125 int offset = off / BANK_SZ;
126
127 ret = i2c_smbus_read_byte_data(chip->client,
128 (reg << bank_shift) + offset);
129 *val = ret;
130
131 if (ret < 0) {
132 dev_err(&chip->client->dev, "failed reading register\n");
133 return ret;
134 }
135
136 return 0;
137}
138
139static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
140 int off)
141{
8c7a92da 142 int ret;
f5f0b7aa
GC
143 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
144 int offset = off / BANK_SZ;
145
146 ret = i2c_smbus_write_byte_data(chip->client,
147 (reg << bank_shift) + offset, val);
148
149 if (ret < 0) {
150 dev_err(&chip->client->dev, "failed writing register\n");
151 return ret;
152 }
153
154 return 0;
155}
156
157static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 158{
33226ffd 159 int ret = 0;
f5e8ff48
GL
160
161 if (chip->gpio_chip.ngpio <= 8)
f5f0b7aa
GC
162 ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
163 else if (chip->gpio_chip.ngpio >= 24) {
164 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
96b70641 165 ret = i2c_smbus_write_i2c_block_data(chip->client,
f5f0b7aa
GC
166 (reg << bank_shift) | REG_ADDR_AI,
167 NBANK(chip), val);
50e44430 168 } else {
33226ffd 169 switch (chip->chip_type) {
c4d1cbd7
AS
170 case PCA953X_TYPE: {
171 __le16 word = cpu_to_le16(get_unaligned((u16 *)val));
172
173 ret = i2c_smbus_write_word_data(chip->client, reg << 1,
174 (__force u16)word);
33226ffd 175 break;
c4d1cbd7 176 }
33226ffd
HZ
177 case PCA957X_TYPE:
178 ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
f5f0b7aa 179 val[0]);
33226ffd
HZ
180 if (ret < 0)
181 break;
182 ret = i2c_smbus_write_byte_data(chip->client,
183 (reg << 1) + 1,
f5f0b7aa 184 val[1]);
33226ffd
HZ
185 break;
186 }
187 }
f5e8ff48
GL
188
189 if (ret < 0) {
190 dev_err(&chip->client->dev, "failed writing register\n");
ab5dc372 191 return ret;
f5e8ff48
GL
192 }
193
194 return 0;
9e60fdcf 195}
196
f5f0b7aa 197static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 198{
199 int ret;
200
96b70641 201 if (chip->gpio_chip.ngpio <= 8) {
f5e8ff48 202 ret = i2c_smbus_read_byte_data(chip->client, reg);
96b70641 203 *val = ret;
f5f0b7aa
GC
204 } else if (chip->gpio_chip.ngpio >= 24) {
205 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
206
96b70641 207 ret = i2c_smbus_read_i2c_block_data(chip->client,
f5f0b7aa
GC
208 (reg << bank_shift) | REG_ADDR_AI,
209 NBANK(chip), val);
96b70641 210 } else {
f5e8ff48 211 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
f5f0b7aa
GC
212 val[0] = (u16)ret & 0xFF;
213 val[1] = (u16)ret >> 8;
96b70641 214 }
9e60fdcf 215 if (ret < 0) {
216 dev_err(&chip->client->dev, "failed reading register\n");
ab5dc372 217 return ret;
9e60fdcf 218 }
219
9e60fdcf 220 return 0;
221}
222
f3dc3630 223static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
9e60fdcf 224{
468e67f6 225 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 226 u8 reg_val;
33226ffd 227 int ret, offset = 0;
9e60fdcf 228
6e20fb18 229 mutex_lock(&chip->i2c_lock);
f5f0b7aa 230 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
33226ffd
HZ
231
232 switch (chip->chip_type) {
233 case PCA953X_TYPE:
234 offset = PCA953X_DIRECTION;
235 break;
236 case PCA957X_TYPE:
237 offset = PCA957X_CFG;
238 break;
239 }
f5f0b7aa 240 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 241 if (ret)
6e20fb18 242 goto exit;
9e60fdcf 243
f5f0b7aa 244 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
245exit:
246 mutex_unlock(&chip->i2c_lock);
247 return ret;
9e60fdcf 248}
249
f3dc3630 250static int pca953x_gpio_direction_output(struct gpio_chip *gc,
9e60fdcf 251 unsigned off, int val)
252{
468e67f6 253 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 254 u8 reg_val;
33226ffd 255 int ret, offset = 0;
9e60fdcf 256
6e20fb18 257 mutex_lock(&chip->i2c_lock);
9e60fdcf 258 /* set output level */
259 if (val)
f5f0b7aa
GC
260 reg_val = chip->reg_output[off / BANK_SZ]
261 | (1u << (off % BANK_SZ));
9e60fdcf 262 else
f5f0b7aa
GC
263 reg_val = chip->reg_output[off / BANK_SZ]
264 & ~(1u << (off % BANK_SZ));
9e60fdcf 265
33226ffd
HZ
266 switch (chip->chip_type) {
267 case PCA953X_TYPE:
268 offset = PCA953X_OUTPUT;
269 break;
270 case PCA957X_TYPE:
271 offset = PCA957X_OUT;
272 break;
273 }
f5f0b7aa 274 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 275 if (ret)
6e20fb18 276 goto exit;
9e60fdcf 277
f5f0b7aa 278 chip->reg_output[off / BANK_SZ] = reg_val;
9e60fdcf 279
280 /* then direction */
f5f0b7aa 281 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
33226ffd
HZ
282 switch (chip->chip_type) {
283 case PCA953X_TYPE:
284 offset = PCA953X_DIRECTION;
285 break;
286 case PCA957X_TYPE:
287 offset = PCA957X_CFG;
288 break;
289 }
f5f0b7aa 290 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 291 if (ret)
6e20fb18 292 goto exit;
9e60fdcf 293
f5f0b7aa 294 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
295exit:
296 mutex_unlock(&chip->i2c_lock);
297 return ret;
9e60fdcf 298}
299
f3dc3630 300static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
9e60fdcf 301{
468e67f6 302 struct pca953x_chip *chip = gpiochip_get_data(gc);
ae79c190 303 u32 reg_val;
33226ffd 304 int ret, offset = 0;
9e60fdcf 305
6e20fb18 306 mutex_lock(&chip->i2c_lock);
33226ffd
HZ
307 switch (chip->chip_type) {
308 case PCA953X_TYPE:
309 offset = PCA953X_INPUT;
310 break;
311 case PCA957X_TYPE:
312 offset = PCA957X_IN;
313 break;
314 }
f5f0b7aa 315 ret = pca953x_read_single(chip, offset, &reg_val, off);
6e20fb18 316 mutex_unlock(&chip->i2c_lock);
9e60fdcf 317 if (ret < 0) {
318 /* NOTE: diagnostic already emitted; that's all we should
319 * do unless gpio_*_value_cansleep() calls become different
320 * from their nonsleeping siblings (and report faults).
321 */
322 return 0;
323 }
324
40a625da 325 return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
9e60fdcf 326}
327
f3dc3630 328static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
9e60fdcf 329{
468e67f6 330 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 331 u8 reg_val;
33226ffd 332 int ret, offset = 0;
9e60fdcf 333
6e20fb18 334 mutex_lock(&chip->i2c_lock);
9e60fdcf 335 if (val)
f5f0b7aa
GC
336 reg_val = chip->reg_output[off / BANK_SZ]
337 | (1u << (off % BANK_SZ));
9e60fdcf 338 else
f5f0b7aa
GC
339 reg_val = chip->reg_output[off / BANK_SZ]
340 & ~(1u << (off % BANK_SZ));
9e60fdcf 341
33226ffd
HZ
342 switch (chip->chip_type) {
343 case PCA953X_TYPE:
344 offset = PCA953X_OUTPUT;
345 break;
346 case PCA957X_TYPE:
347 offset = PCA957X_OUT;
348 break;
349 }
f5f0b7aa 350 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 351 if (ret)
6e20fb18 352 goto exit;
9e60fdcf 353
f5f0b7aa 354 chip->reg_output[off / BANK_SZ] = reg_val;
6e20fb18
RS
355exit:
356 mutex_unlock(&chip->i2c_lock);
9e60fdcf 357}
358
b4818afe
PR
359static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
360 unsigned long *mask, unsigned long *bits)
361{
468e67f6 362 struct pca953x_chip *chip = gpiochip_get_data(gc);
b4818afe
PR
363 u8 reg_val[MAX_BANK];
364 int ret, offset = 0;
365 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
366 int bank;
367
368 switch (chip->chip_type) {
369 case PCA953X_TYPE:
370 offset = PCA953X_OUTPUT;
371 break;
372 case PCA957X_TYPE:
373 offset = PCA957X_OUT;
374 break;
375 }
376
377 memcpy(reg_val, chip->reg_output, NBANK(chip));
378 mutex_lock(&chip->i2c_lock);
379 for(bank=0; bank<NBANK(chip); bank++) {
e0a8604f
GU
380 unsigned bankmask = mask[bank / sizeof(*mask)] >>
381 ((bank % sizeof(*mask)) * 8);
b4818afe 382 if(bankmask) {
e0a8604f
GU
383 unsigned bankval = bits[bank / sizeof(*bits)] >>
384 ((bank % sizeof(*bits)) * 8);
b4818afe
PR
385 reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval;
386 }
387 }
388 ret = i2c_smbus_write_i2c_block_data(chip->client, offset << bank_shift, NBANK(chip), reg_val);
389 if (ret)
390 goto exit;
391
392 memcpy(chip->reg_output, reg_val, NBANK(chip));
393exit:
394 mutex_unlock(&chip->i2c_lock);
395}
396
f5e8ff48 397static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
9e60fdcf 398{
399 struct gpio_chip *gc;
400
401 gc = &chip->gpio_chip;
402
f3dc3630
GL
403 gc->direction_input = pca953x_gpio_direction_input;
404 gc->direction_output = pca953x_gpio_direction_output;
405 gc->get = pca953x_gpio_get_value;
406 gc->set = pca953x_gpio_set_value;
b4818afe 407 gc->set_multiple = pca953x_gpio_set_multiple;
9fb1f39e 408 gc->can_sleep = true;
9e60fdcf 409
410 gc->base = chip->gpio_start;
f5e8ff48
GL
411 gc->ngpio = gpios;
412 gc->label = chip->client->name;
58383c78 413 gc->parent = &chip->client->dev;
d72cbed0 414 gc->owner = THIS_MODULE;
77906a54 415 gc->names = chip->names;
9e60fdcf 416}
417
89ea8bbe 418#ifdef CONFIG_GPIO_PCA953X_IRQ
6f5cfc0e 419static void pca953x_irq_mask(struct irq_data *d)
89ea8bbe 420{
7bcbce55 421 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 422 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe 423
f5f0b7aa 424 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
89ea8bbe
MZ
425}
426
6f5cfc0e 427static void pca953x_irq_unmask(struct irq_data *d)
89ea8bbe 428{
7bcbce55 429 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 430 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe 431
f5f0b7aa 432 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
433}
434
6f5cfc0e 435static void pca953x_irq_bus_lock(struct irq_data *d)
89ea8bbe 436{
7bcbce55 437 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 438 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe
MZ
439
440 mutex_lock(&chip->irq_lock);
441}
442
6f5cfc0e 443static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
89ea8bbe 444{
7bcbce55 445 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 446 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa
GC
447 u8 new_irqs;
448 int level, i;
44896bea
YL
449 u8 invert_irq_mask[MAX_BANK];
450
451 if (chip->driver_data & PCA_PCAL) {
452 /* Enable latch on interrupt-enabled inputs */
453 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
454
455 for (i = 0; i < NBANK(chip); i++)
456 invert_irq_mask[i] = ~chip->irq_mask[i];
457
458 /* Unmask enabled interrupts */
459 pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
460 }
a2cb9aeb
MZ
461
462 /* Look for any newly setup interrupt */
f5f0b7aa
GC
463 for (i = 0; i < NBANK(chip); i++) {
464 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
465 new_irqs &= ~chip->reg_direction[i];
466
467 while (new_irqs) {
468 level = __ffs(new_irqs);
469 pca953x_gpio_direction_input(&chip->gpio_chip,
470 level + (BANK_SZ * i));
471 new_irqs &= ~(1 << level);
472 }
a2cb9aeb 473 }
89ea8bbe
MZ
474
475 mutex_unlock(&chip->irq_lock);
476}
477
6f5cfc0e 478static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
89ea8bbe 479{
7bcbce55 480 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 481 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa
GC
482 int bank_nb = d->hwirq / BANK_SZ;
483 u8 mask = 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
484
485 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
486 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
6f5cfc0e 487 d->irq, type);
89ea8bbe
MZ
488 return -EINVAL;
489 }
490
491 if (type & IRQ_TYPE_EDGE_FALLING)
f5f0b7aa 492 chip->irq_trig_fall[bank_nb] |= mask;
89ea8bbe 493 else
f5f0b7aa 494 chip->irq_trig_fall[bank_nb] &= ~mask;
89ea8bbe
MZ
495
496 if (type & IRQ_TYPE_EDGE_RISING)
f5f0b7aa 497 chip->irq_trig_raise[bank_nb] |= mask;
89ea8bbe 498 else
f5f0b7aa 499 chip->irq_trig_raise[bank_nb] &= ~mask;
89ea8bbe 500
a2cb9aeb 501 return 0;
89ea8bbe
MZ
502}
503
504static struct irq_chip pca953x_irq_chip = {
505 .name = "pca953x",
6f5cfc0e
LB
506 .irq_mask = pca953x_irq_mask,
507 .irq_unmask = pca953x_irq_unmask,
508 .irq_bus_lock = pca953x_irq_bus_lock,
509 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
510 .irq_set_type = pca953x_irq_set_type,
89ea8bbe
MZ
511};
512
b6ac1280 513static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
89ea8bbe 514{
f5f0b7aa
GC
515 u8 cur_stat[MAX_BANK];
516 u8 old_stat[MAX_BANK];
b6ac1280
JS
517 bool pending_seen = false;
518 bool trigger_seen = false;
519 u8 trigger[MAX_BANK];
f5f0b7aa 520 int ret, i, offset = 0;
33226ffd 521
44896bea
YL
522 if (chip->driver_data & PCA_PCAL) {
523 /* Read the current interrupt status from the device */
524 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
525 if (ret)
526 return false;
527
528 /* Check latched inputs and clear interrupt status */
529 ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
530 if (ret)
531 return false;
532
533 for (i = 0; i < NBANK(chip); i++) {
534 /* Apply filter for rising/falling edge selection */
535 pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
536 (cur_stat[i] & chip->irq_trig_raise[i]);
537 pending[i] &= trigger[i];
538 if (pending[i])
539 pending_seen = true;
540 }
541
542 return pending_seen;
543 }
544
33226ffd
HZ
545 switch (chip->chip_type) {
546 case PCA953X_TYPE:
547 offset = PCA953X_INPUT;
548 break;
549 case PCA957X_TYPE:
550 offset = PCA957X_IN;
551 break;
552 }
f5f0b7aa 553 ret = pca953x_read_regs(chip, offset, cur_stat);
89ea8bbe 554 if (ret)
b6ac1280 555 return false;
89ea8bbe
MZ
556
557 /* Remove output pins from the equation */
f5f0b7aa
GC
558 for (i = 0; i < NBANK(chip); i++)
559 cur_stat[i] &= chip->reg_direction[i];
89ea8bbe 560
f5f0b7aa 561 memcpy(old_stat, chip->irq_stat, NBANK(chip));
89ea8bbe 562
f5f0b7aa
GC
563 for (i = 0; i < NBANK(chip); i++) {
564 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
b6ac1280
JS
565 if (trigger[i])
566 trigger_seen = true;
f5f0b7aa
GC
567 }
568
b6ac1280
JS
569 if (!trigger_seen)
570 return false;
89ea8bbe 571
f5f0b7aa 572 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
89ea8bbe 573
f5f0b7aa
GC
574 for (i = 0; i < NBANK(chip); i++) {
575 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
576 (cur_stat[i] & chip->irq_trig_raise[i]);
577 pending[i] &= trigger[i];
b6ac1280
JS
578 if (pending[i])
579 pending_seen = true;
f5f0b7aa 580 }
89ea8bbe 581
b6ac1280 582 return pending_seen;
89ea8bbe
MZ
583}
584
585static irqreturn_t pca953x_irq_handler(int irq, void *devid)
586{
587 struct pca953x_chip *chip = devid;
f5f0b7aa
GC
588 u8 pending[MAX_BANK];
589 u8 level;
3275d072 590 unsigned nhandled = 0;
f5f0b7aa 591 int i;
89ea8bbe 592
f5f0b7aa 593 if (!pca953x_irq_pending(chip, pending))
3275d072 594 return IRQ_NONE;
89ea8bbe 595
f5f0b7aa
GC
596 for (i = 0; i < NBANK(chip); i++) {
597 while (pending[i]) {
598 level = __ffs(pending[i]);
7bcbce55 599 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
f5f0b7aa
GC
600 level + (BANK_SZ * i)));
601 pending[i] &= ~(1 << level);
3275d072 602 nhandled++;
f5f0b7aa
GC
603 }
604 }
89ea8bbe 605
3275d072 606 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
89ea8bbe
MZ
607}
608
609static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592 610 int irq_base)
89ea8bbe
MZ
611{
612 struct i2c_client *client = chip->client;
f5f0b7aa 613 int ret, i, offset = 0;
89ea8bbe 614
4bb93349 615 if (client->irq && irq_base != -1
c6664149 616 && (chip->driver_data & PCA_INT)) {
89ea8bbe 617
33226ffd
HZ
618 switch (chip->chip_type) {
619 case PCA953X_TYPE:
620 offset = PCA953X_INPUT;
621 break;
622 case PCA957X_TYPE:
623 offset = PCA957X_IN;
624 break;
625 }
f5f0b7aa 626 ret = pca953x_read_regs(chip, offset, chip->irq_stat);
89ea8bbe 627 if (ret)
b42748c9 628 return ret;
89ea8bbe
MZ
629
630 /*
631 * There is no way to know which GPIO line generated the
632 * interrupt. We have to rely on the previous read for
633 * this purpose.
634 */
f5f0b7aa
GC
635 for (i = 0; i < NBANK(chip); i++)
636 chip->irq_stat[i] &= chip->reg_direction[i];
89ea8bbe
MZ
637 mutex_init(&chip->irq_lock);
638
b42748c9
LW
639 ret = devm_request_threaded_irq(&client->dev,
640 client->irq,
89ea8bbe
MZ
641 NULL,
642 pca953x_irq_handler,
91329132
TS
643 IRQF_TRIGGER_LOW | IRQF_ONESHOT |
644 IRQF_SHARED,
89ea8bbe
MZ
645 dev_name(&client->dev), chip);
646 if (ret) {
647 dev_err(&client->dev, "failed to request irq %d\n",
648 client->irq);
0e8f2fda 649 return ret;
89ea8bbe
MZ
650 }
651
7bcbce55
LW
652 ret = gpiochip_irqchip_add(&chip->gpio_chip,
653 &pca953x_irq_chip,
654 irq_base,
655 handle_simple_irq,
656 IRQ_TYPE_NONE);
657 if (ret) {
658 dev_err(&client->dev,
659 "could not connect irqchip to gpiochip\n");
660 return ret;
661 }
fdd50409
GS
662
663 gpiochip_set_chained_irqchip(&chip->gpio_chip,
664 &pca953x_irq_chip,
665 client->irq, NULL);
89ea8bbe
MZ
666 }
667
668 return 0;
89ea8bbe
MZ
669}
670
89ea8bbe
MZ
671#else /* CONFIG_GPIO_PCA953X_IRQ */
672static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592 673 int irq_base)
89ea8bbe
MZ
674{
675 struct i2c_client *client = chip->client;
89ea8bbe 676
c6664149 677 if (irq_base != -1 && (chip->driver_data & PCA_INT))
89ea8bbe
MZ
678 dev_warn(&client->dev, "interrupt support not compiled in\n");
679
680 return 0;
681}
89ea8bbe
MZ
682#endif
683
3836309d 684static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
685{
686 int ret;
f5f0b7aa 687 u8 val[MAX_BANK];
33226ffd 688
f5f0b7aa 689 ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
33226ffd
HZ
690 if (ret)
691 goto out;
692
f5f0b7aa
GC
693 ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
694 chip->reg_direction);
33226ffd
HZ
695 if (ret)
696 goto out;
697
698 /* set platform specific polarity inversion */
f5f0b7aa
GC
699 if (invert)
700 memset(val, 0xFF, NBANK(chip));
701 else
702 memset(val, 0, NBANK(chip));
703
704 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
33226ffd
HZ
705out:
706 return ret;
707}
708
3836309d 709static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
710{
711 int ret;
f5f0b7aa 712 u8 val[MAX_BANK];
33226ffd 713
f5f0b7aa 714 ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
33226ffd
HZ
715 if (ret)
716 goto out;
f5f0b7aa 717 ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
33226ffd
HZ
718 if (ret)
719 goto out;
720
721 /* set platform specific polarity inversion */
f5f0b7aa
GC
722 if (invert)
723 memset(val, 0xFF, NBANK(chip));
724 else
725 memset(val, 0, NBANK(chip));
c75a3772
NK
726 ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
727 if (ret)
728 goto out;
33226ffd 729
20a8a968 730 /* To enable register 6, 7 to control pull up and pull down */
f5f0b7aa 731 memset(val, 0x02, NBANK(chip));
c75a3772
NK
732 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
733 if (ret)
734 goto out;
33226ffd
HZ
735
736 return 0;
737out:
738 return ret;
739}
740
6f29c9af
BD
741static const struct of_device_id pca953x_dt_ids[];
742
3836309d 743static int pca953x_probe(struct i2c_client *client,
3760f736 744 const struct i2c_device_id *id)
9e60fdcf 745{
f3dc3630
GL
746 struct pca953x_platform_data *pdata;
747 struct pca953x_chip *chip;
6a7b36aa 748 int irq_base = 0;
7ea2aa20 749 int ret;
6a7b36aa 750 u32 invert = 0;
e23efa31 751 struct regulator *reg;
9e60fdcf 752
b42748c9
LW
753 chip = devm_kzalloc(&client->dev,
754 sizeof(struct pca953x_chip), GFP_KERNEL);
1965d303
NC
755 if (chip == NULL)
756 return -ENOMEM;
757
e56aee18 758 pdata = dev_get_platdata(&client->dev);
c6dcf592
DJ
759 if (pdata) {
760 irq_base = pdata->irq_base;
761 chip->gpio_start = pdata->gpio_base;
762 invert = pdata->invert;
763 chip->names = pdata->names;
764 } else {
4bb93349
MP
765 chip->gpio_start = -1;
766 irq_base = 0;
1965d303 767 }
9e60fdcf 768
769 chip->client = client;
770
e23efa31
PR
771 reg = devm_regulator_get(&client->dev, "vcc");
772 if (IS_ERR(reg)) {
773 ret = PTR_ERR(reg);
774 if (ret != -EPROBE_DEFER)
775 dev_err(&client->dev, "reg get err: %d\n", ret);
776 return ret;
777 }
778 ret = regulator_enable(reg);
779 if (ret) {
780 dev_err(&client->dev, "reg en err: %d\n", ret);
781 return ret;
782 }
783 chip->regulator = reg;
784
f32517bf
AS
785 if (id) {
786 chip->driver_data = id->driver_data;
787 } else {
788 const struct acpi_device_id *id;
6f29c9af 789 const struct of_device_id *match;
f32517bf 790
6f29c9af
BD
791 match = of_match_device(pca953x_dt_ids, &client->dev);
792 if (match) {
793 chip->driver_data = (int)(uintptr_t)match->data;
794 } else {
795 id = acpi_match_device(pca953x_acpi_ids, &client->dev);
e23efa31
PR
796 if (!id) {
797 ret = -ENODEV;
798 goto err_exit;
799 }
f32517bf 800
6f29c9af
BD
801 chip->driver_data = id->driver_data;
802 }
f32517bf
AS
803 }
804
c6664149 805 chip->chip_type = PCA_CHIP_TYPE(chip->driver_data);
77906a54 806
6e20fb18
RS
807 mutex_init(&chip->i2c_lock);
808
9e60fdcf 809 /* initialize cached registers from their original values.
810 * we can't share this chip with another i2c master.
811 */
c6664149 812 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
f5e8ff48 813
33226ffd 814 if (chip->chip_type == PCA953X_TYPE)
7ea2aa20 815 ret = device_pca953x_init(chip, invert);
33226ffd 816 else
7ea2aa20
WS
817 ret = device_pca957x_init(chip, invert);
818 if (ret)
e23efa31 819 goto err_exit;
9e60fdcf 820
0ece84f5 821 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
89ea8bbe 822 if (ret)
e23efa31 823 goto err_exit;
f5e8ff48 824
c6664149 825 ret = pca953x_irq_setup(chip, irq_base);
9e60fdcf 826 if (ret)
e23efa31 827 goto err_exit;
9e60fdcf 828
c6dcf592 829 if (pdata && pdata->setup) {
9e60fdcf 830 ret = pdata->setup(client, chip->gpio_chip.base,
831 chip->gpio_chip.ngpio, pdata->context);
832 if (ret < 0)
833 dev_warn(&client->dev, "setup failed, %d\n", ret);
834 }
835
836 i2c_set_clientdata(client, chip);
837 return 0;
e23efa31
PR
838
839err_exit:
840 regulator_disable(chip->regulator);
841 return ret;
9e60fdcf 842}
843
f3dc3630 844static int pca953x_remove(struct i2c_client *client)
9e60fdcf 845{
e56aee18 846 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
f3dc3630 847 struct pca953x_chip *chip = i2c_get_clientdata(client);
8c7a92da 848 int ret;
9e60fdcf 849
c6dcf592 850 if (pdata && pdata->teardown) {
9e60fdcf 851 ret = pdata->teardown(client, chip->gpio_chip.base,
852 chip->gpio_chip.ngpio, pdata->context);
e23efa31 853 if (ret < 0)
9e60fdcf 854 dev_err(&client->dev, "%s failed, %d\n",
855 "teardown", ret);
bf62efeb
AB
856 } else {
857 ret = 0;
9e60fdcf 858 }
859
e23efa31
PR
860 regulator_disable(chip->regulator);
861
862 return ret;
9e60fdcf 863}
864
6f29c9af
BD
865/* convenience to stop overlong match-table lines */
866#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
867#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
868
ed32620e 869static const struct of_device_id pca953x_dt_ids[] = {
6f29c9af
BD
870 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
871 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
872 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
873 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
874 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
875 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
876 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
877 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
878 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
879 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
880 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
881 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
882 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
883 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
884
885 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
886 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
887 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
888 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
889
890 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
353661df 891 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
6f29c9af
BD
892 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
893 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
894 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
895
896 { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), },
897
898 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
ed32620e
MR
899 { }
900};
901
902MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
903
f3dc3630 904static struct i2c_driver pca953x_driver = {
9e60fdcf 905 .driver = {
f3dc3630 906 .name = "pca953x",
ed32620e 907 .of_match_table = pca953x_dt_ids,
f32517bf 908 .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
9e60fdcf 909 },
f3dc3630
GL
910 .probe = pca953x_probe,
911 .remove = pca953x_remove,
3760f736 912 .id_table = pca953x_id,
9e60fdcf 913};
914
f3dc3630 915static int __init pca953x_init(void)
9e60fdcf 916{
f3dc3630 917 return i2c_add_driver(&pca953x_driver);
9e60fdcf 918}
2f8d1197
DB
919/* register after i2c postcore initcall and before
920 * subsys initcalls that may rely on these GPIOs
921 */
922subsys_initcall(pca953x_init);
9e60fdcf 923
f3dc3630 924static void __exit pca953x_exit(void)
9e60fdcf 925{
f3dc3630 926 i2c_del_driver(&pca953x_driver);
9e60fdcf 927}
f3dc3630 928module_exit(pca953x_exit);
9e60fdcf 929
930MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
f3dc3630 931MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
9e60fdcf 932MODULE_LICENSE("GPL");