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9e60fdcf 1/*
1e191695 2 * PCA953x 4/8/16/24/40 bit I/O ports
9e60fdcf 3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd.
6 *
7 * Derived from drivers/i2c/chips/pca9539.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
d120c17f 16#include <linux/gpio.h>
89ea8bbe 17#include <linux/interrupt.h>
9e60fdcf 18#include <linux/i2c.h>
5877457a 19#include <linux/platform_data/pca953x.h>
5a0e3ad6 20#include <linux/slab.h>
9b8e3ec3 21#include <asm/unaligned.h>
1965d303 22#include <linux/of_platform.h>
f32517bf 23#include <linux/acpi.h>
9e60fdcf 24
33226ffd
HZ
25#define PCA953X_INPUT 0
26#define PCA953X_OUTPUT 1
27#define PCA953X_INVERT 2
28#define PCA953X_DIRECTION 3
29
ae79c190
AS
30#define REG_ADDR_AI 0x80
31
33226ffd
HZ
32#define PCA957X_IN 0
33#define PCA957X_INVRT 1
34#define PCA957X_BKEN 2
35#define PCA957X_PUPD 3
36#define PCA957X_CFG 4
37#define PCA957X_OUT 5
38#define PCA957X_MSK 6
39#define PCA957X_INTS 7
40
44896bea
YL
41#define PCAL953X_IN_LATCH 34
42#define PCAL953X_INT_MASK 37
43#define PCAL953X_INT_STAT 38
44
33226ffd
HZ
45#define PCA_GPIO_MASK 0x00FF
46#define PCA_INT 0x0100
8c7a92da 47#define PCA_PCAL 0x0200
33226ffd
HZ
48#define PCA953X_TYPE 0x1000
49#define PCA957X_TYPE 0x2000
c6664149
AS
50#define PCA_TYPE_MASK 0xF000
51
52#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
89ea8bbe 53
3760f736 54static const struct i2c_device_id pca953x_id[] = {
89f5df01 55 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
33226ffd
HZ
56 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
57 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
58 { "pca9536", 4 | PCA953X_TYPE, },
59 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
60 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
61 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
62 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
63 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
64 { "pca9556", 8 | PCA953X_TYPE, },
65 { "pca9557", 8 | PCA953X_TYPE, },
66 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
67 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
eb32b5aa 68 { "pca9698", 40 | PCA953X_TYPE, },
33226ffd 69
747e42a1
AS
70 { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
71
33226ffd
HZ
72 { "max7310", 8 | PCA953X_TYPE, },
73 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
74 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
75 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
76 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
77 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
78 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
ae79c190 79 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
2db8aba8 80 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
e73760a6 81 { "xra1202", 8 | PCA953X_TYPE },
3760f736 82 { }
f5e8ff48 83};
3760f736 84MODULE_DEVICE_TABLE(i2c, pca953x_id);
9e60fdcf 85
f32517bf 86static const struct acpi_device_id pca953x_acpi_ids[] = {
44896bea 87 { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
f32517bf
AS
88 { }
89};
90MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
91
f5f0b7aa
GC
92#define MAX_BANK 5
93#define BANK_SZ 8
94
a246b819 95#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
f5f0b7aa 96
f3dc3630 97struct pca953x_chip {
9e60fdcf 98 unsigned gpio_start;
f5f0b7aa
GC
99 u8 reg_output[MAX_BANK];
100 u8 reg_direction[MAX_BANK];
6e20fb18 101 struct mutex i2c_lock;
9e60fdcf 102
89ea8bbe
MZ
103#ifdef CONFIG_GPIO_PCA953X_IRQ
104 struct mutex irq_lock;
f5f0b7aa
GC
105 u8 irq_mask[MAX_BANK];
106 u8 irq_stat[MAX_BANK];
107 u8 irq_trig_raise[MAX_BANK];
108 u8 irq_trig_fall[MAX_BANK];
89ea8bbe
MZ
109#endif
110
9e60fdcf 111 struct i2c_client *client;
112 struct gpio_chip gpio_chip;
62154991 113 const char *const *names;
33226ffd 114 int chip_type;
c6664149 115 unsigned long driver_data;
9e60fdcf 116};
117
f5f0b7aa
GC
118static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
119 int off)
120{
121 int ret;
122 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
123 int offset = off / BANK_SZ;
124
125 ret = i2c_smbus_read_byte_data(chip->client,
126 (reg << bank_shift) + offset);
127 *val = ret;
128
129 if (ret < 0) {
130 dev_err(&chip->client->dev, "failed reading register\n");
131 return ret;
132 }
133
134 return 0;
135}
136
137static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
138 int off)
139{
8c7a92da 140 int ret;
f5f0b7aa
GC
141 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
142 int offset = off / BANK_SZ;
143
144 ret = i2c_smbus_write_byte_data(chip->client,
145 (reg << bank_shift) + offset, val);
146
147 if (ret < 0) {
148 dev_err(&chip->client->dev, "failed writing register\n");
149 return ret;
150 }
151
152 return 0;
153}
154
155static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 156{
33226ffd 157 int ret = 0;
f5e8ff48
GL
158
159 if (chip->gpio_chip.ngpio <= 8)
f5f0b7aa
GC
160 ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
161 else if (chip->gpio_chip.ngpio >= 24) {
162 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
96b70641 163 ret = i2c_smbus_write_i2c_block_data(chip->client,
f5f0b7aa
GC
164 (reg << bank_shift) | REG_ADDR_AI,
165 NBANK(chip), val);
50e44430 166 } else {
33226ffd 167 switch (chip->chip_type) {
c4d1cbd7
AS
168 case PCA953X_TYPE: {
169 __le16 word = cpu_to_le16(get_unaligned((u16 *)val));
170
171 ret = i2c_smbus_write_word_data(chip->client, reg << 1,
172 (__force u16)word);
33226ffd 173 break;
c4d1cbd7 174 }
33226ffd
HZ
175 case PCA957X_TYPE:
176 ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
f5f0b7aa 177 val[0]);
33226ffd
HZ
178 if (ret < 0)
179 break;
180 ret = i2c_smbus_write_byte_data(chip->client,
181 (reg << 1) + 1,
f5f0b7aa 182 val[1]);
33226ffd
HZ
183 break;
184 }
185 }
f5e8ff48
GL
186
187 if (ret < 0) {
188 dev_err(&chip->client->dev, "failed writing register\n");
ab5dc372 189 return ret;
f5e8ff48
GL
190 }
191
192 return 0;
9e60fdcf 193}
194
f5f0b7aa 195static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 196{
197 int ret;
198
96b70641 199 if (chip->gpio_chip.ngpio <= 8) {
f5e8ff48 200 ret = i2c_smbus_read_byte_data(chip->client, reg);
96b70641 201 *val = ret;
f5f0b7aa
GC
202 } else if (chip->gpio_chip.ngpio >= 24) {
203 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
204
96b70641 205 ret = i2c_smbus_read_i2c_block_data(chip->client,
f5f0b7aa
GC
206 (reg << bank_shift) | REG_ADDR_AI,
207 NBANK(chip), val);
96b70641 208 } else {
f5e8ff48 209 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
f5f0b7aa
GC
210 val[0] = (u16)ret & 0xFF;
211 val[1] = (u16)ret >> 8;
96b70641 212 }
9e60fdcf 213 if (ret < 0) {
214 dev_err(&chip->client->dev, "failed reading register\n");
ab5dc372 215 return ret;
9e60fdcf 216 }
217
9e60fdcf 218 return 0;
219}
220
f3dc3630 221static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
9e60fdcf 222{
468e67f6 223 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 224 u8 reg_val;
33226ffd 225 int ret, offset = 0;
9e60fdcf 226
6e20fb18 227 mutex_lock(&chip->i2c_lock);
f5f0b7aa 228 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
33226ffd
HZ
229
230 switch (chip->chip_type) {
231 case PCA953X_TYPE:
232 offset = PCA953X_DIRECTION;
233 break;
234 case PCA957X_TYPE:
235 offset = PCA957X_CFG;
236 break;
237 }
f5f0b7aa 238 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 239 if (ret)
6e20fb18 240 goto exit;
9e60fdcf 241
f5f0b7aa 242 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
243exit:
244 mutex_unlock(&chip->i2c_lock);
245 return ret;
9e60fdcf 246}
247
f3dc3630 248static int pca953x_gpio_direction_output(struct gpio_chip *gc,
9e60fdcf 249 unsigned off, int val)
250{
468e67f6 251 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 252 u8 reg_val;
33226ffd 253 int ret, offset = 0;
9e60fdcf 254
6e20fb18 255 mutex_lock(&chip->i2c_lock);
9e60fdcf 256 /* set output level */
257 if (val)
f5f0b7aa
GC
258 reg_val = chip->reg_output[off / BANK_SZ]
259 | (1u << (off % BANK_SZ));
9e60fdcf 260 else
f5f0b7aa
GC
261 reg_val = chip->reg_output[off / BANK_SZ]
262 & ~(1u << (off % BANK_SZ));
9e60fdcf 263
33226ffd
HZ
264 switch (chip->chip_type) {
265 case PCA953X_TYPE:
266 offset = PCA953X_OUTPUT;
267 break;
268 case PCA957X_TYPE:
269 offset = PCA957X_OUT;
270 break;
271 }
f5f0b7aa 272 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 273 if (ret)
6e20fb18 274 goto exit;
9e60fdcf 275
f5f0b7aa 276 chip->reg_output[off / BANK_SZ] = reg_val;
9e60fdcf 277
278 /* then direction */
f5f0b7aa 279 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
33226ffd
HZ
280 switch (chip->chip_type) {
281 case PCA953X_TYPE:
282 offset = PCA953X_DIRECTION;
283 break;
284 case PCA957X_TYPE:
285 offset = PCA957X_CFG;
286 break;
287 }
f5f0b7aa 288 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 289 if (ret)
6e20fb18 290 goto exit;
9e60fdcf 291
f5f0b7aa 292 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
293exit:
294 mutex_unlock(&chip->i2c_lock);
295 return ret;
9e60fdcf 296}
297
f3dc3630 298static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
9e60fdcf 299{
468e67f6 300 struct pca953x_chip *chip = gpiochip_get_data(gc);
ae79c190 301 u32 reg_val;
33226ffd 302 int ret, offset = 0;
9e60fdcf 303
6e20fb18 304 mutex_lock(&chip->i2c_lock);
33226ffd
HZ
305 switch (chip->chip_type) {
306 case PCA953X_TYPE:
307 offset = PCA953X_INPUT;
308 break;
309 case PCA957X_TYPE:
310 offset = PCA957X_IN;
311 break;
312 }
f5f0b7aa 313 ret = pca953x_read_single(chip, offset, &reg_val, off);
6e20fb18 314 mutex_unlock(&chip->i2c_lock);
9e60fdcf 315 if (ret < 0) {
316 /* NOTE: diagnostic already emitted; that's all we should
317 * do unless gpio_*_value_cansleep() calls become different
318 * from their nonsleeping siblings (and report faults).
319 */
320 return 0;
321 }
322
40a625da 323 return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
9e60fdcf 324}
325
f3dc3630 326static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
9e60fdcf 327{
468e67f6 328 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa 329 u8 reg_val;
33226ffd 330 int ret, offset = 0;
9e60fdcf 331
6e20fb18 332 mutex_lock(&chip->i2c_lock);
9e60fdcf 333 if (val)
f5f0b7aa
GC
334 reg_val = chip->reg_output[off / BANK_SZ]
335 | (1u << (off % BANK_SZ));
9e60fdcf 336 else
f5f0b7aa
GC
337 reg_val = chip->reg_output[off / BANK_SZ]
338 & ~(1u << (off % BANK_SZ));
9e60fdcf 339
33226ffd
HZ
340 switch (chip->chip_type) {
341 case PCA953X_TYPE:
342 offset = PCA953X_OUTPUT;
343 break;
344 case PCA957X_TYPE:
345 offset = PCA957X_OUT;
346 break;
347 }
f5f0b7aa 348 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 349 if (ret)
6e20fb18 350 goto exit;
9e60fdcf 351
f5f0b7aa 352 chip->reg_output[off / BANK_SZ] = reg_val;
6e20fb18
RS
353exit:
354 mutex_unlock(&chip->i2c_lock);
9e60fdcf 355}
356
b4818afe
PR
357static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
358 unsigned long *mask, unsigned long *bits)
359{
468e67f6 360 struct pca953x_chip *chip = gpiochip_get_data(gc);
b4818afe
PR
361 u8 reg_val[MAX_BANK];
362 int ret, offset = 0;
363 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
364 int bank;
365
366 switch (chip->chip_type) {
367 case PCA953X_TYPE:
368 offset = PCA953X_OUTPUT;
369 break;
370 case PCA957X_TYPE:
371 offset = PCA957X_OUT;
372 break;
373 }
374
375 memcpy(reg_val, chip->reg_output, NBANK(chip));
376 mutex_lock(&chip->i2c_lock);
377 for(bank=0; bank<NBANK(chip); bank++) {
e0a8604f
GU
378 unsigned bankmask = mask[bank / sizeof(*mask)] >>
379 ((bank % sizeof(*mask)) * 8);
b4818afe 380 if(bankmask) {
e0a8604f
GU
381 unsigned bankval = bits[bank / sizeof(*bits)] >>
382 ((bank % sizeof(*bits)) * 8);
b4818afe
PR
383 reg_val[bank] = (reg_val[bank] & ~bankmask) | bankval;
384 }
385 }
386 ret = i2c_smbus_write_i2c_block_data(chip->client, offset << bank_shift, NBANK(chip), reg_val);
387 if (ret)
388 goto exit;
389
390 memcpy(chip->reg_output, reg_val, NBANK(chip));
391exit:
392 mutex_unlock(&chip->i2c_lock);
393}
394
f5e8ff48 395static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
9e60fdcf 396{
397 struct gpio_chip *gc;
398
399 gc = &chip->gpio_chip;
400
f3dc3630
GL
401 gc->direction_input = pca953x_gpio_direction_input;
402 gc->direction_output = pca953x_gpio_direction_output;
403 gc->get = pca953x_gpio_get_value;
404 gc->set = pca953x_gpio_set_value;
b4818afe 405 gc->set_multiple = pca953x_gpio_set_multiple;
9fb1f39e 406 gc->can_sleep = true;
9e60fdcf 407
408 gc->base = chip->gpio_start;
f5e8ff48
GL
409 gc->ngpio = gpios;
410 gc->label = chip->client->name;
58383c78 411 gc->parent = &chip->client->dev;
d72cbed0 412 gc->owner = THIS_MODULE;
77906a54 413 gc->names = chip->names;
9e60fdcf 414}
415
89ea8bbe 416#ifdef CONFIG_GPIO_PCA953X_IRQ
6f5cfc0e 417static void pca953x_irq_mask(struct irq_data *d)
89ea8bbe 418{
7bcbce55 419 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 420 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe 421
f5f0b7aa 422 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
89ea8bbe
MZ
423}
424
6f5cfc0e 425static void pca953x_irq_unmask(struct irq_data *d)
89ea8bbe 426{
7bcbce55 427 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 428 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe 429
f5f0b7aa 430 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
431}
432
6f5cfc0e 433static void pca953x_irq_bus_lock(struct irq_data *d)
89ea8bbe 434{
7bcbce55 435 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 436 struct pca953x_chip *chip = gpiochip_get_data(gc);
89ea8bbe
MZ
437
438 mutex_lock(&chip->irq_lock);
439}
440
6f5cfc0e 441static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
89ea8bbe 442{
7bcbce55 443 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 444 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa
GC
445 u8 new_irqs;
446 int level, i;
44896bea
YL
447 u8 invert_irq_mask[MAX_BANK];
448
449 if (chip->driver_data & PCA_PCAL) {
450 /* Enable latch on interrupt-enabled inputs */
451 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
452
453 for (i = 0; i < NBANK(chip); i++)
454 invert_irq_mask[i] = ~chip->irq_mask[i];
455
456 /* Unmask enabled interrupts */
457 pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
458 }
a2cb9aeb
MZ
459
460 /* Look for any newly setup interrupt */
f5f0b7aa
GC
461 for (i = 0; i < NBANK(chip); i++) {
462 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
463 new_irqs &= ~chip->reg_direction[i];
464
465 while (new_irqs) {
466 level = __ffs(new_irqs);
467 pca953x_gpio_direction_input(&chip->gpio_chip,
468 level + (BANK_SZ * i));
469 new_irqs &= ~(1 << level);
470 }
a2cb9aeb 471 }
89ea8bbe
MZ
472
473 mutex_unlock(&chip->irq_lock);
474}
475
6f5cfc0e 476static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
89ea8bbe 477{
7bcbce55 478 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
468e67f6 479 struct pca953x_chip *chip = gpiochip_get_data(gc);
f5f0b7aa
GC
480 int bank_nb = d->hwirq / BANK_SZ;
481 u8 mask = 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
482
483 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
484 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
6f5cfc0e 485 d->irq, type);
89ea8bbe
MZ
486 return -EINVAL;
487 }
488
489 if (type & IRQ_TYPE_EDGE_FALLING)
f5f0b7aa 490 chip->irq_trig_fall[bank_nb] |= mask;
89ea8bbe 491 else
f5f0b7aa 492 chip->irq_trig_fall[bank_nb] &= ~mask;
89ea8bbe
MZ
493
494 if (type & IRQ_TYPE_EDGE_RISING)
f5f0b7aa 495 chip->irq_trig_raise[bank_nb] |= mask;
89ea8bbe 496 else
f5f0b7aa 497 chip->irq_trig_raise[bank_nb] &= ~mask;
89ea8bbe 498
a2cb9aeb 499 return 0;
89ea8bbe
MZ
500}
501
502static struct irq_chip pca953x_irq_chip = {
503 .name = "pca953x",
6f5cfc0e
LB
504 .irq_mask = pca953x_irq_mask,
505 .irq_unmask = pca953x_irq_unmask,
506 .irq_bus_lock = pca953x_irq_bus_lock,
507 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
508 .irq_set_type = pca953x_irq_set_type,
89ea8bbe
MZ
509};
510
b6ac1280 511static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
89ea8bbe 512{
f5f0b7aa
GC
513 u8 cur_stat[MAX_BANK];
514 u8 old_stat[MAX_BANK];
b6ac1280
JS
515 bool pending_seen = false;
516 bool trigger_seen = false;
517 u8 trigger[MAX_BANK];
f5f0b7aa 518 int ret, i, offset = 0;
33226ffd 519
44896bea
YL
520 if (chip->driver_data & PCA_PCAL) {
521 /* Read the current interrupt status from the device */
522 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
523 if (ret)
524 return false;
525
526 /* Check latched inputs and clear interrupt status */
527 ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
528 if (ret)
529 return false;
530
531 for (i = 0; i < NBANK(chip); i++) {
532 /* Apply filter for rising/falling edge selection */
533 pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
534 (cur_stat[i] & chip->irq_trig_raise[i]);
535 pending[i] &= trigger[i];
536 if (pending[i])
537 pending_seen = true;
538 }
539
540 return pending_seen;
541 }
542
33226ffd
HZ
543 switch (chip->chip_type) {
544 case PCA953X_TYPE:
545 offset = PCA953X_INPUT;
546 break;
547 case PCA957X_TYPE:
548 offset = PCA957X_IN;
549 break;
550 }
f5f0b7aa 551 ret = pca953x_read_regs(chip, offset, cur_stat);
89ea8bbe 552 if (ret)
b6ac1280 553 return false;
89ea8bbe
MZ
554
555 /* Remove output pins from the equation */
f5f0b7aa
GC
556 for (i = 0; i < NBANK(chip); i++)
557 cur_stat[i] &= chip->reg_direction[i];
89ea8bbe 558
f5f0b7aa 559 memcpy(old_stat, chip->irq_stat, NBANK(chip));
89ea8bbe 560
f5f0b7aa
GC
561 for (i = 0; i < NBANK(chip); i++) {
562 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
b6ac1280
JS
563 if (trigger[i])
564 trigger_seen = true;
f5f0b7aa
GC
565 }
566
b6ac1280
JS
567 if (!trigger_seen)
568 return false;
89ea8bbe 569
f5f0b7aa 570 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
89ea8bbe 571
f5f0b7aa
GC
572 for (i = 0; i < NBANK(chip); i++) {
573 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
574 (cur_stat[i] & chip->irq_trig_raise[i]);
575 pending[i] &= trigger[i];
b6ac1280
JS
576 if (pending[i])
577 pending_seen = true;
f5f0b7aa 578 }
89ea8bbe 579
b6ac1280 580 return pending_seen;
89ea8bbe
MZ
581}
582
583static irqreturn_t pca953x_irq_handler(int irq, void *devid)
584{
585 struct pca953x_chip *chip = devid;
f5f0b7aa
GC
586 u8 pending[MAX_BANK];
587 u8 level;
3275d072 588 unsigned nhandled = 0;
f5f0b7aa 589 int i;
89ea8bbe 590
f5f0b7aa 591 if (!pca953x_irq_pending(chip, pending))
3275d072 592 return IRQ_NONE;
89ea8bbe 593
f5f0b7aa
GC
594 for (i = 0; i < NBANK(chip); i++) {
595 while (pending[i]) {
596 level = __ffs(pending[i]);
7bcbce55 597 handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
f5f0b7aa
GC
598 level + (BANK_SZ * i)));
599 pending[i] &= ~(1 << level);
3275d072 600 nhandled++;
f5f0b7aa
GC
601 }
602 }
89ea8bbe 603
3275d072 604 return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
89ea8bbe
MZ
605}
606
607static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592 608 int irq_base)
89ea8bbe
MZ
609{
610 struct i2c_client *client = chip->client;
f5f0b7aa 611 int ret, i, offset = 0;
89ea8bbe 612
4bb93349 613 if (client->irq && irq_base != -1
c6664149 614 && (chip->driver_data & PCA_INT)) {
89ea8bbe 615
33226ffd
HZ
616 switch (chip->chip_type) {
617 case PCA953X_TYPE:
618 offset = PCA953X_INPUT;
619 break;
620 case PCA957X_TYPE:
621 offset = PCA957X_IN;
622 break;
623 }
f5f0b7aa 624 ret = pca953x_read_regs(chip, offset, chip->irq_stat);
89ea8bbe 625 if (ret)
b42748c9 626 return ret;
89ea8bbe
MZ
627
628 /*
629 * There is no way to know which GPIO line generated the
630 * interrupt. We have to rely on the previous read for
631 * this purpose.
632 */
f5f0b7aa
GC
633 for (i = 0; i < NBANK(chip); i++)
634 chip->irq_stat[i] &= chip->reg_direction[i];
89ea8bbe
MZ
635 mutex_init(&chip->irq_lock);
636
b42748c9
LW
637 ret = devm_request_threaded_irq(&client->dev,
638 client->irq,
89ea8bbe
MZ
639 NULL,
640 pca953x_irq_handler,
91329132
TS
641 IRQF_TRIGGER_LOW | IRQF_ONESHOT |
642 IRQF_SHARED,
89ea8bbe
MZ
643 dev_name(&client->dev), chip);
644 if (ret) {
645 dev_err(&client->dev, "failed to request irq %d\n",
646 client->irq);
0e8f2fda 647 return ret;
89ea8bbe
MZ
648 }
649
7bcbce55
LW
650 ret = gpiochip_irqchip_add(&chip->gpio_chip,
651 &pca953x_irq_chip,
652 irq_base,
653 handle_simple_irq,
654 IRQ_TYPE_NONE);
655 if (ret) {
656 dev_err(&client->dev,
657 "could not connect irqchip to gpiochip\n");
658 return ret;
659 }
fdd50409
GS
660
661 gpiochip_set_chained_irqchip(&chip->gpio_chip,
662 &pca953x_irq_chip,
663 client->irq, NULL);
89ea8bbe
MZ
664 }
665
666 return 0;
89ea8bbe
MZ
667}
668
89ea8bbe
MZ
669#else /* CONFIG_GPIO_PCA953X_IRQ */
670static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592 671 int irq_base)
89ea8bbe
MZ
672{
673 struct i2c_client *client = chip->client;
89ea8bbe 674
c6664149 675 if (irq_base != -1 && (chip->driver_data & PCA_INT))
89ea8bbe
MZ
676 dev_warn(&client->dev, "interrupt support not compiled in\n");
677
678 return 0;
679}
89ea8bbe
MZ
680#endif
681
3836309d 682static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
683{
684 int ret;
f5f0b7aa 685 u8 val[MAX_BANK];
33226ffd 686
f5f0b7aa 687 ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
33226ffd
HZ
688 if (ret)
689 goto out;
690
f5f0b7aa
GC
691 ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
692 chip->reg_direction);
33226ffd
HZ
693 if (ret)
694 goto out;
695
696 /* set platform specific polarity inversion */
f5f0b7aa
GC
697 if (invert)
698 memset(val, 0xFF, NBANK(chip));
699 else
700 memset(val, 0, NBANK(chip));
701
702 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
33226ffd
HZ
703out:
704 return ret;
705}
706
3836309d 707static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
708{
709 int ret;
f5f0b7aa 710 u8 val[MAX_BANK];
33226ffd 711
f5f0b7aa 712 ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
33226ffd
HZ
713 if (ret)
714 goto out;
f5f0b7aa 715 ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
33226ffd
HZ
716 if (ret)
717 goto out;
718
719 /* set platform specific polarity inversion */
f5f0b7aa
GC
720 if (invert)
721 memset(val, 0xFF, NBANK(chip));
722 else
723 memset(val, 0, NBANK(chip));
c75a3772
NK
724 ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
725 if (ret)
726 goto out;
33226ffd 727
20a8a968 728 /* To enable register 6, 7 to control pull up and pull down */
f5f0b7aa 729 memset(val, 0x02, NBANK(chip));
c75a3772
NK
730 ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
731 if (ret)
732 goto out;
33226ffd
HZ
733
734 return 0;
735out:
736 return ret;
737}
738
6f29c9af
BD
739static const struct of_device_id pca953x_dt_ids[];
740
3836309d 741static int pca953x_probe(struct i2c_client *client,
3760f736 742 const struct i2c_device_id *id)
9e60fdcf 743{
f3dc3630
GL
744 struct pca953x_platform_data *pdata;
745 struct pca953x_chip *chip;
6a7b36aa 746 int irq_base = 0;
7ea2aa20 747 int ret;
6a7b36aa 748 u32 invert = 0;
9e60fdcf 749
b42748c9
LW
750 chip = devm_kzalloc(&client->dev,
751 sizeof(struct pca953x_chip), GFP_KERNEL);
1965d303
NC
752 if (chip == NULL)
753 return -ENOMEM;
754
e56aee18 755 pdata = dev_get_platdata(&client->dev);
c6dcf592
DJ
756 if (pdata) {
757 irq_base = pdata->irq_base;
758 chip->gpio_start = pdata->gpio_base;
759 invert = pdata->invert;
760 chip->names = pdata->names;
761 } else {
4bb93349
MP
762 chip->gpio_start = -1;
763 irq_base = 0;
1965d303 764 }
9e60fdcf 765
766 chip->client = client;
767
f32517bf
AS
768 if (id) {
769 chip->driver_data = id->driver_data;
770 } else {
771 const struct acpi_device_id *id;
6f29c9af 772 const struct of_device_id *match;
f32517bf 773
6f29c9af
BD
774 match = of_match_device(pca953x_dt_ids, &client->dev);
775 if (match) {
776 chip->driver_data = (int)(uintptr_t)match->data;
777 } else {
778 id = acpi_match_device(pca953x_acpi_ids, &client->dev);
779 if (!id)
780 return -ENODEV;
f32517bf 781
6f29c9af
BD
782 chip->driver_data = id->driver_data;
783 }
f32517bf
AS
784 }
785
c6664149 786 chip->chip_type = PCA_CHIP_TYPE(chip->driver_data);
77906a54 787
6e20fb18
RS
788 mutex_init(&chip->i2c_lock);
789
9e60fdcf 790 /* initialize cached registers from their original values.
791 * we can't share this chip with another i2c master.
792 */
c6664149 793 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
f5e8ff48 794
33226ffd 795 if (chip->chip_type == PCA953X_TYPE)
7ea2aa20 796 ret = device_pca953x_init(chip, invert);
33226ffd 797 else
7ea2aa20
WS
798 ret = device_pca957x_init(chip, invert);
799 if (ret)
b42748c9 800 return ret;
9e60fdcf 801
0ece84f5 802 ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
89ea8bbe 803 if (ret)
b42748c9 804 return ret;
f5e8ff48 805
c6664149 806 ret = pca953x_irq_setup(chip, irq_base);
9e60fdcf 807 if (ret)
b42748c9 808 return ret;
9e60fdcf 809
c6dcf592 810 if (pdata && pdata->setup) {
9e60fdcf 811 ret = pdata->setup(client, chip->gpio_chip.base,
812 chip->gpio_chip.ngpio, pdata->context);
813 if (ret < 0)
814 dev_warn(&client->dev, "setup failed, %d\n", ret);
815 }
816
817 i2c_set_clientdata(client, chip);
818 return 0;
9e60fdcf 819}
820
f3dc3630 821static int pca953x_remove(struct i2c_client *client)
9e60fdcf 822{
e56aee18 823 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
f3dc3630 824 struct pca953x_chip *chip = i2c_get_clientdata(client);
8c7a92da 825 int ret;
9e60fdcf 826
c6dcf592 827 if (pdata && pdata->teardown) {
9e60fdcf 828 ret = pdata->teardown(client, chip->gpio_chip.base,
829 chip->gpio_chip.ngpio, pdata->context);
830 if (ret < 0) {
831 dev_err(&client->dev, "%s failed, %d\n",
832 "teardown", ret);
833 return ret;
834 }
835 }
836
9e60fdcf 837 return 0;
838}
839
6f29c9af
BD
840/* convenience to stop overlong match-table lines */
841#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
842#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
843
ed32620e 844static const struct of_device_id pca953x_dt_ids[] = {
6f29c9af
BD
845 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
846 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
847 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
848 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
849 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
850 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
851 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
852 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
853 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
854 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
855 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
856 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
857 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
858 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
859
860 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
861 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
862 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
863 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
864
865 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
353661df 866 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
6f29c9af
BD
867 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
868 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
869 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
870
871 { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), },
872
873 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
ed32620e
MR
874 { }
875};
876
877MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
878
f3dc3630 879static struct i2c_driver pca953x_driver = {
9e60fdcf 880 .driver = {
f3dc3630 881 .name = "pca953x",
ed32620e 882 .of_match_table = pca953x_dt_ids,
f32517bf 883 .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
9e60fdcf 884 },
f3dc3630
GL
885 .probe = pca953x_probe,
886 .remove = pca953x_remove,
3760f736 887 .id_table = pca953x_id,
9e60fdcf 888};
889
f3dc3630 890static int __init pca953x_init(void)
9e60fdcf 891{
f3dc3630 892 return i2c_add_driver(&pca953x_driver);
9e60fdcf 893}
2f8d1197
DB
894/* register after i2c postcore initcall and before
895 * subsys initcalls that may rely on these GPIOs
896 */
897subsys_initcall(pca953x_init);
9e60fdcf 898
f3dc3630 899static void __exit pca953x_exit(void)
9e60fdcf 900{
f3dc3630 901 i2c_del_driver(&pca953x_driver);
9e60fdcf 902}
f3dc3630 903module_exit(pca953x_exit);
9e60fdcf 904
905MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
f3dc3630 906MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
9e60fdcf 907MODULE_LICENSE("GPL");